Unified Coverage Report :: Group Instance : attest_sw_binding_4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1568

1

T1

1

T5

5

T41

1

auto[1]

1759

1

T1

2

T5

1

T6

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	111	1			T28	1		T47	2		T57	1
auto[134217728:268435455]	95	1			T16	1		T120	2		T47	2
auto[268435456:402653183]	98	1			T29	1		T46	1		T47	1
auto[402653184:536870911]	105	1			T46	1		T47	1		T48	1
auto[536870912:671088639]	111	1			T47	3		T80	1		T193	1
auto[671088640:805306367]	109	1			T5	1		T53	1		T47	2
auto[805306368:939524095]	103	1			T6	1		T41	1		T47	4
auto[939524096:1073741823]	104	1			T84	1		T34	1		T200	1
auto[1073741824:1207959551]	105	1			T5	1		T17	1		T28	1
auto[1207959552:1342177279]	106	1			T1	1		T16	1		T47	3
auto[1342177280:1476395007]	106	1			T47	2		T82	1		T90	1
auto[1476395008:1610612735]	97	1			T17	1		T41	1		T84	1
auto[1610612736:1744830463]	95	1			T195	1		T47	2		T7	1
auto[1744830464:1879048191]	96	1			T47	3		T34	1		T153	1
auto[1879048192:2013265919]	97	1			T41	1		T47	1		T19	1
auto[2013265920:2147483647]	109	1			T47	2		T200	2		T61	1
auto[2147483648:2281701375]	99	1			T1	1		T84	1		T26	1
auto[2281701376:2415919103]	102	1			T5	1		T16	1		T195	1
auto[2415919104:2550136831]	122	1			T1	1		T47	1		T48	1
auto[2550136832:2684354559]	79	1			T53	1		T47	2		T7	1
auto[2684354560:2818572287]	98	1			T24	1		T61	1		T49	1
auto[2818572288:2952790015]	109	1			T17	1		T41	1		T84	1
auto[2952790016:3087007743]	109	1			T84	1		T26	1		T195	1
auto[3087007744:3221225471]	104	1			T47	1		T80	1		T406	1
auto[3221225472:3355443199]	117	1			T84	1		T29	1		T195	1
auto[3355443200:3489660927]	86	1			T5	2		T28	1		T195	1
auto[3489660928:3623878655]	110	1			T5	1		T84	1		T120	1
auto[3623878656:3758096383]	120	1			T28	1		T47	3		T48	1
auto[3758096384:3892314111]	93	1			T16	1		T47	1		T82	2
auto[3892314112:4026531839]	122	1			T28	1		T120	1		T47	2
auto[4026531840:4160749567]	110	1			T120	1		T46	1		T47	3
auto[4160749568:4294967295]	100	1			T26	1		T29	1		T195	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	57	1			T57	1		T87	1		T45	1
auto[0:134217727]	auto[1]	54	1			T28	1		T47	2		T9	1
auto[134217728:268435455]	auto[0]	39	1			T47	1		T27	1		T45	1
auto[134217728:268435455]	auto[1]	56	1			T16	1		T120	2		T47	1
auto[268435456:402653183]	auto[0]	41	1			T196	1		T133	1		T42	1
auto[268435456:402653183]	auto[1]	57	1			T29	1		T46	1		T47	1
auto[402653184:536870911]	auto[0]	43	1			T46	1		T48	1		T34	1
auto[402653184:536870911]	auto[1]	62	1			T47	1		T121	1		T176	2
auto[536870912:671088639]	auto[0]	49	1			T47	1		T80	1		T193	1
auto[536870912:671088639]	auto[1]	62	1			T47	2		T138	1		T201	1
auto[671088640:805306367]	auto[0]	63	1			T5	1		T47	1		T193	1
auto[671088640:805306367]	auto[1]	46	1			T53	1		T47	1		T8	1
auto[805306368:939524095]	auto[0]	49	1			T47	2		T50	1		T201	1
auto[805306368:939524095]	auto[1]	54	1			T6	1		T41	1		T47	2
auto[939524096:1073741823]	auto[0]	52	1			T34	1		T24	1		T9	1
auto[939524096:1073741823]	auto[1]	52	1			T84	1		T200	1		T8	1
auto[1073741824:1207959551]	auto[0]	42	1			T5	1		T53	1		T47	1
auto[1073741824:1207959551]	auto[1]	63	1			T17	1		T28	1		T26	1
auto[1207959552:1342177279]	auto[0]	56	1			T47	1		T34	1		T49	1
auto[1207959552:1342177279]	auto[1]	50	1			T1	1		T16	1		T47	2
auto[1342177280:1476395007]	auto[0]	48	1			T47	1		T82	1		T90	1
auto[1342177280:1476395007]	auto[1]	58	1			T47	1		T85	1		T103	1
auto[1476395008:1610612735]	auto[0]	48	1			T41	1		T84	1		T33	1
auto[1476395008:1610612735]	auto[1]	49	1			T17	1		T153	1		T24	1
auto[1610612736:1744830463]	auto[0]	43	1			T195	1		T8	1		T44	1
auto[1610612736:1744830463]	auto[1]	52	1			T47	2		T7	1		T85	1
auto[1744830464:1879048191]	auto[0]	49	1			T47	2		T34	1		T90	1
auto[1744830464:1879048191]	auto[1]	47	1			T47	1		T153	1		T231	1
auto[1879048192:2013265919]	auto[0]	52	1			T47	1		T34	1		T85	1
auto[1879048192:2013265919]	auto[1]	45	1			T41	1		T19	1		T196	1
auto[2013265920:2147483647]	auto[0]	51	1			T47	1		T200	2		T61	1
auto[2013265920:2147483647]	auto[1]	58	1			T47	1		T8	1		T42	1
auto[2147483648:2281701375]	auto[0]	47	1			T1	1		T7	1		T35	1
auto[2147483648:2281701375]	auto[1]	52	1			T84	1		T26	1		T54	1
auto[2281701376:2415919103]	auto[0]	54	1			T5	1		T195	1		T47	1
auto[2281701376:2415919103]	auto[1]	48	1			T16	1		T54	1		T34	1
auto[2415919104:2550136831]	auto[0]	58	1			T47	1		T48	1		T57	1
auto[2415919104:2550136831]	auto[1]	64	1			T1	1		T200	1		T103	1
auto[2550136832:2684354559]	auto[0]	39	1			T53	1		T47	1		T7	1
auto[2550136832:2684354559]	auto[1]	40	1			T47	1		T8	1		T232	1
auto[2684354560:2818572287]	auto[0]	44	1			T24	1		T61	1		T49	1
auto[2684354560:2818572287]	auto[1]	54	1			T406	1		T8	1		T42	1
auto[2818572288:2952790015]	auto[0]	62	1			T33	1		T34	1		T121	1
auto[2818572288:2952790015]	auto[1]	47	1			T17	1		T41	1		T84	1
auto[2952790016:3087007743]	auto[0]	46	1			T26	1		T61	1		T49	1
auto[2952790016:3087007743]	auto[1]	63	1			T84	1		T195	1		T103	2
auto[3087007744:3221225471]	auto[0]	44	1			T80	1		T406	1		T8	1
auto[3087007744:3221225471]	auto[1]	60	1			T47	1		T8	1		T304	1
auto[3221225472:3355443199]	auto[0]	63	1			T29	1		T195	1		T47	2
auto[3221225472:3355443199]	auto[1]	54	1			T84	1		T19	1		T24	1
auto[3355443200:3489660927]	auto[0]	38	1			T5	1		T19	1		T57	1
auto[3355443200:3489660927]	auto[1]	48	1			T5	1		T28	1		T195	1
auto[3489660928:3623878655]	auto[0]	50	1			T5	1		T84	1		T47	1
auto[3489660928:3623878655]	auto[1]	60	1			T120	1		T192	1		T8	1
auto[3623878656:3758096383]	auto[0]	56	1			T47	2		T48	1		T24	2
auto[3623878656:3758096383]	auto[1]	64	1			T28	1		T47	1		T80	1
auto[3758096384:3892314111]	auto[0]	38	1			T193	1		T8	1		T304	1
auto[3758096384:3892314111]	auto[1]	55	1			T16	1		T47	1		T82	2
auto[3892314112:4026531839]	auto[0]	59	1			T120	1		T47	1		T7	1
auto[3892314112:4026531839]	auto[1]	63	1			T28	1		T47	1		T58	1
auto[4026531840:4160749567]	auto[0]	48	1			T46	1		T47	2		T50	1
auto[4026531840:4160749567]	auto[1]	62	1			T120	1		T47	1		T35	1
auto[4160749568:4294967295]	auto[0]	40	1			T26	1		T29	1		T195	1
auto[4160749568:4294967295]	auto[1]	60	1			T47	1		T57	1		T87	1