Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6939

1

T1

4

T5

13

T6

2

auto[1]

321

1

T84

7

T120

2

T121

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2910	1			T1	2		T5	6		T6	1
auto[134217728:268435455]	181	1			T41	2		T28	1		T47	4
auto[268435456:402653183]	180	1			T84	1		T120	1		T47	1
auto[402653184:536870911]	142	1			T84	1		T47	1		T121	2
auto[536870912:671088639]	158	1			T46	2		T47	5		T33	1
auto[671088640:805306367]	145	1			T16	1		T28	1		T195	1
auto[805306368:939524095]	126	1			T5	1		T17	1		T26	1
auto[939524096:1073741823]	125	1			T5	1		T16	2		T17	1
auto[1073741824:1207959551]	142	1			T84	1		T26	1		T47	5
auto[1207959552:1342177279]	135	1			T47	1		T153	1		T27	1
auto[1342177280:1476395007]	134	1			T41	1		T26	1		T195	1
auto[1476395008:1610612735]	131	1			T84	2		T28	1		T26	1
auto[1610612736:1744830463]	143	1			T47	1		T80	1		T57	1
auto[1744830464:1879048191]	108	1			T5	1		T16	1		T28	1
auto[1879048192:2013265919]	133	1			T5	1		T16	1		T47	1
auto[2013265920:2147483647]	133	1			T5	1		T34	1		T193	1
auto[2147483648:2281701375]	125	1			T84	1		T47	3		T34	1
auto[2281701376:2415919103]	155	1			T5	1		T195	1		T120	1
auto[2415919104:2550136831]	141	1			T5	1		T47	1		T82	1
auto[2550136832:2684354559]	139	1			T6	1		T26	1		T120	1
auto[2684354560:2818572287]	163	1			T17	1		T84	1		T195	1
auto[2818572288:2952790015]	143	1			T47	3		T80	1		T34	1
auto[2952790016:3087007743]	129	1			T47	1		T196	1		T200	2
auto[3087007744:3221225471]	131	1			T26	1		T120	1		T46	1
auto[3221225472:3355443199]	139	1			T84	2		T47	2		T19	1
auto[3355443200:3489660927]	134	1			T1	2		T54	1		T47	1
auto[3489660928:3623878655]	138	1			T17	1		T84	2		T47	3
auto[3623878656:3758096383]	131	1			T17	1		T28	1		T47	4
auto[3758096384:3892314111]	150	1			T17	1		T29	1		T120	2
auto[3892314112:4026531839]	121	1			T17	1		T41	1		T26	1
auto[4026531840:4160749567]	136	1			T195	1		T48	1		T80	1
auto[4160749568:4294967295]	159	1			T47	1		T80	1		T82	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2901	1			T1	2		T5	6		T6	1
auto[0:134217727]	auto[1]	9	1			T153	1		T232	1		T264	1
auto[134217728:268435455]	auto[0]	162	1			T41	2		T28	1		T47	4
auto[134217728:268435455]	auto[1]	19	1			T121	1		T238	1		T144	1
auto[268435456:402653183]	auto[0]	164	1			T84	1		T120	1		T47	1
auto[268435456:402653183]	auto[1]	16	1			T238	1		T322	1		T400	2
auto[402653184:536870911]	auto[0]	133	1			T47	1		T121	1		T58	1
auto[402653184:536870911]	auto[1]	9	1			T84	1		T121	1		T234	1
auto[536870912:671088639]	auto[0]	151	1			T46	2		T47	5		T33	1
auto[536870912:671088639]	auto[1]	7	1			T142	2		T143	1		T144	1
auto[671088640:805306367]	auto[0]	134	1			T16	1		T28	1		T195	1
auto[671088640:805306367]	auto[1]	11	1			T144	1		T299	1		T386	1
auto[805306368:939524095]	auto[0]	118	1			T5	1		T17	1		T26	1
auto[805306368:939524095]	auto[1]	8	1			T153	1		T386	1		T346	1
auto[939524096:1073741823]	auto[0]	119	1			T5	1		T16	2		T17	1
auto[939524096:1073741823]	auto[1]	6	1			T84	1		T322	1		T409	1
auto[1073741824:1207959551]	auto[0]	129	1			T26	1		T47	5		T57	1
auto[1073741824:1207959551]	auto[1]	13	1			T84	1		T153	1		T264	1
auto[1207959552:1342177279]	auto[0]	124	1			T47	1		T153	1		T27	1
auto[1207959552:1342177279]	auto[1]	11	1			T238	1		T141	1		T143	1
auto[1342177280:1476395007]	auto[0]	124	1			T41	1		T26	1		T195	1
auto[1342177280:1476395007]	auto[1]	10	1			T121	1		T299	1		T400	1
auto[1476395008:1610612735]	auto[0]	126	1			T84	1		T28	1		T26	1
auto[1476395008:1610612735]	auto[1]	5	1			T84	1		T322	1		T385	1
auto[1610612736:1744830463]	auto[0]	134	1			T47	1		T80	1		T57	1
auto[1610612736:1744830463]	auto[1]	9	1			T264	1		T384	1		T401	1
auto[1744830464:1879048191]	auto[0]	101	1			T5	1		T16	1		T28	1
auto[1744830464:1879048191]	auto[1]	7	1			T232	1		T144	1		T322	1
auto[1879048192:2013265919]	auto[0]	123	1			T5	1		T16	1		T47	1
auto[1879048192:2013265919]	auto[1]	10	1			T121	1		T264	1		T384	1
auto[2013265920:2147483647]	auto[0]	128	1			T5	1		T34	1		T193	1
auto[2013265920:2147483647]	auto[1]	5	1			T144	1		T401	1		T388	1
auto[2147483648:2281701375]	auto[0]	114	1			T84	1		T47	3		T34	1
auto[2147483648:2281701375]	auto[1]	11	1			T153	1		T143	1		T234	1
auto[2281701376:2415919103]	auto[0]	144	1			T5	1		T195	1		T120	1
auto[2281701376:2415919103]	auto[1]	11	1			T264	1		T144	1		T322	1
auto[2415919104:2550136831]	auto[0]	130	1			T5	1		T47	1		T82	1
auto[2415919104:2550136831]	auto[1]	11	1			T322	1		T409	2		T251	1
auto[2550136832:2684354559]	auto[0]	126	1			T6	1		T26	1		T120	1
auto[2550136832:2684354559]	auto[1]	13	1			T232	1		T144	1		T386	1
auto[2684354560:2818572287]	auto[0]	147	1			T17	1		T84	1		T195	1
auto[2684354560:2818572287]	auto[1]	16	1			T232	1		T107	1		T385	2
auto[2818572288:2952790015]	auto[0]	133	1			T47	3		T80	1		T34	1
auto[2818572288:2952790015]	auto[1]	10	1			T232	1		T238	1		T322	1
auto[2952790016:3087007743]	auto[0]	124	1			T47	1		T196	1		T200	2
auto[2952790016:3087007743]	auto[1]	5	1			T322	1		T299	1		T265	1
auto[3087007744:3221225471]	auto[0]	125	1			T26	1		T46	1		T47	3
auto[3087007744:3221225471]	auto[1]	6	1			T120	1		T232	1		T264	1
auto[3221225472:3355443199]	auto[0]	127	1			T84	1		T47	2		T19	1
auto[3221225472:3355443199]	auto[1]	12	1			T84	1		T264	1		T402	1
auto[3355443200:3489660927]	auto[0]	122	1			T1	2		T54	1		T47	1
auto[3355443200:3489660927]	auto[1]	12	1			T153	1		T144	1		T234	2
auto[3489660928:3623878655]	auto[0]	123	1			T17	1		T47	3		T34	2
auto[3489660928:3623878655]	auto[1]	15	1			T84	2		T121	1		T107	1
auto[3623878656:3758096383]	auto[0]	125	1			T17	1		T28	1		T47	4
auto[3623878656:3758096383]	auto[1]	6	1			T386	1		T107	1		T230	2
auto[3758096384:3892314111]	auto[0]	137	1			T17	1		T29	1		T120	1
auto[3758096384:3892314111]	auto[1]	13	1			T120	1		T238	1		T264	1
auto[3892314112:4026531839]	auto[0]	112	1			T17	1		T41	1		T26	1
auto[3892314112:4026531839]	auto[1]	9	1			T264	1		T144	1		T322	1
auto[4026531840:4160749567]	auto[0]	129	1			T195	1		T48	1		T80	1
auto[4026531840:4160749567]	auto[1]	7	1			T289	1		T230	1		T404	1
auto[4160749568:4294967295]	auto[0]	150	1			T47	1		T80	1		T82	1
auto[4160749568:4294967295]	auto[1]	9	1			T322	1		T299	1		T386	1