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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4408 1 T1 6 T5 10 T16 4
auto[1] 2242 1 T5 2 T6 2 T16 4



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 218 1 T1 4 T5 2 T16 2
auto[134217728:268435455] 212 1 T28 2 T47 8 T34 2
auto[268435456:402653183] 188 1 T16 2 T26 2 T47 2
auto[402653184:536870911] 206 1 T5 2 T120 8 T47 2
auto[536870912:671088639] 220 1 T5 2 T46 2 T47 6
auto[671088640:805306367] 248 1 T53 2 T47 8 T80 2
auto[805306368:939524095] 202 1 T17 2 T84 2 T47 2
auto[939524096:1073741823] 200 1 T84 2 T47 6 T7 2
auto[1073741824:1207959551] 192 1 T84 2 T47 2 T33 2
auto[1207959552:1342177279] 206 1 T16 2 T26 2 T195 4
auto[1342177280:1476395007] 214 1 T195 2 T47 4 T48 2
auto[1476395008:1610612735] 208 1 T47 6 T34 2 T90 2
auto[1610612736:1744830463] 208 1 T26 2 T87 2 T49 2
auto[1744830464:1879048191] 178 1 T17 2 T29 2 T47 2
auto[1879048192:2013265919] 206 1 T5 2 T6 2 T120 2
auto[2013265920:2147483647] 194 1 T47 4 T90 2 T103 2
auto[2147483648:2281701375] 248 1 T53 2 T47 2 T7 2
auto[2281701376:2415919103] 230 1 T17 2 T28 2 T26 2
auto[2415919104:2550136831] 188 1 T29 2 T47 2 T34 4
auto[2550136832:2684354559] 220 1 T1 2 T41 2 T195 2
auto[2684354560:2818572287] 214 1 T28 2 T47 8 T153 2
auto[2818572288:2952790015] 240 1 T5 2 T84 2 T195 2
auto[2952790016:3087007743] 202 1 T54 2 T7 2 T196 2
auto[3087007744:3221225471] 186 1 T47 2 T61 2 T231 2
auto[3221225472:3355443199] 172 1 T53 2 T57 4 T90 2
auto[3355443200:3489660927] 206 1 T16 2 T46 2 T47 6
auto[3489660928:3623878655] 222 1 T84 2 T196 2 T58 2
auto[3623878656:3758096383] 188 1 T84 2 T28 2 T47 6
auto[3758096384:3892314111] 196 1 T47 4 T48 2 T82 2
auto[3892314112:4026531839] 180 1 T195 2 T47 2 T19 2
auto[4026531840:4160749567] 220 1 T84 2 T28 2 T47 6
auto[4160749568:4294967295] 238 1 T5 2 T41 6 T47 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 158 1 T1 4 T5 2 T16 2
auto[0:134217727] auto[1] 60 1 T80 2 T57 2 T61 2
auto[134217728:268435455] auto[0] 148 1 T28 2 T47 6 T34 2
auto[134217728:268435455] auto[1] 64 1 T47 2 T49 2 T8 4
auto[268435456:402653183] auto[0] 118 1 T16 2 T47 2 T231 2
auto[268435456:402653183] auto[1] 70 1 T26 2 T34 2 T61 2
auto[402653184:536870911] auto[0] 134 1 T5 2 T120 8 T19 4
auto[402653184:536870911] auto[1] 72 1 T47 2 T8 2 T136 2
auto[536870912:671088639] auto[0] 148 1 T5 2 T47 4 T35 2
auto[536870912:671088639] auto[1] 72 1 T46 2 T47 2 T7 2
auto[671088640:805306367] auto[0] 172 1 T47 8 T80 2 T90 2
auto[671088640:805306367] auto[1] 76 1 T53 2 T82 2 T8 2
auto[805306368:939524095] auto[0] 134 1 T84 2 T24 2 T192 2
auto[805306368:939524095] auto[1] 68 1 T17 2 T47 2 T153 2
auto[939524096:1073741823] auto[0] 132 1 T84 2 T47 4 T82 2
auto[939524096:1073741823] auto[1] 68 1 T47 2 T7 2 T57 2
auto[1073741824:1207959551] auto[0] 124 1 T84 2 T47 2 T33 2
auto[1073741824:1207959551] auto[1] 68 1 T34 2 T58 2 T87 2
auto[1207959552:1342177279] auto[0] 148 1 T26 2 T195 2 T54 2
auto[1207959552:1342177279] auto[1] 58 1 T16 2 T195 2 T8 2
auto[1342177280:1476395007] auto[0] 154 1 T195 2 T47 4 T48 2
auto[1342177280:1476395007] auto[1] 60 1 T103 2 T135 2 T66 2
auto[1476395008:1610612735] auto[0] 142 1 T47 4 T34 2 T90 2
auto[1476395008:1610612735] auto[1] 66 1 T47 2 T8 2 T60 2
auto[1610612736:1744830463] auto[0] 138 1 T26 2 T87 2 T49 2
auto[1610612736:1744830463] auto[1] 70 1 T8 4 T62 2 T42 2
auto[1744830464:1879048191] auto[0] 116 1 T17 2 T47 2 T7 2
auto[1744830464:1879048191] auto[1] 62 1 T29 2 T304 2 T268 2
auto[1879048192:2013265919] auto[0] 122 1 T120 2 T47 2 T196 2
auto[1879048192:2013265919] auto[1] 84 1 T5 2 T6 2 T47 2
auto[2013265920:2147483647] auto[0] 126 1 T47 4 T90 2 T103 2
auto[2013265920:2147483647] auto[1] 68 1 T8 8 T304 2 T67 4
auto[2147483648:2281701375] auto[0] 168 1 T90 2 T49 2 T103 2
auto[2147483648:2281701375] auto[1] 80 1 T53 2 T47 2 T7 2
auto[2281701376:2415919103] auto[0] 162 1 T17 2 T28 2 T26 2
auto[2281701376:2415919103] auto[1] 68 1 T47 2 T34 2 T8 4
auto[2415919104:2550136831] auto[0] 120 1 T47 2 T34 2 T87 2
auto[2415919104:2550136831] auto[1] 68 1 T29 2 T34 2 T121 2
auto[2550136832:2684354559] auto[0] 142 1 T1 2 T41 2 T195 2
auto[2550136832:2684354559] auto[1] 78 1 T46 2 T47 2 T197 2
auto[2684354560:2818572287] auto[0] 142 1 T28 2 T47 6 T9 2
auto[2684354560:2818572287] auto[1] 72 1 T47 2 T153 2 T24 2
auto[2818572288:2952790015] auto[0] 172 1 T5 2 T195 2 T33 2
auto[2818572288:2952790015] auto[1] 68 1 T84 2 T50 2 T8 2
auto[2952790016:3087007743] auto[0] 134 1 T7 2 T200 2 T24 2
auto[2952790016:3087007743] auto[1] 68 1 T54 2 T196 2 T87 2
auto[3087007744:3221225471] auto[0] 124 1 T231 2 T103 4 T8 4
auto[3087007744:3221225471] auto[1] 62 1 T47 2 T61 2 T103 2
auto[3221225472:3355443199] auto[0] 88 1 T57 4 T90 2 T231 2
auto[3221225472:3355443199] auto[1] 84 1 T53 2 T193 2 T49 2
auto[3355443200:3489660927] auto[0] 128 1 T47 6 T80 2 T34 2
auto[3355443200:3489660927] auto[1] 78 1 T16 2 T46 2 T98 2
auto[3489660928:3623878655] auto[0] 146 1 T84 2 T196 2 T406 2
auto[3489660928:3623878655] auto[1] 76 1 T58 2 T135 2 T60 2
auto[3623878656:3758096383] auto[0] 140 1 T84 2 T47 6 T35 2
auto[3623878656:3758096383] auto[1] 48 1 T28 2 T290 2 T410 2
auto[3758096384:3892314111] auto[0] 118 1 T47 2 T48 2 T133 2
auto[3758096384:3892314111] auto[1] 78 1 T47 2 T82 2 T42 2
auto[3892314112:4026531839] auto[0] 104 1 T195 2 T47 2 T19 2
auto[3892314112:4026531839] auto[1] 76 1 T58 2 T103 2 T8 2
auto[4026531840:4160749567] auto[0] 148 1 T84 2 T28 2 T47 6
auto[4026531840:4160749567] auto[1] 72 1 T406 2 T45 2 T98 2
auto[4160749568:4294967295] auto[0] 158 1 T5 2 T41 6 T47 2
auto[4160749568:4294967295] auto[1] 80 1 T153 2 T193 2 T198 2

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