Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.69 99.04 97.95 98.30 100.00 99.02 98.41 91.14


Total test records in report: 1086
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1005 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1717623752 Jul 28 07:25:33 PM PDT 24 Jul 28 07:25:35 PM PDT 24 35910581 ps
T1006 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3631967928 Jul 28 07:25:22 PM PDT 24 Jul 28 07:25:24 PM PDT 24 210833574 ps
T1007 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2088085088 Jul 28 07:25:32 PM PDT 24 Jul 28 07:25:34 PM PDT 24 23147651 ps
T1008 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2038874251 Jul 28 07:25:54 PM PDT 24 Jul 28 07:25:55 PM PDT 24 77171879 ps
T1009 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2887766364 Jul 28 07:25:13 PM PDT 24 Jul 28 07:25:14 PM PDT 24 87831476 ps
T1010 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2886094935 Jul 28 07:25:09 PM PDT 24 Jul 28 07:25:12 PM PDT 24 731770776 ps
T1011 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1749790887 Jul 28 07:25:34 PM PDT 24 Jul 28 07:25:35 PM PDT 24 55665123 ps
T161 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3705465818 Jul 28 07:25:26 PM PDT 24 Jul 28 07:25:29 PM PDT 24 185776129 ps
T1012 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.755624647 Jul 28 07:25:35 PM PDT 24 Jul 28 07:25:37 PM PDT 24 87043718 ps
T1013 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.990472868 Jul 28 07:25:45 PM PDT 24 Jul 28 07:25:48 PM PDT 24 292948040 ps
T1014 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.4200354161 Jul 28 07:25:33 PM PDT 24 Jul 28 07:25:36 PM PDT 24 399982904 ps
T172 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3983227154 Jul 28 07:25:25 PM PDT 24 Jul 28 07:25:32 PM PDT 24 530017959 ps
T1015 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2270481142 Jul 28 07:25:56 PM PDT 24 Jul 28 07:25:57 PM PDT 24 10651686 ps
T1016 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1812844509 Jul 28 07:25:52 PM PDT 24 Jul 28 07:25:53 PM PDT 24 11481277 ps
T1017 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2188348287 Jul 28 07:25:42 PM PDT 24 Jul 28 07:25:45 PM PDT 24 937927690 ps
T1018 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2522598518 Jul 28 07:25:15 PM PDT 24 Jul 28 07:25:16 PM PDT 24 229252505 ps
T1019 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1229602347 Jul 28 07:25:37 PM PDT 24 Jul 28 07:25:38 PM PDT 24 39577091 ps
T1020 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2853321346 Jul 28 07:25:22 PM PDT 24 Jul 28 07:25:23 PM PDT 24 34988264 ps
T1021 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1637970415 Jul 28 07:25:21 PM PDT 24 Jul 28 07:25:38 PM PDT 24 2697713687 ps
T1022 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2332157443 Jul 28 07:25:57 PM PDT 24 Jul 28 07:25:58 PM PDT 24 75076339 ps
T1023 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2910677602 Jul 28 07:25:42 PM PDT 24 Jul 28 07:25:43 PM PDT 24 19077316 ps
T1024 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.50211550 Jul 28 07:25:38 PM PDT 24 Jul 28 07:25:40 PM PDT 24 42899171 ps
T163 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2838960991 Jul 28 07:25:15 PM PDT 24 Jul 28 07:25:21 PM PDT 24 846779818 ps
T1025 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3625705035 Jul 28 07:25:20 PM PDT 24 Jul 28 07:25:22 PM PDT 24 364037204 ps
T1026 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1833016408 Jul 28 07:25:13 PM PDT 24 Jul 28 07:25:21 PM PDT 24 1968426630 ps
T1027 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2168563918 Jul 28 07:25:34 PM PDT 24 Jul 28 07:25:48 PM PDT 24 1328827570 ps
T1028 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1662846127 Jul 28 07:25:16 PM PDT 24 Jul 28 07:25:17 PM PDT 24 26303321 ps
T1029 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.211810401 Jul 28 07:25:43 PM PDT 24 Jul 28 07:25:44 PM PDT 24 21326800 ps
T1030 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2515896191 Jul 28 07:25:53 PM PDT 24 Jul 28 07:25:54 PM PDT 24 106133660 ps
T1031 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1076381113 Jul 28 07:25:09 PM PDT 24 Jul 28 07:25:10 PM PDT 24 53571863 ps
T1032 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3579276946 Jul 28 07:25:51 PM PDT 24 Jul 28 07:25:52 PM PDT 24 16529710 ps
T1033 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.942872326 Jul 28 07:25:27 PM PDT 24 Jul 28 07:25:30 PM PDT 24 432750916 ps
T1034 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.4280183671 Jul 28 07:25:37 PM PDT 24 Jul 28 07:25:39 PM PDT 24 739643447 ps
T1035 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2834644021 Jul 28 07:25:24 PM PDT 24 Jul 28 07:25:28 PM PDT 24 865420563 ps
T1036 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2484824010 Jul 28 07:25:33 PM PDT 24 Jul 28 07:25:35 PM PDT 24 98195205 ps
T1037 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3345193170 Jul 28 07:25:33 PM PDT 24 Jul 28 07:25:48 PM PDT 24 412424515 ps
T1038 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3600679310 Jul 28 07:25:21 PM PDT 24 Jul 28 07:25:23 PM PDT 24 49940322 ps
T1039 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1350344932 Jul 28 07:25:25 PM PDT 24 Jul 28 07:25:26 PM PDT 24 46051830 ps
T1040 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3716363886 Jul 28 07:25:21 PM PDT 24 Jul 28 07:25:23 PM PDT 24 55351323 ps
T1041 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.4290513697 Jul 28 07:25:27 PM PDT 24 Jul 28 07:25:31 PM PDT 24 555772945 ps
T1042 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.910427640 Jul 28 07:25:44 PM PDT 24 Jul 28 07:25:46 PM PDT 24 421230090 ps
T1043 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.95945668 Jul 28 07:25:12 PM PDT 24 Jul 28 07:25:14 PM PDT 24 42558662 ps
T1044 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2435188871 Jul 28 07:25:23 PM PDT 24 Jul 28 07:25:25 PM PDT 24 75929911 ps
T1045 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3821560408 Jul 28 07:25:17 PM PDT 24 Jul 28 07:25:20 PM PDT 24 529609160 ps
T1046 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3836587617 Jul 28 07:25:21 PM PDT 24 Jul 28 07:25:23 PM PDT 24 28547197 ps
T1047 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1075505276 Jul 28 07:25:31 PM PDT 24 Jul 28 07:25:32 PM PDT 24 25161361 ps
T1048 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3069876137 Jul 28 07:25:31 PM PDT 24 Jul 28 07:25:35 PM PDT 24 289817932 ps
T1049 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.781244258 Jul 28 07:25:49 PM PDT 24 Jul 28 07:25:51 PM PDT 24 16656582 ps
T1050 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3164272449 Jul 28 07:25:11 PM PDT 24 Jul 28 07:25:14 PM PDT 24 356492067 ps
T1051 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2960610079 Jul 28 07:25:49 PM PDT 24 Jul 28 07:26:01 PM PDT 24 1765904431 ps
T1052 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3009181128 Jul 28 07:25:34 PM PDT 24 Jul 28 07:25:37 PM PDT 24 114372180 ps
T1053 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1617400339 Jul 28 07:25:54 PM PDT 24 Jul 28 07:25:56 PM PDT 24 20939167 ps
T1054 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3936166668 Jul 28 07:25:35 PM PDT 24 Jul 28 07:25:39 PM PDT 24 512875967 ps
T1055 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1111198416 Jul 28 07:25:17 PM PDT 24 Jul 28 07:25:18 PM PDT 24 56798893 ps
T1056 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3754787765 Jul 28 07:25:18 PM PDT 24 Jul 28 07:25:28 PM PDT 24 206993030 ps
T1057 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2314909962 Jul 28 07:25:26 PM PDT 24 Jul 28 07:25:27 PM PDT 24 19681843 ps
T1058 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.173108471 Jul 28 07:25:48 PM PDT 24 Jul 28 07:25:51 PM PDT 24 183416328 ps
T1059 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.310878978 Jul 28 07:25:21 PM PDT 24 Jul 28 07:25:31 PM PDT 24 468573378 ps
T1060 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1145362481 Jul 28 07:25:17 PM PDT 24 Jul 28 07:25:22 PM PDT 24 320610413 ps
T1061 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1056981607 Jul 28 07:25:47 PM PDT 24 Jul 28 07:25:48 PM PDT 24 16261339 ps
T1062 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1850874225 Jul 28 07:25:28 PM PDT 24 Jul 28 07:25:32 PM PDT 24 144515351 ps
T1063 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1112733262 Jul 28 07:25:57 PM PDT 24 Jul 28 07:25:57 PM PDT 24 47914787 ps
T1064 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.4264733170 Jul 28 07:25:27 PM PDT 24 Jul 28 07:25:29 PM PDT 24 300146991 ps
T1065 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2502827998 Jul 28 07:25:43 PM PDT 24 Jul 28 07:25:49 PM PDT 24 175127137 ps
T1066 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3253468609 Jul 28 07:25:18 PM PDT 24 Jul 28 07:25:19 PM PDT 24 18773967 ps
T1067 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3068211308 Jul 28 07:25:37 PM PDT 24 Jul 28 07:25:40 PM PDT 24 146444234 ps
T1068 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.918511710 Jul 28 07:25:16 PM PDT 24 Jul 28 07:25:17 PM PDT 24 25665827 ps
T1069 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3594969061 Jul 28 07:25:12 PM PDT 24 Jul 28 07:25:26 PM PDT 24 367125495 ps
T1070 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2498902204 Jul 28 07:25:44 PM PDT 24 Jul 28 07:25:46 PM PDT 24 298796325 ps
T1071 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2230136688 Jul 28 07:25:22 PM PDT 24 Jul 28 07:25:23 PM PDT 24 22212903 ps
T1072 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.954473089 Jul 28 07:25:48 PM PDT 24 Jul 28 07:25:49 PM PDT 24 64897907 ps
T1073 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.224580483 Jul 28 07:25:32 PM PDT 24 Jul 28 07:25:34 PM PDT 24 297528768 ps
T1074 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.631586366 Jul 28 07:25:49 PM PDT 24 Jul 28 07:26:02 PM PDT 24 4221365457 ps
T1075 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3484374019 Jul 28 07:25:41 PM PDT 24 Jul 28 07:25:44 PM PDT 24 178651087 ps
T1076 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2194337349 Jul 28 07:25:16 PM PDT 24 Jul 28 07:25:24 PM PDT 24 231445596 ps
T162 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3286799594 Jul 28 07:25:17 PM PDT 24 Jul 28 07:25:23 PM PDT 24 521885948 ps
T1077 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1247441655 Jul 28 07:25:41 PM PDT 24 Jul 28 07:25:44 PM PDT 24 164621834 ps
T1078 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2712471594 Jul 28 07:26:02 PM PDT 24 Jul 28 07:26:03 PM PDT 24 36971204 ps
T1079 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.915088921 Jul 28 07:25:10 PM PDT 24 Jul 28 07:25:26 PM PDT 24 458602224 ps
T1080 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2879586053 Jul 28 07:25:45 PM PDT 24 Jul 28 07:25:53 PM PDT 24 390400146 ps
T1081 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.225271645 Jul 28 07:25:54 PM PDT 24 Jul 28 07:25:56 PM PDT 24 46142348 ps
T1082 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1373752569 Jul 28 07:25:58 PM PDT 24 Jul 28 07:25:59 PM PDT 24 20237399 ps
T1083 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1518112811 Jul 28 07:25:44 PM PDT 24 Jul 28 07:25:46 PM PDT 24 21005633 ps
T1084 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1931644696 Jul 28 07:25:26 PM PDT 24 Jul 28 07:25:28 PM PDT 24 266472732 ps
T1085 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.366614650 Jul 28 07:25:51 PM PDT 24 Jul 28 07:25:53 PM PDT 24 177408926 ps
T1086 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1396158962 Jul 28 07:25:22 PM PDT 24 Jul 28 07:25:25 PM PDT 24 140215405 ps

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.698898663
Short name T17
Test name
Test status
Simulation time 6098990240 ps
CPU time 25.33 seconds
Started Jul 28 07:35:44 PM PDT 24
Finished Jul 28 07:36:09 PM PDT 24
Peak memory 207752 kb
Host smart-0c53a9db-d0d2-4b19-b5ee-c146f2042c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698898663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.698898663
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2233521075
Short name T47
Test name
Test status
Simulation time 44703045042 ps
CPU time 255.6 seconds
Started Jul 28 07:36:47 PM PDT 24
Finished Jul 28 07:41:02 PM PDT 24
Peak memory 222336 kb
Host smart-417f8fd6-f0df-41b5-a1ad-380da1476b76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233521075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2233521075
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3523448387
Short name T8
Test name
Test status
Simulation time 276111254065 ps
CPU time 735.61 seconds
Started Jul 28 07:36:18 PM PDT 24
Finished Jul 28 07:48:34 PM PDT 24
Peak memory 222152 kb
Host smart-15c7432d-5655-460c-926f-9f7b99cd67db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523448387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3523448387
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.4175709169
Short name T28
Test name
Test status
Simulation time 122064820 ps
CPU time 5.82 seconds
Started Jul 28 07:36:06 PM PDT 24
Finished Jul 28 07:36:12 PM PDT 24
Peak memory 218236 kb
Host smart-b8f93137-67d5-44c1-b1f6-1c856564ce9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175709169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.4175709169
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.1417548314
Short name T66
Test name
Test status
Simulation time 4308032653 ps
CPU time 20.73 seconds
Started Jul 28 07:37:32 PM PDT 24
Finished Jul 28 07:37:53 PM PDT 24
Peak memory 222496 kb
Host smart-d104f3b1-a670-43f1-aa0d-475cf08c1ff2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417548314 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.1417548314
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.4035730153
Short name T12
Test name
Test status
Simulation time 912949329 ps
CPU time 7.69 seconds
Started Jul 28 07:35:40 PM PDT 24
Finished Jul 28 07:35:48 PM PDT 24
Peak memory 229684 kb
Host smart-068ea1d6-b959-4a01-8646-d6183b87d9f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035730153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.4035730153
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.4039597928
Short name T55
Test name
Test status
Simulation time 2628948901 ps
CPU time 27.16 seconds
Started Jul 28 07:36:03 PM PDT 24
Finished Jul 28 07:36:31 PM PDT 24
Peak memory 214808 kb
Host smart-5123a719-b4ff-4444-a3a0-1aecd1664c6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039597928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.4039597928
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.874030114
Short name T9
Test name
Test status
Simulation time 131942771 ps
CPU time 2.07 seconds
Started Jul 28 07:36:27 PM PDT 24
Finished Jul 28 07:36:29 PM PDT 24
Peak memory 222532 kb
Host smart-c8baac99-9ef0-41f1-8846-1b8fac8ee86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874030114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.874030114
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2186924101
Short name T84
Test name
Test status
Simulation time 254486686 ps
CPU time 4.17 seconds
Started Jul 28 07:36:06 PM PDT 24
Finished Jul 28 07:36:10 PM PDT 24
Peak memory 215236 kb
Host smart-c6fd61ad-985e-40ee-a836-eaae92cdf65e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2186924101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2186924101
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.968522279
Short name T117
Test name
Test status
Simulation time 1637049985 ps
CPU time 8.49 seconds
Started Jul 28 07:25:16 PM PDT 24
Finished Jul 28 07:25:25 PM PDT 24
Peak memory 214172 kb
Host smart-6b049d50-df3b-4b91-bc9f-1e037e02478e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968522279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.968522279
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.36945822
Short name T51
Test name
Test status
Simulation time 1269554740 ps
CPU time 45.89 seconds
Started Jul 28 07:37:08 PM PDT 24
Finished Jul 28 07:37:54 PM PDT 24
Peak memory 222232 kb
Host smart-e053cd3a-609c-4ba4-825c-9265e2b0024c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36945822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.36945822
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2956789069
Short name T322
Test name
Test status
Simulation time 323474943 ps
CPU time 18.83 seconds
Started Jul 28 07:37:08 PM PDT 24
Finished Jul 28 07:37:27 PM PDT 24
Peak memory 214532 kb
Host smart-2efd7f90-2b34-4f49-9dc8-0c9dd33c6334
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2956789069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2956789069
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.2373487768
Short name T113
Test name
Test status
Simulation time 2387295374 ps
CPU time 13.77 seconds
Started Jul 28 07:35:42 PM PDT 24
Finished Jul 28 07:35:55 PM PDT 24
Peak memory 221676 kb
Host smart-019a5648-5628-4ce1-9085-0ef0c9678c61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373487768 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.2373487768
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2015023790
Short name T5
Test name
Test status
Simulation time 409485777 ps
CPU time 4.46 seconds
Started Jul 28 07:37:22 PM PDT 24
Finished Jul 28 07:37:26 PM PDT 24
Peak memory 214768 kb
Host smart-08c86875-c23b-4dff-a1b7-7eb2ef1beecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015023790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2015023790
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.204050881
Short name T364
Test name
Test status
Simulation time 162661294 ps
CPU time 8.65 seconds
Started Jul 28 07:35:52 PM PDT 24
Finished Jul 28 07:36:01 PM PDT 24
Peak memory 214596 kb
Host smart-ec0dab75-0122-49d1-b22b-7484174d2a65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=204050881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.204050881
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.2601540515
Short name T15
Test name
Test status
Simulation time 265884723 ps
CPU time 5.3 seconds
Started Jul 28 07:37:54 PM PDT 24
Finished Jul 28 07:37:59 PM PDT 24
Peak memory 210964 kb
Host smart-085197a5-a014-4d54-9604-82cc6b3c7ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601540515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.2601540515
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1098216008
Short name T230
Test name
Test status
Simulation time 152853821 ps
CPU time 7.23 seconds
Started Jul 28 07:35:31 PM PDT 24
Finished Jul 28 07:35:38 PM PDT 24
Peak memory 214332 kb
Host smart-83fb6706-e55d-43c4-96a9-aebf714602c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1098216008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1098216008
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.4037295756
Short name T60
Test name
Test status
Simulation time 1340760595 ps
CPU time 52.47 seconds
Started Jul 28 07:37:19 PM PDT 24
Finished Jul 28 07:38:12 PM PDT 24
Peak memory 222316 kb
Host smart-24d7be2e-abee-4968-8d3a-11efa5c39acc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037295756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.4037295756
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3100051566
Short name T409
Test name
Test status
Simulation time 485381700 ps
CPU time 13.93 seconds
Started Jul 28 07:37:10 PM PDT 24
Finished Jul 28 07:37:24 PM PDT 24
Peak memory 215208 kb
Host smart-19c30f22-2a29-478c-a860-89df44b474a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3100051566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3100051566
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2463566517
Short name T50
Test name
Test status
Simulation time 151462496 ps
CPU time 6.34 seconds
Started Jul 28 07:37:30 PM PDT 24
Finished Jul 28 07:37:37 PM PDT 24
Peak memory 214088 kb
Host smart-05a280e2-0352-4b2d-84df-976676489e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463566517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2463566517
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1030592239
Short name T22
Test name
Test status
Simulation time 121828988 ps
CPU time 3.32 seconds
Started Jul 28 07:36:10 PM PDT 24
Finished Jul 28 07:36:14 PM PDT 24
Peak memory 216148 kb
Host smart-56505eb4-c4b4-4904-ad91-c04d1a38047e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030592239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1030592239
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.4201243067
Short name T92
Test name
Test status
Simulation time 1861219575 ps
CPU time 24.74 seconds
Started Jul 28 07:37:00 PM PDT 24
Finished Jul 28 07:37:24 PM PDT 24
Peak memory 222300 kb
Host smart-eb747a0a-340d-4f4c-8efb-4a2446ae53e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201243067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.4201243067
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1472095064
Short name T145
Test name
Test status
Simulation time 1259303363 ps
CPU time 10.09 seconds
Started Jul 28 07:36:51 PM PDT 24
Finished Jul 28 07:37:01 PM PDT 24
Peak memory 222576 kb
Host smart-b6639305-a3a9-4ccf-9ea8-927c03fc060e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472095064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1472095064
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.260042201
Short name T33
Test name
Test status
Simulation time 1865004442 ps
CPU time 27.31 seconds
Started Jul 28 07:36:14 PM PDT 24
Finished Jul 28 07:36:42 PM PDT 24
Peak memory 222236 kb
Host smart-da8ec172-5a1d-4088-843b-d06e8eebf96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260042201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.260042201
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3964708918
Short name T411
Test name
Test status
Simulation time 165990006 ps
CPU time 9.16 seconds
Started Jul 28 07:35:59 PM PDT 24
Finished Jul 28 07:36:08 PM PDT 24
Peak memory 215392 kb
Host smart-c52fbd76-b3a8-4eda-b011-2d1e27659f84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3964708918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3964708918
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2162588507
Short name T68
Test name
Test status
Simulation time 12492935710 ps
CPU time 45.88 seconds
Started Jul 28 07:36:31 PM PDT 24
Finished Jul 28 07:37:17 PM PDT 24
Peak memory 222216 kb
Host smart-6c55e63a-0dad-4e42-8f3b-c04aec228c15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162588507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2162588507
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3014780750
Short name T264
Test name
Test status
Simulation time 1052804176 ps
CPU time 11.72 seconds
Started Jul 28 07:37:51 PM PDT 24
Finished Jul 28 07:38:03 PM PDT 24
Peak memory 214148 kb
Host smart-cc1854ad-09c9-48bb-9972-c0f8db0bbcb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3014780750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3014780750
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.3827779125
Short name T62
Test name
Test status
Simulation time 335607620 ps
CPU time 13.3 seconds
Started Jul 28 07:36:46 PM PDT 24
Finished Jul 28 07:37:00 PM PDT 24
Peak memory 222284 kb
Host smart-4bd99060-a305-4d73-a35b-24755d5ea269
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827779125 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.3827779125
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2636957092
Short name T996
Test name
Test status
Simulation time 169355269 ps
CPU time 2.32 seconds
Started Jul 28 07:25:13 PM PDT 24
Finished Jul 28 07:25:16 PM PDT 24
Peak memory 214228 kb
Host smart-fdc044d5-4b94-4876-9f0f-2f4f2f1b70bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636957092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2636957092
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2952037812
Short name T103
Test name
Test status
Simulation time 9220109781 ps
CPU time 20.15 seconds
Started Jul 28 07:37:21 PM PDT 24
Finished Jul 28 07:37:41 PM PDT 24
Peak memory 216232 kb
Host smart-4af35e07-24fd-4179-be13-4a1dfd96637b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952037812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2952037812
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.745501971
Short name T385
Test name
Test status
Simulation time 146387534 ps
CPU time 7.55 seconds
Started Jul 28 07:37:14 PM PDT 24
Finished Jul 28 07:37:22 PM PDT 24
Peak memory 214264 kb
Host smart-2ded4cd2-e46b-4542-85c8-db7ef87ea49b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=745501971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.745501971
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1289446450
Short name T99
Test name
Test status
Simulation time 1125381920 ps
CPU time 6.44 seconds
Started Jul 28 07:37:05 PM PDT 24
Finished Jul 28 07:37:11 PM PDT 24
Peak memory 222216 kb
Host smart-cdb3f1b8-97b2-4324-bf9d-16fa56b5eda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289446450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1289446450
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1811991824
Short name T69
Test name
Test status
Simulation time 3690115910 ps
CPU time 37.95 seconds
Started Jul 28 07:35:38 PM PDT 24
Finished Jul 28 07:36:16 PM PDT 24
Peak memory 222488 kb
Host smart-ff123263-6399-43fe-ae75-edbf3ab781fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811991824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1811991824
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.4290817517
Short name T418
Test name
Test status
Simulation time 56001441 ps
CPU time 0.8 seconds
Started Jul 28 07:36:25 PM PDT 24
Finished Jul 28 07:36:25 PM PDT 24
Peak memory 205848 kb
Host smart-5dbeda41-ae86-44e0-8df2-5fff8ddbeaca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290817517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.4290817517
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.804402347
Short name T171
Test name
Test status
Simulation time 304532532 ps
CPU time 8.11 seconds
Started Jul 28 07:25:40 PM PDT 24
Finished Jul 28 07:25:48 PM PDT 24
Peak memory 216316 kb
Host smart-6c3048ba-a963-4125-aa18-39c330003b71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804402347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.804402347
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3081134239
Short name T277
Test name
Test status
Simulation time 1706699221 ps
CPU time 90.27 seconds
Started Jul 28 07:37:06 PM PDT 24
Finished Jul 28 07:38:36 PM PDT 24
Peak memory 217184 kb
Host smart-550c92fe-ea2e-436e-9d0a-bc2af70d2ff1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3081134239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3081134239
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2874939851
Short name T89
Test name
Test status
Simulation time 96891429 ps
CPU time 1.83 seconds
Started Jul 28 07:37:40 PM PDT 24
Finished Jul 28 07:37:42 PM PDT 24
Peak memory 214428 kb
Host smart-9b2908fe-4250-44e7-afcb-35142d334c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874939851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2874939851
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.793394836
Short name T128
Test name
Test status
Simulation time 1256246439 ps
CPU time 24.48 seconds
Started Jul 28 07:36:30 PM PDT 24
Finished Jul 28 07:36:54 PM PDT 24
Peak memory 222816 kb
Host smart-f35c5064-4ec8-4288-a074-48f3ebbe6935
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793394836 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.793394836
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1603999737
Short name T63
Test name
Test status
Simulation time 233848064 ps
CPU time 2.82 seconds
Started Jul 28 07:36:40 PM PDT 24
Finished Jul 28 07:36:43 PM PDT 24
Peak memory 210212 kb
Host smart-10bb3a19-3dc5-4f38-936e-22ded827e838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603999737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1603999737
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2626507308
Short name T286
Test name
Test status
Simulation time 195909212 ps
CPU time 10.78 seconds
Started Jul 28 07:35:37 PM PDT 24
Finished Jul 28 07:35:48 PM PDT 24
Peak memory 214196 kb
Host smart-443f9aff-15cb-44da-b122-98a8b41fd7e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2626507308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2626507308
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2445305137
Short name T212
Test name
Test status
Simulation time 47294140 ps
CPU time 2.89 seconds
Started Jul 28 07:37:25 PM PDT 24
Finished Jul 28 07:37:28 PM PDT 24
Peak memory 210012 kb
Host smart-084f9099-f9a3-44f4-907d-41bfa986bc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445305137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2445305137
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2238883690
Short name T119
Test name
Test status
Simulation time 368417002 ps
CPU time 6.65 seconds
Started Jul 28 07:25:11 PM PDT 24
Finished Jul 28 07:25:18 PM PDT 24
Peak memory 214180 kb
Host smart-8520aed8-4a6a-47eb-861b-cef671932df7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238883690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.2238883690
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3970841007
Short name T77
Test name
Test status
Simulation time 1922727471 ps
CPU time 27.76 seconds
Started Jul 28 07:37:23 PM PDT 24
Finished Jul 28 07:37:51 PM PDT 24
Peak memory 222220 kb
Host smart-b2e196a6-b9ba-41cc-8fa9-311d8f3c2953
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970841007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3970841007
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2304222958
Short name T223
Test name
Test status
Simulation time 684708187 ps
CPU time 28.73 seconds
Started Jul 28 07:37:38 PM PDT 24
Finished Jul 28 07:38:07 PM PDT 24
Peak memory 216332 kb
Host smart-acb04e3e-5470-4eb0-8b25-fe10bc71d3df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304222958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2304222958
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2264542780
Short name T160
Test name
Test status
Simulation time 236572930 ps
CPU time 6.45 seconds
Started Jul 28 07:25:12 PM PDT 24
Finished Jul 28 07:25:18 PM PDT 24
Peak memory 213900 kb
Host smart-9021768b-9435-4619-b734-0c4b8af09c13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264542780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2264542780
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2838960991
Short name T163
Test name
Test status
Simulation time 846779818 ps
CPU time 5.68 seconds
Started Jul 28 07:25:15 PM PDT 24
Finished Jul 28 07:25:21 PM PDT 24
Peak memory 213948 kb
Host smart-7548a9dd-ed4d-4a4c-9d23-4dd6032ab567
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838960991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2838960991
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.407525596
Short name T88
Test name
Test status
Simulation time 80736824 ps
CPU time 2.9 seconds
Started Jul 28 07:36:32 PM PDT 24
Finished Jul 28 07:36:35 PM PDT 24
Peak memory 214176 kb
Host smart-bffdf986-aeb6-4418-91e1-1a5c9fa8349d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407525596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.407525596
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.737726083
Short name T90
Test name
Test status
Simulation time 169076758 ps
CPU time 3.92 seconds
Started Jul 28 07:37:00 PM PDT 24
Finished Jul 28 07:37:04 PM PDT 24
Peak memory 222188 kb
Host smart-b25ada35-a332-468e-9b43-e2a8c51b60ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737726083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.737726083
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.889106779
Short name T284
Test name
Test status
Simulation time 89695692 ps
CPU time 1.78 seconds
Started Jul 28 07:37:46 PM PDT 24
Finished Jul 28 07:37:48 PM PDT 24
Peak memory 214072 kb
Host smart-cde69f38-e97e-4ba7-9a9c-880ea485a984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889106779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.889106779
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.4252554179
Short name T216
Test name
Test status
Simulation time 35288511415 ps
CPU time 222.62 seconds
Started Jul 28 07:37:52 PM PDT 24
Finished Jul 28 07:41:34 PM PDT 24
Peak memory 222308 kb
Host smart-4fabe3d1-fee3-43c7-8c38-c55b30a1ec07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252554179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.4252554179
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1773071365
Short name T157
Test name
Test status
Simulation time 408664204 ps
CPU time 6.38 seconds
Started Jul 28 07:25:42 PM PDT 24
Finished Jul 28 07:25:48 PM PDT 24
Peak memory 213956 kb
Host smart-b8fd27d8-4afe-43d7-a318-fb841f1d94fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773071365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1773071365
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2535905345
Short name T167
Test name
Test status
Simulation time 94159422 ps
CPU time 2.51 seconds
Started Jul 28 07:25:45 PM PDT 24
Finished Jul 28 07:25:47 PM PDT 24
Peak memory 213916 kb
Host smart-f469028c-633e-4b5d-a159-0b50483d3d9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535905345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2535905345
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1278695438
Short name T178
Test name
Test status
Simulation time 206545892 ps
CPU time 5.19 seconds
Started Jul 28 07:35:31 PM PDT 24
Finished Jul 28 07:35:36 PM PDT 24
Peak memory 222320 kb
Host smart-0307d881-bebb-42eb-8357-60a4834d4be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278695438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1278695438
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.4237252697
Short name T177
Test name
Test status
Simulation time 2841719374 ps
CPU time 5.45 seconds
Started Jul 28 07:36:38 PM PDT 24
Finished Jul 28 07:36:43 PM PDT 24
Peak memory 218408 kb
Host smart-29c14047-4b76-4984-bbf9-e37202bd85c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237252697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.4237252697
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3250261374
Short name T108
Test name
Test status
Simulation time 7651805246 ps
CPU time 78.27 seconds
Started Jul 28 07:35:28 PM PDT 24
Finished Jul 28 07:36:46 PM PDT 24
Peak memory 216212 kb
Host smart-cf8e8f80-d2de-4475-b121-497935c1c68c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250261374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3250261374
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3229904017
Short name T337
Test name
Test status
Simulation time 122043859 ps
CPU time 2.07 seconds
Started Jul 28 07:35:28 PM PDT 24
Finished Jul 28 07:35:30 PM PDT 24
Peak memory 208416 kb
Host smart-8047b55b-d0c0-465d-a0ea-91aed758ca7a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229904017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3229904017
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3367987019
Short name T388
Test name
Test status
Simulation time 407618490 ps
CPU time 5.67 seconds
Started Jul 28 07:36:28 PM PDT 24
Finished Jul 28 07:36:34 PM PDT 24
Peak memory 214276 kb
Host smart-91e3eac1-5ff0-40e7-a299-1a05a432d444
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3367987019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3367987019
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2583992774
Short name T360
Test name
Test status
Simulation time 94296574 ps
CPU time 5.55 seconds
Started Jul 28 07:36:52 PM PDT 24
Finished Jul 28 07:36:57 PM PDT 24
Peak memory 215344 kb
Host smart-e19ab2ad-3f49-4dcf-b5e6-e0cd9dc0eb6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2583992774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2583992774
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3472774423
Short name T333
Test name
Test status
Simulation time 165289976 ps
CPU time 3.14 seconds
Started Jul 28 07:36:59 PM PDT 24
Finished Jul 28 07:37:03 PM PDT 24
Peak memory 214024 kb
Host smart-0a5bc0ec-1cde-45bd-8c5a-268b10474c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472774423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3472774423
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.4047513606
Short name T244
Test name
Test status
Simulation time 78001407 ps
CPU time 2.64 seconds
Started Jul 28 07:37:10 PM PDT 24
Finished Jul 28 07:37:13 PM PDT 24
Peak memory 214100 kb
Host smart-438b9395-ebc4-4426-9c42-d869cf301015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047513606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.4047513606
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3690902824
Short name T206
Test name
Test status
Simulation time 1536481828 ps
CPU time 30.69 seconds
Started Jul 28 07:37:50 PM PDT 24
Finished Jul 28 07:38:21 PM PDT 24
Peak memory 222328 kb
Host smart-52203543-1626-4b92-b647-e85390264684
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690902824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3690902824
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.1753156641
Short name T38
Test name
Test status
Simulation time 78907414 ps
CPU time 1.62 seconds
Started Jul 28 07:35:59 PM PDT 24
Finished Jul 28 07:36:01 PM PDT 24
Peak memory 209484 kb
Host smart-ade3fe5c-80ed-4db7-a2fa-580a49a0aea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753156641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1753156641
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.1525446161
Short name T180
Test name
Test status
Simulation time 154405305 ps
CPU time 3.53 seconds
Started Jul 28 07:37:38 PM PDT 24
Finished Jul 28 07:37:42 PM PDT 24
Peak memory 222496 kb
Host smart-f0205890-8768-487b-a42d-495c7e6280f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525446161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1525446161
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2223215025
Short name T175
Test name
Test status
Simulation time 380167124 ps
CPU time 2.65 seconds
Started Jul 28 07:36:09 PM PDT 24
Finished Jul 28 07:36:12 PM PDT 24
Peak memory 217576 kb
Host smart-05c1cc50-8cef-4f51-bbff-308c0d08013e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223215025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2223215025
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.137456587
Short name T326
Test name
Test status
Simulation time 283242155 ps
CPU time 4.23 seconds
Started Jul 28 07:36:07 PM PDT 24
Finished Jul 28 07:36:12 PM PDT 24
Peak memory 208024 kb
Host smart-af1dd7bb-eb35-4928-8710-53f21906ebe1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137456587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.137456587
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1802911860
Short name T296
Test name
Test status
Simulation time 411096550 ps
CPU time 22.11 seconds
Started Jul 28 07:36:00 PM PDT 24
Finished Jul 28 07:36:22 PM PDT 24
Peak memory 222332 kb
Host smart-f3004b72-8ee6-46fd-bf96-65d630f4ccb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802911860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1802911860
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.4076731927
Short name T314
Test name
Test status
Simulation time 116543082 ps
CPU time 2.09 seconds
Started Jul 28 07:36:18 PM PDT 24
Finished Jul 28 07:36:20 PM PDT 24
Peak memory 213952 kb
Host smart-891a5679-c3fb-4092-89a9-4dcfb0a72e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076731927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.4076731927
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1360852328
Short name T356
Test name
Test status
Simulation time 60503879 ps
CPU time 2.29 seconds
Started Jul 28 07:36:49 PM PDT 24
Finished Jul 28 07:36:51 PM PDT 24
Peak memory 214080 kb
Host smart-e537f478-8e15-4c42-99ee-aba00808b73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360852328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1360852328
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.841337879
Short name T229
Test name
Test status
Simulation time 1776944308 ps
CPU time 6.22 seconds
Started Jul 28 07:37:05 PM PDT 24
Finished Jul 28 07:37:11 PM PDT 24
Peak memory 222152 kb
Host smart-48e43cf5-5a88-4f83-aaf0-de466ead4eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841337879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.841337879
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3554124349
Short name T153
Test name
Test status
Simulation time 52861609 ps
CPU time 4.07 seconds
Started Jul 28 07:37:29 PM PDT 24
Finished Jul 28 07:37:33 PM PDT 24
Peak memory 214156 kb
Host smart-424c01e9-403f-4f85-b610-1827ef600bd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3554124349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3554124349
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1705458795
Short name T218
Test name
Test status
Simulation time 161265422 ps
CPU time 3.88 seconds
Started Jul 28 07:37:41 PM PDT 24
Finished Jul 28 07:37:45 PM PDT 24
Peak memory 208848 kb
Host smart-e1a454a6-3462-4b2a-858b-8746b0e7d9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705458795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1705458795
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2046307743
Short name T339
Test name
Test status
Simulation time 661445586 ps
CPU time 6.09 seconds
Started Jul 28 07:35:56 PM PDT 24
Finished Jul 28 07:36:02 PM PDT 24
Peak memory 214124 kb
Host smart-4bd71647-c374-447f-8f28-7a2fec76ed0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046307743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2046307743
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3076259691
Short name T170
Test name
Test status
Simulation time 506943684 ps
CPU time 5.5 seconds
Started Jul 28 07:25:55 PM PDT 24
Finished Jul 28 07:26:01 PM PDT 24
Peak memory 213920 kb
Host smart-9ef3b29c-23ca-4510-b845-5e7712e004e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076259691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3076259691
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1098442994
Short name T168
Test name
Test status
Simulation time 198934681 ps
CPU time 2.76 seconds
Started Jul 28 07:36:19 PM PDT 24
Finished Jul 28 07:36:22 PM PDT 24
Peak memory 209736 kb
Host smart-61ecffe5-9cd3-45ca-9121-2d37da0f554d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098442994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1098442994
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.801893400
Short name T164
Test name
Test status
Simulation time 90270897 ps
CPU time 2.93 seconds
Started Jul 28 07:35:46 PM PDT 24
Finished Jul 28 07:35:49 PM PDT 24
Peak memory 210352 kb
Host smart-d005efa9-1fa1-44f4-9aaf-fd38085da8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801893400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.801893400
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.1109840070
Short name T54
Test name
Test status
Simulation time 86172994 ps
CPU time 3.1 seconds
Started Jul 28 07:35:57 PM PDT 24
Finished Jul 28 07:36:01 PM PDT 24
Peak memory 222512 kb
Host smart-b73b1c65-1319-44bc-bb37-51516c38d046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109840070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.1109840070
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.4005238128
Short name T302
Test name
Test status
Simulation time 761598062 ps
CPU time 11.18 seconds
Started Jul 28 07:35:28 PM PDT 24
Finished Jul 28 07:35:40 PM PDT 24
Peak memory 222280 kb
Host smart-c2dd731c-c167-4030-8dbc-f20cf2daaafa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005238128 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.4005238128
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3477734258
Short name T384
Test name
Test status
Simulation time 78350756 ps
CPU time 5.37 seconds
Started Jul 28 07:35:59 PM PDT 24
Finished Jul 28 07:36:05 PM PDT 24
Peak memory 222404 kb
Host smart-c9d1ed6e-f9ef-4ef3-ad3d-b7d245ad3c12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3477734258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3477734258
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1976026164
Short name T220
Test name
Test status
Simulation time 350723039 ps
CPU time 2.38 seconds
Started Jul 28 07:36:02 PM PDT 24
Finished Jul 28 07:36:04 PM PDT 24
Peak memory 208016 kb
Host smart-4f4ef8b4-4012-40ea-a71d-3657a026fd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976026164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1976026164
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_sideload.426972940
Short name T666
Test name
Test status
Simulation time 120824519 ps
CPU time 3.3 seconds
Started Jul 28 07:36:07 PM PDT 24
Finished Jul 28 07:36:10 PM PDT 24
Peak memory 208596 kb
Host smart-c06ffd54-4750-41cc-b785-2f0ee84eb717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426972940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.426972940
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1497450091
Short name T347
Test name
Test status
Simulation time 1802549281 ps
CPU time 34.41 seconds
Started Jul 28 07:36:05 PM PDT 24
Finished Jul 28 07:36:39 PM PDT 24
Peak memory 215364 kb
Host smart-830fe7f1-1619-4666-9cfc-51be302daa83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497450091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1497450091
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1931409953
Short name T310
Test name
Test status
Simulation time 767986254 ps
CPU time 5.04 seconds
Started Jul 28 07:36:23 PM PDT 24
Finished Jul 28 07:36:28 PM PDT 24
Peak memory 214232 kb
Host smart-2cd9a511-abe6-47a2-916d-020b1cc5ac77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1931409953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1931409953
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.721817438
Short name T912
Test name
Test status
Simulation time 923811376 ps
CPU time 5.95 seconds
Started Jul 28 07:36:30 PM PDT 24
Finished Jul 28 07:36:36 PM PDT 24
Peak memory 215252 kb
Host smart-21a85e64-c1ec-458f-8744-71b442fe4161
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=721817438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.721817438
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1402782653
Short name T208
Test name
Test status
Simulation time 117029065 ps
CPU time 4.16 seconds
Started Jul 28 07:36:26 PM PDT 24
Finished Jul 28 07:36:30 PM PDT 24
Peak memory 209448 kb
Host smart-6056fb36-fed4-4aa2-a2a8-dce2a0967393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402782653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1402782653
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.2343801898
Short name T140
Test name
Test status
Simulation time 3100707940 ps
CPU time 30.09 seconds
Started Jul 28 07:36:28 PM PDT 24
Finished Jul 28 07:36:58 PM PDT 24
Peak memory 220884 kb
Host smart-465d72f3-4e36-4fe8-9ce7-d1b908ff8ba6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343801898 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.2343801898
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2072819239
Short name T369
Test name
Test status
Simulation time 222570896 ps
CPU time 5.87 seconds
Started Jul 28 07:36:31 PM PDT 24
Finished Jul 28 07:36:37 PM PDT 24
Peak memory 214044 kb
Host smart-ff4efa6b-7a6a-46cd-8dd8-1e8a1f0110b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072819239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2072819239
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1828067579
Short name T93
Test name
Test status
Simulation time 302437336 ps
CPU time 4.01 seconds
Started Jul 28 07:35:31 PM PDT 24
Finished Jul 28 07:35:35 PM PDT 24
Peak memory 214128 kb
Host smart-d571cc82-a54f-4d62-a32b-3a8c9ffae519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828067579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1828067579
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2734946203
Short name T373
Test name
Test status
Simulation time 524405496 ps
CPU time 4.74 seconds
Started Jul 28 07:35:37 PM PDT 24
Finished Jul 28 07:35:42 PM PDT 24
Peak memory 222268 kb
Host smart-466d2daf-5ea1-4f33-b948-156b250cf064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734946203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2734946203
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1567433227
Short name T196
Test name
Test status
Simulation time 444873011 ps
CPU time 9.21 seconds
Started Jul 28 07:35:36 PM PDT 24
Finished Jul 28 07:35:45 PM PDT 24
Peak memory 219516 kb
Host smart-abeb3075-f797-4475-bc69-1c6b362b639b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567433227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1567433227
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1456449768
Short name T405
Test name
Test status
Simulation time 56308680 ps
CPU time 3.89 seconds
Started Jul 28 07:36:31 PM PDT 24
Finished Jul 28 07:36:35 PM PDT 24
Peak memory 214136 kb
Host smart-6e92576a-5141-4dfb-a3c1-1dc66ea0b084
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1456449768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1456449768
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2660759487
Short name T67
Test name
Test status
Simulation time 2646513977 ps
CPU time 31.45 seconds
Started Jul 28 07:36:38 PM PDT 24
Finished Jul 28 07:37:09 PM PDT 24
Peak memory 222360 kb
Host smart-4344fbe4-f85a-47da-b9ec-e45f8d0de7ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660759487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2660759487
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.4171204226
Short name T225
Test name
Test status
Simulation time 821183254 ps
CPU time 5.3 seconds
Started Jul 28 07:36:51 PM PDT 24
Finished Jul 28 07:36:56 PM PDT 24
Peak memory 220148 kb
Host smart-08204ee4-8e87-4129-8f3c-63268e48e8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171204226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.4171204226
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3013920608
Short name T256
Test name
Test status
Simulation time 21281173454 ps
CPU time 625.19 seconds
Started Jul 28 07:37:28 PM PDT 24
Finished Jul 28 07:47:54 PM PDT 24
Peak memory 221892 kb
Host smart-f07d5ea7-9ace-4f6d-a496-3e7079a32cde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013920608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3013920608
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.767228078
Short name T52
Test name
Test status
Simulation time 247666005 ps
CPU time 10.62 seconds
Started Jul 28 07:37:33 PM PDT 24
Finished Jul 28 07:37:44 PM PDT 24
Peak memory 220488 kb
Host smart-f053d5af-b240-4039-b601-09f662773c66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767228078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.767228078
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.805768564
Short name T358
Test name
Test status
Simulation time 168271494 ps
CPU time 5.01 seconds
Started Jul 28 07:37:37 PM PDT 24
Finished Jul 28 07:37:42 PM PDT 24
Peak memory 214848 kb
Host smart-d2a4659f-7e3d-4c8b-a5bc-f258abd1df3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=805768564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.805768564
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2382529547
Short name T317
Test name
Test status
Simulation time 291727410 ps
CPU time 1.95 seconds
Started Jul 28 07:37:50 PM PDT 24
Finished Jul 28 07:37:52 PM PDT 24
Peak memory 214124 kb
Host smart-126610ac-0f69-4142-a008-8a1d18a132f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382529547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2382529547
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.915088921
Short name T1079
Test name
Test status
Simulation time 458602224 ps
CPU time 15.6 seconds
Started Jul 28 07:25:10 PM PDT 24
Finished Jul 28 07:25:26 PM PDT 24
Peak memory 205752 kb
Host smart-2565a0a7-fb1f-4a2b-8b24-2c3258f7b424
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915088921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.915088921
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1833016408
Short name T1026
Test name
Test status
Simulation time 1968426630 ps
CPU time 7.52 seconds
Started Jul 28 07:25:13 PM PDT 24
Finished Jul 28 07:25:21 PM PDT 24
Peak memory 205688 kb
Host smart-3d233610-a608-47f7-8101-bce48310f3ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833016408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
833016408
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1250887354
Short name T939
Test name
Test status
Simulation time 18603083 ps
CPU time 1.31 seconds
Started Jul 28 07:25:17 PM PDT 24
Finished Jul 28 07:25:18 PM PDT 24
Peak memory 205700 kb
Host smart-cd8059de-d0b2-4ec4-9cd8-3fa758fc04e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250887354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
250887354
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3242486116
Short name T982
Test name
Test status
Simulation time 31988582 ps
CPU time 1.61 seconds
Started Jul 28 07:25:13 PM PDT 24
Finished Jul 28 07:25:14 PM PDT 24
Peak memory 213940 kb
Host smart-0fea6280-c963-4115-84c8-d1caaea7b493
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242486116 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3242486116
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.902828049
Short name T382
Test name
Test status
Simulation time 18636251 ps
CPU time 0.9 seconds
Started Jul 28 07:25:10 PM PDT 24
Finished Jul 28 07:25:11 PM PDT 24
Peak memory 205572 kb
Host smart-4f14e4dd-0366-45a6-ba25-4a359fa40c33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902828049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.902828049
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2002700342
Short name T960
Test name
Test status
Simulation time 25904762 ps
CPU time 0.89 seconds
Started Jul 28 07:25:17 PM PDT 24
Finished Jul 28 07:25:18 PM PDT 24
Peak memory 205664 kb
Host smart-c4787aef-f188-4a08-ada5-959df16c1b94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002700342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2002700342
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3546307453
Short name T152
Test name
Test status
Simulation time 74528217 ps
CPU time 1.27 seconds
Started Jul 28 07:25:14 PM PDT 24
Finished Jul 28 07:25:15 PM PDT 24
Peak memory 205716 kb
Host smart-8d3dfd06-c990-491c-8f12-fe1bbd14e69e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546307453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3546307453
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1990860265
Short name T126
Test name
Test status
Simulation time 172194004 ps
CPU time 2.74 seconds
Started Jul 28 07:25:08 PM PDT 24
Finished Jul 28 07:25:11 PM PDT 24
Peak memory 214152 kb
Host smart-43d9af68-7bfd-4171-adde-7073e5d7108b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990860265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1990860265
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3164272449
Short name T1050
Test name
Test status
Simulation time 356492067 ps
CPU time 2.5 seconds
Started Jul 28 07:25:11 PM PDT 24
Finished Jul 28 07:25:14 PM PDT 24
Peak memory 213936 kb
Host smart-3e60903c-85e8-4473-bbad-e51ee9d408ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164272449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3164272449
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3594969061
Short name T1069
Test name
Test status
Simulation time 367125495 ps
CPU time 14.06 seconds
Started Jul 28 07:25:12 PM PDT 24
Finished Jul 28 07:25:26 PM PDT 24
Peak memory 205752 kb
Host smart-d77ff2e5-2525-4983-8352-f6df01525cda
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594969061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
594969061
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2353580627
Short name T938
Test name
Test status
Simulation time 904587081 ps
CPU time 13.84 seconds
Started Jul 28 07:25:15 PM PDT 24
Finished Jul 28 07:25:29 PM PDT 24
Peak memory 205736 kb
Host smart-d6df0be4-5d97-40eb-b5a4-40867d3a1b8c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353580627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
353580627
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2887766364
Short name T1009
Test name
Test status
Simulation time 87831476 ps
CPU time 1.17 seconds
Started Jul 28 07:25:13 PM PDT 24
Finished Jul 28 07:25:14 PM PDT 24
Peak memory 205968 kb
Host smart-457534a6-f25d-497e-b70e-d5273fc0a844
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887766364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
887766364
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.95945668
Short name T1043
Test name
Test status
Simulation time 42558662 ps
CPU time 1.63 seconds
Started Jul 28 07:25:12 PM PDT 24
Finished Jul 28 07:25:14 PM PDT 24
Peak memory 219424 kb
Host smart-8e278da9-3fd1-44a9-b948-8785921f7378
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95945668 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.95945668
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1076381113
Short name T1031
Test name
Test status
Simulation time 53571863 ps
CPU time 1.13 seconds
Started Jul 28 07:25:09 PM PDT 24
Finished Jul 28 07:25:10 PM PDT 24
Peak memory 205664 kb
Host smart-06cd9385-e7b2-4306-a3ec-9cf9d568ddd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076381113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1076381113
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1216838963
Short name T991
Test name
Test status
Simulation time 32207432 ps
CPU time 0.74 seconds
Started Jul 28 07:25:10 PM PDT 24
Finished Jul 28 07:25:10 PM PDT 24
Peak memory 205572 kb
Host smart-d70b1e51-ce46-4d12-bad4-888ef5da9b6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216838963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1216838963
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.52794113
Short name T988
Test name
Test status
Simulation time 159731649 ps
CPU time 1.77 seconds
Started Jul 28 07:25:13 PM PDT 24
Finished Jul 28 07:25:15 PM PDT 24
Peak memory 205920 kb
Host smart-3ee7d02c-7825-4984-b7c5-5d64b0935f20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52794113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_same
_csr_outstanding.52794113
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.287550105
Short name T116
Test name
Test status
Simulation time 392055014 ps
CPU time 13.49 seconds
Started Jul 28 07:25:11 PM PDT 24
Finished Jul 28 07:25:25 PM PDT 24
Peak memory 220884 kb
Host smart-2a49c085-e54e-4fdb-b9f2-185bd6f00400
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287550105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.287550105
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3146357768
Short name T953
Test name
Test status
Simulation time 21133079 ps
CPU time 1.58 seconds
Started Jul 28 07:25:15 PM PDT 24
Finished Jul 28 07:25:17 PM PDT 24
Peak memory 214924 kb
Host smart-dbf4f7fd-a4ea-47ef-9b27-e4be588aaf88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146357768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3146357768
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.612204447
Short name T962
Test name
Test status
Simulation time 192762962 ps
CPU time 3.12 seconds
Started Jul 28 07:25:12 PM PDT 24
Finished Jul 28 07:25:15 PM PDT 24
Peak memory 213844 kb
Host smart-85831701-c81e-4cf7-b1bc-b366c9be3e9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612204447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
612204447
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.755624647
Short name T1012
Test name
Test status
Simulation time 87043718 ps
CPU time 2.38 seconds
Started Jul 28 07:25:35 PM PDT 24
Finished Jul 28 07:25:37 PM PDT 24
Peak memory 213968 kb
Host smart-cbf2e7d7-5456-44aa-81e1-580391f48bd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755624647 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.755624647
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2670505112
Short name T919
Test name
Test status
Simulation time 33485607 ps
CPU time 1.61 seconds
Started Jul 28 07:25:31 PM PDT 24
Finished Jul 28 07:25:33 PM PDT 24
Peak memory 205744 kb
Host smart-5ada51d5-c9f6-445a-ac78-ec98516ade59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670505112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2670505112
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1075505276
Short name T1047
Test name
Test status
Simulation time 25161361 ps
CPU time 0.88 seconds
Started Jul 28 07:25:31 PM PDT 24
Finished Jul 28 07:25:32 PM PDT 24
Peak memory 205536 kb
Host smart-090e6daf-7377-42f0-be01-357d2b2f88b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075505276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1075505276
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1321642137
Short name T992
Test name
Test status
Simulation time 74916105 ps
CPU time 1.59 seconds
Started Jul 28 07:25:31 PM PDT 24
Finished Jul 28 07:25:33 PM PDT 24
Peak memory 205736 kb
Host smart-10dda4a4-58b7-49da-8510-2b852e73b5e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321642137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1321642137
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.4200354161
Short name T1014
Test name
Test status
Simulation time 399982904 ps
CPU time 3.4 seconds
Started Jul 28 07:25:33 PM PDT 24
Finished Jul 28 07:25:36 PM PDT 24
Peak memory 214164 kb
Host smart-4f5dc30e-33df-452a-a68c-cd7f30d5b7fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200354161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.4200354161
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3345193170
Short name T1037
Test name
Test status
Simulation time 412424515 ps
CPU time 14.75 seconds
Started Jul 28 07:25:33 PM PDT 24
Finished Jul 28 07:25:48 PM PDT 24
Peak memory 214208 kb
Host smart-0b5cd23b-6d71-4f0d-b2df-ad4219bd7743
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345193170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3345193170
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.224580483
Short name T1073
Test name
Test status
Simulation time 297528768 ps
CPU time 1.84 seconds
Started Jul 28 07:25:32 PM PDT 24
Finished Jul 28 07:25:34 PM PDT 24
Peak memory 213824 kb
Host smart-38111fa9-6eed-4d28-b352-003b6d06f5ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224580483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.224580483
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3069876137
Short name T1048
Test name
Test status
Simulation time 289817932 ps
CPU time 3.9 seconds
Started Jul 28 07:25:31 PM PDT 24
Finished Jul 28 07:25:35 PM PDT 24
Peak memory 213868 kb
Host smart-8f8f6e3f-84e8-4d4f-975f-76e77d3707e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069876137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3069876137
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3214166406
Short name T1003
Test name
Test status
Simulation time 170638595 ps
CPU time 1.82 seconds
Started Jul 28 07:25:31 PM PDT 24
Finished Jul 28 07:25:33 PM PDT 24
Peak memory 222184 kb
Host smart-62fa641f-0eb3-4e4f-9eaf-f4596f7929e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214166406 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3214166406
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2484824010
Short name T1036
Test name
Test status
Simulation time 98195205 ps
CPU time 1.14 seconds
Started Jul 28 07:25:33 PM PDT 24
Finished Jul 28 07:25:35 PM PDT 24
Peak memory 205728 kb
Host smart-b728234e-a88a-4101-93d8-e840e4007c91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484824010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2484824010
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.404255533
Short name T979
Test name
Test status
Simulation time 34798229 ps
CPU time 0.79 seconds
Started Jul 28 07:25:33 PM PDT 24
Finished Jul 28 07:25:33 PM PDT 24
Peak memory 205548 kb
Host smart-638545a4-a12f-4c70-84dd-37dc2462a6a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404255533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.404255533
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1717623752
Short name T1005
Test name
Test status
Simulation time 35910581 ps
CPU time 2.33 seconds
Started Jul 28 07:25:33 PM PDT 24
Finished Jul 28 07:25:35 PM PDT 24
Peak memory 205844 kb
Host smart-4552a69e-1ed1-4426-bc98-71c3ec47c982
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717623752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1717623752
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.992072737
Short name T1002
Test name
Test status
Simulation time 357570187 ps
CPU time 5.82 seconds
Started Jul 28 07:25:34 PM PDT 24
Finished Jul 28 07:25:40 PM PDT 24
Peak memory 214120 kb
Host smart-c6a2e6b5-dd53-42bd-ab02-bdc7bc94ae8f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992072737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.992072737
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2680569981
Short name T955
Test name
Test status
Simulation time 368705625 ps
CPU time 14.04 seconds
Started Jul 28 07:25:32 PM PDT 24
Finished Jul 28 07:25:46 PM PDT 24
Peak memory 214224 kb
Host smart-08607f51-dedf-440f-bb23-cf1c334e3253
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680569981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2680569981
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3009181128
Short name T1052
Test name
Test status
Simulation time 114372180 ps
CPU time 3.03 seconds
Started Jul 28 07:25:34 PM PDT 24
Finished Jul 28 07:25:37 PM PDT 24
Peak memory 213900 kb
Host smart-00ceed20-47c5-4661-9803-7c594cfe2178
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009181128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3009181128
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3936166668
Short name T1054
Test name
Test status
Simulation time 512875967 ps
CPU time 3.47 seconds
Started Jul 28 07:25:35 PM PDT 24
Finished Jul 28 07:25:39 PM PDT 24
Peak memory 213948 kb
Host smart-174e448e-c6e1-49da-bdaa-0939f35b80b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936166668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3936166668
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.50211550
Short name T1024
Test name
Test status
Simulation time 42899171 ps
CPU time 1.86 seconds
Started Jul 28 07:25:38 PM PDT 24
Finished Jul 28 07:25:40 PM PDT 24
Peak memory 213976 kb
Host smart-d9a4eccd-38a4-49cb-a1b5-42094bc7746d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50211550 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.50211550
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1229602347
Short name T1019
Test name
Test status
Simulation time 39577091 ps
CPU time 1.13 seconds
Started Jul 28 07:25:37 PM PDT 24
Finished Jul 28 07:25:38 PM PDT 24
Peak memory 205652 kb
Host smart-0697c651-bffb-4a94-85ce-30e4616a8e0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229602347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1229602347
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3777073786
Short name T956
Test name
Test status
Simulation time 41837293 ps
CPU time 0.7 seconds
Started Jul 28 07:25:36 PM PDT 24
Finished Jul 28 07:25:37 PM PDT 24
Peak memory 205424 kb
Host smart-3a83158d-959a-4952-a340-b420b7239084
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777073786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3777073786
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2188348287
Short name T1017
Test name
Test status
Simulation time 937927690 ps
CPU time 3 seconds
Started Jul 28 07:25:42 PM PDT 24
Finished Jul 28 07:25:45 PM PDT 24
Peak memory 205632 kb
Host smart-a190c1c3-4757-4256-a77d-210ab6e00f3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188348287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2188348287
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.839380796
Short name T122
Test name
Test status
Simulation time 162081701 ps
CPU time 1.95 seconds
Started Jul 28 07:25:34 PM PDT 24
Finished Jul 28 07:25:36 PM PDT 24
Peak memory 214184 kb
Host smart-e9142f00-a235-454f-8146-9c6bdf643b45
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839380796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.839380796
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2168563918
Short name T1027
Test name
Test status
Simulation time 1328827570 ps
CPU time 13.15 seconds
Started Jul 28 07:25:34 PM PDT 24
Finished Jul 28 07:25:48 PM PDT 24
Peak memory 220832 kb
Host smart-ba8a53ff-7a6c-4423-a209-b19dce6650f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168563918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2168563918
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2363906451
Short name T968
Test name
Test status
Simulation time 425990923 ps
CPU time 2.08 seconds
Started Jul 28 07:25:36 PM PDT 24
Finished Jul 28 07:25:38 PM PDT 24
Peak memory 213948 kb
Host smart-68287d55-dd2c-45a4-b5a6-34abbefecd51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363906451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2363906451
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.4087331802
Short name T154
Test name
Test status
Simulation time 768372208 ps
CPU time 8.35 seconds
Started Jul 28 07:25:37 PM PDT 24
Finished Jul 28 07:25:45 PM PDT 24
Peak memory 205760 kb
Host smart-26c48abc-770f-4d4b-8387-8d03db1c897b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087331802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.4087331802
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3125234974
Short name T946
Test name
Test status
Simulation time 66890517 ps
CPU time 1.52 seconds
Started Jul 28 07:25:39 PM PDT 24
Finished Jul 28 07:25:40 PM PDT 24
Peak memory 214156 kb
Host smart-dce86ef0-47c8-4e74-a6b4-ba2b29a7191d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125234974 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3125234974
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2910677602
Short name T1023
Test name
Test status
Simulation time 19077316 ps
CPU time 1.01 seconds
Started Jul 28 07:25:42 PM PDT 24
Finished Jul 28 07:25:43 PM PDT 24
Peak memory 205704 kb
Host smart-bd93c09c-dba4-4f19-9eaf-222f99792aef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910677602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2910677602
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.143743720
Short name T966
Test name
Test status
Simulation time 14730821 ps
CPU time 0.91 seconds
Started Jul 28 07:25:44 PM PDT 24
Finished Jul 28 07:25:45 PM PDT 24
Peak memory 205704 kb
Host smart-e57f2ba4-78bb-41ac-ba59-0f5dd5053c74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143743720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.143743720
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1518112811
Short name T1083
Test name
Test status
Simulation time 21005633 ps
CPU time 1.67 seconds
Started Jul 28 07:25:44 PM PDT 24
Finished Jul 28 07:25:46 PM PDT 24
Peak memory 205744 kb
Host smart-00fa5264-4529-41a1-83b0-184d99b46f78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518112811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1518112811
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.4280183671
Short name T1034
Test name
Test status
Simulation time 739643447 ps
CPU time 2.49 seconds
Started Jul 28 07:25:37 PM PDT 24
Finished Jul 28 07:25:39 PM PDT 24
Peak memory 214092 kb
Host smart-01861ae0-9f3a-4333-b3f5-582c672cbdd9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280183671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.4280183671
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3975764138
Short name T936
Test name
Test status
Simulation time 668983125 ps
CPU time 6.78 seconds
Started Jul 28 07:25:37 PM PDT 24
Finished Jul 28 07:25:44 PM PDT 24
Peak memory 214164 kb
Host smart-a2d4abb0-7877-4b29-b2f0-cd0bfd55e901
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975764138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3975764138
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3068211308
Short name T1067
Test name
Test status
Simulation time 146444234 ps
CPU time 3.61 seconds
Started Jul 28 07:25:37 PM PDT 24
Finished Jul 28 07:25:40 PM PDT 24
Peak memory 213916 kb
Host smart-958323ce-a1f8-4121-b150-bc0093bf684b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068211308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3068211308
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1247441655
Short name T1077
Test name
Test status
Simulation time 164621834 ps
CPU time 2.07 seconds
Started Jul 28 07:25:41 PM PDT 24
Finished Jul 28 07:25:44 PM PDT 24
Peak memory 214028 kb
Host smart-76b103b3-309e-4a8d-9aa8-a85fad17a6bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247441655 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1247441655
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.4181400295
Short name T146
Test name
Test status
Simulation time 12553821 ps
CPU time 1.07 seconds
Started Jul 28 07:25:41 PM PDT 24
Finished Jul 28 07:25:42 PM PDT 24
Peak memory 205704 kb
Host smart-abf83d14-7660-4f28-a22e-ac2cf1a89bd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181400295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.4181400295
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.487664213
Short name T952
Test name
Test status
Simulation time 164489604 ps
CPU time 0.86 seconds
Started Jul 28 07:25:41 PM PDT 24
Finished Jul 28 07:25:42 PM PDT 24
Peak memory 205512 kb
Host smart-6c936bb3-b427-45e1-a83e-b368bf599c97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487664213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.487664213
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.910427640
Short name T1042
Test name
Test status
Simulation time 421230090 ps
CPU time 2.64 seconds
Started Jul 28 07:25:44 PM PDT 24
Finished Jul 28 07:25:46 PM PDT 24
Peak memory 205772 kb
Host smart-799fefb9-dc1b-484e-b2db-4b9ef19db801
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910427640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.910427640
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3214500665
Short name T118
Test name
Test status
Simulation time 272155303 ps
CPU time 2.67 seconds
Started Jul 28 07:25:41 PM PDT 24
Finished Jul 28 07:25:44 PM PDT 24
Peak memory 214200 kb
Host smart-554c0384-38d3-4751-8644-0c7dd2b6d200
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214500665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3214500665
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1724121048
Short name T981
Test name
Test status
Simulation time 558939934 ps
CPU time 5.28 seconds
Started Jul 28 07:25:40 PM PDT 24
Finished Jul 28 07:25:46 PM PDT 24
Peak memory 214168 kb
Host smart-02ce8720-9b8b-49a9-8dc1-7c97ae1aab3a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724121048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1724121048
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.211810401
Short name T1029
Test name
Test status
Simulation time 21326800 ps
CPU time 1.36 seconds
Started Jul 28 07:25:43 PM PDT 24
Finished Jul 28 07:25:44 PM PDT 24
Peak memory 213992 kb
Host smart-db9d85c9-a285-4fdf-8319-3ebe053193ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211810401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.211810401
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1205429040
Short name T942
Test name
Test status
Simulation time 110174255 ps
CPU time 2.43 seconds
Started Jul 28 07:25:44 PM PDT 24
Finished Jul 28 07:25:47 PM PDT 24
Peak memory 214012 kb
Host smart-44c07dea-9340-4fe8-90d6-61aa9e628578
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205429040 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1205429040
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3973380106
Short name T148
Test name
Test status
Simulation time 47877464 ps
CPU time 1.28 seconds
Started Jul 28 07:25:46 PM PDT 24
Finished Jul 28 07:25:47 PM PDT 24
Peak memory 205736 kb
Host smart-1581bb99-ae18-4561-8c18-75733155fbf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973380106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3973380106
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.334583221
Short name T994
Test name
Test status
Simulation time 9816915 ps
CPU time 0.71 seconds
Started Jul 28 07:25:53 PM PDT 24
Finished Jul 28 07:25:54 PM PDT 24
Peak memory 205496 kb
Host smart-0aa04ba4-afe5-4f3c-aa9e-766c5e345e25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334583221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.334583221
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1617550410
Short name T964
Test name
Test status
Simulation time 110613785 ps
CPU time 2.36 seconds
Started Jul 28 07:25:47 PM PDT 24
Finished Jul 28 07:25:49 PM PDT 24
Peak memory 205760 kb
Host smart-30355f40-e68d-48b7-802b-39843a7a9b1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617550410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1617550410
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.396207136
Short name T987
Test name
Test status
Simulation time 53986327 ps
CPU time 1.82 seconds
Started Jul 28 07:25:42 PM PDT 24
Finished Jul 28 07:25:44 PM PDT 24
Peak memory 214216 kb
Host smart-a9b87a47-01d9-475f-8370-22064dcf8c42
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396207136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.396207136
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2502827998
Short name T1065
Test name
Test status
Simulation time 175127137 ps
CPU time 6.66 seconds
Started Jul 28 07:25:43 PM PDT 24
Finished Jul 28 07:25:49 PM PDT 24
Peak memory 214172 kb
Host smart-8bd1430a-382e-431d-b44d-0d64a994c1c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502827998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2502827998
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3484374019
Short name T1075
Test name
Test status
Simulation time 178651087 ps
CPU time 3.01 seconds
Started Jul 28 07:25:41 PM PDT 24
Finished Jul 28 07:25:44 PM PDT 24
Peak memory 216288 kb
Host smart-f02c8e19-522a-4548-9256-6457146e148a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484374019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3484374019
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1069295464
Short name T156
Test name
Test status
Simulation time 100020057 ps
CPU time 2.66 seconds
Started Jul 28 07:25:46 PM PDT 24
Finished Jul 28 07:25:49 PM PDT 24
Peak memory 213944 kb
Host smart-ea81dead-1218-4503-b234-02405b6ab933
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069295464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1069295464
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.4040416197
Short name T983
Test name
Test status
Simulation time 59099726 ps
CPU time 1.6 seconds
Started Jul 28 07:25:46 PM PDT 24
Finished Jul 28 07:25:47 PM PDT 24
Peak memory 213992 kb
Host smart-9b98b360-8907-44b1-8f5e-62960a74b9c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040416197 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.4040416197
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2906916515
Short name T998
Test name
Test status
Simulation time 28543734 ps
CPU time 1.15 seconds
Started Jul 28 07:25:59 PM PDT 24
Finished Jul 28 07:26:00 PM PDT 24
Peak memory 205724 kb
Host smart-65d5ecf0-54ea-4904-bacc-ea107ae0f8dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906916515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2906916515
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.4119165033
Short name T948
Test name
Test status
Simulation time 12342605 ps
CPU time 0.72 seconds
Started Jul 28 07:25:44 PM PDT 24
Finished Jul 28 07:25:45 PM PDT 24
Peak memory 205536 kb
Host smart-6a361c37-edf4-4cd4-8157-cf7f272da1a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119165033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.4119165033
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.880608709
Short name T150
Test name
Test status
Simulation time 237020181 ps
CPU time 1.98 seconds
Started Jul 28 07:25:45 PM PDT 24
Finished Jul 28 07:25:47 PM PDT 24
Peak memory 205664 kb
Host smart-86c750ce-87c6-47b7-9711-d79badc6bca4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880608709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.880608709
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2498902204
Short name T1070
Test name
Test status
Simulation time 298796325 ps
CPU time 1.82 seconds
Started Jul 28 07:25:44 PM PDT 24
Finished Jul 28 07:25:46 PM PDT 24
Peak memory 214152 kb
Host smart-795d7c84-1cc4-44b5-bf64-5073ef265e90
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498902204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2498902204
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2879586053
Short name T1080
Test name
Test status
Simulation time 390400146 ps
CPU time 7.09 seconds
Started Jul 28 07:25:45 PM PDT 24
Finished Jul 28 07:25:53 PM PDT 24
Peak memory 214196 kb
Host smart-a19feca3-8cd5-45a2-bf1c-4fa5b0245466
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879586053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.2879586053
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.990472868
Short name T1013
Test name
Test status
Simulation time 292948040 ps
CPU time 2.09 seconds
Started Jul 28 07:25:45 PM PDT 24
Finished Jul 28 07:25:48 PM PDT 24
Peak memory 213956 kb
Host smart-2b076efc-26b6-4dff-8bab-4b82401f76a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990472868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.990472868
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1245432864
Short name T990
Test name
Test status
Simulation time 29660181 ps
CPU time 1.44 seconds
Started Jul 28 07:25:45 PM PDT 24
Finished Jul 28 07:25:46 PM PDT 24
Peak memory 214012 kb
Host smart-56bf55ce-4793-49f2-80de-359f606c9f5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245432864 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1245432864
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.954473089
Short name T1072
Test name
Test status
Simulation time 64897907 ps
CPU time 0.95 seconds
Started Jul 28 07:25:48 PM PDT 24
Finished Jul 28 07:25:49 PM PDT 24
Peak memory 205628 kb
Host smart-1b12e3dd-7cdb-4ec4-b13b-9555c11b3e59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954473089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.954473089
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3703434586
Short name T999
Test name
Test status
Simulation time 18155836 ps
CPU time 0.69 seconds
Started Jul 28 07:25:48 PM PDT 24
Finished Jul 28 07:25:49 PM PDT 24
Peak memory 205472 kb
Host smart-16bd793b-eb53-46ce-a536-289009d45453
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703434586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3703434586
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.552627734
Short name T950
Test name
Test status
Simulation time 230510639 ps
CPU time 2.13 seconds
Started Jul 28 07:25:45 PM PDT 24
Finished Jul 28 07:25:47 PM PDT 24
Peak memory 205792 kb
Host smart-ad352089-8127-4c7a-9fd7-bae3a2179044
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552627734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.552627734
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.173108471
Short name T1058
Test name
Test status
Simulation time 183416328 ps
CPU time 3.41 seconds
Started Jul 28 07:25:48 PM PDT 24
Finished Jul 28 07:25:51 PM PDT 24
Peak memory 214116 kb
Host smart-c2c5c656-0dd3-49dc-a145-cf5c9cd1e63f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173108471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.173108471
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.631586366
Short name T1074
Test name
Test status
Simulation time 4221365457 ps
CPU time 12.8 seconds
Started Jul 28 07:25:49 PM PDT 24
Finished Jul 28 07:26:02 PM PDT 24
Peak memory 214164 kb
Host smart-d7033cc9-566b-4bc3-9d08-cce867c71fd5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631586366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.631586366
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3490057462
Short name T940
Test name
Test status
Simulation time 1047278388 ps
CPU time 2.55 seconds
Started Jul 28 07:25:45 PM PDT 24
Finished Jul 28 07:25:48 PM PDT 24
Peak memory 213968 kb
Host smart-2fcb3443-74be-40d4-b2a2-f34217b7a2b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490057462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3490057462
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.647816343
Short name T918
Test name
Test status
Simulation time 256506428 ps
CPU time 3.73 seconds
Started Jul 28 07:25:48 PM PDT 24
Finished Jul 28 07:25:52 PM PDT 24
Peak memory 213932 kb
Host smart-88a5948f-52b1-4cdb-9cd6-c39fa1df7d8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647816343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err
.647816343
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2055426512
Short name T383
Test name
Test status
Simulation time 48210434 ps
CPU time 1.23 seconds
Started Jul 28 07:25:53 PM PDT 24
Finished Jul 28 07:25:54 PM PDT 24
Peak memory 205864 kb
Host smart-ff94ca10-b74a-4403-8a0c-9508097d3b77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055426512 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2055426512
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.781244258
Short name T1049
Test name
Test status
Simulation time 16656582 ps
CPU time 1.05 seconds
Started Jul 28 07:25:49 PM PDT 24
Finished Jul 28 07:25:51 PM PDT 24
Peak memory 205608 kb
Host smart-79c752da-3481-46ea-8086-444d329d7251
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781244258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.781244258
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2801664183
Short name T925
Test name
Test status
Simulation time 18711858 ps
CPU time 0.9 seconds
Started Jul 28 07:25:56 PM PDT 24
Finished Jul 28 07:25:57 PM PDT 24
Peak memory 205448 kb
Host smart-39c748f8-bd58-494a-9dd7-89064a70c53d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801664183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2801664183
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2463198936
Short name T149
Test name
Test status
Simulation time 22417300 ps
CPU time 1.81 seconds
Started Jul 28 07:25:51 PM PDT 24
Finished Jul 28 07:25:53 PM PDT 24
Peak memory 205740 kb
Host smart-a65a75f6-698d-4a04-b096-96583e5e59c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463198936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2463198936
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3719491141
Short name T944
Test name
Test status
Simulation time 89944043 ps
CPU time 3.23 seconds
Started Jul 28 07:25:51 PM PDT 24
Finished Jul 28 07:25:55 PM PDT 24
Peak memory 214156 kb
Host smart-5e6e1bc7-b405-4e9b-8c24-2c441c81d11a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719491141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3719491141
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.879498103
Short name T124
Test name
Test status
Simulation time 198931934 ps
CPU time 7.44 seconds
Started Jul 28 07:25:47 PM PDT 24
Finished Jul 28 07:25:54 PM PDT 24
Peak memory 214188 kb
Host smart-e7d9cdf7-ea17-4ab1-b852-bf40235bea96
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879498103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_shadow_reg_errors_with_csr_rw.879498103
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2049976287
Short name T930
Test name
Test status
Simulation time 366187504 ps
CPU time 2.86 seconds
Started Jul 28 07:25:54 PM PDT 24
Finished Jul 28 07:25:58 PM PDT 24
Peak memory 213964 kb
Host smart-769afd70-1ceb-44d8-954b-8e2e33e3650b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049976287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2049976287
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1959322895
Short name T169
Test name
Test status
Simulation time 3736204014 ps
CPU time 8.94 seconds
Started Jul 28 07:25:56 PM PDT 24
Finished Jul 28 07:26:05 PM PDT 24
Peak memory 213864 kb
Host smart-6353a239-5c85-486e-aaa2-17d8346f738b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959322895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1959322895
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1711647131
Short name T971
Test name
Test status
Simulation time 33537099 ps
CPU time 1.45 seconds
Started Jul 28 07:25:50 PM PDT 24
Finished Jul 28 07:25:51 PM PDT 24
Peak memory 205864 kb
Host smart-8a1c4a1c-95f2-4ba3-b899-2b4617348c22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711647131 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1711647131
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3634055365
Short name T973
Test name
Test status
Simulation time 17848803 ps
CPU time 1.19 seconds
Started Jul 28 07:25:50 PM PDT 24
Finished Jul 28 07:25:51 PM PDT 24
Peak memory 205920 kb
Host smart-8f66f31b-a9f1-4775-944e-e25a4200cfa0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634055365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3634055365
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1056981607
Short name T1061
Test name
Test status
Simulation time 16261339 ps
CPU time 0.74 seconds
Started Jul 28 07:25:47 PM PDT 24
Finished Jul 28 07:25:48 PM PDT 24
Peak memory 205460 kb
Host smart-0111da99-36eb-4ab1-ba02-fbe82c500fff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056981607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1056981607
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3879055456
Short name T151
Test name
Test status
Simulation time 47246707 ps
CPU time 2.2 seconds
Started Jul 28 07:25:58 PM PDT 24
Finished Jul 28 07:26:00 PM PDT 24
Peak memory 205724 kb
Host smart-b2ce2eb3-9c02-4b60-bfcd-11e9a8c44222
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879055456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.3879055456
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.366614650
Short name T1085
Test name
Test status
Simulation time 177408926 ps
CPU time 1.86 seconds
Started Jul 28 07:25:51 PM PDT 24
Finished Jul 28 07:25:53 PM PDT 24
Peak memory 214168 kb
Host smart-735e015b-bf3e-414c-878f-1e6a9a5e33e6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366614650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.366614650
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2960610079
Short name T1051
Test name
Test status
Simulation time 1765904431 ps
CPU time 12.25 seconds
Started Jul 28 07:25:49 PM PDT 24
Finished Jul 28 07:26:01 PM PDT 24
Peak memory 214180 kb
Host smart-c6db17e7-c554-4cd9-9df1-2cee6f9a53f8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960610079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2960610079
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2967351487
Short name T933
Test name
Test status
Simulation time 164490222 ps
CPU time 3.07 seconds
Started Jul 28 07:25:50 PM PDT 24
Finished Jul 28 07:25:53 PM PDT 24
Peak memory 217004 kb
Host smart-cc9cf939-430e-4a0b-b2f4-275e29365ee8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967351487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2967351487
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3754787765
Short name T1056
Test name
Test status
Simulation time 206993030 ps
CPU time 9.11 seconds
Started Jul 28 07:25:18 PM PDT 24
Finished Jul 28 07:25:28 PM PDT 24
Peak memory 205688 kb
Host smart-049f16e5-dadf-4e15-b9ce-95f295d6f638
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754787765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
754787765
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.4279208427
Short name T949
Test name
Test status
Simulation time 1809702199 ps
CPU time 6.42 seconds
Started Jul 28 07:25:17 PM PDT 24
Finished Jul 28 07:25:24 PM PDT 24
Peak memory 205792 kb
Host smart-ffbdb9dc-853d-4d03-8554-99790298f880
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279208427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.4
279208427
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2522598518
Short name T1018
Test name
Test status
Simulation time 229252505 ps
CPU time 1.18 seconds
Started Jul 28 07:25:15 PM PDT 24
Finished Jul 28 07:25:16 PM PDT 24
Peak memory 205648 kb
Host smart-47082899-e375-48cb-adf2-b2325c0a8ba3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522598518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2
522598518
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.765101978
Short name T977
Test name
Test status
Simulation time 56611712 ps
CPU time 2.16 seconds
Started Jul 28 07:25:21 PM PDT 24
Finished Jul 28 07:25:24 PM PDT 24
Peak memory 205840 kb
Host smart-0fddbed1-5569-4679-b105-d2b69572d39c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765101978 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.765101978
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1111198416
Short name T1055
Test name
Test status
Simulation time 56798893 ps
CPU time 0.92 seconds
Started Jul 28 07:25:17 PM PDT 24
Finished Jul 28 07:25:18 PM PDT 24
Peak memory 205560 kb
Host smart-3d50dd05-9604-48e0-9701-b0432b4696de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111198416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1111198416
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.4200769011
Short name T928
Test name
Test status
Simulation time 22976852 ps
CPU time 0.87 seconds
Started Jul 28 07:25:18 PM PDT 24
Finished Jul 28 07:25:19 PM PDT 24
Peak memory 205504 kb
Host smart-9186de39-3b55-4d10-9eb6-5f9ebad9fc10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200769011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.4200769011
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1816284868
Short name T941
Test name
Test status
Simulation time 384604748 ps
CPU time 4.15 seconds
Started Jul 28 07:25:21 PM PDT 24
Finished Jul 28 07:25:26 PM PDT 24
Peak memory 205748 kb
Host smart-de2c5608-b3d8-42cd-b700-222d6d709aa1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816284868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1816284868
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2886094935
Short name T1010
Test name
Test status
Simulation time 731770776 ps
CPU time 2.67 seconds
Started Jul 28 07:25:09 PM PDT 24
Finished Jul 28 07:25:12 PM PDT 24
Peak memory 214328 kb
Host smart-6b6137c4-beb4-4106-a63f-21d9e2d6833b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886094935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2886094935
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3079955161
Short name T965
Test name
Test status
Simulation time 264368103 ps
CPU time 4.59 seconds
Started Jul 28 07:25:15 PM PDT 24
Finished Jul 28 07:25:20 PM PDT 24
Peak memory 213908 kb
Host smart-e84b3d2c-8fe7-46dd-968d-2170148f0e80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079955161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3079955161
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3678649029
Short name T917
Test name
Test status
Simulation time 585044763 ps
CPU time 3.67 seconds
Started Jul 28 07:25:16 PM PDT 24
Finished Jul 28 07:25:20 PM PDT 24
Peak memory 213900 kb
Host smart-04218011-0004-4df4-944d-6fd07dcb3981
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678649029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3678649029
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.138406083
Short name T958
Test name
Test status
Simulation time 15640936 ps
CPU time 0.92 seconds
Started Jul 28 07:25:50 PM PDT 24
Finished Jul 28 07:25:52 PM PDT 24
Peak memory 205576 kb
Host smart-2088ff85-7672-4cd0-89ab-c486a474a87f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138406083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.138406083
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2172225663
Short name T916
Test name
Test status
Simulation time 33911129 ps
CPU time 0.7 seconds
Started Jul 28 07:25:50 PM PDT 24
Finished Jul 28 07:25:51 PM PDT 24
Peak memory 205516 kb
Host smart-d6c4564c-6a4e-4076-b66b-4dfdf6ccbb61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172225663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2172225663
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1178812251
Short name T947
Test name
Test status
Simulation time 7495905 ps
CPU time 0.78 seconds
Started Jul 28 07:25:52 PM PDT 24
Finished Jul 28 07:25:53 PM PDT 24
Peak memory 205516 kb
Host smart-fd6715aa-6964-4e3c-8b0f-1db02437fb7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178812251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1178812251
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2034005074
Short name T978
Test name
Test status
Simulation time 26504762 ps
CPU time 0.89 seconds
Started Jul 28 07:25:56 PM PDT 24
Finished Jul 28 07:25:57 PM PDT 24
Peak memory 205516 kb
Host smart-28bc1b33-1185-4844-8870-fca8971938d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034005074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2034005074
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.39461756
Short name T951
Test name
Test status
Simulation time 8257827 ps
CPU time 0.72 seconds
Started Jul 28 07:25:49 PM PDT 24
Finished Jul 28 07:25:50 PM PDT 24
Peak memory 205572 kb
Host smart-1b6cd468-e6f2-41ff-908c-60346e85f491
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39461756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.39461756
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2515896191
Short name T1030
Test name
Test status
Simulation time 106133660 ps
CPU time 0.73 seconds
Started Jul 28 07:25:53 PM PDT 24
Finished Jul 28 07:25:54 PM PDT 24
Peak memory 205500 kb
Host smart-59b87bb2-6bb0-4c5f-8bb3-e222090c05c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515896191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2515896191
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3579276946
Short name T1032
Test name
Test status
Simulation time 16529710 ps
CPU time 0.7 seconds
Started Jul 28 07:25:51 PM PDT 24
Finished Jul 28 07:25:52 PM PDT 24
Peak memory 205424 kb
Host smart-ed1ec602-a7a1-425e-ad69-c53cf159e134
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579276946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3579276946
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2038874251
Short name T1008
Test name
Test status
Simulation time 77171879 ps
CPU time 0.73 seconds
Started Jul 28 07:25:54 PM PDT 24
Finished Jul 28 07:25:55 PM PDT 24
Peak memory 205424 kb
Host smart-37d96028-9126-4cd6-a120-a79378b73f9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038874251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2038874251
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1812844509
Short name T1016
Test name
Test status
Simulation time 11481277 ps
CPU time 0.95 seconds
Started Jul 28 07:25:52 PM PDT 24
Finished Jul 28 07:25:53 PM PDT 24
Peak memory 205544 kb
Host smart-e8c91f9a-b4f8-4585-8390-aae6c8eedf93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812844509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1812844509
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2898043344
Short name T934
Test name
Test status
Simulation time 115655083 ps
CPU time 0.82 seconds
Started Jul 28 07:25:49 PM PDT 24
Finished Jul 28 07:25:50 PM PDT 24
Peak memory 205528 kb
Host smart-260c9e5a-0cee-4fe8-aeb9-97d2286bcbc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898043344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2898043344
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3529974966
Short name T984
Test name
Test status
Simulation time 496024075 ps
CPU time 4.77 seconds
Started Jul 28 07:25:15 PM PDT 24
Finished Jul 28 07:25:20 PM PDT 24
Peak memory 205732 kb
Host smart-e10d3231-5404-4a21-9f2d-d44d28663f0b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529974966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
529974966
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1637970415
Short name T1021
Test name
Test status
Simulation time 2697713687 ps
CPU time 16.45 seconds
Started Jul 28 07:25:21 PM PDT 24
Finished Jul 28 07:25:38 PM PDT 24
Peak memory 205796 kb
Host smart-90ba1e1b-754d-4aab-8de1-58661e308dd7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637970415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
637970415
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1418467479
Short name T1000
Test name
Test status
Simulation time 50285256 ps
CPU time 0.87 seconds
Started Jul 28 07:25:14 PM PDT 24
Finished Jul 28 07:25:15 PM PDT 24
Peak memory 205584 kb
Host smart-53c80b97-94b1-484f-b85c-9ec13c1cf583
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418467479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
418467479
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1221582108
Short name T995
Test name
Test status
Simulation time 55884447 ps
CPU time 1.68 seconds
Started Jul 28 07:25:21 PM PDT 24
Finished Jul 28 07:25:23 PM PDT 24
Peak memory 214080 kb
Host smart-c62adc07-93ee-43de-828b-5f0718d5e0f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221582108 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.1221582108
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.918511710
Short name T1068
Test name
Test status
Simulation time 25665827 ps
CPU time 1.14 seconds
Started Jul 28 07:25:16 PM PDT 24
Finished Jul 28 07:25:17 PM PDT 24
Peak memory 205768 kb
Host smart-10479745-7a5f-42ad-8a18-fa279f40ef62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918511710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.918511710
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3253468609
Short name T1066
Test name
Test status
Simulation time 18773967 ps
CPU time 0.94 seconds
Started Jul 28 07:25:18 PM PDT 24
Finished Jul 28 07:25:19 PM PDT 24
Peak memory 205576 kb
Host smart-949357d6-96a0-428f-ad8e-2d1783ceca61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253468609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3253468609
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3216939774
Short name T993
Test name
Test status
Simulation time 613204667 ps
CPU time 2.17 seconds
Started Jul 28 07:25:16 PM PDT 24
Finished Jul 28 07:25:18 PM PDT 24
Peak memory 205716 kb
Host smart-7a9ae0b8-ae22-42f5-86a1-b8b418d52eeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216939774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3216939774
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1890824149
Short name T980
Test name
Test status
Simulation time 370134319 ps
CPU time 2.03 seconds
Started Jul 28 07:25:17 PM PDT 24
Finished Jul 28 07:25:19 PM PDT 24
Peak memory 214180 kb
Host smart-6f57fbf8-ed32-4875-8eae-5fc5d8177fcd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890824149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1890824149
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1145362481
Short name T1060
Test name
Test status
Simulation time 320610413 ps
CPU time 4.58 seconds
Started Jul 28 07:25:17 PM PDT 24
Finished Jul 28 07:25:22 PM PDT 24
Peak memory 214136 kb
Host smart-5acaed6d-b9eb-40bb-9e03-4d51f07fc1e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145362481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1145362481
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3821560408
Short name T1045
Test name
Test status
Simulation time 529609160 ps
CPU time 3.42 seconds
Started Jul 28 07:25:17 PM PDT 24
Finished Jul 28 07:25:20 PM PDT 24
Peak memory 213956 kb
Host smart-2ac01061-6b0f-451f-b646-84c1239e2413
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821560408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3821560408
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.722221920
Short name T924
Test name
Test status
Simulation time 11594930 ps
CPU time 0.74 seconds
Started Jul 28 07:25:55 PM PDT 24
Finished Jul 28 07:25:56 PM PDT 24
Peak memory 205488 kb
Host smart-8d5af8cb-5169-40dc-928e-4a25deac1c2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722221920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.722221920
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2332157443
Short name T1022
Test name
Test status
Simulation time 75076339 ps
CPU time 0.71 seconds
Started Jul 28 07:25:57 PM PDT 24
Finished Jul 28 07:25:58 PM PDT 24
Peak memory 205360 kb
Host smart-b9d06aa7-5241-42f9-ac97-4f2602a688f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332157443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2332157443
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.225271645
Short name T1081
Test name
Test status
Simulation time 46142348 ps
CPU time 0.84 seconds
Started Jul 28 07:25:54 PM PDT 24
Finished Jul 28 07:25:56 PM PDT 24
Peak memory 205436 kb
Host smart-fb4fecf5-9200-4eda-87c3-26160f53ee45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225271645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.225271645
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1617400339
Short name T1053
Test name
Test status
Simulation time 20939167 ps
CPU time 0.71 seconds
Started Jul 28 07:25:54 PM PDT 24
Finished Jul 28 07:25:56 PM PDT 24
Peak memory 205516 kb
Host smart-c683ef73-8498-4537-95af-3fd09cfabb66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617400339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1617400339
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2395904851
Short name T961
Test name
Test status
Simulation time 83788762 ps
CPU time 0.75 seconds
Started Jul 28 07:25:53 PM PDT 24
Finished Jul 28 07:25:54 PM PDT 24
Peak memory 205440 kb
Host smart-5ef06336-5d4d-47f4-8aec-1ced28ab2ea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395904851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2395904851
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.740742601
Short name T915
Test name
Test status
Simulation time 18815148 ps
CPU time 0.77 seconds
Started Jul 28 07:25:58 PM PDT 24
Finished Jul 28 07:25:59 PM PDT 24
Peak memory 205512 kb
Host smart-25a66742-ca11-4cdb-b9bd-6aa98b7b1a9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740742601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.740742601
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3918160945
Short name T957
Test name
Test status
Simulation time 37181801 ps
CPU time 0.73 seconds
Started Jul 28 07:25:55 PM PDT 24
Finished Jul 28 07:25:56 PM PDT 24
Peak memory 205536 kb
Host smart-2a05d0d9-ae7d-4197-8dfa-342bcf8ce3c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918160945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3918160945
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.816416355
Short name T972
Test name
Test status
Simulation time 22953141 ps
CPU time 0.73 seconds
Started Jul 28 07:25:53 PM PDT 24
Finished Jul 28 07:25:54 PM PDT 24
Peak memory 205528 kb
Host smart-a4299cc3-e7d8-4f64-882b-5ca6f1765072
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816416355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.816416355
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.678989910
Short name T959
Test name
Test status
Simulation time 18517266 ps
CPU time 0.7 seconds
Started Jul 28 07:25:55 PM PDT 24
Finished Jul 28 07:25:56 PM PDT 24
Peak memory 205428 kb
Host smart-87743f0d-b226-46a1-b1f6-9f86be706f73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678989910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.678989910
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2712471594
Short name T1078
Test name
Test status
Simulation time 36971204 ps
CPU time 0.86 seconds
Started Jul 28 07:26:02 PM PDT 24
Finished Jul 28 07:26:03 PM PDT 24
Peak memory 205516 kb
Host smart-f4a6d2c8-2973-4cab-8f55-aab0e02cd12d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712471594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2712471594
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1494423240
Short name T976
Test name
Test status
Simulation time 740213316 ps
CPU time 8.02 seconds
Started Jul 28 07:25:23 PM PDT 24
Finished Jul 28 07:25:31 PM PDT 24
Peak memory 205660 kb
Host smart-8bd5f0ed-62c3-459e-bd3d-f2690cc8c2e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494423240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
494423240
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2518623426
Short name T921
Test name
Test status
Simulation time 137545079 ps
CPU time 8.01 seconds
Started Jul 28 07:25:16 PM PDT 24
Finished Jul 28 07:25:24 PM PDT 24
Peak memory 205792 kb
Host smart-71da07b0-dc71-405e-9341-faa831e66847
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518623426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
518623426
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1662846127
Short name T1028
Test name
Test status
Simulation time 26303321 ps
CPU time 1.04 seconds
Started Jul 28 07:25:16 PM PDT 24
Finished Jul 28 07:25:17 PM PDT 24
Peak memory 205648 kb
Host smart-39097e75-ac4c-420a-b4b2-dc55ae68e282
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662846127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
662846127
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2230136688
Short name T1071
Test name
Test status
Simulation time 22212903 ps
CPU time 1.08 seconds
Started Jul 28 07:25:22 PM PDT 24
Finished Jul 28 07:25:23 PM PDT 24
Peak memory 205716 kb
Host smart-a6149e80-5882-4fa9-8342-daa6a5ee7d11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230136688 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2230136688
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.4063041750
Short name T997
Test name
Test status
Simulation time 55584122 ps
CPU time 1.09 seconds
Started Jul 28 07:25:16 PM PDT 24
Finished Jul 28 07:25:17 PM PDT 24
Peak memory 205840 kb
Host smart-651d2f65-8277-407f-83fb-b10aee4f1a12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063041750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.4063041750
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2202611712
Short name T935
Test name
Test status
Simulation time 22659827 ps
CPU time 0.72 seconds
Started Jul 28 07:25:15 PM PDT 24
Finished Jul 28 07:25:16 PM PDT 24
Peak memory 205548 kb
Host smart-8b37437e-0b15-4793-81ae-6e596374efa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202611712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2202611712
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3631967928
Short name T1006
Test name
Test status
Simulation time 210833574 ps
CPU time 1.53 seconds
Started Jul 28 07:25:22 PM PDT 24
Finished Jul 28 07:25:24 PM PDT 24
Peak memory 205736 kb
Host smart-dddf0fee-5036-41d2-a4c0-a64a2dd7f9f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631967928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.3631967928
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3556094384
Short name T125
Test name
Test status
Simulation time 78623786 ps
CPU time 1.86 seconds
Started Jul 28 07:25:15 PM PDT 24
Finished Jul 28 07:25:17 PM PDT 24
Peak memory 214100 kb
Host smart-465c9b53-9c7b-4824-8752-006c6ebd2fd7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556094384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3556094384
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2194337349
Short name T1076
Test name
Test status
Simulation time 231445596 ps
CPU time 7.25 seconds
Started Jul 28 07:25:16 PM PDT 24
Finished Jul 28 07:25:24 PM PDT 24
Peak memory 214012 kb
Host smart-322d33d7-552d-495d-9a7c-fd7cc0f8fcb1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194337349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2194337349
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2539307500
Short name T937
Test name
Test status
Simulation time 368318317 ps
CPU time 3.16 seconds
Started Jul 28 07:25:16 PM PDT 24
Finished Jul 28 07:25:19 PM PDT 24
Peak memory 217152 kb
Host smart-b7b85d6e-ec50-4000-b12e-d7c1c929334c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539307500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2539307500
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3286799594
Short name T162
Test name
Test status
Simulation time 521885948 ps
CPU time 5.3 seconds
Started Jul 28 07:25:17 PM PDT 24
Finished Jul 28 07:25:23 PM PDT 24
Peak memory 214108 kb
Host smart-df2e73dc-4e05-4e2d-81bb-a5b9827ece23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286799594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3286799594
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1373752569
Short name T1082
Test name
Test status
Simulation time 20237399 ps
CPU time 0.72 seconds
Started Jul 28 07:25:58 PM PDT 24
Finished Jul 28 07:25:59 PM PDT 24
Peak memory 205472 kb
Host smart-3421ac7b-2bb9-48e4-9330-4873906428d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373752569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1373752569
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1580176090
Short name T945
Test name
Test status
Simulation time 35617736 ps
CPU time 0.82 seconds
Started Jul 28 07:25:55 PM PDT 24
Finished Jul 28 07:25:56 PM PDT 24
Peak memory 205468 kb
Host smart-332b3b4f-ef31-4b02-93d4-6f716023cce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580176090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1580176090
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1899019790
Short name T969
Test name
Test status
Simulation time 9092489 ps
CPU time 0.72 seconds
Started Jul 28 07:25:55 PM PDT 24
Finished Jul 28 07:25:56 PM PDT 24
Peak memory 205528 kb
Host smart-97bbc9af-78ee-47f8-b56c-5fe33ba84d56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899019790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1899019790
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1541708799
Short name T931
Test name
Test status
Simulation time 14707129 ps
CPU time 0.9 seconds
Started Jul 28 07:25:57 PM PDT 24
Finished Jul 28 07:25:58 PM PDT 24
Peak memory 205588 kb
Host smart-2ccf9837-cbcd-4603-81a8-3c5698212b83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541708799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1541708799
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2270481142
Short name T1015
Test name
Test status
Simulation time 10651686 ps
CPU time 0.85 seconds
Started Jul 28 07:25:56 PM PDT 24
Finished Jul 28 07:25:57 PM PDT 24
Peak memory 205508 kb
Host smart-66d516f6-7b78-40f0-a61e-523042c56464
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270481142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2270481142
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.703959269
Short name T985
Test name
Test status
Simulation time 24583094 ps
CPU time 0.78 seconds
Started Jul 28 07:25:58 PM PDT 24
Finished Jul 28 07:25:59 PM PDT 24
Peak memory 205504 kb
Host smart-7bff8438-17ba-4107-b6ab-054eccf86b93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703959269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.703959269
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.4236584775
Short name T922
Test name
Test status
Simulation time 37705368 ps
CPU time 0.77 seconds
Started Jul 28 07:25:54 PM PDT 24
Finished Jul 28 07:25:56 PM PDT 24
Peak memory 205568 kb
Host smart-d1195fdb-5534-4a86-a411-b2696778490f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236584775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.4236584775
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3891632694
Short name T932
Test name
Test status
Simulation time 77004795 ps
CPU time 0.78 seconds
Started Jul 28 07:25:57 PM PDT 24
Finished Jul 28 07:25:58 PM PDT 24
Peak memory 205508 kb
Host smart-cc20bb1a-a88c-4dbd-a8a4-eb80c02fca7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891632694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3891632694
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3279746955
Short name T943
Test name
Test status
Simulation time 9988557 ps
CPU time 0.8 seconds
Started Jul 28 07:25:55 PM PDT 24
Finished Jul 28 07:25:56 PM PDT 24
Peak memory 205528 kb
Host smart-2a7d9569-8c0f-46ed-a8e2-4389f720a4fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279746955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3279746955
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1112733262
Short name T1063
Test name
Test status
Simulation time 47914787 ps
CPU time 0.79 seconds
Started Jul 28 07:25:57 PM PDT 24
Finished Jul 28 07:25:57 PM PDT 24
Peak memory 205528 kb
Host smart-9f11d98e-cdd8-412c-acbd-670aa425389d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112733262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1112733262
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3625705035
Short name T1025
Test name
Test status
Simulation time 364037204 ps
CPU time 1.68 seconds
Started Jul 28 07:25:20 PM PDT 24
Finished Jul 28 07:25:22 PM PDT 24
Peak memory 213924 kb
Host smart-d63e6efc-18d6-4a64-9fbe-4310874113f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625705035 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3625705035
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3836587617
Short name T1046
Test name
Test status
Simulation time 28547197 ps
CPU time 1.57 seconds
Started Jul 28 07:25:21 PM PDT 24
Finished Jul 28 07:25:23 PM PDT 24
Peak memory 205796 kb
Host smart-c26b83d3-ead4-4e95-a252-fde936a87007
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836587617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3836587617
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.813440256
Short name T927
Test name
Test status
Simulation time 21398771 ps
CPU time 0.84 seconds
Started Jul 28 07:25:25 PM PDT 24
Finished Jul 28 07:25:26 PM PDT 24
Peak memory 205476 kb
Host smart-8b2643a9-f7f0-49ea-9e43-118358b053cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813440256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.813440256
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2435188871
Short name T1044
Test name
Test status
Simulation time 75929911 ps
CPU time 1.22 seconds
Started Jul 28 07:25:23 PM PDT 24
Finished Jul 28 07:25:25 PM PDT 24
Peak memory 205580 kb
Host smart-8dd0f783-4fed-45c6-8f48-212eb7f9d3c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435188871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.2435188871
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2834644021
Short name T1035
Test name
Test status
Simulation time 865420563 ps
CPU time 3.81 seconds
Started Jul 28 07:25:24 PM PDT 24
Finished Jul 28 07:25:28 PM PDT 24
Peak memory 214232 kb
Host smart-de94f268-65c2-485b-8686-ca996f97f33a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834644021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2834644021
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1120895616
Short name T123
Test name
Test status
Simulation time 461666843 ps
CPU time 15.74 seconds
Started Jul 28 07:25:22 PM PDT 24
Finished Jul 28 07:25:38 PM PDT 24
Peak memory 214200 kb
Host smart-6d3e81e3-92e3-41a3-9e82-b25fe85dd83f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120895616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1120895616
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.732111544
Short name T975
Test name
Test status
Simulation time 255133627 ps
CPU time 2.63 seconds
Started Jul 28 07:25:21 PM PDT 24
Finished Jul 28 07:25:24 PM PDT 24
Peak memory 214016 kb
Host smart-40f0f300-042f-48c2-b501-86b5e9c509e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732111544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.732111544
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2373424199
Short name T155
Test name
Test status
Simulation time 311557983 ps
CPU time 10.77 seconds
Started Jul 28 07:25:24 PM PDT 24
Finished Jul 28 07:25:35 PM PDT 24
Peak memory 213912 kb
Host smart-7deba270-5f45-4319-ada8-b2f2cf5e8836
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373424199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2373424199
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2853321346
Short name T1020
Test name
Test status
Simulation time 34988264 ps
CPU time 1.13 seconds
Started Jul 28 07:25:22 PM PDT 24
Finished Jul 28 07:25:23 PM PDT 24
Peak memory 205840 kb
Host smart-7ebb9c23-a860-40d9-8f99-299f337e7b81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853321346 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2853321346
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3716363886
Short name T1040
Test name
Test status
Simulation time 55351323 ps
CPU time 1.08 seconds
Started Jul 28 07:25:21 PM PDT 24
Finished Jul 28 07:25:23 PM PDT 24
Peak memory 205644 kb
Host smart-de2fad81-bec9-4a5a-aca4-1d90f704bc7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716363886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3716363886
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.4144712396
Short name T1004
Test name
Test status
Simulation time 35477925 ps
CPU time 0.7 seconds
Started Jul 28 07:25:23 PM PDT 24
Finished Jul 28 07:25:24 PM PDT 24
Peak memory 205500 kb
Host smart-c0c97568-1c0b-4494-a99d-d40f5e64944b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144712396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.4144712396
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.184351204
Short name T954
Test name
Test status
Simulation time 45722289 ps
CPU time 1.38 seconds
Started Jul 28 07:25:22 PM PDT 24
Finished Jul 28 07:25:23 PM PDT 24
Peak memory 205864 kb
Host smart-21735381-7bd7-4752-a48b-515ff738b706
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184351204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.184351204
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3600679310
Short name T1038
Test name
Test status
Simulation time 49940322 ps
CPU time 1.58 seconds
Started Jul 28 07:25:21 PM PDT 24
Finished Jul 28 07:25:23 PM PDT 24
Peak memory 214164 kb
Host smart-f619ac97-56c6-45da-820e-191044be86bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600679310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3600679310
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.310878978
Short name T1059
Test name
Test status
Simulation time 468573378 ps
CPU time 9.63 seconds
Started Jul 28 07:25:21 PM PDT 24
Finished Jul 28 07:25:31 PM PDT 24
Peak memory 220696 kb
Host smart-250d4f7a-3bfb-44d7-b5b4-f5066135bc8e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310878978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.310878978
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1510178907
Short name T929
Test name
Test status
Simulation time 52975801 ps
CPU time 1.97 seconds
Started Jul 28 07:25:21 PM PDT 24
Finished Jul 28 07:25:23 PM PDT 24
Peak memory 213948 kb
Host smart-1611d534-3f86-4ca3-bc7e-f47536d334a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510178907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1510178907
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.413313952
Short name T158
Test name
Test status
Simulation time 142006745 ps
CPU time 3.67 seconds
Started Jul 28 07:25:23 PM PDT 24
Finished Jul 28 07:25:27 PM PDT 24
Peak memory 213904 kb
Host smart-f31b76a8-aadf-4c51-b154-31298d7e6437
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413313952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
413313952
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2016028922
Short name T920
Test name
Test status
Simulation time 27961734 ps
CPU time 1.19 seconds
Started Jul 28 07:25:29 PM PDT 24
Finished Jul 28 07:25:31 PM PDT 24
Peak memory 205780 kb
Host smart-2baa4622-1702-4135-a8e2-da21133f2596
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016028922 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2016028922
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.630683138
Short name T989
Test name
Test status
Simulation time 31077360 ps
CPU time 1.61 seconds
Started Jul 28 07:25:26 PM PDT 24
Finished Jul 28 07:25:28 PM PDT 24
Peak memory 205792 kb
Host smart-a7049d7f-099e-4097-9972-53405cf86aff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630683138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.630683138
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2314909962
Short name T1057
Test name
Test status
Simulation time 19681843 ps
CPU time 0.81 seconds
Started Jul 28 07:25:26 PM PDT 24
Finished Jul 28 07:25:27 PM PDT 24
Peak memory 205436 kb
Host smart-60b419b7-c2a5-4b1a-818e-b93b63e6ea22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314909962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2314909962
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.767060581
Short name T147
Test name
Test status
Simulation time 660942434 ps
CPU time 2.11 seconds
Started Jul 28 07:25:28 PM PDT 24
Finished Jul 28 07:25:30 PM PDT 24
Peak memory 205800 kb
Host smart-93f5b7dc-762d-482b-aaa6-5170c8d7d536
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767060581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sam
e_csr_outstanding.767060581
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1396158962
Short name T1086
Test name
Test status
Simulation time 140215405 ps
CPU time 2.43 seconds
Started Jul 28 07:25:22 PM PDT 24
Finished Jul 28 07:25:25 PM PDT 24
Peak memory 214188 kb
Host smart-2e940029-cc13-4866-b044-de29cd179551
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396158962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1396158962
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1346546939
Short name T970
Test name
Test status
Simulation time 94540368 ps
CPU time 4.85 seconds
Started Jul 28 07:25:22 PM PDT 24
Finished Jul 28 07:25:27 PM PDT 24
Peak memory 214276 kb
Host smart-91f7288d-f936-4c37-a077-96639f362d1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346546939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.1346546939
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1392970461
Short name T923
Test name
Test status
Simulation time 100523441 ps
CPU time 2.65 seconds
Started Jul 28 07:25:24 PM PDT 24
Finished Jul 28 07:25:26 PM PDT 24
Peak memory 213908 kb
Host smart-bfa066f5-e9f5-4d96-a7f0-79e9d7b1b931
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392970461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1392970461
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.4290513697
Short name T1041
Test name
Test status
Simulation time 555772945 ps
CPU time 4.06 seconds
Started Jul 28 07:25:27 PM PDT 24
Finished Jul 28 07:25:31 PM PDT 24
Peak memory 213920 kb
Host smart-6e03f2f7-3e86-4b21-a067-b7eb1a99eced
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290513697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.4290513697
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1350344932
Short name T1039
Test name
Test status
Simulation time 46051830 ps
CPU time 1.03 seconds
Started Jul 28 07:25:25 PM PDT 24
Finished Jul 28 07:25:26 PM PDT 24
Peak memory 205636 kb
Host smart-809d9b06-a287-49b3-a371-bac6b98c07be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350344932 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1350344932
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2253717438
Short name T967
Test name
Test status
Simulation time 15867630 ps
CPU time 1.01 seconds
Started Jul 28 07:25:24 PM PDT 24
Finished Jul 28 07:25:25 PM PDT 24
Peak memory 205652 kb
Host smart-9f722854-e652-47ed-b2ae-ca91fae59977
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253717438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2253717438
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2347673730
Short name T926
Test name
Test status
Simulation time 18307544 ps
CPU time 0.8 seconds
Started Jul 28 07:25:27 PM PDT 24
Finished Jul 28 07:25:28 PM PDT 24
Peak memory 205452 kb
Host smart-f69f13be-e0fa-44f5-aafd-6c28a9e065f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347673730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2347673730
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3630449558
Short name T963
Test name
Test status
Simulation time 27412417 ps
CPU time 1.33 seconds
Started Jul 28 07:25:28 PM PDT 24
Finished Jul 28 07:25:30 PM PDT 24
Peak memory 205752 kb
Host smart-f0738f4d-8b5e-4470-ae82-3aa2e512d8eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630449558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3630449558
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3049339243
Short name T127
Test name
Test status
Simulation time 89375200 ps
CPU time 3.29 seconds
Started Jul 28 07:25:27 PM PDT 24
Finished Jul 28 07:25:30 PM PDT 24
Peak memory 214184 kb
Host smart-b432f1af-5497-43ed-b4e3-46c99fde6d0e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049339243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3049339243
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2806198539
Short name T974
Test name
Test status
Simulation time 340095661 ps
CPU time 4.71 seconds
Started Jul 28 07:25:28 PM PDT 24
Finished Jul 28 07:25:33 PM PDT 24
Peak memory 214140 kb
Host smart-5f997036-0669-4c52-bf75-598644983a3a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806198539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.2806198539
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.4264733170
Short name T1064
Test name
Test status
Simulation time 300146991 ps
CPU time 2.33 seconds
Started Jul 28 07:25:27 PM PDT 24
Finished Jul 28 07:25:29 PM PDT 24
Peak memory 222020 kb
Host smart-ad568e06-a2f5-46df-b6c1-ce8e80a361f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264733170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.4264733170
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3705465818
Short name T161
Test name
Test status
Simulation time 185776129 ps
CPU time 2.71 seconds
Started Jul 28 07:25:26 PM PDT 24
Finished Jul 28 07:25:29 PM PDT 24
Peak memory 205796 kb
Host smart-0f427978-eaa9-4b7c-9875-6aab1206f9f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705465818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3705465818
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.178500145
Short name T1001
Test name
Test status
Simulation time 50279182 ps
CPU time 1.39 seconds
Started Jul 28 07:25:33 PM PDT 24
Finished Jul 28 07:25:35 PM PDT 24
Peak memory 213948 kb
Host smart-ec758080-8de3-48b6-8ab4-51d211d84070
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178500145 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.178500145
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2088085088
Short name T1007
Test name
Test status
Simulation time 23147651 ps
CPU time 0.96 seconds
Started Jul 28 07:25:32 PM PDT 24
Finished Jul 28 07:25:34 PM PDT 24
Peak memory 205460 kb
Host smart-b5012287-a1be-4d8d-9769-6274448c3a46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088085088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2088085088
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3098985056
Short name T986
Test name
Test status
Simulation time 26298935 ps
CPU time 0.73 seconds
Started Jul 28 07:25:32 PM PDT 24
Finished Jul 28 07:25:33 PM PDT 24
Peak memory 205380 kb
Host smart-143108bb-9e58-4d1b-8fa8-250a48b1497a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098985056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3098985056
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1749790887
Short name T1011
Test name
Test status
Simulation time 55665123 ps
CPU time 1.65 seconds
Started Jul 28 07:25:34 PM PDT 24
Finished Jul 28 07:25:35 PM PDT 24
Peak memory 205700 kb
Host smart-dd301fb6-c701-4e85-831c-7e09406d01e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749790887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1749790887
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1931644696
Short name T1084
Test name
Test status
Simulation time 266472732 ps
CPU time 2.36 seconds
Started Jul 28 07:25:26 PM PDT 24
Finished Jul 28 07:25:28 PM PDT 24
Peak memory 214100 kb
Host smart-adaed187-c38f-4a12-84b3-c3138d94cf71
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931644696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1931644696
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1850874225
Short name T1062
Test name
Test status
Simulation time 144515351 ps
CPU time 4.46 seconds
Started Jul 28 07:25:28 PM PDT 24
Finished Jul 28 07:25:32 PM PDT 24
Peak memory 214164 kb
Host smart-3ed73be1-977d-4fb7-970a-38b5292e2170
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850874225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1850874225
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.942872326
Short name T1033
Test name
Test status
Simulation time 432750916 ps
CPU time 2.91 seconds
Started Jul 28 07:25:27 PM PDT 24
Finished Jul 28 07:25:30 PM PDT 24
Peak memory 215984 kb
Host smart-7b0ca2d9-eef9-455e-9ba4-357588509e4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942872326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.942872326
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3983227154
Short name T172
Test name
Test status
Simulation time 530017959 ps
CPU time 7.01 seconds
Started Jul 28 07:25:25 PM PDT 24
Finished Jul 28 07:25:32 PM PDT 24
Peak memory 205644 kb
Host smart-a85b8b46-c1fe-47c8-804f-12ab2603b9c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983227154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3983227154
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1439806490
Short name T588
Test name
Test status
Simulation time 47182538 ps
CPU time 0.78 seconds
Started Jul 28 07:35:31 PM PDT 24
Finished Jul 28 07:35:32 PM PDT 24
Peak memory 205940 kb
Host smart-bebbb9f2-4187-4667-bedb-b10b316cfc39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439806490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1439806490
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.583278629
Short name T414
Test name
Test status
Simulation time 57866122 ps
CPU time 2.33 seconds
Started Jul 28 07:35:22 PM PDT 24
Finished Jul 28 07:35:24 PM PDT 24
Peak memory 214160 kb
Host smart-cefd3e2a-bb1d-493a-9296-ca63ab739367
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=583278629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.583278629
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.181706297
Short name T766
Test name
Test status
Simulation time 327557744 ps
CPU time 4.22 seconds
Started Jul 28 07:35:26 PM PDT 24
Finished Jul 28 07:35:30 PM PDT 24
Peak memory 214112 kb
Host smart-2b723489-54d1-482a-b4c7-af6fd264a6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181706297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.181706297
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1977583825
Short name T616
Test name
Test status
Simulation time 516673311 ps
CPU time 2.74 seconds
Started Jul 28 07:35:26 PM PDT 24
Finished Jul 28 07:35:29 PM PDT 24
Peak memory 214256 kb
Host smart-dcf93b1a-12bb-4f64-b5e4-7538fc9b4012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977583825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1977583825
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1212578484
Short name T849
Test name
Test status
Simulation time 177227963 ps
CPU time 3.39 seconds
Started Jul 28 07:35:28 PM PDT 24
Finished Jul 28 07:35:31 PM PDT 24
Peak memory 222256 kb
Host smart-eccc073b-d1c8-43cd-a06f-1b9b3decccd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212578484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1212578484
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.531883748
Short name T441
Test name
Test status
Simulation time 120723473 ps
CPU time 4.3 seconds
Started Jul 28 07:35:33 PM PDT 24
Finished Jul 28 07:35:38 PM PDT 24
Peak memory 206708 kb
Host smart-aecf593a-d53c-4733-acfa-24be4591afff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531883748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.531883748
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2748850237
Short name T260
Test name
Test status
Simulation time 276009751 ps
CPU time 3.68 seconds
Started Jul 28 07:35:24 PM PDT 24
Finished Jul 28 07:35:28 PM PDT 24
Peak memory 214212 kb
Host smart-dda5c4d7-0950-4155-bf7a-e63de03bf17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748850237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2748850237
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1778200874
Short name T13
Test name
Test status
Simulation time 1721795247 ps
CPU time 10.21 seconds
Started Jul 28 07:35:34 PM PDT 24
Finished Jul 28 07:35:44 PM PDT 24
Peak memory 230332 kb
Host smart-56a3018a-ec7b-413f-b446-9556cad5def9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778200874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1778200874
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1847037697
Short name T759
Test name
Test status
Simulation time 365670758 ps
CPU time 7.94 seconds
Started Jul 28 07:35:25 PM PDT 24
Finished Jul 28 07:35:33 PM PDT 24
Peak memory 207048 kb
Host smart-1fa2b670-db55-4509-9903-8cad3d56c031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847037697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1847037697
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3519588375
Short name T448
Test name
Test status
Simulation time 333969100 ps
CPU time 3.26 seconds
Started Jul 28 07:35:23 PM PDT 24
Finished Jul 28 07:35:26 PM PDT 24
Peak memory 208548 kb
Host smart-b8752fae-f7cd-470e-a106-95195288c097
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519588375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3519588375
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1081460400
Short name T644
Test name
Test status
Simulation time 499970727 ps
CPU time 6.49 seconds
Started Jul 28 07:35:25 PM PDT 24
Finished Jul 28 07:35:32 PM PDT 24
Peak memory 208804 kb
Host smart-f44a5211-252f-434f-9041-51fbcea7601a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081460400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1081460400
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2448387718
Short name T571
Test name
Test status
Simulation time 1297903340 ps
CPU time 6.18 seconds
Started Jul 28 07:35:25 PM PDT 24
Finished Jul 28 07:35:31 PM PDT 24
Peak memory 208464 kb
Host smart-bddb6d59-062f-4466-9f0e-2862fde13130
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448387718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2448387718
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.3217700651
Short name T433
Test name
Test status
Simulation time 2818182757 ps
CPU time 6.33 seconds
Started Jul 28 07:35:27 PM PDT 24
Finished Jul 28 07:35:34 PM PDT 24
Peak memory 209460 kb
Host smart-60e6ea72-606f-4ee4-8775-8314ac2a855a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217700651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3217700651
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3355969720
Short name T756
Test name
Test status
Simulation time 83952769 ps
CPU time 3.18 seconds
Started Jul 28 07:35:23 PM PDT 24
Finished Jul 28 07:35:26 PM PDT 24
Peak memory 208436 kb
Host smart-5c02aa72-e315-4b1c-bb41-90723d3ee992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355969720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3355969720
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.60269980
Short name T582
Test name
Test status
Simulation time 1181624465 ps
CPU time 16.08 seconds
Started Jul 28 07:35:34 PM PDT 24
Finished Jul 28 07:35:50 PM PDT 24
Peak memory 208404 kb
Host smart-3c4eedd1-4401-4197-aa34-72dedf90d9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60269980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.60269980
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1564434545
Short name T114
Test name
Test status
Simulation time 65982065 ps
CPU time 2.93 seconds
Started Jul 28 07:35:32 PM PDT 24
Finished Jul 28 07:35:35 PM PDT 24
Peak memory 210104 kb
Host smart-79522d42-1bca-4239-8be5-a9af07cab93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564434545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1564434545
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.166212597
Short name T596
Test name
Test status
Simulation time 19621787 ps
CPU time 0.89 seconds
Started Jul 28 07:35:30 PM PDT 24
Finished Jul 28 07:35:31 PM PDT 24
Peak memory 206008 kb
Host smart-8d2be644-0113-4797-983b-92fce5726f9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166212597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.166212597
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.18476208
Short name T670
Test name
Test status
Simulation time 622049713 ps
CPU time 4.72 seconds
Started Jul 28 07:35:32 PM PDT 24
Finished Jul 28 07:35:37 PM PDT 24
Peak memory 208996 kb
Host smart-1810cc4d-a9fb-4354-9661-f26850718735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18476208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.18476208
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3869620629
Short name T634
Test name
Test status
Simulation time 108123523 ps
CPU time 2.19 seconds
Started Jul 28 07:35:34 PM PDT 24
Finished Jul 28 07:35:36 PM PDT 24
Peak memory 214168 kb
Host smart-c9da606c-4e0b-4186-be91-6a515222c258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869620629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3869620629
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2714901318
Short name T97
Test name
Test status
Simulation time 107674823 ps
CPU time 3.14 seconds
Started Jul 28 07:35:28 PM PDT 24
Finished Jul 28 07:35:31 PM PDT 24
Peak memory 208632 kb
Host smart-2c650f87-eb9f-4ca9-98ce-1da90215032f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714901318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2714901318
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3682536143
Short name T210
Test name
Test status
Simulation time 204809389 ps
CPU time 3.55 seconds
Started Jul 28 07:35:30 PM PDT 24
Finished Jul 28 07:35:33 PM PDT 24
Peak memory 219656 kb
Host smart-65b07c77-d162-4e3b-9b14-76184c4a99bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682536143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3682536143
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1201289668
Short name T617
Test name
Test status
Simulation time 567210611 ps
CPU time 6.74 seconds
Started Jul 28 07:35:30 PM PDT 24
Finished Jul 28 07:35:37 PM PDT 24
Peak memory 214064 kb
Host smart-d514a66c-4cc0-4778-ba7f-857cb12d3c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201289668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1201289668
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1260526071
Short name T104
Test name
Test status
Simulation time 440266987 ps
CPU time 10.4 seconds
Started Jul 28 07:35:35 PM PDT 24
Finished Jul 28 07:35:45 PM PDT 24
Peak memory 230420 kb
Host smart-e375155b-9b00-4f79-b9e3-2754845c9474
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260526071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1260526071
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1772257017
Short name T609
Test name
Test status
Simulation time 348142483 ps
CPU time 4.33 seconds
Started Jul 28 07:35:30 PM PDT 24
Finished Jul 28 07:35:35 PM PDT 24
Peak memory 208544 kb
Host smart-542e0804-8f40-4f87-9c9a-1c89042a7d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772257017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1772257017
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2907786213
Short name T840
Test name
Test status
Simulation time 231315159 ps
CPU time 3.71 seconds
Started Jul 28 07:35:37 PM PDT 24
Finished Jul 28 07:35:41 PM PDT 24
Peak memory 208756 kb
Host smart-ac371aa2-56f8-4bbc-b17d-ada6b2d4ccd2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907786213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2907786213
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.941360863
Short name T462
Test name
Test status
Simulation time 1178425179 ps
CPU time 9.91 seconds
Started Jul 28 07:35:26 PM PDT 24
Finished Jul 28 07:35:36 PM PDT 24
Peak memory 208932 kb
Host smart-099a356c-ef41-4a64-a578-2beac0ca6f11
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941360863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.941360863
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.583158976
Short name T736
Test name
Test status
Simulation time 63472141 ps
CPU time 1.92 seconds
Started Jul 28 07:35:30 PM PDT 24
Finished Jul 28 07:35:32 PM PDT 24
Peak memory 207936 kb
Host smart-904c8ccf-48e8-4759-9aa8-ba4cc1e1d1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583158976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.583158976
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1416225965
Short name T436
Test name
Test status
Simulation time 787882829 ps
CPU time 16.43 seconds
Started Jul 28 07:35:27 PM PDT 24
Finished Jul 28 07:35:44 PM PDT 24
Peak memory 207980 kb
Host smart-a167fcc4-f6d5-4261-8d3a-c4c0676bf6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416225965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1416225965
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2984923536
Short name T279
Test name
Test status
Simulation time 11478263883 ps
CPU time 102.67 seconds
Started Jul 28 07:35:28 PM PDT 24
Finished Jul 28 07:37:11 PM PDT 24
Peak memory 217012 kb
Host smart-410c93bc-5e00-4703-920e-a0f79617b2bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984923536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2984923536
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.807426450
Short name T56
Test name
Test status
Simulation time 1567156338 ps
CPU time 22.97 seconds
Started Jul 28 07:35:29 PM PDT 24
Finished Jul 28 07:35:52 PM PDT 24
Peak memory 222412 kb
Host smart-250a55be-b901-43e8-9cd5-eabec15e3462
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807426450 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.807426450
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3574630150
Short name T888
Test name
Test status
Simulation time 351117618 ps
CPU time 4.64 seconds
Started Jul 28 07:35:32 PM PDT 24
Finished Jul 28 07:35:37 PM PDT 24
Peak memory 207052 kb
Host smart-f4ef7141-940a-4c58-a6f0-acea4ffd29e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574630150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3574630150
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.576968491
Short name T504
Test name
Test status
Simulation time 165285148 ps
CPU time 1.67 seconds
Started Jul 28 07:35:30 PM PDT 24
Finished Jul 28 07:35:32 PM PDT 24
Peak memory 209892 kb
Host smart-78f50498-b641-42b9-9d20-3ec7e65b851d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576968491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.576968491
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2973845448
Short name T606
Test name
Test status
Simulation time 32499744 ps
CPU time 0.83 seconds
Started Jul 28 07:35:59 PM PDT 24
Finished Jul 28 07:36:00 PM PDT 24
Peak memory 205888 kb
Host smart-e21a5f19-2863-4da9-ba62-b5bcc075ebcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973845448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2973845448
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.4245847228
Short name T871
Test name
Test status
Simulation time 185423723 ps
CPU time 6.63 seconds
Started Jul 28 07:35:59 PM PDT 24
Finished Jul 28 07:36:06 PM PDT 24
Peak memory 208576 kb
Host smart-8e5ff056-b61e-45e7-ae85-62e2037fab74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245847228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.4245847228
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1059765851
Short name T681
Test name
Test status
Simulation time 90164554 ps
CPU time 2.67 seconds
Started Jul 28 07:36:00 PM PDT 24
Finished Jul 28 07:36:03 PM PDT 24
Peak memory 208540 kb
Host smart-fa7d33ca-0a19-42d1-b146-7481d08de256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059765851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1059765851
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2846081263
Short name T243
Test name
Test status
Simulation time 80271220 ps
CPU time 1.55 seconds
Started Jul 28 07:35:58 PM PDT 24
Finished Jul 28 07:36:00 PM PDT 24
Peak memory 214136 kb
Host smart-0fb2b8b0-f20d-4460-baa3-1edbe5c8a4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846081263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2846081263
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.26383588
Short name T561
Test name
Test status
Simulation time 122852966 ps
CPU time 2.59 seconds
Started Jul 28 07:35:59 PM PDT 24
Finished Jul 28 07:36:01 PM PDT 24
Peak memory 214084 kb
Host smart-0aef1ae7-d1b3-416b-8bfa-aa8c1a7ccf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26383588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.26383588
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_random.3964056998
Short name T706
Test name
Test status
Simulation time 169325929 ps
CPU time 5.2 seconds
Started Jul 28 07:36:01 PM PDT 24
Finished Jul 28 07:36:07 PM PDT 24
Peak memory 207712 kb
Host smart-0ad380f7-d297-4bf2-9454-339eb92963af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964056998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3964056998
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1926167703
Short name T809
Test name
Test status
Simulation time 145002016 ps
CPU time 1.71 seconds
Started Jul 28 07:35:59 PM PDT 24
Finished Jul 28 07:36:01 PM PDT 24
Peak memory 206776 kb
Host smart-7f39012c-b626-43dd-a815-a9fba42a1b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926167703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1926167703
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3997792747
Short name T581
Test name
Test status
Simulation time 121946490 ps
CPU time 3.27 seconds
Started Jul 28 07:36:02 PM PDT 24
Finished Jul 28 07:36:06 PM PDT 24
Peak memory 208520 kb
Host smart-e2352218-d321-43f1-9f6e-4e722054e730
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997792747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3997792747
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1402396119
Short name T760
Test name
Test status
Simulation time 246946009 ps
CPU time 5.77 seconds
Started Jul 28 07:35:56 PM PDT 24
Finished Jul 28 07:36:02 PM PDT 24
Peak memory 206792 kb
Host smart-238f3465-302e-4406-b476-f5e71b3b0a3e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402396119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1402396119
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3461142029
Short name T502
Test name
Test status
Simulation time 215853551 ps
CPU time 2.31 seconds
Started Jul 28 07:36:00 PM PDT 24
Finished Jul 28 07:36:02 PM PDT 24
Peak memory 207948 kb
Host smart-4a62e0c5-6756-4448-ac80-cf2e16589d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461142029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3461142029
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2602657233
Short name T702
Test name
Test status
Simulation time 218442596 ps
CPU time 4.89 seconds
Started Jul 28 07:35:58 PM PDT 24
Finished Jul 28 07:36:03 PM PDT 24
Peak memory 208092 kb
Host smart-593a576b-5d0d-43a4-8d2d-6dd069b4ff2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602657233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2602657233
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3337654893
Short name T728
Test name
Test status
Simulation time 327166822 ps
CPU time 3.95 seconds
Started Jul 28 07:35:58 PM PDT 24
Finished Jul 28 07:36:03 PM PDT 24
Peak memory 207692 kb
Host smart-9eb4f5cf-2e4e-4b55-b4ae-5d9939ab1e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337654893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3337654893
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3957594087
Short name T903
Test name
Test status
Simulation time 33277985 ps
CPU time 0.74 seconds
Started Jul 28 07:36:06 PM PDT 24
Finished Jul 28 07:36:07 PM PDT 24
Peak memory 205816 kb
Host smart-69cba3ef-8dc0-43e0-993b-eb6c3c907a70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957594087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3957594087
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3298317936
Short name T659
Test name
Test status
Simulation time 105608988 ps
CPU time 2.71 seconds
Started Jul 28 07:36:00 PM PDT 24
Finished Jul 28 07:36:03 PM PDT 24
Peak memory 214152 kb
Host smart-39f602df-4306-472c-86d5-6c3dc4aef9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298317936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3298317936
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.176914507
Short name T625
Test name
Test status
Simulation time 1817379462 ps
CPU time 3.16 seconds
Started Jul 28 07:36:00 PM PDT 24
Finished Jul 28 07:36:03 PM PDT 24
Peak memory 222292 kb
Host smart-995f7b68-9655-43d4-8aa2-0ed7f08fddcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176914507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.176914507
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2414863579
Short name T331
Test name
Test status
Simulation time 125207115 ps
CPU time 3.28 seconds
Started Jul 28 07:35:59 PM PDT 24
Finished Jul 28 07:36:02 PM PDT 24
Peak memory 214072 kb
Host smart-1baf810f-f680-445a-9c40-77a15f9b52dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414863579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2414863579
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3850041435
Short name T174
Test name
Test status
Simulation time 125446648 ps
CPU time 2.09 seconds
Started Jul 28 07:36:07 PM PDT 24
Finished Jul 28 07:36:10 PM PDT 24
Peak memory 219560 kb
Host smart-aaa23e07-7c41-42c7-8572-0fcf45eaf57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850041435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3850041435
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3419914296
Short name T16
Test name
Test status
Simulation time 238769687 ps
CPU time 5.31 seconds
Started Jul 28 07:36:00 PM PDT 24
Finished Jul 28 07:36:06 PM PDT 24
Peak memory 209028 kb
Host smart-68a1ebbc-df9c-4e86-92fc-43cd971d06f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419914296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3419914296
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.171513357
Short name T475
Test name
Test status
Simulation time 253106584 ps
CPU time 2.9 seconds
Started Jul 28 07:36:01 PM PDT 24
Finished Jul 28 07:36:04 PM PDT 24
Peak memory 208160 kb
Host smart-8e94d974-0cf2-49fc-8980-668d3d61edcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171513357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.171513357
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2801682345
Short name T329
Test name
Test status
Simulation time 10516230908 ps
CPU time 31.87 seconds
Started Jul 28 07:36:07 PM PDT 24
Finished Jul 28 07:36:39 PM PDT 24
Peak memory 207892 kb
Host smart-945226fa-7697-4350-b357-20afc2ed4e12
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801682345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2801682345
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3608362764
Short name T862
Test name
Test status
Simulation time 881367830 ps
CPU time 20.36 seconds
Started Jul 28 07:36:07 PM PDT 24
Finished Jul 28 07:36:27 PM PDT 24
Peak memory 208016 kb
Host smart-a602f199-1c80-46e4-acad-fa1216970263
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608362764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3608362764
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.856326490
Short name T570
Test name
Test status
Simulation time 876701438 ps
CPU time 6.69 seconds
Started Jul 28 07:35:59 PM PDT 24
Finished Jul 28 07:36:05 PM PDT 24
Peak memory 206796 kb
Host smart-dddff58a-5cdf-43a5-a574-b5ba50a36e3e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856326490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.856326490
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1865061230
Short name T195
Test name
Test status
Simulation time 279811822 ps
CPU time 3.7 seconds
Started Jul 28 07:36:06 PM PDT 24
Finished Jul 28 07:36:10 PM PDT 24
Peak memory 209820 kb
Host smart-d28cd115-d74b-404b-af17-b80c68f7277f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865061230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1865061230
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3020870584
Short name T531
Test name
Test status
Simulation time 142071859 ps
CPU time 3.05 seconds
Started Jul 28 07:36:01 PM PDT 24
Finished Jul 28 07:36:04 PM PDT 24
Peak memory 206744 kb
Host smart-28864c99-f39e-4ac5-bb3a-63b61d987833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020870584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3020870584
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3523128794
Short name T336
Test name
Test status
Simulation time 2681335592 ps
CPU time 15.69 seconds
Started Jul 28 07:36:07 PM PDT 24
Finished Jul 28 07:36:23 PM PDT 24
Peak memory 219444 kb
Host smart-bf6c2f89-4b9d-4ccd-9665-1ae84fb72e91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523128794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3523128794
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3533579274
Short name T884
Test name
Test status
Simulation time 4531805863 ps
CPU time 17.06 seconds
Started Jul 28 07:36:08 PM PDT 24
Finished Jul 28 07:36:26 PM PDT 24
Peak memory 222804 kb
Host smart-ba3e6a4f-dd10-44fb-8e06-1e234d72031d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533579274 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3533579274
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3086564705
Short name T802
Test name
Test status
Simulation time 895525249 ps
CPU time 6.92 seconds
Started Jul 28 07:36:01 PM PDT 24
Finished Jul 28 07:36:08 PM PDT 24
Peak memory 208824 kb
Host smart-e903fc05-17eb-47c0-b937-beb313493224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086564705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3086564705
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.4252573199
Short name T59
Test name
Test status
Simulation time 76171364 ps
CPU time 2.88 seconds
Started Jul 28 07:36:09 PM PDT 24
Finished Jul 28 07:36:12 PM PDT 24
Peak memory 209708 kb
Host smart-b6592638-644b-4159-94f3-d5a85080032a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252573199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.4252573199
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2984796240
Short name T792
Test name
Test status
Simulation time 9454657 ps
CPU time 0.74 seconds
Started Jul 28 07:36:09 PM PDT 24
Finished Jul 28 07:36:10 PM PDT 24
Peak memory 205928 kb
Host smart-575e2afc-bbd3-4c53-a3a9-42eb281e5371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984796240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2984796240
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1014544985
Short name T305
Test name
Test status
Simulation time 85228183 ps
CPU time 2.4 seconds
Started Jul 28 07:36:09 PM PDT 24
Finished Jul 28 07:36:12 PM PDT 24
Peak memory 207436 kb
Host smart-b8b61d15-bc9f-4a69-b420-cdc6116ad637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014544985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1014544985
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2245394495
Short name T308
Test name
Test status
Simulation time 1145427275 ps
CPU time 26.82 seconds
Started Jul 28 07:36:09 PM PDT 24
Finished Jul 28 07:36:36 PM PDT 24
Peak memory 214120 kb
Host smart-e8216378-3fc5-4fb7-aacf-ec021d86de5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245394495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2245394495
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.314043101
Short name T813
Test name
Test status
Simulation time 393600734 ps
CPU time 11.54 seconds
Started Jul 28 07:36:07 PM PDT 24
Finished Jul 28 07:36:19 PM PDT 24
Peak memory 222168 kb
Host smart-9c7a6053-bc05-4c54-9558-fed56346ad44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314043101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.314043101
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3716603515
Short name T410
Test name
Test status
Simulation time 193839310 ps
CPU time 3.18 seconds
Started Jul 28 07:36:06 PM PDT 24
Finished Jul 28 07:36:09 PM PDT 24
Peak memory 205888 kb
Host smart-8bf7123a-d17d-40c0-a1c1-80ff83a6a2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716603515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3716603515
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3951640762
Short name T293
Test name
Test status
Simulation time 55557332 ps
CPU time 3.13 seconds
Started Jul 28 07:36:05 PM PDT 24
Finished Jul 28 07:36:09 PM PDT 24
Peak memory 207364 kb
Host smart-59c8ea8f-97bc-4b13-b72c-ff6ba83b6b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951640762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3951640762
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3427610213
Short name T535
Test name
Test status
Simulation time 60137733 ps
CPU time 2.89 seconds
Started Jul 28 07:36:06 PM PDT 24
Finished Jul 28 07:36:09 PM PDT 24
Peak memory 206848 kb
Host smart-b29b1f8d-2e8a-47fc-a939-a62965d1d2e6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427610213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3427610213
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.4240275117
Short name T233
Test name
Test status
Simulation time 165831729 ps
CPU time 3.33 seconds
Started Jul 28 07:36:06 PM PDT 24
Finished Jul 28 07:36:10 PM PDT 24
Peak memory 208720 kb
Host smart-ad057528-a24d-460c-b69f-e88877d49b1d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240275117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.4240275117
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.2111861567
Short name T349
Test name
Test status
Simulation time 175540583 ps
CPU time 5.98 seconds
Started Jul 28 07:36:06 PM PDT 24
Finished Jul 28 07:36:12 PM PDT 24
Peak memory 206772 kb
Host smart-9014b37b-d9eb-4a31-9a95-c6cef315d33d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111861567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2111861567
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.396729269
Short name T341
Test name
Test status
Simulation time 27152713 ps
CPU time 2.16 seconds
Started Jul 28 07:36:07 PM PDT 24
Finished Jul 28 07:36:09 PM PDT 24
Peak memory 218204 kb
Host smart-c727cde4-e227-4425-9f89-db1608a081e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396729269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.396729269
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2959405882
Short name T622
Test name
Test status
Simulation time 222820880 ps
CPU time 4.6 seconds
Started Jul 28 07:36:10 PM PDT 24
Finished Jul 28 07:36:15 PM PDT 24
Peak memory 206500 kb
Host smart-c48b9374-e49c-4fbf-8785-5e696d22349f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959405882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2959405882
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.294906028
Short name T253
Test name
Test status
Simulation time 492376122 ps
CPU time 12.94 seconds
Started Jul 28 07:36:09 PM PDT 24
Finished Jul 28 07:36:23 PM PDT 24
Peak memory 222284 kb
Host smart-7879a67d-c495-430f-be22-6344625f1288
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294906028 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.294906028
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3920282287
Short name T479
Test name
Test status
Simulation time 12919831991 ps
CPU time 60.79 seconds
Started Jul 28 07:36:08 PM PDT 24
Finished Jul 28 07:37:09 PM PDT 24
Peak memory 214192 kb
Host smart-7498b59d-28fe-4cff-806c-b2f169947a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920282287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3920282287
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.71263389
Short name T173
Test name
Test status
Simulation time 110445954 ps
CPU time 2.06 seconds
Started Jul 28 07:36:05 PM PDT 24
Finished Jul 28 07:36:07 PM PDT 24
Peak memory 210024 kb
Host smart-54fd2261-17df-49fc-b8d2-7a7103d23f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71263389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.71263389
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2810532303
Short name T642
Test name
Test status
Simulation time 22378115 ps
CPU time 0.78 seconds
Started Jul 28 07:36:11 PM PDT 24
Finished Jul 28 07:36:12 PM PDT 24
Peak memory 205852 kb
Host smart-30b92853-528c-4b17-82a9-3638677d83f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810532303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2810532303
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3320264473
Short name T400
Test name
Test status
Simulation time 684804193 ps
CPU time 10.17 seconds
Started Jul 28 07:36:12 PM PDT 24
Finished Jul 28 07:36:23 PM PDT 24
Peak memory 214096 kb
Host smart-6d16d182-7ccb-4a81-b3c9-c8c7cf553f19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3320264473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3320264473
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3219875451
Short name T509
Test name
Test status
Simulation time 46022651 ps
CPU time 2.22 seconds
Started Jul 28 07:36:12 PM PDT 24
Finished Jul 28 07:36:14 PM PDT 24
Peak memory 209648 kb
Host smart-ce8be1c3-9ad4-413c-817b-ba26762ec15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219875451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3219875451
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1789988973
Short name T267
Test name
Test status
Simulation time 41149198 ps
CPU time 2.18 seconds
Started Jul 28 07:36:12 PM PDT 24
Finished Jul 28 07:36:14 PM PDT 24
Peak memory 214168 kb
Host smart-ef7850f8-bd6e-45a7-b5fc-de1af37ea516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789988973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1789988973
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1257976868
Short name T35
Test name
Test status
Simulation time 372095506 ps
CPU time 3.13 seconds
Started Jul 28 07:36:09 PM PDT 24
Finished Jul 28 07:36:12 PM PDT 24
Peak memory 214108 kb
Host smart-e338ca54-294a-4d23-82da-556cad3e0855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257976868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1257976868
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.197870657
Short name T43
Test name
Test status
Simulation time 94617221 ps
CPU time 2.82 seconds
Started Jul 28 07:36:10 PM PDT 24
Finished Jul 28 07:36:13 PM PDT 24
Peak memory 217896 kb
Host smart-e12bd59e-e69f-42ad-aaa5-8aa5e331e237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197870657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.197870657
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3394345412
Short name T685
Test name
Test status
Simulation time 271653987 ps
CPU time 5.65 seconds
Started Jul 28 07:36:16 PM PDT 24
Finished Jul 28 07:36:21 PM PDT 24
Peak memory 209960 kb
Host smart-9fdb7029-04fd-4717-a252-542edaeb431d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394345412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3394345412
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2572131752
Short name T427
Test name
Test status
Simulation time 255031924 ps
CPU time 4.12 seconds
Started Jul 28 07:36:12 PM PDT 24
Finished Jul 28 07:36:16 PM PDT 24
Peak memory 206816 kb
Host smart-0d369f87-5e49-479d-88d0-d7b872b133db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572131752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2572131752
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2527901228
Short name T718
Test name
Test status
Simulation time 279135114 ps
CPU time 3.91 seconds
Started Jul 28 07:36:12 PM PDT 24
Finished Jul 28 07:36:16 PM PDT 24
Peak memory 206812 kb
Host smart-5114b037-c307-4b00-8fb8-ef49ab39faa2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527901228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2527901228
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.182385492
Short name T544
Test name
Test status
Simulation time 356066888 ps
CPU time 2.55 seconds
Started Jul 28 07:36:11 PM PDT 24
Finished Jul 28 07:36:14 PM PDT 24
Peak memory 206664 kb
Host smart-c828d93a-fda0-48b6-b0c2-8ad5fb9783e2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182385492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.182385492
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3940206551
Short name T835
Test name
Test status
Simulation time 570154725 ps
CPU time 19.94 seconds
Started Jul 28 07:36:11 PM PDT 24
Finished Jul 28 07:36:31 PM PDT 24
Peak memory 208636 kb
Host smart-548076cb-88cf-40f2-a482-b52b68c3017e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940206551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3940206551
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.1065466218
Short name T739
Test name
Test status
Simulation time 168232244 ps
CPU time 1.54 seconds
Started Jul 28 07:36:07 PM PDT 24
Finished Jul 28 07:36:09 PM PDT 24
Peak memory 208156 kb
Host smart-2bdeb34b-1e8b-4ea8-bb30-ecef1897abf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065466218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1065466218
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2574759572
Short name T573
Test name
Test status
Simulation time 24634335 ps
CPU time 1.96 seconds
Started Jul 28 07:36:09 PM PDT 24
Finished Jul 28 07:36:11 PM PDT 24
Peak memory 208136 kb
Host smart-eb73f525-8033-48c9-ba8e-a510e6a3866c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574759572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2574759572
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3729874414
Short name T75
Test name
Test status
Simulation time 1025105447 ps
CPU time 20.38 seconds
Started Jul 28 07:36:16 PM PDT 24
Finished Jul 28 07:36:37 PM PDT 24
Peak memory 219568 kb
Host smart-7209ab9a-bf8c-455a-add6-cd3536bfbe11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729874414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3729874414
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2830590148
Short name T482
Test name
Test status
Simulation time 436489562 ps
CPU time 8.1 seconds
Started Jul 28 07:36:11 PM PDT 24
Finished Jul 28 07:36:20 PM PDT 24
Peak memory 209048 kb
Host smart-7fb8d3fa-12fc-41b3-a0ad-f9de54953890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830590148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2830590148
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2075931381
Short name T166
Test name
Test status
Simulation time 132554192 ps
CPU time 2.99 seconds
Started Jul 28 07:36:10 PM PDT 24
Finished Jul 28 07:36:13 PM PDT 24
Peak memory 210260 kb
Host smart-e2a926fa-9b98-471a-bba7-2a850c1bfa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075931381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2075931381
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.2853770385
Short name T746
Test name
Test status
Simulation time 8141295 ps
CPU time 0.72 seconds
Started Jul 28 07:36:17 PM PDT 24
Finished Jul 28 07:36:18 PM PDT 24
Peak memory 205792 kb
Host smart-8e83566a-d47c-466b-a640-a09adff13f4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853770385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2853770385
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1904343676
Short name T299
Test name
Test status
Simulation time 41719062 ps
CPU time 3 seconds
Started Jul 28 07:36:11 PM PDT 24
Finished Jul 28 07:36:14 PM PDT 24
Peak memory 214196 kb
Host smart-16affd77-01da-4c75-9db9-87410508f7f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1904343676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1904343676
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2541565905
Short name T807
Test name
Test status
Simulation time 279119944 ps
CPU time 4.22 seconds
Started Jul 28 07:36:17 PM PDT 24
Finished Jul 28 07:36:21 PM PDT 24
Peak memory 217476 kb
Host smart-c43c7c83-8ec1-4d9e-84d3-5d633ac55ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541565905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2541565905
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.981509039
Short name T701
Test name
Test status
Simulation time 1239126349 ps
CPU time 3.61 seconds
Started Jul 28 07:36:14 PM PDT 24
Finished Jul 28 07:36:18 PM PDT 24
Peak memory 209840 kb
Host smart-ac23a4b1-22bb-4f7f-adcb-964229cc5d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981509039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.981509039
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3764482830
Short name T96
Test name
Test status
Simulation time 143559770 ps
CPU time 2.78 seconds
Started Jul 28 07:36:16 PM PDT 24
Finished Jul 28 07:36:19 PM PDT 24
Peak memory 214208 kb
Host smart-ab3eca1c-c2bf-4ff5-b1a7-eb60965154b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764482830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3764482830
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2693995541
Short name T758
Test name
Test status
Simulation time 320602345 ps
CPU time 3.82 seconds
Started Jul 28 07:36:17 PM PDT 24
Finished Jul 28 07:36:21 PM PDT 24
Peak memory 214088 kb
Host smart-19d1bff2-9630-4561-833a-959fcd65e863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693995541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2693995541
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2927698633
Short name T846
Test name
Test status
Simulation time 106040528 ps
CPU time 4.27 seconds
Started Jul 28 07:36:14 PM PDT 24
Finished Jul 28 07:36:18 PM PDT 24
Peak memory 210436 kb
Host smart-733bb6a3-597e-47cc-9a4c-fd3bf2dfe707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927698633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2927698633
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3671706151
Short name T677
Test name
Test status
Simulation time 151278720 ps
CPU time 5.24 seconds
Started Jul 28 07:36:11 PM PDT 24
Finished Jul 28 07:36:16 PM PDT 24
Peak memory 207212 kb
Host smart-b0ef37a7-cc89-4c6d-b7fb-792624a5aec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671706151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3671706151
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.407439390
Short name T709
Test name
Test status
Simulation time 557466175 ps
CPU time 3.28 seconds
Started Jul 28 07:36:11 PM PDT 24
Finished Jul 28 07:36:14 PM PDT 24
Peak memory 208424 kb
Host smart-e9906f5d-0de3-47e5-8f29-ea63e0513e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407439390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.407439390
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3638165787
Short name T460
Test name
Test status
Simulation time 304278877 ps
CPU time 3.59 seconds
Started Jul 28 07:36:11 PM PDT 24
Finished Jul 28 07:36:14 PM PDT 24
Peak memory 208604 kb
Host smart-b7a53ab2-9f77-400b-ab6c-3e39be2de7e0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638165787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3638165787
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.964178285
Short name T658
Test name
Test status
Simulation time 196772011 ps
CPU time 2.93 seconds
Started Jul 28 07:36:11 PM PDT 24
Finished Jul 28 07:36:14 PM PDT 24
Peak memory 206684 kb
Host smart-56adcba0-9c9e-4f6c-9db9-3fc6993aaa94
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964178285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.964178285
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3840577041
Short name T537
Test name
Test status
Simulation time 336245818 ps
CPU time 9.04 seconds
Started Jul 28 07:36:10 PM PDT 24
Finished Jul 28 07:36:19 PM PDT 24
Peak memory 208412 kb
Host smart-e9d0b341-1c83-4b19-8d4b-e08a5470a198
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840577041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3840577041
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1835358673
Short name T558
Test name
Test status
Simulation time 29507343 ps
CPU time 2.01 seconds
Started Jul 28 07:36:14 PM PDT 24
Finished Jul 28 07:36:16 PM PDT 24
Peak memory 207116 kb
Host smart-ae70408d-4f72-4a68-9570-9982fbfbd750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835358673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1835358673
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.444282839
Short name T399
Test name
Test status
Simulation time 267898108 ps
CPU time 3.46 seconds
Started Jul 28 07:36:10 PM PDT 24
Finished Jul 28 07:36:14 PM PDT 24
Peak memory 208228 kb
Host smart-32c8e98e-7378-43fa-a223-d970e95f2065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444282839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.444282839
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.3084186231
Short name T671
Test name
Test status
Simulation time 3019929887 ps
CPU time 30.25 seconds
Started Jul 28 07:36:15 PM PDT 24
Finished Jul 28 07:36:45 PM PDT 24
Peak memory 216600 kb
Host smart-48bdb9b0-4092-474d-a71c-ae40ff3f8446
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084186231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3084186231
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.3698939257
Short name T889
Test name
Test status
Simulation time 348720614 ps
CPU time 19.77 seconds
Started Jul 28 07:36:17 PM PDT 24
Finished Jul 28 07:36:37 PM PDT 24
Peak memory 222332 kb
Host smart-5b9019b6-c2b7-49ee-858e-4dcf6716953b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698939257 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.3698939257
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.979522459
Short name T135
Test name
Test status
Simulation time 397667704 ps
CPU time 9.6 seconds
Started Jul 28 07:36:14 PM PDT 24
Finished Jul 28 07:36:23 PM PDT 24
Peak memory 208656 kb
Host smart-457257e6-d719-4f81-99a4-afc95aa86a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979522459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.979522459
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.2229330948
Short name T619
Test name
Test status
Simulation time 31452495 ps
CPU time 1.12 seconds
Started Jul 28 07:36:22 PM PDT 24
Finished Jul 28 07:36:23 PM PDT 24
Peak memory 205884 kb
Host smart-1f03a751-b57e-4291-bcc6-e9b9c6cdb3c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229330948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2229330948
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2198857897
Short name T404
Test name
Test status
Simulation time 83577134 ps
CPU time 4.85 seconds
Started Jul 28 07:36:16 PM PDT 24
Finished Jul 28 07:36:21 PM PDT 24
Peak memory 215268 kb
Host smart-c64f29c0-655e-42b2-ad0b-99519df20a59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2198857897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2198857897
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1134784224
Short name T629
Test name
Test status
Simulation time 23954424 ps
CPU time 1.91 seconds
Started Jul 28 07:36:18 PM PDT 24
Finished Jul 28 07:36:20 PM PDT 24
Peak memory 207064 kb
Host smart-4f371d73-4595-4bd7-b95a-a8c63830d301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134784224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1134784224
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2212668407
Short name T494
Test name
Test status
Simulation time 72751049 ps
CPU time 2.95 seconds
Started Jul 28 07:36:17 PM PDT 24
Finished Jul 28 07:36:20 PM PDT 24
Peak memory 214076 kb
Host smart-619837e1-15c4-49b9-ab1e-0bbdb47b0e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212668407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2212668407
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.269916813
Short name T416
Test name
Test status
Simulation time 85053433 ps
CPU time 3.63 seconds
Started Jul 28 07:36:17 PM PDT 24
Finished Jul 28 07:36:21 PM PDT 24
Peak memory 220268 kb
Host smart-a255aeee-59b2-415f-b95a-cdedb3829545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269916813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.269916813
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.4147040646
Short name T683
Test name
Test status
Simulation time 1398026697 ps
CPU time 14.94 seconds
Started Jul 28 07:36:16 PM PDT 24
Finished Jul 28 07:36:31 PM PDT 24
Peak memory 214208 kb
Host smart-ed717143-8df9-4fef-a45d-334817741b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147040646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.4147040646
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.352958375
Short name T258
Test name
Test status
Simulation time 188411751 ps
CPU time 2.77 seconds
Started Jul 28 07:36:18 PM PDT 24
Finished Jul 28 07:36:21 PM PDT 24
Peak memory 206540 kb
Host smart-4f4c2f8a-013b-45cf-b5e2-d2d79d3b3db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352958375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.352958375
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2742920467
Short name T767
Test name
Test status
Simulation time 1805442208 ps
CPU time 11.96 seconds
Started Jul 28 07:36:17 PM PDT 24
Finished Jul 28 07:36:29 PM PDT 24
Peak memory 208340 kb
Host smart-96ed2065-2b4e-4f11-b5e3-849eed25d79e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742920467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2742920467
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2237843872
Short name T626
Test name
Test status
Simulation time 283083157 ps
CPU time 3.14 seconds
Started Jul 28 07:36:16 PM PDT 24
Finished Jul 28 07:36:19 PM PDT 24
Peak memory 208292 kb
Host smart-9a969efb-13c5-4fab-a68f-fd6cd86615d2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237843872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2237843872
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3560969647
Short name T708
Test name
Test status
Simulation time 9919317295 ps
CPU time 25.35 seconds
Started Jul 28 07:36:18 PM PDT 24
Finished Jul 28 07:36:44 PM PDT 24
Peak memory 206316 kb
Host smart-f127a867-2438-4d3d-a880-a37e9c935ca2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560969647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3560969647
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3238870361
Short name T106
Test name
Test status
Simulation time 204629633 ps
CPU time 2.05 seconds
Started Jul 28 07:36:15 PM PDT 24
Finished Jul 28 07:36:17 PM PDT 24
Peak memory 208012 kb
Host smart-088674e0-1562-4e21-9e8d-9b25c7240823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238870361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3238870361
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1543216576
Short name T815
Test name
Test status
Simulation time 56017395 ps
CPU time 2.16 seconds
Started Jul 28 07:36:16 PM PDT 24
Finished Jul 28 07:36:18 PM PDT 24
Peak memory 206680 kb
Host smart-78567454-242a-40c8-806b-eb024c1754f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543216576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1543216576
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.150508311
Short name T80
Test name
Test status
Simulation time 157793336 ps
CPU time 3.73 seconds
Started Jul 28 07:36:17 PM PDT 24
Finished Jul 28 07:36:21 PM PDT 24
Peak memory 214156 kb
Host smart-c55c7762-d3b8-4bfb-b6ff-e1b1c1125e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150508311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.150508311
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.151188953
Short name T653
Test name
Test status
Simulation time 560385445 ps
CPU time 2.65 seconds
Started Jul 28 07:36:16 PM PDT 24
Finished Jul 28 07:36:19 PM PDT 24
Peak memory 209688 kb
Host smart-5c62ae29-24db-45a6-a62b-f765fd80902a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151188953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.151188953
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.220152635
Short name T628
Test name
Test status
Simulation time 79538217 ps
CPU time 0.79 seconds
Started Jul 28 07:36:30 PM PDT 24
Finished Jul 28 07:36:31 PM PDT 24
Peak memory 205884 kb
Host smart-4de731f9-4549-4151-aaac-81f284a957e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220152635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.220152635
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2605295879
Short name T74
Test name
Test status
Simulation time 247161065 ps
CPU time 3.13 seconds
Started Jul 28 07:36:20 PM PDT 24
Finished Jul 28 07:36:24 PM PDT 24
Peak memory 214156 kb
Host smart-48e5d156-7b00-4925-9911-a6278373ae04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605295879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2605295879
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2301411304
Short name T335
Test name
Test status
Simulation time 325136157 ps
CPU time 2.74 seconds
Started Jul 28 07:36:27 PM PDT 24
Finished Jul 28 07:36:30 PM PDT 24
Peak memory 222160 kb
Host smart-5f926d0d-e8df-40ab-a461-9f4da4b15423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301411304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2301411304
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2133307524
Short name T583
Test name
Test status
Simulation time 159396780 ps
CPU time 1.98 seconds
Started Jul 28 07:36:23 PM PDT 24
Finished Jul 28 07:36:25 PM PDT 24
Peak memory 214036 kb
Host smart-e4f4b5ad-dcb4-4ea4-83cc-b58317c2aa8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133307524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2133307524
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2687960316
Short name T914
Test name
Test status
Simulation time 115329371 ps
CPU time 2.49 seconds
Started Jul 28 07:36:19 PM PDT 24
Finished Jul 28 07:36:22 PM PDT 24
Peak memory 208824 kb
Host smart-940d3c61-f128-4d47-acd1-f70aaf65f4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687960316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2687960316
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3500131065
Short name T487
Test name
Test status
Simulation time 3851588546 ps
CPU time 19.16 seconds
Started Jul 28 07:36:21 PM PDT 24
Finished Jul 28 07:36:41 PM PDT 24
Peak memory 217996 kb
Host smart-f02bcbc1-fee4-4e76-86ec-f7d100e48caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500131065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3500131065
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1384967543
Short name T430
Test name
Test status
Simulation time 55532378 ps
CPU time 2.3 seconds
Started Jul 28 07:36:24 PM PDT 24
Finished Jul 28 07:36:27 PM PDT 24
Peak memory 206764 kb
Host smart-9fe0888d-f4f6-4b54-9689-4a72fff902ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384967543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1384967543
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.857551526
Short name T632
Test name
Test status
Simulation time 120837576 ps
CPU time 2.7 seconds
Started Jul 28 07:36:18 PM PDT 24
Finished Jul 28 07:36:21 PM PDT 24
Peak memory 207212 kb
Host smart-6ce5db74-031c-4849-ad36-cc35de74368d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857551526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.857551526
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2130749010
Short name T569
Test name
Test status
Simulation time 120625297 ps
CPU time 2.31 seconds
Started Jul 28 07:36:27 PM PDT 24
Finished Jul 28 07:36:30 PM PDT 24
Peak memory 206800 kb
Host smart-4f8369e6-52cc-4c1b-9dec-f00a89f64895
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130749010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2130749010
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2784080140
Short name T254
Test name
Test status
Simulation time 52284746 ps
CPU time 2.85 seconds
Started Jul 28 07:36:30 PM PDT 24
Finished Jul 28 07:36:33 PM PDT 24
Peak memory 206724 kb
Host smart-4aec63ca-0992-497c-ad4a-ed9c2d7421f9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784080140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2784080140
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3339291108
Short name T271
Test name
Test status
Simulation time 317495868 ps
CPU time 3.27 seconds
Started Jul 28 07:36:23 PM PDT 24
Finished Jul 28 07:36:26 PM PDT 24
Peak memory 218056 kb
Host smart-2d69305a-ed30-4e5a-9ff1-5cd82c4fcb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339291108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3339291108
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.36554006
Short name T526
Test name
Test status
Simulation time 137793724 ps
CPU time 2.8 seconds
Started Jul 28 07:36:28 PM PDT 24
Finished Jul 28 07:36:31 PM PDT 24
Peak memory 208488 kb
Host smart-e3f7856f-d98f-4c78-80fe-05874be50c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36554006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.36554006
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.1044406165
Short name T757
Test name
Test status
Simulation time 1164056529 ps
CPU time 16.87 seconds
Started Jul 28 07:36:28 PM PDT 24
Finished Jul 28 07:36:45 PM PDT 24
Peak memory 220516 kb
Host smart-58725dfd-a71d-43af-9b33-c1aaf8ad3114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044406165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.1044406165
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1463156613
Short name T275
Test name
Test status
Simulation time 366174678 ps
CPU time 4.36 seconds
Started Jul 28 07:36:23 PM PDT 24
Finished Jul 28 07:36:27 PM PDT 24
Peak memory 207844 kb
Host smart-a77fbaab-a08f-44dd-aa66-56f45b7a7df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463156613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1463156613
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3934454710
Short name T159
Test name
Test status
Simulation time 971124236 ps
CPU time 15.55 seconds
Started Jul 28 07:36:20 PM PDT 24
Finished Jul 28 07:36:36 PM PDT 24
Peak memory 210788 kb
Host smart-743a7f5a-9a2c-425e-afa4-e591d2a15079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934454710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3934454710
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3698886362
Short name T10
Test name
Test status
Simulation time 143611495 ps
CPU time 3.21 seconds
Started Jul 28 07:36:23 PM PDT 24
Finished Jul 28 07:36:27 PM PDT 24
Peak memory 222496 kb
Host smart-39829267-d642-4a48-9f33-7bcc9b141367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698886362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3698886362
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.163924441
Short name T488
Test name
Test status
Simulation time 111347311 ps
CPU time 2.07 seconds
Started Jul 28 07:36:22 PM PDT 24
Finished Jul 28 07:36:25 PM PDT 24
Peak memory 207412 kb
Host smart-afc7c6f6-8917-486e-997c-05eedf373713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163924441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.163924441
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2364798986
Short name T510
Test name
Test status
Simulation time 270990575 ps
CPU time 9.07 seconds
Started Jul 28 07:36:20 PM PDT 24
Finished Jul 28 07:36:30 PM PDT 24
Peak memory 214124 kb
Host smart-fd3c15df-50fa-46b6-8d78-06f1b214d638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364798986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2364798986
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3705563280
Short name T589
Test name
Test status
Simulation time 225961075 ps
CPU time 4.91 seconds
Started Jul 28 07:36:29 PM PDT 24
Finished Jul 28 07:36:34 PM PDT 24
Peak memory 220960 kb
Host smart-f83ae4e5-2279-4c92-b87f-7a417879a489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705563280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3705563280
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2435298960
Short name T863
Test name
Test status
Simulation time 137113640 ps
CPU time 2.67 seconds
Started Jul 28 07:36:28 PM PDT 24
Finished Jul 28 07:36:30 PM PDT 24
Peak memory 221664 kb
Host smart-b09d6102-d6fc-4aac-98ec-67205a883d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435298960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2435298960
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2246053596
Short name T466
Test name
Test status
Simulation time 8975083478 ps
CPU time 51.34 seconds
Started Jul 28 07:36:28 PM PDT 24
Finished Jul 28 07:37:19 PM PDT 24
Peak memory 218392 kb
Host smart-e5b87dbd-9003-47cd-b81e-a3ae8219ed22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246053596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2246053596
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.520046324
Short name T468
Test name
Test status
Simulation time 1173037046 ps
CPU time 13.43 seconds
Started Jul 28 07:36:31 PM PDT 24
Finished Jul 28 07:36:44 PM PDT 24
Peak memory 206744 kb
Host smart-e9b7b570-a8ff-4c7d-bda9-2c1444811c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520046324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.520046324
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.56529279
Short name T630
Test name
Test status
Simulation time 238539567 ps
CPU time 3.25 seconds
Started Jul 28 07:36:21 PM PDT 24
Finished Jul 28 07:36:24 PM PDT 24
Peak memory 206756 kb
Host smart-1d0083cf-e5c0-4933-a4e2-14066deafec5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56529279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.56529279
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2523574841
Short name T320
Test name
Test status
Simulation time 483699170 ps
CPU time 6.92 seconds
Started Jul 28 07:36:24 PM PDT 24
Finished Jul 28 07:36:31 PM PDT 24
Peak memory 208568 kb
Host smart-4f1c3162-d978-4fc7-9684-b2cdd1314c63
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523574841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2523574841
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2979987651
Short name T273
Test name
Test status
Simulation time 36389404 ps
CPU time 2.62 seconds
Started Jul 28 07:36:24 PM PDT 24
Finished Jul 28 07:36:27 PM PDT 24
Peak memory 208504 kb
Host smart-81962fe4-eae3-4e39-95d3-2ae3fb462e9a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979987651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2979987651
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3492629727
Short name T795
Test name
Test status
Simulation time 108341029 ps
CPU time 2.98 seconds
Started Jul 28 07:36:28 PM PDT 24
Finished Jul 28 07:36:31 PM PDT 24
Peak memory 208516 kb
Host smart-f6aa8835-09ca-41a9-97b7-491714c73a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492629727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3492629727
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3394224538
Short name T836
Test name
Test status
Simulation time 375153819 ps
CPU time 8.67 seconds
Started Jul 28 07:36:19 PM PDT 24
Finished Jul 28 07:36:28 PM PDT 24
Peak memory 208380 kb
Host smart-4bafc711-2524-449b-bd9c-624d5e308597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394224538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3394224538
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2227901107
Short name T738
Test name
Test status
Simulation time 3903563301 ps
CPU time 42.32 seconds
Started Jul 28 07:36:32 PM PDT 24
Finished Jul 28 07:37:14 PM PDT 24
Peak memory 222216 kb
Host smart-d8fd6f43-1b75-4ce0-bd0d-6cada520d4fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227901107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2227901107
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1043939509
Short name T844
Test name
Test status
Simulation time 7567491882 ps
CPU time 31.48 seconds
Started Jul 28 07:36:23 PM PDT 24
Finished Jul 28 07:36:55 PM PDT 24
Peak memory 218504 kb
Host smart-5a152a2e-9b45-400b-888f-ca4e5e4c0aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043939509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1043939509
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1546787592
Short name T3
Test name
Test status
Simulation time 131909622 ps
CPU time 2.82 seconds
Started Jul 28 07:36:31 PM PDT 24
Finished Jul 28 07:36:34 PM PDT 24
Peak memory 210484 kb
Host smart-135fef16-4d47-402e-a2a1-6eda5e9710e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546787592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1546787592
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.3310784085
Short name T610
Test name
Test status
Simulation time 50696271 ps
CPU time 0.76 seconds
Started Jul 28 07:36:26 PM PDT 24
Finished Jul 28 07:36:27 PM PDT 24
Peak memory 205884 kb
Host smart-3b7899ef-aef2-4af1-b14a-1cc7aca8db02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310784085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.3310784085
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3489717029
Short name T614
Test name
Test status
Simulation time 355813746 ps
CPU time 3.2 seconds
Started Jul 28 07:36:24 PM PDT 24
Finished Jul 28 07:36:27 PM PDT 24
Peak memory 209196 kb
Host smart-db84d8f5-d3ff-495f-88f6-e4bea93f3d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489717029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3489717029
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.327071813
Short name T24
Test name
Test status
Simulation time 1566069599 ps
CPU time 47.61 seconds
Started Jul 28 07:36:22 PM PDT 24
Finished Jul 28 07:37:10 PM PDT 24
Peak memory 214296 kb
Host smart-d4905181-fe5a-4c8d-8b93-82ce4ce79bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327071813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.327071813
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.4257061504
Short name T65
Test name
Test status
Simulation time 44356500 ps
CPU time 2.98 seconds
Started Jul 28 07:36:28 PM PDT 24
Finished Jul 28 07:36:31 PM PDT 24
Peak memory 222324 kb
Host smart-45a83a01-e0f9-4e55-b0eb-5d55803d6058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257061504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.4257061504
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2349094361
Short name T458
Test name
Test status
Simulation time 178300276 ps
CPU time 3.32 seconds
Started Jul 28 07:36:28 PM PDT 24
Finished Jul 28 07:36:31 PM PDT 24
Peak memory 208844 kb
Host smart-fd42efdd-88d6-4b98-902f-60fead7e0f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349094361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2349094361
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2546038216
Short name T897
Test name
Test status
Simulation time 432705904 ps
CPU time 6.38 seconds
Started Jul 28 07:36:29 PM PDT 24
Finished Jul 28 07:36:36 PM PDT 24
Peak memory 219552 kb
Host smart-d9c3044f-1401-4205-9369-5000613387d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546038216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2546038216
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1311534858
Short name T547
Test name
Test status
Simulation time 211425781 ps
CPU time 2.9 seconds
Started Jul 28 07:36:25 PM PDT 24
Finished Jul 28 07:36:28 PM PDT 24
Peak memory 206804 kb
Host smart-e4c7ed7a-c7db-4350-ac30-2d9f96eb75c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311534858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1311534858
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.402163205
Short name T18
Test name
Test status
Simulation time 197899240 ps
CPU time 2.72 seconds
Started Jul 28 07:36:25 PM PDT 24
Finished Jul 28 07:36:28 PM PDT 24
Peak memory 206736 kb
Host smart-efb3e798-c7da-4325-81bd-dc40aed0ed73
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402163205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.402163205
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1245490723
Short name T656
Test name
Test status
Simulation time 91071754 ps
CPU time 2.71 seconds
Started Jul 28 07:36:25 PM PDT 24
Finished Jul 28 07:36:28 PM PDT 24
Peak memory 206872 kb
Host smart-a804cb65-0d06-48f0-8726-931d841a09c0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245490723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1245490723
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2338743538
Short name T590
Test name
Test status
Simulation time 87688137 ps
CPU time 2.31 seconds
Started Jul 28 07:36:31 PM PDT 24
Finished Jul 28 07:36:34 PM PDT 24
Peak memory 206712 kb
Host smart-f528d72d-375a-47d6-bd7c-bfd7c308357c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338743538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2338743538
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.4123841228
Short name T343
Test name
Test status
Simulation time 298497857 ps
CPU time 3.85 seconds
Started Jul 28 07:36:29 PM PDT 24
Finished Jul 28 07:36:33 PM PDT 24
Peak memory 209732 kb
Host smart-69681267-dabd-4df9-ab41-149669cb5a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123841228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.4123841228
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.4201836419
Short name T478
Test name
Test status
Simulation time 1147077859 ps
CPU time 3.25 seconds
Started Jul 28 07:36:33 PM PDT 24
Finished Jul 28 07:36:36 PM PDT 24
Peak memory 208744 kb
Host smart-ab91c9c2-f9f9-464f-bc4e-8583e874f030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201836419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.4201836419
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2017558482
Short name T732
Test name
Test status
Simulation time 92466309 ps
CPU time 3.65 seconds
Started Jul 28 07:36:26 PM PDT 24
Finished Jul 28 07:36:30 PM PDT 24
Peak memory 207488 kb
Host smart-156770fa-df92-409a-bc7a-1ef866d78614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017558482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2017558482
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3172739915
Short name T511
Test name
Test status
Simulation time 386644958 ps
CPU time 3.94 seconds
Started Jul 28 07:36:31 PM PDT 24
Finished Jul 28 07:36:35 PM PDT 24
Peak memory 210264 kb
Host smart-655f81ea-af64-4153-8fc1-01a21f7eb210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172739915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3172739915
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.210264620
Short name T100
Test name
Test status
Simulation time 70503735 ps
CPU time 0.75 seconds
Started Jul 28 07:36:37 PM PDT 24
Finished Jul 28 07:36:38 PM PDT 24
Peak memory 205880 kb
Host smart-2ee6574e-106b-4c03-acee-1da2a0808301
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210264620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.210264620
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2536317461
Short name T402
Test name
Test status
Simulation time 43668993 ps
CPU time 2.84 seconds
Started Jul 28 07:36:26 PM PDT 24
Finished Jul 28 07:36:29 PM PDT 24
Peak memory 214148 kb
Host smart-df53687f-b6b4-4de4-8cb2-3b7b77d4df44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2536317461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2536317461
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1172049304
Short name T37
Test name
Test status
Simulation time 134115702 ps
CPU time 2.85 seconds
Started Jul 28 07:36:29 PM PDT 24
Finished Jul 28 07:36:32 PM PDT 24
Peak memory 207676 kb
Host smart-68a93195-81a5-4150-955c-e9a942e536d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172049304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1172049304
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.2954094097
Short name T747
Test name
Test status
Simulation time 244604809 ps
CPU time 5.8 seconds
Started Jul 28 07:36:29 PM PDT 24
Finished Jul 28 07:36:34 PM PDT 24
Peak memory 214112 kb
Host smart-8f250b79-018a-4fbc-bcf2-0d25b78082ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954094097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2954094097
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2039906679
Short name T791
Test name
Test status
Simulation time 167256462 ps
CPU time 2.58 seconds
Started Jul 28 07:36:38 PM PDT 24
Finished Jul 28 07:36:41 PM PDT 24
Peak memory 214092 kb
Host smart-db9e83a1-a7a4-41ad-a0b3-3741195febab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039906679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2039906679
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.259379626
Short name T856
Test name
Test status
Simulation time 169012546 ps
CPU time 2.84 seconds
Started Jul 28 07:36:31 PM PDT 24
Finished Jul 28 07:36:34 PM PDT 24
Peak memory 220148 kb
Host smart-b0422189-e37b-44c4-904d-cd07e759b39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259379626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.259379626
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.4191726074
Short name T780
Test name
Test status
Simulation time 357088289 ps
CPU time 4.7 seconds
Started Jul 28 07:36:29 PM PDT 24
Finished Jul 28 07:36:34 PM PDT 24
Peak memory 207380 kb
Host smart-bca1a701-ee83-4851-9dce-7b4ff38dba3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191726074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.4191726074
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.4121662906
Short name T641
Test name
Test status
Simulation time 195266014 ps
CPU time 4.25 seconds
Started Jul 28 07:36:27 PM PDT 24
Finished Jul 28 07:36:32 PM PDT 24
Peak memory 207796 kb
Host smart-5b48e291-4e6f-405f-8583-7f439752e7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121662906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.4121662906
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2191843268
Short name T675
Test name
Test status
Simulation time 59717786 ps
CPU time 3.1 seconds
Started Jul 28 07:36:31 PM PDT 24
Finished Jul 28 07:36:35 PM PDT 24
Peak memory 206788 kb
Host smart-e53414cb-337f-4abe-b50c-129456522150
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191843268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2191843268
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3835333077
Short name T288
Test name
Test status
Simulation time 243996118 ps
CPU time 5.69 seconds
Started Jul 28 07:36:29 PM PDT 24
Finished Jul 28 07:36:35 PM PDT 24
Peak memory 208308 kb
Host smart-b6fbce77-a03d-4ded-a4f2-8ab310e11d1f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835333077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3835333077
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2256498966
Short name T652
Test name
Test status
Simulation time 174701496 ps
CPU time 3.34 seconds
Started Jul 28 07:36:31 PM PDT 24
Finished Jul 28 07:36:35 PM PDT 24
Peak memory 208656 kb
Host smart-25aea524-bc97-4d5e-bf05-de923ac8f860
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256498966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2256498966
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2126655946
Short name T363
Test name
Test status
Simulation time 60323056 ps
CPU time 2.18 seconds
Started Jul 28 07:36:33 PM PDT 24
Finished Jul 28 07:36:36 PM PDT 24
Peak memory 218120 kb
Host smart-e7754641-59ef-493b-a7fb-f02e08499429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126655946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2126655946
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3058691585
Short name T456
Test name
Test status
Simulation time 720164079 ps
CPU time 3.09 seconds
Started Jul 28 07:36:30 PM PDT 24
Finished Jul 28 07:36:33 PM PDT 24
Peak memory 208316 kb
Host smart-84f82867-6368-499e-a1fd-7b5ae40184a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058691585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3058691585
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3018729141
Short name T866
Test name
Test status
Simulation time 59367300 ps
CPU time 3.98 seconds
Started Jul 28 07:36:34 PM PDT 24
Finished Jul 28 07:36:39 PM PDT 24
Peak memory 208128 kb
Host smart-88a0d4b5-c47d-48fe-9a02-bd99b68763d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018729141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3018729141
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1854343139
Short name T201
Test name
Test status
Simulation time 836945993 ps
CPU time 5.85 seconds
Started Jul 28 07:36:32 PM PDT 24
Finished Jul 28 07:36:38 PM PDT 24
Peak memory 218160 kb
Host smart-97c0f2ab-b978-46c3-92b8-78d26adaaf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854343139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1854343139
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3189384490
Short name T765
Test name
Test status
Simulation time 3104422316 ps
CPU time 8.52 seconds
Started Jul 28 07:36:32 PM PDT 24
Finished Jul 28 07:36:41 PM PDT 24
Peak memory 211120 kb
Host smart-79a2efe9-fbfd-444d-9e83-aa8d2cbbbf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189384490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3189384490
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1923589682
Short name T600
Test name
Test status
Simulation time 114781266 ps
CPU time 0.9 seconds
Started Jul 28 07:35:32 PM PDT 24
Finished Jul 28 07:35:33 PM PDT 24
Peak memory 205852 kb
Host smart-266c0924-0361-4546-8727-40e4104f8a64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923589682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1923589682
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.441484490
Short name T327
Test name
Test status
Simulation time 61050435 ps
CPU time 2.53 seconds
Started Jul 28 07:35:37 PM PDT 24
Finished Jul 28 07:35:40 PM PDT 24
Peak memory 214148 kb
Host smart-7e475afe-5abc-41d1-bc69-9ef3a4ab1815
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=441484490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.441484490
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.237531381
Short name T860
Test name
Test status
Simulation time 367064789 ps
CPU time 3.8 seconds
Started Jul 28 07:35:35 PM PDT 24
Finished Jul 28 07:35:39 PM PDT 24
Peak memory 217272 kb
Host smart-2739e2e2-2ce9-44af-91ef-f134003c2e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237531381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.237531381
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.131805774
Short name T344
Test name
Test status
Simulation time 54375096 ps
CPU time 2.99 seconds
Started Jul 28 07:35:34 PM PDT 24
Finished Jul 28 07:35:37 PM PDT 24
Peak memory 207188 kb
Host smart-fa3c1de9-fe0b-42d4-8968-efff107d7234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131805774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.131805774
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1129113235
Short name T406
Test name
Test status
Simulation time 50189058 ps
CPU time 1.65 seconds
Started Jul 28 07:35:33 PM PDT 24
Finished Jul 28 07:35:34 PM PDT 24
Peak memory 214240 kb
Host smart-0d8d562d-8225-4c1a-b4c4-1b5b3a71bf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129113235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1129113235
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3697591979
Short name T319
Test name
Test status
Simulation time 298845703 ps
CPU time 5.8 seconds
Started Jul 28 07:35:34 PM PDT 24
Finished Jul 28 07:35:39 PM PDT 24
Peak memory 210064 kb
Host smart-f239230c-b7c1-49c8-8900-c399ead372a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697591979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3697591979
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2888121222
Short name T14
Test name
Test status
Simulation time 1785286341 ps
CPU time 11.57 seconds
Started Jul 28 07:35:36 PM PDT 24
Finished Jul 28 07:35:48 PM PDT 24
Peak memory 239832 kb
Host smart-3f4a7ad4-2e21-46b1-bcc1-00c782e7682b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888121222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2888121222
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1177585116
Short name T199
Test name
Test status
Simulation time 458047174 ps
CPU time 2.85 seconds
Started Jul 28 07:35:34 PM PDT 24
Finished Jul 28 07:35:37 PM PDT 24
Peak memory 206796 kb
Host smart-63854a34-3eb9-4e38-a348-f5fea9502f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177585116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1177585116
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3100161276
Short name T519
Test name
Test status
Simulation time 22330036 ps
CPU time 1.76 seconds
Started Jul 28 07:35:35 PM PDT 24
Finished Jul 28 07:35:37 PM PDT 24
Peak memory 206692 kb
Host smart-30a90f0c-b8e1-48a7-9f0e-f9715851f3ef
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100161276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3100161276
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.3313140349
Short name T437
Test name
Test status
Simulation time 2258415164 ps
CPU time 23.35 seconds
Started Jul 28 07:35:36 PM PDT 24
Finished Jul 28 07:35:59 PM PDT 24
Peak memory 208492 kb
Host smart-e2940b6d-e20a-436f-a46c-28dc097d5daf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313140349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3313140349
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3380797196
Short name T721
Test name
Test status
Simulation time 3262599407 ps
CPU time 38.68 seconds
Started Jul 28 07:35:35 PM PDT 24
Finished Jul 28 07:36:13 PM PDT 24
Peak memory 208668 kb
Host smart-a607a969-f416-463c-ab60-a840e42a131e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380797196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3380797196
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1301956692
Short name T439
Test name
Test status
Simulation time 97427035 ps
CPU time 2.23 seconds
Started Jul 28 07:35:33 PM PDT 24
Finished Jul 28 07:35:36 PM PDT 24
Peak memory 209252 kb
Host smart-50e53384-967d-454e-8242-9e113e19b252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301956692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1301956692
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2809298052
Short name T909
Test name
Test status
Simulation time 46761077 ps
CPU time 2.48 seconds
Started Jul 28 07:35:35 PM PDT 24
Finished Jul 28 07:35:37 PM PDT 24
Peak memory 206684 kb
Host smart-519f9575-f7b6-4563-88be-c90b4ff5dae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809298052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2809298052
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1289685413
Short name T190
Test name
Test status
Simulation time 4406331949 ps
CPU time 78.25 seconds
Started Jul 28 07:35:36 PM PDT 24
Finished Jul 28 07:36:54 PM PDT 24
Peak memory 218416 kb
Host smart-8fac1619-dfcf-4897-8e92-dd8d17f3714c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289685413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1289685413
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1941016990
Short name T130
Test name
Test status
Simulation time 102528166 ps
CPU time 7.06 seconds
Started Jul 28 07:35:36 PM PDT 24
Finished Jul 28 07:35:43 PM PDT 24
Peak memory 222480 kb
Host smart-410a7831-6b28-4390-9c17-95adbe61b26c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941016990 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.1941016990
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2941792727
Short name T607
Test name
Test status
Simulation time 746391129 ps
CPU time 2.55 seconds
Started Jul 28 07:35:35 PM PDT 24
Finished Jul 28 07:35:37 PM PDT 24
Peak memory 210248 kb
Host smart-e9e39f84-aeb2-4576-b57f-1df57e676524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941792727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2941792727
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.360751927
Short name T594
Test name
Test status
Simulation time 23941559 ps
CPU time 0.76 seconds
Started Jul 28 07:36:32 PM PDT 24
Finished Jul 28 07:36:32 PM PDT 24
Peak memory 205884 kb
Host smart-1600db9a-a3ee-450d-9588-a64ec1609daa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360751927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.360751927
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2140657104
Short name T71
Test name
Test status
Simulation time 151958691 ps
CPU time 3.78 seconds
Started Jul 28 07:36:33 PM PDT 24
Finished Jul 28 07:36:37 PM PDT 24
Peak memory 209952 kb
Host smart-375d12d7-5080-4149-aa86-6588c612cab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140657104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2140657104
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3652641975
Short name T48
Test name
Test status
Simulation time 928547834 ps
CPU time 5.68 seconds
Started Jul 28 07:36:30 PM PDT 24
Finished Jul 28 07:36:36 PM PDT 24
Peak memory 218220 kb
Host smart-8b0a351e-bbd3-438c-9f30-4c71e7a57634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652641975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3652641975
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1289399397
Short name T357
Test name
Test status
Simulation time 306804028 ps
CPU time 2.39 seconds
Started Jul 28 07:36:31 PM PDT 24
Finished Jul 28 07:36:33 PM PDT 24
Peak memory 222320 kb
Host smart-32ad75fa-2fa3-4d74-9131-36ce460c3a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289399397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1289399397
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.4123960146
Short name T786
Test name
Test status
Simulation time 260239708 ps
CPU time 2.9 seconds
Started Jul 28 07:36:34 PM PDT 24
Finished Jul 28 07:36:37 PM PDT 24
Peak memory 219680 kb
Host smart-8d03de5a-6e6c-4271-892a-442ccd4a42a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123960146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.4123960146
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1751310636
Short name T838
Test name
Test status
Simulation time 372201737 ps
CPU time 4.61 seconds
Started Jul 28 07:36:31 PM PDT 24
Finished Jul 28 07:36:36 PM PDT 24
Peak memory 208588 kb
Host smart-30fe85e8-cd6c-4288-bda8-eaffd4529978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751310636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1751310636
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1769546155
Short name T507
Test name
Test status
Simulation time 33680836 ps
CPU time 2.42 seconds
Started Jul 28 07:36:33 PM PDT 24
Finished Jul 28 07:36:36 PM PDT 24
Peak memory 208312 kb
Host smart-1c6e83e9-33fe-4c44-8df9-670c74f1f601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769546155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1769546155
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1286408849
Short name T848
Test name
Test status
Simulation time 234151376 ps
CPU time 3.09 seconds
Started Jul 28 07:36:31 PM PDT 24
Finished Jul 28 07:36:34 PM PDT 24
Peak memory 208292 kb
Host smart-ee2df6de-5576-4026-8801-3170a62234dc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286408849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1286408849
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.1570194745
Short name T826
Test name
Test status
Simulation time 37704838 ps
CPU time 1.67 seconds
Started Jul 28 07:36:31 PM PDT 24
Finished Jul 28 07:36:33 PM PDT 24
Peak memory 206804 kb
Host smart-264559c7-3d20-46ed-91d7-051dab5e8bc1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570194745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1570194745
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.427503232
Short name T489
Test name
Test status
Simulation time 353458387 ps
CPU time 4.12 seconds
Started Jul 28 07:36:30 PM PDT 24
Finished Jul 28 07:36:34 PM PDT 24
Peak memory 208816 kb
Host smart-0772e086-b3ca-4273-bcd2-2c0ead4508f6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427503232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.427503232
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.335927136
Short name T797
Test name
Test status
Simulation time 485259635 ps
CPU time 2.06 seconds
Started Jul 28 07:36:33 PM PDT 24
Finished Jul 28 07:36:36 PM PDT 24
Peak memory 207320 kb
Host smart-fc41bc06-7613-406d-8326-1ef4d60e3a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335927136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.335927136
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1912433603
Short name T678
Test name
Test status
Simulation time 619466867 ps
CPU time 12.67 seconds
Started Jul 28 07:36:38 PM PDT 24
Finished Jul 28 07:36:51 PM PDT 24
Peak memory 208364 kb
Host smart-c5b19c90-d8a5-4ca6-81aa-f11495f0b6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912433603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1912433603
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1282698119
Short name T42
Test name
Test status
Simulation time 1769292919 ps
CPU time 19.38 seconds
Started Jul 28 07:36:31 PM PDT 24
Finished Jul 28 07:36:50 PM PDT 24
Peak memory 220576 kb
Host smart-a5d3159f-a474-47f7-9b38-5ea87a0e5fa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282698119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1282698119
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.733109052
Short name T555
Test name
Test status
Simulation time 199744872 ps
CPU time 2.81 seconds
Started Jul 28 07:36:33 PM PDT 24
Finished Jul 28 07:36:36 PM PDT 24
Peak memory 207912 kb
Host smart-3a46ba6b-124c-4442-a813-c93660274fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733109052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.733109052
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1100365731
Short name T804
Test name
Test status
Simulation time 186158160 ps
CPU time 4.33 seconds
Started Jul 28 07:36:33 PM PDT 24
Finished Jul 28 07:36:37 PM PDT 24
Peak memory 210212 kb
Host smart-aef45b9a-c8a2-48c7-a152-0be0695d9ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100365731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1100365731
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2028169706
Short name T541
Test name
Test status
Simulation time 134990514 ps
CPU time 0.78 seconds
Started Jul 28 07:36:41 PM PDT 24
Finished Jul 28 07:36:42 PM PDT 24
Peak memory 205864 kb
Host smart-0cbe7c79-3ae0-488e-ae9d-500b8d2e671d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028169706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2028169706
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.856755159
Short name T620
Test name
Test status
Simulation time 30197134 ps
CPU time 2.49 seconds
Started Jul 28 07:36:37 PM PDT 24
Finished Jul 28 07:36:40 PM PDT 24
Peak memory 214192 kb
Host smart-7abcc6bd-4747-4a76-bf85-ad49f87f2c73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=856755159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.856755159
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.367403801
Short name T309
Test name
Test status
Simulation time 662286643 ps
CPU time 4.54 seconds
Started Jul 28 07:36:40 PM PDT 24
Finished Jul 28 07:36:44 PM PDT 24
Peak memory 208928 kb
Host smart-51ba9e08-e4eb-4dfc-a2db-3b5600029f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367403801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.367403801
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.393963150
Short name T85
Test name
Test status
Simulation time 89323122 ps
CPU time 3.28 seconds
Started Jul 28 07:36:40 PM PDT 24
Finished Jul 28 07:36:43 PM PDT 24
Peak memory 208956 kb
Host smart-d6ffbba7-6c55-4d00-b5f9-d81fea51d7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393963150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.393963150
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2526114495
Short name T246
Test name
Test status
Simulation time 88265048 ps
CPU time 3.77 seconds
Started Jul 28 07:36:37 PM PDT 24
Finished Jul 28 07:36:41 PM PDT 24
Peak memory 207276 kb
Host smart-202ca886-17a4-4864-bf01-c47f348506e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526114495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2526114495
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2221689237
Short name T45
Test name
Test status
Simulation time 478233253 ps
CPU time 6.17 seconds
Started Jul 28 07:36:36 PM PDT 24
Finished Jul 28 07:36:43 PM PDT 24
Peak memory 208912 kb
Host smart-01ae0dc0-a4c9-4b20-ae39-0ef7fdf6fd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221689237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2221689237
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.700903432
Short name T687
Test name
Test status
Simulation time 727558696 ps
CPU time 8.46 seconds
Started Jul 28 07:36:32 PM PDT 24
Finished Jul 28 07:36:41 PM PDT 24
Peak memory 208960 kb
Host smart-2b6f3109-1e50-4c75-8f1a-9543c56cfa2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700903432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.700903432
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.193246788
Short name T443
Test name
Test status
Simulation time 65786496 ps
CPU time 2.51 seconds
Started Jul 28 07:36:38 PM PDT 24
Finished Jul 28 07:36:41 PM PDT 24
Peak memory 206772 kb
Host smart-853028af-973e-4ff7-a178-83cd33950f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193246788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.193246788
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3842830373
Short name T362
Test name
Test status
Simulation time 69296098 ps
CPU time 3.62 seconds
Started Jul 28 07:36:34 PM PDT 24
Finished Jul 28 07:36:38 PM PDT 24
Peak memory 208472 kb
Host smart-48118b3b-af73-46d7-aaf1-984824e29add
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842830373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3842830373
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2890552195
Short name T139
Test name
Test status
Simulation time 92958918 ps
CPU time 2.72 seconds
Started Jul 28 07:36:32 PM PDT 24
Finished Jul 28 07:36:35 PM PDT 24
Peak memory 206864 kb
Host smart-091d94ba-21aa-4a45-8499-cfd84b72fe30
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890552195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2890552195
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1184951515
Short name T274
Test name
Test status
Simulation time 2985694517 ps
CPU time 22.67 seconds
Started Jul 28 07:36:33 PM PDT 24
Finished Jul 28 07:36:56 PM PDT 24
Peak memory 208544 kb
Host smart-e38087dd-7cd2-434f-af4d-5d796df94632
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184951515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1184951515
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1201589024
Short name T806
Test name
Test status
Simulation time 151252542 ps
CPU time 2.16 seconds
Started Jul 28 07:36:40 PM PDT 24
Finished Jul 28 07:36:42 PM PDT 24
Peak memory 209144 kb
Host smart-728fbd0d-c045-4246-8f56-b3231c46aa09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201589024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1201589024
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1164269138
Short name T710
Test name
Test status
Simulation time 1739064284 ps
CPU time 7.33 seconds
Started Jul 28 07:36:38 PM PDT 24
Finished Jul 28 07:36:45 PM PDT 24
Peak memory 206868 kb
Host smart-9a9778e2-9a1d-43db-bab9-de4759a65225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164269138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1164269138
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1662449845
Short name T663
Test name
Test status
Simulation time 149822677 ps
CPU time 4.82 seconds
Started Jul 28 07:36:37 PM PDT 24
Finished Jul 28 07:36:42 PM PDT 24
Peak memory 214780 kb
Host smart-79badd4c-5832-487a-bb9d-40ee3713936a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662449845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1662449845
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.4101760
Short name T262
Test name
Test status
Simulation time 69850456 ps
CPU time 2.65 seconds
Started Jul 28 07:36:41 PM PDT 24
Finished Jul 28 07:36:44 PM PDT 24
Peak memory 219596 kb
Host smart-05a854f1-88a4-4c9c-8b54-71cce86741ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.4101760
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.4165559853
Short name T421
Test name
Test status
Simulation time 90252162 ps
CPU time 0.79 seconds
Started Jul 28 07:36:40 PM PDT 24
Finished Jul 28 07:36:41 PM PDT 24
Peak memory 205772 kb
Host smart-df70c655-319e-4d93-a8f3-6c2514fa2883
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165559853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.4165559853
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.399249538
Short name T412
Test name
Test status
Simulation time 100724326 ps
CPU time 3.78 seconds
Started Jul 28 07:36:40 PM PDT 24
Finished Jul 28 07:36:44 PM PDT 24
Peak memory 214108 kb
Host smart-b0e631cd-0045-407b-a4fc-d8dbb5f205b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=399249538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.399249538
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3655767357
Short name T281
Test name
Test status
Simulation time 1639231511 ps
CPU time 17.6 seconds
Started Jul 28 07:36:45 PM PDT 24
Finished Jul 28 07:37:02 PM PDT 24
Peak memory 207976 kb
Host smart-b6e6d676-15ac-42a9-bd48-c81c0f3052f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655767357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3655767357
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1418612755
Short name T91
Test name
Test status
Simulation time 99079472 ps
CPU time 3.18 seconds
Started Jul 28 07:36:41 PM PDT 24
Finished Jul 28 07:36:44 PM PDT 24
Peak memory 208824 kb
Host smart-00dc7e5a-d401-45c5-905d-fd83aefde727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418612755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1418612755
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2847407780
Short name T737
Test name
Test status
Simulation time 108625057 ps
CPU time 3.6 seconds
Started Jul 28 07:36:36 PM PDT 24
Finished Jul 28 07:36:40 PM PDT 24
Peak memory 214196 kb
Host smart-93d8b9e8-ce6f-4f69-92c4-9cb12dfd6d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847407780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2847407780
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.509288283
Short name T715
Test name
Test status
Simulation time 1224450191 ps
CPU time 4.27 seconds
Started Jul 28 07:36:37 PM PDT 24
Finished Jul 28 07:36:42 PM PDT 24
Peak memory 207844 kb
Host smart-5d48e90d-9eeb-441d-81f2-fa9dc18bf6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509288283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.509288283
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3929304269
Short name T775
Test name
Test status
Simulation time 62964086 ps
CPU time 3.65 seconds
Started Jul 28 07:36:37 PM PDT 24
Finished Jul 28 07:36:41 PM PDT 24
Peak memory 214144 kb
Host smart-41c7cf97-e61b-4824-8c26-d97f3bc8f683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929304269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3929304269
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3060625580
Short name T351
Test name
Test status
Simulation time 547656891 ps
CPU time 4.15 seconds
Started Jul 28 07:36:35 PM PDT 24
Finished Jul 28 07:36:40 PM PDT 24
Peak memory 208368 kb
Host smart-15e45cb0-4a89-4d60-9618-5cc8546b4b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060625580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3060625580
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3836353058
Short name T438
Test name
Test status
Simulation time 2151822907 ps
CPU time 14.66 seconds
Started Jul 28 07:36:39 PM PDT 24
Finished Jul 28 07:36:54 PM PDT 24
Peak memory 208044 kb
Host smart-db92827e-f8ce-44be-a0e9-ef138305373a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836353058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3836353058
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2517495533
Short name T505
Test name
Test status
Simulation time 2211476250 ps
CPU time 57.46 seconds
Started Jul 28 07:36:38 PM PDT 24
Finished Jul 28 07:37:35 PM PDT 24
Peak memory 208960 kb
Host smart-d1990ae3-1c52-4f56-a921-b98aec95f3ef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517495533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2517495533
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.973411832
Short name T763
Test name
Test status
Simulation time 161212563 ps
CPU time 2.85 seconds
Started Jul 28 07:36:38 PM PDT 24
Finished Jul 28 07:36:41 PM PDT 24
Peak memory 208952 kb
Host smart-dc7d6e92-82ce-4f34-bdd5-22910f24eabc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973411832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.973411832
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2531161114
Short name T136
Test name
Test status
Simulation time 619963980 ps
CPU time 4.41 seconds
Started Jul 28 07:36:38 PM PDT 24
Finished Jul 28 07:36:43 PM PDT 24
Peak memory 214128 kb
Host smart-be09a127-314b-49bc-abe4-8483422c6056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531161114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2531161114
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.183794208
Short name T686
Test name
Test status
Simulation time 112967009 ps
CPU time 2.78 seconds
Started Jul 28 07:36:42 PM PDT 24
Finished Jul 28 07:36:44 PM PDT 24
Peak memory 206740 kb
Host smart-f299ebc4-b860-4582-bccf-74c88490786c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183794208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.183794208
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1336544000
Short name T193
Test name
Test status
Simulation time 301011978 ps
CPU time 3.88 seconds
Started Jul 28 07:36:40 PM PDT 24
Finished Jul 28 07:36:44 PM PDT 24
Peak memory 219556 kb
Host smart-91e9a62f-f1e4-4d0c-8050-97dcd4962146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336544000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1336544000
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.2788726837
Short name T764
Test name
Test status
Simulation time 1230418498 ps
CPU time 2.32 seconds
Started Jul 28 07:36:35 PM PDT 24
Finished Jul 28 07:36:38 PM PDT 24
Peak memory 209872 kb
Host smart-a6891262-5ce9-4463-8da9-7402f97bcb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788726837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2788726837
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.429219959
Short name T664
Test name
Test status
Simulation time 11593820 ps
CPU time 0.9 seconds
Started Jul 28 07:36:46 PM PDT 24
Finished Jul 28 07:36:47 PM PDT 24
Peak memory 205840 kb
Host smart-1f7824e6-7944-4c8e-8f29-4a69427ac068
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429219959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.429219959
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1151798867
Short name T704
Test name
Test status
Simulation time 1511260646 ps
CPU time 39.72 seconds
Started Jul 28 07:36:45 PM PDT 24
Finished Jul 28 07:37:25 PM PDT 24
Peak memory 214040 kb
Host smart-19a079fa-448a-449e-87cc-e8cab7829aaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1151798867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1151798867
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.800206086
Short name T623
Test name
Test status
Simulation time 789466441 ps
CPU time 3.21 seconds
Started Jul 28 07:36:46 PM PDT 24
Finished Jul 28 07:36:49 PM PDT 24
Peak memory 214084 kb
Host smart-fbf2cc84-5b50-4c6f-afab-d6835b8e98d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800206086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.800206086
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2124723986
Short name T61
Test name
Test status
Simulation time 128358453 ps
CPU time 3.02 seconds
Started Jul 28 07:36:38 PM PDT 24
Finished Jul 28 07:36:42 PM PDT 24
Peak memory 208808 kb
Host smart-f75c7088-39db-487b-8a42-0c6162ab822d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124723986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2124723986
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2013725499
Short name T94
Test name
Test status
Simulation time 99088275 ps
CPU time 2.42 seconds
Started Jul 28 07:36:40 PM PDT 24
Finished Jul 28 07:36:42 PM PDT 24
Peak memory 214100 kb
Host smart-5bcf3ac5-c0d5-4790-8d0f-2bf5f52eff0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013725499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2013725499
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.4100163372
Short name T636
Test name
Test status
Simulation time 80423787 ps
CPU time 3.88 seconds
Started Jul 28 07:36:40 PM PDT 24
Finished Jul 28 07:36:44 PM PDT 24
Peak memory 214068 kb
Host smart-315de1f7-6ad1-407c-a542-975f078c2951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100163372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.4100163372
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.4043695234
Short name T695
Test name
Test status
Simulation time 101053135 ps
CPU time 3.98 seconds
Started Jul 28 07:36:41 PM PDT 24
Finished Jul 28 07:36:46 PM PDT 24
Peak memory 217608 kb
Host smart-e63bb49f-647d-4b9c-9995-aa5a2ae18350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043695234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.4043695234
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3245539684
Short name T464
Test name
Test status
Simulation time 141358343 ps
CPU time 3.77 seconds
Started Jul 28 07:36:38 PM PDT 24
Finished Jul 28 07:36:41 PM PDT 24
Peak memory 209232 kb
Host smart-10430d0d-79e0-41f8-bb57-4460f529bef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245539684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3245539684
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2860607952
Short name T741
Test name
Test status
Simulation time 136691620 ps
CPU time 4.59 seconds
Started Jul 28 07:36:39 PM PDT 24
Finished Jul 28 07:36:44 PM PDT 24
Peak memory 207268 kb
Host smart-f282e70b-6a59-49ec-bf2d-d19c4b2132aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860607952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2860607952
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.543370404
Short name T631
Test name
Test status
Simulation time 848287277 ps
CPU time 6 seconds
Started Jul 28 07:36:42 PM PDT 24
Finished Jul 28 07:36:48 PM PDT 24
Peak memory 208816 kb
Host smart-4624e1d0-47de-4443-944a-6088660a2da2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543370404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.543370404
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3779785494
Short name T521
Test name
Test status
Simulation time 148281169 ps
CPU time 2.31 seconds
Started Jul 28 07:36:38 PM PDT 24
Finished Jul 28 07:36:41 PM PDT 24
Peak memory 206772 kb
Host smart-b3026df9-4197-43fd-970a-21d3d61941fa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779785494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3779785494
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.4082511813
Short name T449
Test name
Test status
Simulation time 206636292 ps
CPU time 2.52 seconds
Started Jul 28 07:36:37 PM PDT 24
Finished Jul 28 07:36:39 PM PDT 24
Peak memory 207440 kb
Host smart-b805b1e1-c314-4cec-b370-bdc0c7203d4d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082511813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.4082511813
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.4056272101
Short name T649
Test name
Test status
Simulation time 551290090 ps
CPU time 17.63 seconds
Started Jul 28 07:36:41 PM PDT 24
Finished Jul 28 07:36:59 PM PDT 24
Peak memory 214124 kb
Host smart-34d38885-02ae-4d70-913c-7724586932d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056272101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.4056272101
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2497322445
Short name T660
Test name
Test status
Simulation time 681414362 ps
CPU time 7.15 seconds
Started Jul 28 07:36:39 PM PDT 24
Finished Jul 28 07:36:46 PM PDT 24
Peak memory 208380 kb
Host smart-ca9eac35-1073-4de7-b369-0634df41380f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497322445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2497322445
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1351230801
Short name T266
Test name
Test status
Simulation time 37722379 ps
CPU time 1.87 seconds
Started Jul 28 07:36:44 PM PDT 24
Finished Jul 28 07:36:46 PM PDT 24
Peak memory 208156 kb
Host smart-0357e857-74c5-49d6-a65e-4cdefa5c1160
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351230801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1351230801
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3655975488
Short name T189
Test name
Test status
Simulation time 663027992 ps
CPU time 15.25 seconds
Started Jul 28 07:36:41 PM PDT 24
Finished Jul 28 07:36:57 PM PDT 24
Peak memory 222392 kb
Host smart-9f6261a8-37b9-4456-aca5-93f8f5ce1e29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655975488 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3655975488
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.4080663968
Short name T348
Test name
Test status
Simulation time 508734891 ps
CPU time 4.29 seconds
Started Jul 28 07:36:41 PM PDT 24
Finished Jul 28 07:36:45 PM PDT 24
Peak memory 214140 kb
Host smart-d7455d35-077e-430f-907a-c7c63560cf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080663968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.4080663968
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2096765784
Short name T794
Test name
Test status
Simulation time 98311520 ps
CPU time 3.41 seconds
Started Jul 28 07:36:41 PM PDT 24
Finished Jul 28 07:36:45 PM PDT 24
Peak memory 210736 kb
Host smart-b6effccd-404b-469e-9528-adbc99bf53b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096765784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2096765784
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.425724533
Short name T536
Test name
Test status
Simulation time 29785343 ps
CPU time 0.72 seconds
Started Jul 28 07:36:44 PM PDT 24
Finished Jul 28 07:36:45 PM PDT 24
Peak memory 205828 kb
Host smart-dfef9819-be86-4bac-bc94-ca07875d50a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425724533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.425724533
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2718736635
Short name T386
Test name
Test status
Simulation time 187379390 ps
CPU time 5.67 seconds
Started Jul 28 07:36:43 PM PDT 24
Finished Jul 28 07:36:49 PM PDT 24
Peak memory 215084 kb
Host smart-5bc7a15d-abd5-4c98-b112-9596137c8918
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2718736635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2718736635
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1862860782
Short name T20
Test name
Test status
Simulation time 172149105 ps
CPU time 4.22 seconds
Started Jul 28 07:36:44 PM PDT 24
Finished Jul 28 07:36:48 PM PDT 24
Peak memory 208584 kb
Host smart-feeeb623-44bc-408a-bf27-bf57b4f07635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862860782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1862860782
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.4206707291
Short name T78
Test name
Test status
Simulation time 109535305 ps
CPU time 3.97 seconds
Started Jul 28 07:36:44 PM PDT 24
Finished Jul 28 07:36:48 PM PDT 24
Peak memory 207176 kb
Host smart-be5c2a83-3bc8-47e5-98d2-e66f1f2fe055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206707291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.4206707291
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.745863882
Short name T25
Test name
Test status
Simulation time 725770506 ps
CPU time 6.1 seconds
Started Jul 28 07:36:42 PM PDT 24
Finished Jul 28 07:36:48 PM PDT 24
Peak memory 214124 kb
Host smart-25ba62e0-73af-46fc-8bf5-56b2927c57fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745863882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.745863882
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2954682682
Short name T316
Test name
Test status
Simulation time 135285078 ps
CPU time 3.74 seconds
Started Jul 28 07:36:41 PM PDT 24
Finished Jul 28 07:36:45 PM PDT 24
Peak memory 220752 kb
Host smart-4613b48f-205c-4732-9ac8-788b8ed34a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954682682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2954682682
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1849278499
Short name T211
Test name
Test status
Simulation time 81388581 ps
CPU time 2.09 seconds
Started Jul 28 07:36:45 PM PDT 24
Finished Jul 28 07:36:47 PM PDT 24
Peak memory 218980 kb
Host smart-357cce7c-58f2-4d32-a075-39878b3e405d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849278499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1849278499
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1683450776
Short name T549
Test name
Test status
Simulation time 32298721 ps
CPU time 2.48 seconds
Started Jul 28 07:36:41 PM PDT 24
Finished Jul 28 07:36:44 PM PDT 24
Peak memory 206616 kb
Host smart-1845d661-c51d-430f-81c7-62b33404ccaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683450776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1683450776
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3367938183
Short name T237
Test name
Test status
Simulation time 7155862737 ps
CPU time 42.05 seconds
Started Jul 28 07:36:47 PM PDT 24
Finished Jul 28 07:37:29 PM PDT 24
Peak memory 208164 kb
Host smart-beb12c30-cd26-4fcf-930f-5e29ff7cb393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367938183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3367938183
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.801549103
Short name T669
Test name
Test status
Simulation time 306157234 ps
CPU time 3.63 seconds
Started Jul 28 07:36:41 PM PDT 24
Finished Jul 28 07:36:45 PM PDT 24
Peak memory 208428 kb
Host smart-1821ff22-0bd2-4847-bc47-a99a24839002
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801549103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.801549103
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.4151819375
Short name T391
Test name
Test status
Simulation time 88957088 ps
CPU time 3.03 seconds
Started Jul 28 07:36:47 PM PDT 24
Finished Jul 28 07:36:50 PM PDT 24
Peak memory 206840 kb
Host smart-44e58b1c-d942-499c-a715-a1553a3ca6c9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151819375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.4151819375
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2408720440
Short name T852
Test name
Test status
Simulation time 62725082 ps
CPU time 3.14 seconds
Started Jul 28 07:36:43 PM PDT 24
Finished Jul 28 07:36:47 PM PDT 24
Peak memory 208576 kb
Host smart-c31ce96a-5b74-4df6-a19c-e48905dbd9e0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408720440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2408720440
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1259754098
Short name T431
Test name
Test status
Simulation time 130079782 ps
CPU time 2.36 seconds
Started Jul 28 07:36:44 PM PDT 24
Finished Jul 28 07:36:47 PM PDT 24
Peak memory 208680 kb
Host smart-9ad256a7-6590-4914-a3c6-0ffe8bbf8816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259754098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1259754098
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2438406483
Short name T496
Test name
Test status
Simulation time 85784118 ps
CPU time 2.26 seconds
Started Jul 28 07:36:44 PM PDT 24
Finished Jul 28 07:36:46 PM PDT 24
Peak memory 206628 kb
Host smart-379bbbd9-a4ef-4a29-9d9e-d39e8bc39247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438406483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2438406483
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.975518506
Short name T176
Test name
Test status
Simulation time 401163064 ps
CPU time 15.94 seconds
Started Jul 28 07:36:46 PM PDT 24
Finished Jul 28 07:37:02 PM PDT 24
Peak memory 215388 kb
Host smart-498d8ded-5cb5-44d3-b63b-2ff479231c46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975518506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.975518506
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1521775481
Short name T698
Test name
Test status
Simulation time 609203371 ps
CPU time 4.02 seconds
Started Jul 28 07:36:47 PM PDT 24
Finished Jul 28 07:36:51 PM PDT 24
Peak memory 206788 kb
Host smart-eae647c1-72c9-4722-86f3-a2927392fecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521775481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1521775481
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3844543015
Short name T829
Test name
Test status
Simulation time 228901463 ps
CPU time 2.97 seconds
Started Jul 28 07:36:43 PM PDT 24
Finished Jul 28 07:36:46 PM PDT 24
Peak memory 210020 kb
Host smart-f43dfdf2-395f-42ab-bc6b-776c306249b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844543015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3844543015
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3930245388
Short name T810
Test name
Test status
Simulation time 11821752 ps
CPU time 0.72 seconds
Started Jul 28 07:36:46 PM PDT 24
Finished Jul 28 07:36:47 PM PDT 24
Peak memory 205792 kb
Host smart-1bde279a-77d8-4938-b0a1-2d3837c686f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930245388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3930245388
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1952190793
Short name T142
Test name
Test status
Simulation time 769995060 ps
CPU time 3.34 seconds
Started Jul 28 07:36:42 PM PDT 24
Finished Jul 28 07:36:45 PM PDT 24
Peak memory 214504 kb
Host smart-045b8d3a-c39c-44cb-b306-5be22cd95949
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1952190793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1952190793
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.740443472
Short name T11
Test name
Test status
Simulation time 128279710 ps
CPU time 4.89 seconds
Started Jul 28 07:36:42 PM PDT 24
Finished Jul 28 07:36:47 PM PDT 24
Peak memory 222552 kb
Host smart-530625f7-2f1c-4450-860d-c7e4a0a244c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740443472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.740443472
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.857754930
Short name T729
Test name
Test status
Simulation time 3176262592 ps
CPU time 21.48 seconds
Started Jul 28 07:36:43 PM PDT 24
Finished Jul 28 07:37:04 PM PDT 24
Peak memory 218332 kb
Host smart-01be2a81-e276-4174-8318-cc98a5258ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857754930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.857754930
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1115135114
Short name T647
Test name
Test status
Simulation time 87814385 ps
CPU time 2.48 seconds
Started Jul 28 07:36:43 PM PDT 24
Finished Jul 28 07:36:46 PM PDT 24
Peak memory 214148 kb
Host smart-4dba3704-2ca9-424f-a51c-38891751b58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115135114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1115135114
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2374683738
Short name T242
Test name
Test status
Simulation time 177975485 ps
CPU time 2 seconds
Started Jul 28 07:36:43 PM PDT 24
Finished Jul 28 07:36:45 PM PDT 24
Peak memory 218760 kb
Host smart-75b93d3d-a84d-4738-afba-f7ba2c8e0f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374683738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2374683738
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3729345561
Short name T481
Test name
Test status
Simulation time 664198125 ps
CPU time 5.37 seconds
Started Jul 28 07:36:40 PM PDT 24
Finished Jul 28 07:36:46 PM PDT 24
Peak memory 222420 kb
Host smart-3cbf2590-dba5-438b-9648-26d7fe058ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729345561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3729345561
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3868693917
Short name T366
Test name
Test status
Simulation time 129957667 ps
CPU time 5.83 seconds
Started Jul 28 07:36:46 PM PDT 24
Finished Jul 28 07:36:52 PM PDT 24
Peak memory 208600 kb
Host smart-1c58284b-a4c6-411f-abee-f2888bbc5321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868693917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3868693917
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3360119608
Short name T875
Test name
Test status
Simulation time 154941026 ps
CPU time 2.98 seconds
Started Jul 28 07:36:42 PM PDT 24
Finished Jul 28 07:36:45 PM PDT 24
Peak memory 206716 kb
Host smart-1db7d050-fda1-4a7d-a263-fa4987361314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360119608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3360119608
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3436520719
Short name T261
Test name
Test status
Simulation time 184234046 ps
CPU time 7.71 seconds
Started Jul 28 07:36:48 PM PDT 24
Finished Jul 28 07:36:55 PM PDT 24
Peak memory 207860 kb
Host smart-373a397b-5a83-4368-b036-c47fa361d902
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436520719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3436520719
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3717397671
Short name T472
Test name
Test status
Simulation time 48419302 ps
CPU time 2.55 seconds
Started Jul 28 07:36:42 PM PDT 24
Finished Jul 28 07:36:44 PM PDT 24
Peak memory 206776 kb
Host smart-2746cef3-2c6e-4a45-a2df-972544e125d4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717397671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3717397671
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2955473296
Short name T397
Test name
Test status
Simulation time 73145318 ps
CPU time 1.76 seconds
Started Jul 28 07:36:41 PM PDT 24
Finished Jul 28 07:36:43 PM PDT 24
Peak memory 206784 kb
Host smart-6bf25ad4-7dad-4b5e-bcf8-10061bcc6cf4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955473296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2955473296
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1338232706
Short name T539
Test name
Test status
Simulation time 86744804 ps
CPU time 1.85 seconds
Started Jul 28 07:36:45 PM PDT 24
Finished Jul 28 07:36:47 PM PDT 24
Peak memory 210396 kb
Host smart-ddf2449e-dce2-4f1f-9984-f662bf0fd8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338232706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1338232706
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.4117074207
Short name T512
Test name
Test status
Simulation time 170798958 ps
CPU time 2.23 seconds
Started Jul 28 07:36:44 PM PDT 24
Finished Jul 28 07:36:46 PM PDT 24
Peak memory 206628 kb
Host smart-97af6fe1-40dd-450a-944a-35844c34a68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117074207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.4117074207
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2911553520
Short name T868
Test name
Test status
Simulation time 772358047 ps
CPU time 10.73 seconds
Started Jul 28 07:36:46 PM PDT 24
Finished Jul 28 07:36:57 PM PDT 24
Peak memory 222320 kb
Host smart-9b82dacb-51b2-43fa-8215-bd1ab7fb29d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911553520 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2911553520
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2098671682
Short name T575
Test name
Test status
Simulation time 197238813 ps
CPU time 3.86 seconds
Started Jul 28 07:36:42 PM PDT 24
Finished Jul 28 07:36:46 PM PDT 24
Peak memory 207600 kb
Host smart-3703ed67-259b-459e-95b0-cad64a32256e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098671682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2098671682
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1020770182
Short name T691
Test name
Test status
Simulation time 123430160 ps
CPU time 1.8 seconds
Started Jul 28 07:36:44 PM PDT 24
Finished Jul 28 07:36:46 PM PDT 24
Peak memory 210024 kb
Host smart-f69ab949-db21-4d0e-a7ed-c1db8b6c99f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020770182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1020770182
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.378813638
Short name T81
Test name
Test status
Simulation time 21048184 ps
CPU time 0.76 seconds
Started Jul 28 07:36:49 PM PDT 24
Finished Jul 28 07:36:49 PM PDT 24
Peak memory 205868 kb
Host smart-9e8df23a-99b4-4a2c-b18d-3e836f7d2bf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378813638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.378813638
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3512788588
Short name T265
Test name
Test status
Simulation time 269255019 ps
CPU time 7.93 seconds
Started Jul 28 07:36:50 PM PDT 24
Finished Jul 28 07:36:58 PM PDT 24
Peak memory 214164 kb
Host smart-0521bc80-799e-4f02-9a8a-5f56e1957f52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3512788588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3512788588
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1583793583
Short name T181
Test name
Test status
Simulation time 71736272 ps
CPU time 2.19 seconds
Started Jul 28 07:36:49 PM PDT 24
Finished Jul 28 07:36:51 PM PDT 24
Peak memory 216380 kb
Host smart-13c972f8-810a-4bfa-a72e-a0d277fe2116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583793583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1583793583
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2009600599
Short name T554
Test name
Test status
Simulation time 296570918 ps
CPU time 3.02 seconds
Started Jul 28 07:36:48 PM PDT 24
Finished Jul 28 07:36:51 PM PDT 24
Peak memory 209736 kb
Host smart-5e3dd7d0-fa67-4896-83aa-388a7b316195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009600599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2009600599
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3904638850
Short name T95
Test name
Test status
Simulation time 153614497 ps
CPU time 2.6 seconds
Started Jul 28 07:36:58 PM PDT 24
Finished Jul 28 07:37:01 PM PDT 24
Peak memory 208584 kb
Host smart-d872ecf4-95d7-4610-8100-ce5e08c3b675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904638850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3904638850
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2885205399
Short name T222
Test name
Test status
Simulation time 74475739 ps
CPU time 3.77 seconds
Started Jul 28 07:36:50 PM PDT 24
Finished Jul 28 07:36:54 PM PDT 24
Peak memory 214128 kb
Host smart-dd15ddba-ec43-4ae5-8dcb-aaf536981c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885205399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2885205399
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.2650041149
Short name T699
Test name
Test status
Simulation time 4614209704 ps
CPU time 29.91 seconds
Started Jul 28 07:36:49 PM PDT 24
Finished Jul 28 07:37:19 PM PDT 24
Peak memory 208556 kb
Host smart-3b50d371-c7d4-4dac-a499-861b0eccf3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650041149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2650041149
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.713953505
Short name T459
Test name
Test status
Simulation time 316200455 ps
CPU time 6.57 seconds
Started Jul 28 07:36:48 PM PDT 24
Finished Jul 28 07:36:54 PM PDT 24
Peak memory 207664 kb
Host smart-cfe52908-2ade-46a7-9d88-fb40bd700d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713953505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.713953505
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.578413714
Short name T692
Test name
Test status
Simulation time 113487457 ps
CPU time 3.18 seconds
Started Jul 28 07:36:47 PM PDT 24
Finished Jul 28 07:36:50 PM PDT 24
Peak memory 208204 kb
Host smart-342f2943-8e27-42be-a8bd-c37c5ff21f1d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578413714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.578413714
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2283245608
Short name T338
Test name
Test status
Simulation time 621499893 ps
CPU time 15.29 seconds
Started Jul 28 07:36:51 PM PDT 24
Finished Jul 28 07:37:06 PM PDT 24
Peak memory 208720 kb
Host smart-ae485679-7b3d-4b8e-9f2f-12f2c277a5b1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283245608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2283245608
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1166250502
Short name T870
Test name
Test status
Simulation time 152894773 ps
CPU time 4.85 seconds
Started Jul 28 07:36:46 PM PDT 24
Finished Jul 28 07:36:51 PM PDT 24
Peak memory 208432 kb
Host smart-e13e11f4-4924-4e4a-8e73-acd203ca0d46
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166250502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1166250502
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2598034288
Short name T518
Test name
Test status
Simulation time 84231677 ps
CPU time 2.48 seconds
Started Jul 28 07:36:52 PM PDT 24
Finished Jul 28 07:36:55 PM PDT 24
Peak memory 208076 kb
Host smart-bf56a028-ee9e-4a6f-9119-4f327b1828f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598034288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2598034288
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3991173090
Short name T831
Test name
Test status
Simulation time 180605716 ps
CPU time 2.68 seconds
Started Jul 28 07:36:50 PM PDT 24
Finished Jul 28 07:36:53 PM PDT 24
Peak memory 206756 kb
Host smart-601c109c-ac39-45e4-a2ff-aeb2091151a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991173090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3991173090
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.848242551
Short name T371
Test name
Test status
Simulation time 1180655578 ps
CPU time 33.85 seconds
Started Jul 28 07:36:51 PM PDT 24
Finished Jul 28 07:37:25 PM PDT 24
Peak memory 216344 kb
Host smart-27c5e187-9f86-4f21-99e6-8cd9dea24fab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848242551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.848242551
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.701231933
Short name T231
Test name
Test status
Simulation time 817506253 ps
CPU time 4.76 seconds
Started Jul 28 07:36:49 PM PDT 24
Finished Jul 28 07:36:54 PM PDT 24
Peak memory 209100 kb
Host smart-e9155be9-a804-4224-b53d-364e6f923553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701231933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.701231933
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2876831105
Short name T711
Test name
Test status
Simulation time 141640845 ps
CPU time 2.4 seconds
Started Jul 28 07:36:48 PM PDT 24
Finished Jul 28 07:36:51 PM PDT 24
Peak memory 210360 kb
Host smart-c63e6c4c-4171-484e-a491-e58d17f72a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876831105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2876831105
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.969338331
Short name T132
Test name
Test status
Simulation time 8291235 ps
CPU time 0.81 seconds
Started Jul 28 07:36:51 PM PDT 24
Finished Jul 28 07:36:51 PM PDT 24
Peak memory 205848 kb
Host smart-1307e0e8-379d-4955-b40f-cee012a07eaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969338331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.969338331
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1796198902
Short name T712
Test name
Test status
Simulation time 246768043 ps
CPU time 2.17 seconds
Started Jul 28 07:36:48 PM PDT 24
Finished Jul 28 07:36:51 PM PDT 24
Peak memory 207536 kb
Host smart-54b415f2-a69e-42a6-a9c2-f0699a8b077a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796198902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1796198902
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1727586752
Short name T470
Test name
Test status
Simulation time 211834977 ps
CPU time 2.73 seconds
Started Jul 28 07:36:50 PM PDT 24
Finished Jul 28 07:36:52 PM PDT 24
Peak memory 214368 kb
Host smart-568f2cd9-1fd1-4a57-a421-39a6fa62a146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727586752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1727586752
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.438712577
Short name T477
Test name
Test status
Simulation time 34563671 ps
CPU time 1.97 seconds
Started Jul 28 07:36:50 PM PDT 24
Finished Jul 28 07:36:52 PM PDT 24
Peak memory 215880 kb
Host smart-3c3c9111-c825-4e5a-8ac9-bbb73a4854fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438712577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.438712577
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2452782422
Short name T307
Test name
Test status
Simulation time 233885086 ps
CPU time 6.16 seconds
Started Jul 28 07:36:51 PM PDT 24
Finished Jul 28 07:36:58 PM PDT 24
Peak memory 208632 kb
Host smart-614ee6e4-b600-471a-a3c8-9a9f9ddfdd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452782422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2452782422
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2143038726
Short name T904
Test name
Test status
Simulation time 119246189 ps
CPU time 1.83 seconds
Started Jul 28 07:36:51 PM PDT 24
Finished Jul 28 07:36:53 PM PDT 24
Peak memory 206684 kb
Host smart-f2802e84-243b-4ed4-a738-51502ed242b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143038726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2143038726
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.574160170
Short name T832
Test name
Test status
Simulation time 66652076 ps
CPU time 2.48 seconds
Started Jul 28 07:36:50 PM PDT 24
Finished Jul 28 07:36:53 PM PDT 24
Peak memory 207188 kb
Host smart-aeb03b14-8510-4a81-9975-3f0c1ca33d61
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574160170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.574160170
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2672206001
Short name T455
Test name
Test status
Simulation time 623627989 ps
CPU time 12.24 seconds
Started Jul 28 07:36:52 PM PDT 24
Finished Jul 28 07:37:04 PM PDT 24
Peak memory 208084 kb
Host smart-9bc662bb-d7b2-47fb-ab54-38c497ddc2a5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672206001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2672206001
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2810677925
Short name T769
Test name
Test status
Simulation time 129403157 ps
CPU time 3.84 seconds
Started Jul 28 07:36:49 PM PDT 24
Finished Jul 28 07:36:53 PM PDT 24
Peak memory 207812 kb
Host smart-5eff0ec2-a906-449d-aa08-6c2be284dcd8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810677925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2810677925
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2825324776
Short name T276
Test name
Test status
Simulation time 162728806 ps
CPU time 1.79 seconds
Started Jul 28 07:36:52 PM PDT 24
Finished Jul 28 07:36:54 PM PDT 24
Peak memory 214204 kb
Host smart-79765051-51b9-47e6-8d7a-fb6a160985c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825324776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2825324776
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.4243235124
Short name T584
Test name
Test status
Simulation time 541239786 ps
CPU time 5.1 seconds
Started Jul 28 07:36:49 PM PDT 24
Finished Jul 28 07:36:54 PM PDT 24
Peak memory 208048 kb
Host smart-bbc6fd4f-6a5d-42b4-acac-b8a94bdfd1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243235124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.4243235124
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1663640176
Short name T457
Test name
Test status
Simulation time 39298461 ps
CPU time 2.21 seconds
Started Jul 28 07:36:51 PM PDT 24
Finished Jul 28 07:36:54 PM PDT 24
Peak memory 206780 kb
Host smart-ce5bcfc6-18f4-4bc0-b1c0-54a7a956f40c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663640176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1663640176
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.151083337
Short name T26
Test name
Test status
Simulation time 109324149 ps
CPU time 4.58 seconds
Started Jul 28 07:36:51 PM PDT 24
Finished Jul 28 07:36:56 PM PDT 24
Peak memory 207520 kb
Host smart-03127889-147f-4e30-8123-6836db3a94df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151083337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.151083337
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3659472869
Short name T682
Test name
Test status
Simulation time 1651721838 ps
CPU time 24.05 seconds
Started Jul 28 07:36:47 PM PDT 24
Finished Jul 28 07:37:11 PM PDT 24
Peak memory 210852 kb
Host smart-7362b731-c88c-4cd3-a129-b416513b9964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659472869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3659472869
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1017437620
Short name T781
Test name
Test status
Simulation time 28509628 ps
CPU time 0.93 seconds
Started Jul 28 07:36:57 PM PDT 24
Finished Jul 28 07:36:58 PM PDT 24
Peak memory 205884 kb
Host smart-2371a72f-93fc-4cb6-b8c6-e48353f3df70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017437620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1017437620
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3332240013
Short name T251
Test name
Test status
Simulation time 44089062 ps
CPU time 3.61 seconds
Started Jul 28 07:36:58 PM PDT 24
Finished Jul 28 07:37:02 PM PDT 24
Peak memory 214848 kb
Host smart-c45c899c-1ca9-4f91-aa90-7e6198aced66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3332240013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3332240013
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.69028239
Short name T21
Test name
Test status
Simulation time 351900642 ps
CPU time 2.14 seconds
Started Jul 28 07:36:54 PM PDT 24
Finished Jul 28 07:36:57 PM PDT 24
Peak memory 214372 kb
Host smart-cfc57e06-f807-431f-82bd-00fd3db82a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69028239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.69028239
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2910646325
Short name T825
Test name
Test status
Simulation time 99836500 ps
CPU time 2.1 seconds
Started Jul 28 07:37:00 PM PDT 24
Finished Jul 28 07:37:02 PM PDT 24
Peak memory 218184 kb
Host smart-02c4c605-83cd-4755-a2e0-5c5dc7cea30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910646325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2910646325
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.4047034033
Short name T908
Test name
Test status
Simulation time 355549950 ps
CPU time 2.94 seconds
Started Jul 28 07:36:53 PM PDT 24
Finished Jul 28 07:36:56 PM PDT 24
Peak memory 214176 kb
Host smart-0a97133d-7fff-46f8-ab3c-2777de73483f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047034033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.4047034033
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3678034748
Short name T7
Test name
Test status
Simulation time 50016436 ps
CPU time 1.82 seconds
Started Jul 28 07:37:00 PM PDT 24
Finished Jul 28 07:37:02 PM PDT 24
Peak memory 214464 kb
Host smart-fbf74292-2a54-4fd8-8992-4fa9ccca77af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678034748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3678034748
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1123857803
Short name T474
Test name
Test status
Simulation time 1682919549 ps
CPU time 7.46 seconds
Started Jul 28 07:36:54 PM PDT 24
Finished Jul 28 07:37:02 PM PDT 24
Peak memory 214128 kb
Host smart-2ba0a228-3b45-4d83-a73f-84193aad164b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123857803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1123857803
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1042726013
Short name T651
Test name
Test status
Simulation time 958591579 ps
CPU time 6.6 seconds
Started Jul 28 07:36:57 PM PDT 24
Finished Jul 28 07:37:04 PM PDT 24
Peak memory 208272 kb
Host smart-96a405f0-67cb-42f9-b37d-97125a2b01cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042726013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1042726013
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3343075426
Short name T367
Test name
Test status
Simulation time 91809949 ps
CPU time 2.36 seconds
Started Jul 28 07:36:57 PM PDT 24
Finished Jul 28 07:37:00 PM PDT 24
Peak memory 206744 kb
Host smart-527923bd-5915-4168-8e11-927bef12a19b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343075426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3343075426
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2358306890
Short name T520
Test name
Test status
Simulation time 67267527 ps
CPU time 2.21 seconds
Started Jul 28 07:36:56 PM PDT 24
Finished Jul 28 07:36:59 PM PDT 24
Peak memory 206776 kb
Host smart-7e430f1b-f96a-4f51-931a-671536bf3823
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358306890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2358306890
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.4119737867
Short name T102
Test name
Test status
Simulation time 1096875352 ps
CPU time 13.32 seconds
Started Jul 28 07:36:54 PM PDT 24
Finished Jul 28 07:37:08 PM PDT 24
Peak memory 208052 kb
Host smart-6280aa93-5864-498f-b816-2aebfc93d7a7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119737867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.4119737867
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1527046135
Short name T138
Test name
Test status
Simulation time 88562670 ps
CPU time 3.85 seconds
Started Jul 28 07:36:57 PM PDT 24
Finished Jul 28 07:37:01 PM PDT 24
Peak memory 218164 kb
Host smart-d65493f2-5e5e-433e-ab33-29fcbfad268b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527046135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1527046135
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.414142438
Short name T423
Test name
Test status
Simulation time 425258587 ps
CPU time 2.69 seconds
Started Jul 28 07:36:50 PM PDT 24
Finished Jul 28 07:36:53 PM PDT 24
Peak memory 206700 kb
Host smart-6c6bd6b4-0e88-4414-9072-d44f460c1d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414142438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.414142438
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.927111481
Short name T530
Test name
Test status
Simulation time 2838171649 ps
CPU time 31.94 seconds
Started Jul 28 07:36:58 PM PDT 24
Finished Jul 28 07:37:30 PM PDT 24
Peak memory 220920 kb
Host smart-5511a9bd-7910-48cf-853e-9bbe60732ba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927111481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.927111481
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.1931940885
Short name T187
Test name
Test status
Simulation time 917775618 ps
CPU time 16.07 seconds
Started Jul 28 07:36:52 PM PDT 24
Finished Jul 28 07:37:08 PM PDT 24
Peak memory 220648 kb
Host smart-1e44f5e6-eb73-4360-a775-51da7b3fc2ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931940885 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.1931940885
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3517272630
Short name T593
Test name
Test status
Simulation time 277643156 ps
CPU time 6.87 seconds
Started Jul 28 07:36:57 PM PDT 24
Finished Jul 28 07:37:04 PM PDT 24
Peak memory 209556 kb
Host smart-113a227a-a528-4843-a093-7b3eced410a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517272630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3517272630
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.119858369
Short name T39
Test name
Test status
Simulation time 308255161 ps
CPU time 2.52 seconds
Started Jul 28 07:36:55 PM PDT 24
Finished Jul 28 07:36:58 PM PDT 24
Peak memory 210344 kb
Host smart-a2b79700-02ec-4ac0-bd18-61c3170339c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119858369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.119858369
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.936625214
Short name T79
Test name
Test status
Simulation time 23669746 ps
CPU time 0.8 seconds
Started Jul 28 07:37:00 PM PDT 24
Finished Jul 28 07:37:01 PM PDT 24
Peak memory 205804 kb
Host smart-bee1331a-bb7a-4bd8-92d2-a73f99a25911
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936625214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.936625214
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.552090114
Short name T144
Test name
Test status
Simulation time 198686218 ps
CPU time 10.61 seconds
Started Jul 28 07:36:56 PM PDT 24
Finished Jul 28 07:37:07 PM PDT 24
Peak memory 215052 kb
Host smart-42bb17c1-467c-409f-bc97-758f39e0aca1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=552090114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.552090114
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1715813476
Short name T70
Test name
Test status
Simulation time 505572637 ps
CPU time 3.62 seconds
Started Jul 28 07:36:58 PM PDT 24
Finished Jul 28 07:37:02 PM PDT 24
Peak memory 214352 kb
Host smart-0a4039c2-6c1e-4f9b-b2cc-d629e58fe447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715813476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1715813476
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.4008420376
Short name T608
Test name
Test status
Simulation time 56456344 ps
CPU time 2.56 seconds
Started Jul 28 07:36:50 PM PDT 24
Finished Jul 28 07:36:53 PM PDT 24
Peak memory 209260 kb
Host smart-832bf932-af61-4d62-b6be-30191b334a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008420376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.4008420376
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3217436635
Short name T545
Test name
Test status
Simulation time 92876398 ps
CPU time 3.41 seconds
Started Jul 28 07:36:53 PM PDT 24
Finished Jul 28 07:36:57 PM PDT 24
Peak memory 214088 kb
Host smart-5e8feced-265f-4816-ad7b-f35a11c044c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217436635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3217436635
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.4108687698
Short name T245
Test name
Test status
Simulation time 1282874303 ps
CPU time 6.87 seconds
Started Jul 28 07:36:56 PM PDT 24
Finished Jul 28 07:37:03 PM PDT 24
Peak memory 222256 kb
Host smart-b751f35c-15ca-4bda-a08d-16fd6afddd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108687698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.4108687698
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1093662933
Short name T408
Test name
Test status
Simulation time 81301868 ps
CPU time 3.57 seconds
Started Jul 28 07:36:53 PM PDT 24
Finished Jul 28 07:36:57 PM PDT 24
Peak memory 216220 kb
Host smart-47a4aae6-fbeb-4dbf-b591-3f5e27e78912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093662933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1093662933
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1882169932
Short name T881
Test name
Test status
Simulation time 696102014 ps
CPU time 4.66 seconds
Started Jul 28 07:36:56 PM PDT 24
Finished Jul 28 07:37:01 PM PDT 24
Peak memory 208880 kb
Host smart-5114a174-c508-46dc-a2d7-208aa872160a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882169932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1882169932
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2190347408
Short name T743
Test name
Test status
Simulation time 1210373342 ps
CPU time 27.05 seconds
Started Jul 28 07:36:59 PM PDT 24
Finished Jul 28 07:37:27 PM PDT 24
Peak memory 208272 kb
Host smart-c0ece063-4547-48fe-b07b-d930bb2e2add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190347408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2190347408
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2104325095
Short name T895
Test name
Test status
Simulation time 75977242 ps
CPU time 3.55 seconds
Started Jul 28 07:36:56 PM PDT 24
Finished Jul 28 07:37:00 PM PDT 24
Peak memory 208688 kb
Host smart-297d9285-44cb-4c43-941a-8b8a7b76a428
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104325095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2104325095
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.41452211
Short name T252
Test name
Test status
Simulation time 922900770 ps
CPU time 7.03 seconds
Started Jul 28 07:36:57 PM PDT 24
Finished Jul 28 07:37:04 PM PDT 24
Peak memory 208456 kb
Host smart-33bca2a8-7bb5-4245-8b91-c9f8a171ed9b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41452211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.41452211
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.343168326
Short name T345
Test name
Test status
Simulation time 7879055885 ps
CPU time 19.34 seconds
Started Jul 28 07:36:55 PM PDT 24
Finished Jul 28 07:37:15 PM PDT 24
Peak memory 207844 kb
Host smart-96c7a11a-3326-44fd-b41a-770eac05a2bc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343168326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.343168326
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3274681584
Short name T824
Test name
Test status
Simulation time 29119914 ps
CPU time 2.09 seconds
Started Jul 28 07:37:00 PM PDT 24
Finished Jul 28 07:37:02 PM PDT 24
Peak memory 208064 kb
Host smart-b665cef0-60cd-40f0-968a-67520e0404a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274681584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3274681584
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.4184639119
Short name T901
Test name
Test status
Simulation time 155133921 ps
CPU time 3.88 seconds
Started Jul 28 07:36:53 PM PDT 24
Finished Jul 28 07:36:57 PM PDT 24
Peak memory 206704 kb
Host smart-9da7747e-d5ec-413f-9776-0c95e13482b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184639119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.4184639119
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3422343713
Short name T340
Test name
Test status
Simulation time 1461179721 ps
CPU time 25.58 seconds
Started Jul 28 07:36:57 PM PDT 24
Finished Jul 28 07:37:23 PM PDT 24
Peak memory 219072 kb
Host smart-103f3d48-5a12-4d88-8a09-358d281a02a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422343713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3422343713
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.2826411856
Short name T744
Test name
Test status
Simulation time 2343169862 ps
CPU time 11.36 seconds
Started Jul 28 07:37:02 PM PDT 24
Finished Jul 28 07:37:14 PM PDT 24
Peak memory 222368 kb
Host smart-7142eef0-f612-4a69-ac6e-1096f9b32554
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826411856 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.2826411856
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1227097563
Short name T282
Test name
Test status
Simulation time 513937617 ps
CPU time 7.32 seconds
Started Jul 28 07:36:55 PM PDT 24
Finished Jul 28 07:37:03 PM PDT 24
Peak memory 209772 kb
Host smart-16f4f1f7-be51-416b-84a7-a9f0a8e3123f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227097563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1227097563
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.882282892
Short name T380
Test name
Test status
Simulation time 126165647 ps
CPU time 1.41 seconds
Started Jul 28 07:36:59 PM PDT 24
Finished Jul 28 07:37:01 PM PDT 24
Peak memory 209664 kb
Host smart-2e2df31d-9c82-4621-bf2d-4ff0ab4d2579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882282892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.882282892
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.922421947
Short name T730
Test name
Test status
Simulation time 163702978 ps
CPU time 0.76 seconds
Started Jul 28 07:35:41 PM PDT 24
Finished Jul 28 07:35:42 PM PDT 24
Peak memory 205860 kb
Host smart-c29a5680-3820-487e-937b-d6de1f13289b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922421947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.922421947
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1459795738
Short name T219
Test name
Test status
Simulation time 1289177431 ps
CPU time 29.37 seconds
Started Jul 28 07:35:40 PM PDT 24
Finished Jul 28 07:36:09 PM PDT 24
Peak memory 222412 kb
Host smart-3cece1f2-44cc-4c55-8d09-1723a66f398e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459795738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1459795738
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2381306221
Short name T894
Test name
Test status
Simulation time 731931950 ps
CPU time 5.72 seconds
Started Jul 28 07:35:39 PM PDT 24
Finished Jul 28 07:35:45 PM PDT 24
Peak memory 207572 kb
Host smart-04ae8c9a-ed69-4c64-851c-e9c247be5662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381306221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2381306221
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1993159367
Short name T635
Test name
Test status
Simulation time 235797151 ps
CPU time 1.99 seconds
Started Jul 28 07:35:39 PM PDT 24
Finished Jul 28 07:35:41 PM PDT 24
Peak memory 214188 kb
Host smart-ff72cb99-8dea-49ce-b8ba-d8cef7983206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993159367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1993159367
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.117078749
Short name T697
Test name
Test status
Simulation time 93823118 ps
CPU time 4.22 seconds
Started Jul 28 07:35:37 PM PDT 24
Finished Jul 28 07:35:42 PM PDT 24
Peak memory 214048 kb
Host smart-e9b56ec3-b719-4522-9db6-111f1c5dcfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117078749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.117078749
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1734328025
Short name T217
Test name
Test status
Simulation time 114486186 ps
CPU time 2.38 seconds
Started Jul 28 07:35:41 PM PDT 24
Finished Jul 28 07:35:43 PM PDT 24
Peak memory 208200 kb
Host smart-99ca81fe-9f27-433c-af89-2ec101f80b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734328025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1734328025
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.796214771
Short name T751
Test name
Test status
Simulation time 132409419 ps
CPU time 4.55 seconds
Started Jul 28 07:35:41 PM PDT 24
Finished Jul 28 07:35:45 PM PDT 24
Peak memory 208420 kb
Host smart-933f97c4-db3e-419b-8ca5-73cd1fbfa9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796214771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.796214771
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.805294839
Short name T359
Test name
Test status
Simulation time 158078519 ps
CPU time 4.35 seconds
Started Jul 28 07:35:36 PM PDT 24
Finished Jul 28 07:35:41 PM PDT 24
Peak memory 208488 kb
Host smart-f2264847-6768-48fe-a15e-d405b618ed5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805294839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.805294839
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1395100991
Short name T580
Test name
Test status
Simulation time 173114681 ps
CPU time 5.01 seconds
Started Jul 28 07:35:38 PM PDT 24
Finished Jul 28 07:35:43 PM PDT 24
Peak memory 208592 kb
Host smart-5318042e-66df-4b69-8f9a-db697e7093ae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395100991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1395100991
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.4078759905
Short name T203
Test name
Test status
Simulation time 277558345 ps
CPU time 3.04 seconds
Started Jul 28 07:35:41 PM PDT 24
Finished Jul 28 07:35:44 PM PDT 24
Peak memory 206688 kb
Host smart-fa1d0303-5419-462b-bb37-fe6d0f320950
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078759905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.4078759905
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2276800618
Short name T864
Test name
Test status
Simulation time 152106187 ps
CPU time 3.83 seconds
Started Jul 28 07:35:36 PM PDT 24
Finished Jul 28 07:35:40 PM PDT 24
Peak memory 208352 kb
Host smart-b804a978-5ed2-40cc-b092-4bf4e23f1ddf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276800618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2276800618
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1773145998
Short name T876
Test name
Test status
Simulation time 53019705 ps
CPU time 2.79 seconds
Started Jul 28 07:35:41 PM PDT 24
Finished Jul 28 07:35:44 PM PDT 24
Peak memory 209284 kb
Host smart-b2b0a9ee-c6a5-46d4-bef9-6739cc1c9e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773145998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1773145998
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1439743160
Short name T527
Test name
Test status
Simulation time 274957325 ps
CPU time 3.01 seconds
Started Jul 28 07:35:38 PM PDT 24
Finished Jul 28 07:35:41 PM PDT 24
Peak memory 208340 kb
Host smart-274d70ef-34b3-47b4-98c0-584672ac891d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439743160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1439743160
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.4227079744
Short name T82
Test name
Test status
Simulation time 242513731 ps
CPU time 3.09 seconds
Started Jul 28 07:35:38 PM PDT 24
Finished Jul 28 07:35:41 PM PDT 24
Peak memory 207080 kb
Host smart-87a87ae5-29a4-4116-9e01-b0f245f2b221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227079744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.4227079744
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1316604775
Short name T378
Test name
Test status
Simulation time 44181038 ps
CPU time 1.96 seconds
Started Jul 28 07:35:39 PM PDT 24
Finished Jul 28 07:35:41 PM PDT 24
Peak memory 209744 kb
Host smart-97ec61ab-94c7-421a-ae98-5424665103b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316604775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1316604775
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2186178001
Short name T808
Test name
Test status
Simulation time 24138279 ps
CPU time 0.77 seconds
Started Jul 28 07:37:03 PM PDT 24
Finished Jul 28 07:37:04 PM PDT 24
Peak memory 205900 kb
Host smart-1b7fb353-2d4c-4953-be0e-57083dca40b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186178001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2186178001
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1682545757
Short name T232
Test name
Test status
Simulation time 2252374324 ps
CPU time 8.26 seconds
Started Jul 28 07:37:04 PM PDT 24
Finished Jul 28 07:37:12 PM PDT 24
Peak memory 215516 kb
Host smart-789ca26c-40e9-4ca4-9ba9-3f1216df6221
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1682545757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1682545757
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1592358585
Short name T29
Test name
Test status
Simulation time 136484846 ps
CPU time 3.41 seconds
Started Jul 28 07:37:06 PM PDT 24
Finished Jul 28 07:37:09 PM PDT 24
Peak memory 209572 kb
Host smart-48381149-51ea-4911-9e15-de21de46cdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592358585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1592358585
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2956993493
Short name T58
Test name
Test status
Simulation time 24334664 ps
CPU time 1.75 seconds
Started Jul 28 07:37:04 PM PDT 24
Finished Jul 28 07:37:06 PM PDT 24
Peak memory 207604 kb
Host smart-db4fb504-b72a-4a30-9763-c9870fa76f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956993493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2956993493
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3513612108
Short name T221
Test name
Test status
Simulation time 350411874 ps
CPU time 4.58 seconds
Started Jul 28 07:36:59 PM PDT 24
Finished Jul 28 07:37:04 PM PDT 24
Peak memory 214252 kb
Host smart-426e5930-8fe4-4031-a5c9-4fc55dc96d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513612108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3513612108
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1018612674
Short name T801
Test name
Test status
Simulation time 293552870 ps
CPU time 5.9 seconds
Started Jul 28 07:37:00 PM PDT 24
Finished Jul 28 07:37:06 PM PDT 24
Peak memory 214172 kb
Host smart-7fd65e2d-345b-4789-8f1a-c6fdb1670ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018612674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1018612674
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.724524512
Short name T446
Test name
Test status
Simulation time 222040877 ps
CPU time 2.85 seconds
Started Jul 28 07:37:00 PM PDT 24
Finished Jul 28 07:37:03 PM PDT 24
Peak memory 206752 kb
Host smart-4f39d5fb-18cd-4ed2-9dbd-f4658e585bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724524512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.724524512
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.399050453
Short name T906
Test name
Test status
Simulation time 2938251581 ps
CPU time 48.35 seconds
Started Jul 28 07:37:00 PM PDT 24
Finished Jul 28 07:37:49 PM PDT 24
Peak memory 208032 kb
Host smart-0e3de8d7-fc64-4de5-8c51-0008394b2edb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399050453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.399050453
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3698861567
Short name T872
Test name
Test status
Simulation time 226308983 ps
CPU time 7.89 seconds
Started Jul 28 07:37:00 PM PDT 24
Finished Jul 28 07:37:08 PM PDT 24
Peak memory 208504 kb
Host smart-c3c8e7e3-3d93-4fb3-be64-163452ba8e13
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698861567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3698861567
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2078884860
Short name T785
Test name
Test status
Simulation time 258478202 ps
CPU time 5.64 seconds
Started Jul 28 07:37:04 PM PDT 24
Finished Jul 28 07:37:10 PM PDT 24
Peak memory 206764 kb
Host smart-770ff4c9-b167-48b7-b222-e439523ef7dc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078884860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2078884860
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.329795499
Short name T867
Test name
Test status
Simulation time 278095748 ps
CPU time 7.2 seconds
Started Jul 28 07:37:00 PM PDT 24
Finished Jul 28 07:37:07 PM PDT 24
Peak memory 209536 kb
Host smart-3781c112-a705-483b-ab5c-8804a52e77bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329795499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.329795499
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2000677631
Short name T900
Test name
Test status
Simulation time 127982541 ps
CPU time 3.14 seconds
Started Jul 28 07:37:02 PM PDT 24
Finished Jul 28 07:37:06 PM PDT 24
Peak memory 206576 kb
Host smart-71bbf019-9655-417c-8ad1-f3e9a7f202b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000677631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2000677631
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.790471326
Short name T591
Test name
Test status
Simulation time 19431686207 ps
CPU time 141.12 seconds
Started Jul 28 07:37:04 PM PDT 24
Finished Jul 28 07:39:25 PM PDT 24
Peak memory 216312 kb
Host smart-ac32bc88-0b96-4f33-a0cf-6e845bbcedb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790471326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.790471326
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3908817740
Short name T259
Test name
Test status
Simulation time 544774703 ps
CPU time 6.19 seconds
Started Jul 28 07:37:00 PM PDT 24
Finished Jul 28 07:37:06 PM PDT 24
Peak memory 218032 kb
Host smart-77dbed63-72a6-4c66-a5e4-601f36893431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908817740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3908817740
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.953599547
Short name T533
Test name
Test status
Simulation time 2526438385 ps
CPU time 4.51 seconds
Started Jul 28 07:37:04 PM PDT 24
Finished Jul 28 07:37:08 PM PDT 24
Peak memory 210216 kb
Host smart-5d63c0c6-f7bd-4fe0-9952-3ed6eca57549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953599547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.953599547
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3635269914
Short name T725
Test name
Test status
Simulation time 19119990 ps
CPU time 1.01 seconds
Started Jul 28 07:37:06 PM PDT 24
Finished Jul 28 07:37:07 PM PDT 24
Peak memory 205968 kb
Host smart-a78d05a2-062f-4fe3-90f4-763187ec4581
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635269914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3635269914
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.764128219
Short name T428
Test name
Test status
Simulation time 409989576 ps
CPU time 3.77 seconds
Started Jul 28 07:37:08 PM PDT 24
Finished Jul 28 07:37:12 PM PDT 24
Peak memory 217548 kb
Host smart-c6ae9742-4ae2-4d84-b904-5e2821ed5040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764128219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.764128219
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1364517087
Short name T370
Test name
Test status
Simulation time 106904879 ps
CPU time 4.13 seconds
Started Jul 28 07:37:08 PM PDT 24
Finished Jul 28 07:37:12 PM PDT 24
Peak memory 218184 kb
Host smart-65e0e47d-5150-486c-93ad-6bbd99252825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364517087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1364517087
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.603379940
Short name T372
Test name
Test status
Simulation time 185000517 ps
CPU time 2.71 seconds
Started Jul 28 07:37:05 PM PDT 24
Finished Jul 28 07:37:08 PM PDT 24
Peak memory 214060 kb
Host smart-3826c9dc-c26c-4c7b-86ee-dd95cf523677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603379940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.603379940
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1500453040
Short name T301
Test name
Test status
Simulation time 35958965 ps
CPU time 2.73 seconds
Started Jul 28 07:37:07 PM PDT 24
Finished Jul 28 07:37:10 PM PDT 24
Peak memory 209540 kb
Host smart-8393467b-d0a8-4418-8979-7f31530b7414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500453040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1500453040
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3388035740
Short name T495
Test name
Test status
Simulation time 72463670 ps
CPU time 2.99 seconds
Started Jul 28 07:37:06 PM PDT 24
Finished Jul 28 07:37:10 PM PDT 24
Peak memory 214172 kb
Host smart-8f257a3f-aa50-423b-b1c4-8dd9476f2f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388035740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3388035740
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3297635440
Short name T899
Test name
Test status
Simulation time 56981102 ps
CPU time 2.69 seconds
Started Jul 28 07:37:01 PM PDT 24
Finished Jul 28 07:37:04 PM PDT 24
Peak memory 207868 kb
Host smart-6269d009-6f29-476a-9ec9-7af7aa165c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297635440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3297635440
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3664176343
Short name T713
Test name
Test status
Simulation time 234278870 ps
CPU time 5.13 seconds
Started Jul 28 07:37:06 PM PDT 24
Finished Jul 28 07:37:12 PM PDT 24
Peak memory 208480 kb
Host smart-3424c852-4b43-4a7a-8dab-3a26bf00755e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664176343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3664176343
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.814410838
Short name T270
Test name
Test status
Simulation time 27702254 ps
CPU time 2.12 seconds
Started Jul 28 07:37:06 PM PDT 24
Finished Jul 28 07:37:08 PM PDT 24
Peak memory 208204 kb
Host smart-dee019d6-a0b4-4355-8bc4-213980227ba0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814410838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.814410838
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.4236142992
Short name T694
Test name
Test status
Simulation time 143482654 ps
CPU time 2.64 seconds
Started Jul 28 07:37:06 PM PDT 24
Finished Jul 28 07:37:09 PM PDT 24
Peak memory 208692 kb
Host smart-b55a7839-703c-4c64-8bc3-5c29b72e00dc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236142992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.4236142992
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1294530233
Short name T857
Test name
Test status
Simulation time 55052131 ps
CPU time 2.5 seconds
Started Jul 28 07:37:03 PM PDT 24
Finished Jul 28 07:37:06 PM PDT 24
Peak memory 208468 kb
Host smart-9e4ab258-d185-4316-994c-3d51ebfff613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294530233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1294530233
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.787161244
Short name T733
Test name
Test status
Simulation time 43729017 ps
CPU time 2.25 seconds
Started Jul 28 07:37:01 PM PDT 24
Finished Jul 28 07:37:03 PM PDT 24
Peak memory 208272 kb
Host smart-20601ddd-f354-4fd0-93c6-a66c8c0c29ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787161244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.787161244
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2187866357
Short name T303
Test name
Test status
Simulation time 56527953 ps
CPU time 3.63 seconds
Started Jul 28 07:37:02 PM PDT 24
Finished Jul 28 07:37:06 PM PDT 24
Peak memory 209720 kb
Host smart-b315525b-f415-44db-b94f-1f2e5ecdaee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187866357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2187866357
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1737905632
Short name T700
Test name
Test status
Simulation time 69558267 ps
CPU time 1.97 seconds
Started Jul 28 07:37:08 PM PDT 24
Finished Jul 28 07:37:10 PM PDT 24
Peak memory 209748 kb
Host smart-26beac59-afeb-400f-9459-6eeb451e4929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737905632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1737905632
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3406770566
Short name T892
Test name
Test status
Simulation time 28641549 ps
CPU time 0.72 seconds
Started Jul 28 07:37:14 PM PDT 24
Finished Jul 28 07:37:15 PM PDT 24
Peak memory 205908 kb
Host smart-ef08fc85-734f-454a-a0df-ade52b9e3ef0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406770566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3406770566
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3744601107
Short name T724
Test name
Test status
Simulation time 72167654 ps
CPU time 3.09 seconds
Started Jul 28 07:37:17 PM PDT 24
Finished Jul 28 07:37:20 PM PDT 24
Peak memory 222548 kb
Host smart-28e3bf41-7f51-4f50-95f9-11a310f25876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744601107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3744601107
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1060216966
Short name T278
Test name
Test status
Simulation time 177000226 ps
CPU time 3.21 seconds
Started Jul 28 07:37:03 PM PDT 24
Finished Jul 28 07:37:07 PM PDT 24
Peak memory 218472 kb
Host smart-028c1908-5869-42ba-bd00-387f462f46a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060216966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1060216966
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3496705274
Short name T613
Test name
Test status
Simulation time 85390088 ps
CPU time 2.91 seconds
Started Jul 28 07:37:06 PM PDT 24
Finished Jul 28 07:37:09 PM PDT 24
Peak memory 205944 kb
Host smart-8c78f4dd-ac7c-4225-9ba3-f1dd6dd7edeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496705274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3496705274
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.885698782
Short name T508
Test name
Test status
Simulation time 275846730 ps
CPU time 4.81 seconds
Started Jul 28 07:37:07 PM PDT 24
Finished Jul 28 07:37:12 PM PDT 24
Peak memory 222264 kb
Host smart-2ff2c96b-9a85-4718-8454-97c6442a14c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885698782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.885698782
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2769871142
Short name T578
Test name
Test status
Simulation time 28594610 ps
CPU time 2.24 seconds
Started Jul 28 07:37:08 PM PDT 24
Finished Jul 28 07:37:11 PM PDT 24
Peak memory 207056 kb
Host smart-bc57a070-db50-470f-8dcf-842cffb38633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769871142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2769871142
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2241820454
Short name T689
Test name
Test status
Simulation time 58994442 ps
CPU time 3.11 seconds
Started Jul 28 07:37:03 PM PDT 24
Finished Jul 28 07:37:06 PM PDT 24
Peak memory 206812 kb
Host smart-cf7b6654-8790-49a4-bcfd-0c15a37fb4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241820454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2241820454
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3233043812
Short name T845
Test name
Test status
Simulation time 101042825 ps
CPU time 2.02 seconds
Started Jul 28 07:37:04 PM PDT 24
Finished Jul 28 07:37:06 PM PDT 24
Peak memory 208432 kb
Host smart-3ad8186d-87f5-4b67-bdd6-c74630728e49
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233043812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3233043812
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2301106778
Short name T821
Test name
Test status
Simulation time 209687876 ps
CPU time 2.26 seconds
Started Jul 28 07:37:07 PM PDT 24
Finished Jul 28 07:37:09 PM PDT 24
Peak memory 208812 kb
Host smart-5e523810-017a-4325-b576-ada2569d0884
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301106778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2301106778
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.237778673
Short name T562
Test name
Test status
Simulation time 240416948 ps
CPU time 3.83 seconds
Started Jul 28 07:37:04 PM PDT 24
Finished Jul 28 07:37:08 PM PDT 24
Peak memory 208516 kb
Host smart-2f466c02-d60e-4db9-a6fe-3dc1e3d5c8b0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237778673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.237778673
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.606032242
Short name T879
Test name
Test status
Simulation time 37078920 ps
CPU time 1.86 seconds
Started Jul 28 07:37:10 PM PDT 24
Finished Jul 28 07:37:12 PM PDT 24
Peak memory 207712 kb
Host smart-4e188f84-267b-471b-aa33-afaf99f99735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606032242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.606032242
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.935478625
Short name T820
Test name
Test status
Simulation time 190266184 ps
CPU time 3.06 seconds
Started Jul 28 07:37:07 PM PDT 24
Finished Jul 28 07:37:10 PM PDT 24
Peak memory 208300 kb
Host smart-bc137600-aa2a-493c-b012-ea7adb3b3af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935478625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.935478625
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.251975036
Short name T294
Test name
Test status
Simulation time 4752262236 ps
CPU time 71.94 seconds
Started Jul 28 07:37:13 PM PDT 24
Finished Jul 28 07:38:25 PM PDT 24
Peak memory 214976 kb
Host smart-59c3e5f8-86df-4fb1-b3e6-7f8ef748a674
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251975036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.251975036
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1523130876
Short name T236
Test name
Test status
Simulation time 980618792 ps
CPU time 9.61 seconds
Started Jul 28 07:37:06 PM PDT 24
Finished Jul 28 07:37:16 PM PDT 24
Peak memory 217988 kb
Host smart-b0db45a6-2693-4a25-ab4a-9a540a886ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523130876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1523130876
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3386746469
Short name T828
Test name
Test status
Simulation time 97883795 ps
CPU time 3.33 seconds
Started Jul 28 07:37:10 PM PDT 24
Finished Jul 28 07:37:14 PM PDT 24
Peak memory 209868 kb
Host smart-7be7087f-193c-4dc4-9a31-c874d963acc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386746469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3386746469
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.224808085
Short name T563
Test name
Test status
Simulation time 12103458 ps
CPU time 0.71 seconds
Started Jul 28 07:37:11 PM PDT 24
Finished Jul 28 07:37:12 PM PDT 24
Peak memory 205888 kb
Host smart-35f47873-4aaa-414f-a5a5-f2e768608fb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224808085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.224808085
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3416131168
Short name T234
Test name
Test status
Simulation time 54127279 ps
CPU time 3.35 seconds
Started Jul 28 07:37:15 PM PDT 24
Finished Jul 28 07:37:19 PM PDT 24
Peak memory 214116 kb
Host smart-d33392fa-e1c5-4386-8f82-ec0ae65c306b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3416131168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3416131168
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3239826956
Short name T36
Test name
Test status
Simulation time 126881214 ps
CPU time 4.87 seconds
Started Jul 28 07:37:13 PM PDT 24
Finished Jul 28 07:37:18 PM PDT 24
Peak memory 220796 kb
Host smart-127eb656-42d6-4173-a14d-33a32e43ca68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239826956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3239826956
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2271315386
Short name T877
Test name
Test status
Simulation time 285977995 ps
CPU time 3.7 seconds
Started Jul 28 07:37:14 PM PDT 24
Finished Jul 28 07:37:18 PM PDT 24
Peak memory 207844 kb
Host smart-9b2a5a70-c49b-4796-ad22-4a0c01d1a7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271315386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2271315386
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.508661883
Short name T227
Test name
Test status
Simulation time 2931362388 ps
CPU time 7.68 seconds
Started Jul 28 07:37:12 PM PDT 24
Finished Jul 28 07:37:20 PM PDT 24
Peak memory 214148 kb
Host smart-8b083454-6577-4034-9dde-8464dec3bbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508661883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.508661883
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1742168172
Short name T283
Test name
Test status
Simulation time 190422706 ps
CPU time 2.33 seconds
Started Jul 28 07:37:12 PM PDT 24
Finished Jul 28 07:37:14 PM PDT 24
Peak memory 221224 kb
Host smart-007eb26b-3896-473d-b3d1-455ea38b32f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742168172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1742168172
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3626877885
Short name T568
Test name
Test status
Simulation time 162924842 ps
CPU time 3.27 seconds
Started Jul 28 07:37:17 PM PDT 24
Finished Jul 28 07:37:20 PM PDT 24
Peak memory 219988 kb
Host smart-67416635-838a-45c8-bac1-f1004566eef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626877885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3626877885
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.3413587431
Short name T565
Test name
Test status
Simulation time 73033294 ps
CPU time 4.23 seconds
Started Jul 28 07:37:10 PM PDT 24
Finished Jul 28 07:37:15 PM PDT 24
Peak memory 218816 kb
Host smart-84092141-fb2c-4113-b618-0134fd0268b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413587431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3413587431
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1218129038
Short name T830
Test name
Test status
Simulation time 51099703 ps
CPU time 2.52 seconds
Started Jul 28 07:37:12 PM PDT 24
Finished Jul 28 07:37:15 PM PDT 24
Peak memory 206728 kb
Host smart-a37a1719-8abc-41aa-a61e-369257d62251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218129038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1218129038
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2106377192
Short name T551
Test name
Test status
Simulation time 45964853 ps
CPU time 2.26 seconds
Started Jul 28 07:37:13 PM PDT 24
Finished Jul 28 07:37:16 PM PDT 24
Peak memory 206792 kb
Host smart-126c6783-b5f4-4f69-8953-7c2f250cbf36
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106377192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2106377192
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.4012785728
Short name T503
Test name
Test status
Simulation time 781954903 ps
CPU time 5.34 seconds
Started Jul 28 07:37:14 PM PDT 24
Finished Jul 28 07:37:19 PM PDT 24
Peak memory 208684 kb
Host smart-b44c97fd-80a4-48f7-a7bf-9cc020310797
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012785728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.4012785728
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3421781721
Short name T463
Test name
Test status
Simulation time 532623985 ps
CPU time 3.38 seconds
Started Jul 28 07:37:09 PM PDT 24
Finished Jul 28 07:37:12 PM PDT 24
Peak memory 206704 kb
Host smart-4a2ba8d2-b65f-4fa5-98bd-22a41cfa067b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421781721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3421781721
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2778283293
Short name T595
Test name
Test status
Simulation time 198552401 ps
CPU time 3.33 seconds
Started Jul 28 07:37:11 PM PDT 24
Finished Jul 28 07:37:14 PM PDT 24
Peak memory 218292 kb
Host smart-5186a8e0-bb7c-47de-a4cc-e2a92d78817a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778283293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2778283293
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.441174582
Short name T572
Test name
Test status
Simulation time 33048406 ps
CPU time 2.06 seconds
Started Jul 28 07:37:12 PM PDT 24
Finished Jul 28 07:37:15 PM PDT 24
Peak memory 206684 kb
Host smart-cf59728b-5af5-43d9-a412-c6cd6a58bb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441174582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.441174582
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.447243214
Short name T885
Test name
Test status
Simulation time 718450760 ps
CPU time 12.02 seconds
Started Jul 28 07:37:14 PM PDT 24
Finished Jul 28 07:37:26 PM PDT 24
Peak memory 219860 kb
Host smart-31595f6f-cf56-49ca-a56c-86091e8ef9b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447243214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.447243214
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.617832278
Short name T185
Test name
Test status
Simulation time 114083080 ps
CPU time 4.18 seconds
Started Jul 28 07:37:13 PM PDT 24
Finished Jul 28 07:37:17 PM PDT 24
Peak memory 214240 kb
Host smart-ad9b1a1a-190d-4281-9259-09cefe0dbd8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617832278 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.617832278
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1513733777
Short name T498
Test name
Test status
Simulation time 81566343 ps
CPU time 2.66 seconds
Started Jul 28 07:37:13 PM PDT 24
Finished Jul 28 07:37:16 PM PDT 24
Peak memory 209540 kb
Host smart-447a3d8e-d5ad-42c4-92a1-d5c8fa047235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513733777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1513733777
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3986216703
Short name T188
Test name
Test status
Simulation time 73707694 ps
CPU time 1.93 seconds
Started Jul 28 07:37:11 PM PDT 24
Finished Jul 28 07:37:13 PM PDT 24
Peak memory 209512 kb
Host smart-ec3f757b-e07c-4a84-b2b8-e8311d2d67ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986216703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3986216703
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2978071283
Short name T768
Test name
Test status
Simulation time 31700595 ps
CPU time 0.77 seconds
Started Jul 28 07:37:10 PM PDT 24
Finished Jul 28 07:37:11 PM PDT 24
Peak memory 205892 kb
Host smart-761908a6-58f1-4560-9062-2e2431703e43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978071283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2978071283
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1503059789
Short name T27
Test name
Test status
Simulation time 963827535 ps
CPU time 6 seconds
Started Jul 28 07:37:13 PM PDT 24
Finished Jul 28 07:37:19 PM PDT 24
Peak memory 209568 kb
Host smart-bae5f564-09c4-4989-b64d-82d5a5910fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503059789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1503059789
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2423747060
Short name T453
Test name
Test status
Simulation time 122521742 ps
CPU time 2.75 seconds
Started Jul 28 07:37:11 PM PDT 24
Finished Jul 28 07:37:14 PM PDT 24
Peak memory 207568 kb
Host smart-dd09c2d1-7912-4a19-bc1e-233fad4d0622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423747060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2423747060
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3802273159
Short name T534
Test name
Test status
Simulation time 194807255 ps
CPU time 4.56 seconds
Started Jul 28 07:37:10 PM PDT 24
Finished Jul 28 07:37:15 PM PDT 24
Peak memory 208712 kb
Host smart-9759d063-5b89-4e86-826a-afc1cc7ff158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802273159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3802273159
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2402497702
Short name T717
Test name
Test status
Simulation time 77332226 ps
CPU time 2.67 seconds
Started Jul 28 07:37:14 PM PDT 24
Finished Jul 28 07:37:17 PM PDT 24
Peak memory 214992 kb
Host smart-30012f1e-7a7d-4b94-b87a-7db0e4196834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402497702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2402497702
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.1426858297
Short name T817
Test name
Test status
Simulation time 1888862008 ps
CPU time 13.48 seconds
Started Jul 28 07:37:10 PM PDT 24
Finished Jul 28 07:37:24 PM PDT 24
Peak memory 218156 kb
Host smart-1cc33881-11d8-4a36-ad8a-d2102cb24f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426858297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1426858297
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2440596783
Short name T690
Test name
Test status
Simulation time 144185296 ps
CPU time 3.2 seconds
Started Jul 28 07:37:13 PM PDT 24
Finished Jul 28 07:37:16 PM PDT 24
Peak memory 208468 kb
Host smart-95bdf173-c02f-4bd5-a729-cebf16ab1aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440596783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2440596783
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.4007776942
Short name T542
Test name
Test status
Simulation time 60437968 ps
CPU time 3.11 seconds
Started Jul 28 07:37:14 PM PDT 24
Finished Jul 28 07:37:17 PM PDT 24
Peak memory 207112 kb
Host smart-24a027b1-6bb8-4c7b-a89d-9b5c1a881283
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007776942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.4007776942
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2739062671
Short name T287
Test name
Test status
Simulation time 161893108 ps
CPU time 2.43 seconds
Started Jul 28 07:37:12 PM PDT 24
Finished Jul 28 07:37:15 PM PDT 24
Peak memory 208500 kb
Host smart-9c10e254-bf85-440a-8c10-9ce7c1374ac1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739062671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2739062671
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3032536440
Short name T529
Test name
Test status
Simulation time 523208880 ps
CPU time 6.46 seconds
Started Jul 28 07:37:10 PM PDT 24
Finished Jul 28 07:37:16 PM PDT 24
Peak memory 207932 kb
Host smart-cd489530-0984-4693-aed2-10050752000f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032536440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3032536440
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1600463819
Short name T197
Test name
Test status
Simulation time 40237148 ps
CPU time 1.59 seconds
Started Jul 28 07:37:11 PM PDT 24
Finished Jul 28 07:37:13 PM PDT 24
Peak memory 207764 kb
Host smart-05b20a15-6e99-440c-8bc2-8d4e508e7858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600463819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1600463819
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2691317545
Short name T783
Test name
Test status
Simulation time 58624293 ps
CPU time 2.03 seconds
Started Jul 28 07:37:12 PM PDT 24
Finished Jul 28 07:37:14 PM PDT 24
Peak memory 206572 kb
Host smart-8ec24f3e-1724-4aca-898b-de55a02e87bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691317545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2691317545
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.4216375900
Short name T605
Test name
Test status
Simulation time 497124960 ps
CPU time 5.48 seconds
Started Jul 28 07:37:12 PM PDT 24
Finished Jul 28 07:37:18 PM PDT 24
Peak memory 206768 kb
Host smart-268039cb-44eb-4f71-978c-397067ef0f46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216375900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.4216375900
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2197690541
Short name T452
Test name
Test status
Simulation time 4112449323 ps
CPU time 9.54 seconds
Started Jul 28 07:37:11 PM PDT 24
Finished Jul 28 07:37:21 PM PDT 24
Peak memory 209276 kb
Host smart-141004dd-75cd-4a19-8baf-ad1c9682a592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197690541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2197690541
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1812622889
Short name T165
Test name
Test status
Simulation time 377266327 ps
CPU time 2.77 seconds
Started Jul 28 07:37:13 PM PDT 24
Finished Jul 28 07:37:16 PM PDT 24
Peak memory 209872 kb
Host smart-79ba6178-11cd-4f22-98cb-1b74f1a81083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812622889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1812622889
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3360934268
Short name T869
Test name
Test status
Simulation time 14423083 ps
CPU time 0.97 seconds
Started Jul 28 07:37:19 PM PDT 24
Finished Jul 28 07:37:20 PM PDT 24
Peak memory 205944 kb
Host smart-d7fc2f02-aee6-40e6-bfb4-11c42199c566
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360934268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3360934268
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.615012319
Short name T403
Test name
Test status
Simulation time 1720061233 ps
CPU time 82.53 seconds
Started Jul 28 07:37:21 PM PDT 24
Finished Jul 28 07:38:43 PM PDT 24
Peak memory 214680 kb
Host smart-7dff5c3a-c91f-4c10-a34d-2ff0e34981ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=615012319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.615012319
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3757381808
Short name T23
Test name
Test status
Simulation time 73986648 ps
CPU time 4.22 seconds
Started Jul 28 07:37:16 PM PDT 24
Finished Jul 28 07:37:20 PM PDT 24
Peak memory 209672 kb
Host smart-5a90b52f-36f2-482d-becf-9aec878c01e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757381808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3757381808
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3385802772
Short name T814
Test name
Test status
Simulation time 298903326 ps
CPU time 3.64 seconds
Started Jul 28 07:37:14 PM PDT 24
Finished Jul 28 07:37:18 PM PDT 24
Peak memory 207608 kb
Host smart-0e67d796-81b9-4c52-8d56-f53911981315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385802772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3385802772
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1652217170
Short name T353
Test name
Test status
Simulation time 124081091 ps
CPU time 2.46 seconds
Started Jul 28 07:37:18 PM PDT 24
Finished Jul 28 07:37:21 PM PDT 24
Peak memory 222360 kb
Host smart-80bba9ba-86f4-44a3-988e-7de6bc621e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652217170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1652217170
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2838376918
Short name T315
Test name
Test status
Simulation time 37051990 ps
CPU time 2.56 seconds
Started Jul 28 07:37:16 PM PDT 24
Finished Jul 28 07:37:19 PM PDT 24
Peak memory 211344 kb
Host smart-6429a53d-ce91-48ad-b44b-bee97749b1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838376918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2838376918
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1270661002
Short name T601
Test name
Test status
Simulation time 30413937 ps
CPU time 2.04 seconds
Started Jul 28 07:37:20 PM PDT 24
Finished Jul 28 07:37:22 PM PDT 24
Peak memory 215544 kb
Host smart-5bf261eb-c4e2-407a-bd0b-e7214b7e4de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270661002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1270661002
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1383013633
Short name T779
Test name
Test status
Simulation time 3188293136 ps
CPU time 32.62 seconds
Started Jul 28 07:37:21 PM PDT 24
Finished Jul 28 07:37:54 PM PDT 24
Peak memory 218312 kb
Host smart-6df83b6e-66fd-432c-a1b6-ea7f1da16c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383013633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1383013633
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3473736797
Short name T497
Test name
Test status
Simulation time 847424999 ps
CPU time 17.04 seconds
Started Jul 28 07:37:18 PM PDT 24
Finished Jul 28 07:37:35 PM PDT 24
Peak memory 207804 kb
Host smart-5ce5e58d-d6d0-4aa1-bfda-2c289df63e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473736797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3473736797
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.4237174416
Short name T513
Test name
Test status
Simulation time 144952350 ps
CPU time 6.41 seconds
Started Jul 28 07:37:14 PM PDT 24
Finished Jul 28 07:37:21 PM PDT 24
Peak memory 208760 kb
Host smart-53a48994-f71e-4851-964f-c85650eae94a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237174416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.4237174416
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.867489759
Short name T576
Test name
Test status
Simulation time 114330799 ps
CPU time 1.79 seconds
Started Jul 28 07:37:11 PM PDT 24
Finished Jul 28 07:37:13 PM PDT 24
Peak memory 206764 kb
Host smart-53a6bf00-5b13-41c8-8533-de3794385826
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867489759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.867489759
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.4073001022
Short name T2
Test name
Test status
Simulation time 281035015 ps
CPU time 5.88 seconds
Started Jul 28 07:37:12 PM PDT 24
Finished Jul 28 07:37:18 PM PDT 24
Peak memory 208368 kb
Host smart-a3e9b534-c9b8-4c2e-9495-b685f2291c02
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073001022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.4073001022
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.2908715854
Short name T447
Test name
Test status
Simulation time 327348215 ps
CPU time 2.87 seconds
Started Jul 28 07:37:20 PM PDT 24
Finished Jul 28 07:37:23 PM PDT 24
Peak memory 215444 kb
Host smart-5a4f5818-d2e7-44d8-8d10-83092274e2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908715854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2908715854
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2563157291
Short name T467
Test name
Test status
Simulation time 132375020 ps
CPU time 3.92 seconds
Started Jul 28 07:37:13 PM PDT 24
Finished Jul 28 07:37:17 PM PDT 24
Peak memory 208352 kb
Host smart-e1249501-7b90-4876-ad6b-9b73e477743b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563157291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2563157291
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3449914810
Short name T186
Test name
Test status
Simulation time 1196066566 ps
CPU time 8.34 seconds
Started Jul 28 07:37:17 PM PDT 24
Finished Jul 28 07:37:25 PM PDT 24
Peak memory 222416 kb
Host smart-94eb8e0e-9325-4ef8-aa40-9dc4f3ba29b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449914810 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3449914810
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3543601229
Short name T392
Test name
Test status
Simulation time 136612915 ps
CPU time 3.45 seconds
Started Jul 28 07:37:18 PM PDT 24
Finished Jul 28 07:37:22 PM PDT 24
Peak memory 207812 kb
Host smart-a440d62e-48a2-456f-8ce5-0127af1d5af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543601229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3543601229
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2403895310
Short name T592
Test name
Test status
Simulation time 433062477 ps
CPU time 9.95 seconds
Started Jul 28 07:37:17 PM PDT 24
Finished Jul 28 07:37:27 PM PDT 24
Peak memory 210932 kb
Host smart-65adf06e-ee16-4b53-acd0-b3e861b8a084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403895310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2403895310
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.1408184388
Short name T454
Test name
Test status
Simulation time 201029816 ps
CPU time 0.81 seconds
Started Jul 28 07:37:16 PM PDT 24
Finished Jul 28 07:37:17 PM PDT 24
Peak memory 205860 kb
Host smart-05aca2d0-e606-4661-89a8-efe52b5212f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408184388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1408184388
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1115276178
Short name T753
Test name
Test status
Simulation time 69385580 ps
CPU time 3.81 seconds
Started Jul 28 07:37:15 PM PDT 24
Finished Jul 28 07:37:19 PM PDT 24
Peak memory 221380 kb
Host smart-c8965877-e3f9-4bb3-8c9f-aafc8656aca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115276178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1115276178
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2235228256
Short name T754
Test name
Test status
Simulation time 37277898 ps
CPU time 1.97 seconds
Started Jul 28 07:37:24 PM PDT 24
Finished Jul 28 07:37:26 PM PDT 24
Peak memory 208936 kb
Host smart-fa39a48d-563a-40e4-90cf-06d15d02bf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235228256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2235228256
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3579379545
Short name T86
Test name
Test status
Simulation time 389937833 ps
CPU time 3.26 seconds
Started Jul 28 07:37:16 PM PDT 24
Finished Jul 28 07:37:19 PM PDT 24
Peak memory 214224 kb
Host smart-30d69285-44d5-4af7-87ad-75f2b5e097fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579379545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3579379545
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1173884008
Short name T295
Test name
Test status
Simulation time 405910443 ps
CPU time 6.03 seconds
Started Jul 28 07:37:24 PM PDT 24
Finished Jul 28 07:37:30 PM PDT 24
Peak memory 214132 kb
Host smart-6f10d0ec-c207-43b5-8405-de9b18958e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173884008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1173884008
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.284718867
Short name T599
Test name
Test status
Simulation time 50580040 ps
CPU time 1.93 seconds
Started Jul 28 07:37:16 PM PDT 24
Finished Jul 28 07:37:18 PM PDT 24
Peak memory 214144 kb
Host smart-8711fb42-d90e-4c51-ab28-7dc6d2cfd16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284718867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.284718867
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1710946042
Short name T444
Test name
Test status
Simulation time 327878918 ps
CPU time 4.26 seconds
Started Jul 28 07:37:15 PM PDT 24
Finished Jul 28 07:37:20 PM PDT 24
Peak memory 207332 kb
Host smart-a7116967-0ef4-44b4-8d11-988d0eab8c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710946042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1710946042
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3210812258
Short name T471
Test name
Test status
Simulation time 181688605 ps
CPU time 2.7 seconds
Started Jul 28 07:37:16 PM PDT 24
Finished Jul 28 07:37:18 PM PDT 24
Peak memory 206832 kb
Host smart-5f31f41d-fe76-4cd3-88ba-429eb2573d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210812258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3210812258
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2818119899
Short name T902
Test name
Test status
Simulation time 180416135 ps
CPU time 2.55 seconds
Started Jul 28 07:37:19 PM PDT 24
Finished Jul 28 07:37:21 PM PDT 24
Peak memory 206864 kb
Host smart-e5cb6dcd-6ecf-4cce-ad71-ee5ecff3608d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818119899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2818119899
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1575615178
Short name T745
Test name
Test status
Simulation time 10404602051 ps
CPU time 62.22 seconds
Started Jul 28 07:37:17 PM PDT 24
Finished Jul 28 07:38:20 PM PDT 24
Peak memory 207772 kb
Host smart-e4987bf0-88f7-4921-b861-3be729648516
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575615178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1575615178
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3116052253
Short name T204
Test name
Test status
Simulation time 157252432 ps
CPU time 1.88 seconds
Started Jul 28 07:37:22 PM PDT 24
Finished Jul 28 07:37:24 PM PDT 24
Peak memory 206836 kb
Host smart-1499c45b-4cc4-429c-b66c-0b2ba1dfe880
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116052253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3116052253
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3613190351
Short name T255
Test name
Test status
Simulation time 27635069 ps
CPU time 2.02 seconds
Started Jul 28 07:37:18 PM PDT 24
Finished Jul 28 07:37:20 PM PDT 24
Peak memory 207428 kb
Host smart-da2f3a84-1e3b-4859-b86c-d57bc6decd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613190351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3613190351
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2888742195
Short name T450
Test name
Test status
Simulation time 84995674 ps
CPU time 3.47 seconds
Started Jul 28 07:37:24 PM PDT 24
Finished Jul 28 07:37:28 PM PDT 24
Peak memory 207940 kb
Host smart-d12aafbb-48c5-4369-8600-35cef69f1bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888742195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2888742195
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.1407463627
Short name T129
Test name
Test status
Simulation time 262733700 ps
CPU time 7.1 seconds
Started Jul 28 07:37:17 PM PDT 24
Finished Jul 28 07:37:24 PM PDT 24
Peak memory 219436 kb
Host smart-10b72fe6-d953-4752-9599-0afa15d777ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407463627 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.1407463627
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2206539073
Short name T731
Test name
Test status
Simulation time 106533890 ps
CPU time 4.47 seconds
Started Jul 28 07:37:21 PM PDT 24
Finished Jul 28 07:37:25 PM PDT 24
Peak memory 210184 kb
Host smart-9ab122c2-0bed-4c22-8f3f-9888b4fcf349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206539073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2206539073
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1886226480
Short name T379
Test name
Test status
Simulation time 42773084 ps
CPU time 2.14 seconds
Started Jul 28 07:37:21 PM PDT 24
Finished Jul 28 07:37:23 PM PDT 24
Peak memory 209960 kb
Host smart-20409982-4b0c-4044-87fc-c1d924c00669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886226480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1886226480
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.4002645988
Short name T861
Test name
Test status
Simulation time 59117742 ps
CPU time 0.78 seconds
Started Jul 28 07:37:23 PM PDT 24
Finished Jul 28 07:37:24 PM PDT 24
Peak memory 205904 kb
Host smart-286430be-2c63-427f-92d1-cd0ba21dfc6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002645988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.4002645988
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3316602959
Short name T346
Test name
Test status
Simulation time 188871623 ps
CPU time 2.75 seconds
Started Jul 28 07:37:19 PM PDT 24
Finished Jul 28 07:37:22 PM PDT 24
Peak memory 214144 kb
Host smart-f816160f-d424-490f-99cc-1097385e6600
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3316602959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3316602959
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3770049173
Short name T662
Test name
Test status
Simulation time 225531329 ps
CPU time 5.37 seconds
Started Jul 28 07:37:24 PM PDT 24
Finished Jul 28 07:37:30 PM PDT 24
Peak memory 214472 kb
Host smart-9ff917a0-a10f-49bf-8de9-abcf1a436c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770049173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3770049173
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.3588823990
Short name T755
Test name
Test status
Simulation time 1437017010 ps
CPU time 17.91 seconds
Started Jul 28 07:37:19 PM PDT 24
Finished Jul 28 07:37:36 PM PDT 24
Peak memory 218008 kb
Host smart-7c3d2f60-95c3-46be-abc3-259bc559e0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588823990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3588823990
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.740064775
Short name T312
Test name
Test status
Simulation time 101625928 ps
CPU time 2.13 seconds
Started Jul 28 07:37:30 PM PDT 24
Finished Jul 28 07:37:32 PM PDT 24
Peak memory 214096 kb
Host smart-15ae202b-0f8e-490c-b80a-6af27c28ec1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740064775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.740064775
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1163677549
Short name T49
Test name
Test status
Simulation time 267435591 ps
CPU time 4.38 seconds
Started Jul 28 07:37:22 PM PDT 24
Finished Jul 28 07:37:27 PM PDT 24
Peak memory 214080 kb
Host smart-410b3b46-87c6-4866-a5bb-3cbb3739c223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163677549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1163677549
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3165512199
Short name T249
Test name
Test status
Simulation time 83568575 ps
CPU time 2.84 seconds
Started Jul 28 07:37:23 PM PDT 24
Finished Jul 28 07:37:25 PM PDT 24
Peak memory 222360 kb
Host smart-1f5302bf-4be7-4770-b330-9b65037dc3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165512199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3165512199
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1715152824
Short name T41
Test name
Test status
Simulation time 683228841 ps
CPU time 7.49 seconds
Started Jul 28 07:37:20 PM PDT 24
Finished Jul 28 07:37:28 PM PDT 24
Peak memory 214168 kb
Host smart-320c41d4-e7d3-446f-9256-ca422a773433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715152824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1715152824
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2396569803
Short name T772
Test name
Test status
Simulation time 145976070 ps
CPU time 2.85 seconds
Started Jul 28 07:37:20 PM PDT 24
Finished Jul 28 07:37:23 PM PDT 24
Peak memory 206836 kb
Host smart-a1528007-1403-49bb-a0bb-2ce890acfaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396569803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2396569803
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.648293556
Short name T800
Test name
Test status
Simulation time 826507398 ps
CPU time 6.09 seconds
Started Jul 28 07:37:20 PM PDT 24
Finished Jul 28 07:37:26 PM PDT 24
Peak memory 207996 kb
Host smart-c6367d27-5970-4886-93a7-1e40e634289f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648293556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.648293556
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1611365947
Short name T248
Test name
Test status
Simulation time 230005553 ps
CPU time 3.18 seconds
Started Jul 28 07:37:21 PM PDT 24
Finished Jul 28 07:37:24 PM PDT 24
Peak memory 208556 kb
Host smart-579b35ad-438f-4e0c-9531-590ff86b2375
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611365947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1611365947
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.1396435862
Short name T235
Test name
Test status
Simulation time 183959358 ps
CPU time 5.36 seconds
Started Jul 28 07:37:18 PM PDT 24
Finished Jul 28 07:37:24 PM PDT 24
Peak memory 206804 kb
Host smart-b3d5c0b3-9aeb-41c0-9c2f-1093f6c6d260
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396435862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1396435862
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3579321373
Short name T611
Test name
Test status
Simulation time 193686842 ps
CPU time 2.48 seconds
Started Jul 28 07:37:21 PM PDT 24
Finished Jul 28 07:37:24 PM PDT 24
Peak memory 220192 kb
Host smart-80f9d716-431e-44bc-a1e5-828220e80c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579321373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3579321373
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.4157325779
Short name T525
Test name
Test status
Simulation time 205300539 ps
CPU time 2.91 seconds
Started Jul 28 07:37:16 PM PDT 24
Finished Jul 28 07:37:19 PM PDT 24
Peak memory 208664 kb
Host smart-ec2be5c3-db3c-4cc2-b084-718dfa13b829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157325779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.4157325779
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.4143356704
Short name T789
Test name
Test status
Simulation time 1823847328 ps
CPU time 22.64 seconds
Started Jul 28 07:37:21 PM PDT 24
Finished Jul 28 07:37:44 PM PDT 24
Peak memory 214976 kb
Host smart-e305d337-9046-4f1c-9cd3-74cf12306c79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143356704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.4143356704
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.3148039275
Short name T207
Test name
Test status
Simulation time 1330628615 ps
CPU time 19.93 seconds
Started Jul 28 07:37:23 PM PDT 24
Finished Jul 28 07:37:43 PM PDT 24
Peak memory 222280 kb
Host smart-f5bc342e-4aa4-4c88-ba95-8c2bad3ffab6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148039275 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.3148039275
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2863704666
Short name T516
Test name
Test status
Simulation time 987492523 ps
CPU time 26.08 seconds
Started Jul 28 07:37:23 PM PDT 24
Finished Jul 28 07:37:50 PM PDT 24
Peak memory 210196 kb
Host smart-5e6c40a9-384e-4d86-9404-52347ae49c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863704666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2863704666
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3827103058
Short name T484
Test name
Test status
Simulation time 150245443 ps
CPU time 2.64 seconds
Started Jul 28 07:37:23 PM PDT 24
Finished Jul 28 07:37:26 PM PDT 24
Peak memory 209952 kb
Host smart-dca5a218-0a7c-4e7b-b739-7663c228d385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827103058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3827103058
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.3068305494
Short name T476
Test name
Test status
Simulation time 19707424 ps
CPU time 0.85 seconds
Started Jul 28 07:37:23 PM PDT 24
Finished Jul 28 07:37:24 PM PDT 24
Peak memory 205864 kb
Host smart-f4041b3e-1c94-4bcd-b718-4df602f872d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068305494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3068305494
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2204449813
Short name T143
Test name
Test status
Simulation time 201930233 ps
CPU time 2.87 seconds
Started Jul 28 07:37:25 PM PDT 24
Finished Jul 28 07:37:28 PM PDT 24
Peak memory 214724 kb
Host smart-cbc90122-01e8-40c1-b6e3-c5c57e56d3ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2204449813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2204449813
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2769229935
Short name T640
Test name
Test status
Simulation time 1880315644 ps
CPU time 18.79 seconds
Started Jul 28 07:37:30 PM PDT 24
Finished Jul 28 07:37:49 PM PDT 24
Peak memory 214116 kb
Host smart-1e4d42eb-97a7-48b2-b444-ef451f0bc725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769229935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2769229935
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1204900895
Short name T374
Test name
Test status
Simulation time 68259745 ps
CPU time 2.84 seconds
Started Jul 28 07:37:24 PM PDT 24
Finished Jul 28 07:37:27 PM PDT 24
Peak memory 222156 kb
Host smart-ab1f6bf2-9e26-40b3-87fa-0cc29282d133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204900895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1204900895
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.941965131
Short name T645
Test name
Test status
Simulation time 46007532 ps
CPU time 3.05 seconds
Started Jul 28 07:37:27 PM PDT 24
Finished Jul 28 07:37:30 PM PDT 24
Peak memory 209180 kb
Host smart-f43f7553-80bc-4b87-ba5a-b2ad788014d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941965131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.941965131
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3286183711
Short name T621
Test name
Test status
Simulation time 1040171196 ps
CPU time 11.42 seconds
Started Jul 28 07:37:23 PM PDT 24
Finished Jul 28 07:37:34 PM PDT 24
Peak memory 207944 kb
Host smart-444d1431-4876-4bf3-8d09-e6d90d8101e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286183711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3286183711
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.4088031682
Short name T469
Test name
Test status
Simulation time 123795502 ps
CPU time 3.39 seconds
Started Jul 28 07:37:30 PM PDT 24
Finished Jul 28 07:37:34 PM PDT 24
Peak memory 208408 kb
Host smart-49f5701c-4844-4a01-a92f-7c7ec159c66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088031682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.4088031682
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.3653917866
Short name T101
Test name
Test status
Simulation time 48133081 ps
CPU time 2.07 seconds
Started Jul 28 07:37:23 PM PDT 24
Finished Jul 28 07:37:25 PM PDT 24
Peak memory 208460 kb
Host smart-8a9483af-eb74-4c41-82bf-32ce6e33563f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653917866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3653917866
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.4064310447
Short name T893
Test name
Test status
Simulation time 67928358 ps
CPU time 2.86 seconds
Started Jul 28 07:37:24 PM PDT 24
Finished Jul 28 07:37:27 PM PDT 24
Peak memory 206852 kb
Host smart-7cf08e75-76a4-49a5-b30d-6272a00fcff6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064310447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.4064310447
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.255154968
Short name T445
Test name
Test status
Simulation time 312471665 ps
CPU time 3.09 seconds
Started Jul 28 07:37:22 PM PDT 24
Finished Jul 28 07:37:26 PM PDT 24
Peak memory 206916 kb
Host smart-dc547e54-06cb-4e71-85af-f25536ab19be
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255154968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.255154968
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3928336340
Short name T292
Test name
Test status
Simulation time 135302054 ps
CPU time 2.14 seconds
Started Jul 28 07:37:22 PM PDT 24
Finished Jul 28 07:37:24 PM PDT 24
Peak memory 215348 kb
Host smart-0f960f6a-d04b-4e7a-bd62-42f6bb5e07c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928336340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3928336340
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3298483027
Short name T770
Test name
Test status
Simulation time 33528972 ps
CPU time 2.03 seconds
Started Jul 28 07:37:23 PM PDT 24
Finished Jul 28 07:37:25 PM PDT 24
Peak memory 206644 kb
Host smart-2bbe294f-4d43-4cec-8ce0-097883821ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298483027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3298483027
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.4205511249
Short name T550
Test name
Test status
Simulation time 404461862 ps
CPU time 4.5 seconds
Started Jul 28 07:37:23 PM PDT 24
Finished Jul 28 07:37:28 PM PDT 24
Peak memory 209796 kb
Host smart-4d9c2aec-b93c-45c1-88f6-51260ad3247c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205511249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.4205511249
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1613942792
Short name T182
Test name
Test status
Simulation time 2365811341 ps
CPU time 15.08 seconds
Started Jul 28 07:37:26 PM PDT 24
Finished Jul 28 07:37:41 PM PDT 24
Peak memory 222396 kb
Host smart-b8413f86-e506-4a19-a45e-abd601bfef17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613942792 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1613942792
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3030270489
Short name T306
Test name
Test status
Simulation time 881977631 ps
CPU time 4.12 seconds
Started Jul 28 07:37:19 PM PDT 24
Finished Jul 28 07:37:24 PM PDT 24
Peak memory 209476 kb
Host smart-836024f8-51dd-4344-b945-2feebea7f475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030270489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3030270489
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1418176051
Short name T639
Test name
Test status
Simulation time 3150494029 ps
CPU time 4.55 seconds
Started Jul 28 07:37:25 PM PDT 24
Finished Jul 28 07:37:30 PM PDT 24
Peak memory 211300 kb
Host smart-f3fcf48c-7014-4f45-9865-26cc1a19ba8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418176051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1418176051
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1622072361
Short name T858
Test name
Test status
Simulation time 40280059 ps
CPU time 0.91 seconds
Started Jul 28 07:37:24 PM PDT 24
Finished Jul 28 07:37:25 PM PDT 24
Peak memory 205876 kb
Host smart-554031dc-77cb-4fa9-b885-1481767a4b39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622072361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1622072361
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2233438506
Short name T324
Test name
Test status
Simulation time 175846502 ps
CPU time 9.34 seconds
Started Jul 28 07:37:30 PM PDT 24
Finished Jul 28 07:37:39 PM PDT 24
Peak memory 214108 kb
Host smart-b6c34a7a-1cf1-4b36-ace0-45c92be54ccc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2233438506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2233438506
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.2769972902
Short name T30
Test name
Test status
Simulation time 184784522 ps
CPU time 1.81 seconds
Started Jul 28 07:37:30 PM PDT 24
Finished Jul 28 07:37:32 PM PDT 24
Peak memory 214056 kb
Host smart-076951b5-bee2-4915-bc69-3a318c656791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769972902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.2769972902
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.613638219
Short name T72
Test name
Test status
Simulation time 111457505 ps
CPU time 2.22 seconds
Started Jul 28 07:37:23 PM PDT 24
Finished Jul 28 07:37:26 PM PDT 24
Peak memory 214192 kb
Host smart-5a51b3bd-542a-4682-bd59-fb350a2aeb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613638219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.613638219
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2352200534
Short name T239
Test name
Test status
Simulation time 97191136 ps
CPU time 2.13 seconds
Started Jul 28 07:37:23 PM PDT 24
Finished Jul 28 07:37:25 PM PDT 24
Peak memory 214260 kb
Host smart-a9267023-0985-4e0a-98b8-5f573019877f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352200534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2352200534
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.371385970
Short name T285
Test name
Test status
Simulation time 125232841 ps
CPU time 3.38 seconds
Started Jul 28 07:37:24 PM PDT 24
Finished Jul 28 07:37:27 PM PDT 24
Peak memory 214092 kb
Host smart-692ff595-798a-42c8-91bb-d43602c59e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371385970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.371385970
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2349287737
Short name T586
Test name
Test status
Simulation time 172795932 ps
CPU time 2.96 seconds
Started Jul 28 07:37:27 PM PDT 24
Finished Jul 28 07:37:30 PM PDT 24
Peak memory 214256 kb
Host smart-2bed9bcd-3dcb-45dd-8b02-a1b07db4d498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349287737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2349287737
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3745269749
Short name T290
Test name
Test status
Simulation time 179169088 ps
CPU time 5.19 seconds
Started Jul 28 07:37:25 PM PDT 24
Finished Jul 28 07:37:30 PM PDT 24
Peak memory 207704 kb
Host smart-fbdc70d2-4a07-456d-92b0-191cd1ab40dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745269749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3745269749
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.331661442
Short name T559
Test name
Test status
Simulation time 154601787 ps
CPU time 3.73 seconds
Started Jul 28 07:37:25 PM PDT 24
Finished Jul 28 07:37:29 PM PDT 24
Peak memory 208608 kb
Host smart-ea0a06e2-706b-4206-9ee2-cf34e4e8c457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331661442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.331661442
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3240389891
Short name T352
Test name
Test status
Simulation time 32345052 ps
CPU time 2.34 seconds
Started Jul 28 07:37:25 PM PDT 24
Finished Jul 28 07:37:27 PM PDT 24
Peak memory 206864 kb
Host smart-90e8d588-583b-49f5-8823-2243b0a9dce3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240389891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3240389891
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1933419323
Short name T523
Test name
Test status
Simulation time 72613967 ps
CPU time 3.75 seconds
Started Jul 28 07:37:30 PM PDT 24
Finished Jul 28 07:37:35 PM PDT 24
Peak memory 207904 kb
Host smart-a83de2d5-7b39-479b-9840-1fdc806a9f72
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933419323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1933419323
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.4252308340
Short name T368
Test name
Test status
Simulation time 2463132471 ps
CPU time 5.71 seconds
Started Jul 28 07:37:25 PM PDT 24
Finished Jul 28 07:37:31 PM PDT 24
Peak memory 208476 kb
Host smart-9a055e7d-b655-4cc6-8d3f-bc670f16ed93
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252308340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.4252308340
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2224542492
Short name T752
Test name
Test status
Simulation time 691887634 ps
CPU time 3.43 seconds
Started Jul 28 07:37:20 PM PDT 24
Finished Jul 28 07:37:24 PM PDT 24
Peak memory 214172 kb
Host smart-9cb0e036-4f47-4c47-bd2c-3c1c8b13f7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224542492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2224542492
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2700788800
Short name T425
Test name
Test status
Simulation time 22944112 ps
CPU time 1.76 seconds
Started Jul 28 07:37:24 PM PDT 24
Finished Jul 28 07:37:26 PM PDT 24
Peak memory 206836 kb
Host smart-85fb7021-a6ad-4553-8cb5-f294640c6153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700788800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2700788800
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.1358032622
Short name T115
Test name
Test status
Simulation time 530900514 ps
CPU time 5.12 seconds
Started Jul 28 07:37:28 PM PDT 24
Finished Jul 28 07:37:33 PM PDT 24
Peak memory 222256 kb
Host smart-ed82bbf0-8f3c-4144-b5b7-b143adab9d9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358032622 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.1358032622
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2141264597
Short name T834
Test name
Test status
Simulation time 613772757 ps
CPU time 5.29 seconds
Started Jul 28 07:37:22 PM PDT 24
Finished Jul 28 07:37:27 PM PDT 24
Peak memory 210064 kb
Host smart-cea384bf-454f-4630-8b2a-b698f39cc82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141264597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2141264597
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.273836453
Short name T112
Test name
Test status
Simulation time 91496425 ps
CPU time 2.12 seconds
Started Jul 28 07:37:27 PM PDT 24
Finished Jul 28 07:37:29 PM PDT 24
Peak memory 209752 kb
Host smart-395e29de-a748-4920-9602-60efb5c9e169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273836453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.273836453
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1322435545
Short name T771
Test name
Test status
Simulation time 18062050 ps
CPU time 0.79 seconds
Started Jul 28 07:35:43 PM PDT 24
Finished Jul 28 07:35:44 PM PDT 24
Peak memory 205796 kb
Host smart-bb0be4e9-652f-4300-ba6e-89f189572dd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322435545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1322435545
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.50407198
Short name T120
Test name
Test status
Simulation time 115157369 ps
CPU time 4.14 seconds
Started Jul 28 07:35:42 PM PDT 24
Finished Jul 28 07:35:46 PM PDT 24
Peak memory 215428 kb
Host smart-d0944f22-65e2-4e62-bfc1-e5524360227a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=50407198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.50407198
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1045738721
Short name T1
Test name
Test status
Simulation time 255844541 ps
CPU time 3.79 seconds
Started Jul 28 07:35:44 PM PDT 24
Finished Jul 28 07:35:48 PM PDT 24
Peak memory 216652 kb
Host smart-2c544ed8-8cbe-4a16-a8f0-2894cd18fea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045738721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1045738721
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1368105256
Short name T603
Test name
Test status
Simulation time 141032472 ps
CPU time 3.77 seconds
Started Jul 28 07:35:43 PM PDT 24
Finished Jul 28 07:35:47 PM PDT 24
Peak memory 214256 kb
Host smart-2478dc64-1c4a-495c-b050-a7a1e689fbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368105256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1368105256
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3463986813
Short name T224
Test name
Test status
Simulation time 389655225 ps
CPU time 3.72 seconds
Started Jul 28 07:35:39 PM PDT 24
Finished Jul 28 07:35:43 PM PDT 24
Peak memory 214256 kb
Host smart-bd775e37-9311-4a28-9764-0705b085cbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463986813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3463986813
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2868193373
Short name T532
Test name
Test status
Simulation time 49066749 ps
CPU time 2.27 seconds
Started Jul 28 07:35:41 PM PDT 24
Finished Jul 28 07:35:44 PM PDT 24
Peak memory 220428 kb
Host smart-a0f10ddd-d5f0-4166-9d90-79d38ffcab4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868193373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2868193373
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3376614983
Short name T716
Test name
Test status
Simulation time 235015040 ps
CPU time 7.06 seconds
Started Jul 28 07:35:43 PM PDT 24
Finished Jul 28 07:35:50 PM PDT 24
Peak memory 219996 kb
Host smart-b3fc7ede-786c-4586-bb73-bc9e0fa280a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376614983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3376614983
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.1480420716
Short name T734
Test name
Test status
Simulation time 28504606 ps
CPU time 2.02 seconds
Started Jul 28 07:35:46 PM PDT 24
Finished Jul 28 07:35:49 PM PDT 24
Peak memory 207740 kb
Host smart-c7b9a3d0-677d-4973-896e-bbdf8a441313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480420716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1480420716
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1272692676
Short name T40
Test name
Test status
Simulation time 4452407116 ps
CPU time 11.7 seconds
Started Jul 28 07:35:44 PM PDT 24
Finished Jul 28 07:35:56 PM PDT 24
Peak memory 239716 kb
Host smart-d81635d0-7d47-40ad-a09e-243e38da38a7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272692676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1272692676
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1692529820
Short name T517
Test name
Test status
Simulation time 362494725 ps
CPU time 6.64 seconds
Started Jul 28 07:35:38 PM PDT 24
Finished Jul 28 07:35:45 PM PDT 24
Peak memory 207720 kb
Host smart-7a8f9ffb-c631-403d-a37f-348588a2a777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692529820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1692529820
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3751176448
Short name T891
Test name
Test status
Simulation time 53815891 ps
CPU time 2.57 seconds
Started Jul 28 07:35:46 PM PDT 24
Finished Jul 28 07:35:49 PM PDT 24
Peak memory 206640 kb
Host smart-2ceba9f5-e8ef-49c8-8517-c87955af30d9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751176448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3751176448
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.601134370
Short name T480
Test name
Test status
Simulation time 95413104 ps
CPU time 2.62 seconds
Started Jul 28 07:35:39 PM PDT 24
Finished Jul 28 07:35:42 PM PDT 24
Peak memory 207996 kb
Host smart-30d1a835-9e20-4550-93c6-e9f6e1916122
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601134370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.601134370
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1007743540
Short name T790
Test name
Test status
Simulation time 208358923 ps
CPU time 6.39 seconds
Started Jul 28 07:35:43 PM PDT 24
Finished Jul 28 07:35:49 PM PDT 24
Peak memory 208356 kb
Host smart-1cf8df1d-b4b4-4194-b797-12a9126fe10d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007743540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1007743540
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1760438534
Short name T272
Test name
Test status
Simulation time 654842632 ps
CPU time 19.38 seconds
Started Jul 28 07:35:49 PM PDT 24
Finished Jul 28 07:36:08 PM PDT 24
Peak memory 220116 kb
Host smart-8e68c0a8-0fde-4888-a0f9-94b5486165b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760438534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1760438534
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.810148442
Short name T798
Test name
Test status
Simulation time 140270707 ps
CPU time 3.35 seconds
Started Jul 28 07:35:39 PM PDT 24
Finished Jul 28 07:35:43 PM PDT 24
Peak memory 208680 kb
Host smart-101b43c8-66a0-4358-b353-40aeb3191cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810148442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.810148442
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.548808932
Short name T723
Test name
Test status
Simulation time 1998932170 ps
CPU time 35.88 seconds
Started Jul 28 07:35:43 PM PDT 24
Finished Jul 28 07:36:19 PM PDT 24
Peak memory 214184 kb
Host smart-4a3f13ed-73e2-4bb8-838b-54bf5298695f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548808932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.548808932
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1010570341
Short name T839
Test name
Test status
Simulation time 355730741 ps
CPU time 5.48 seconds
Started Jul 28 07:35:43 PM PDT 24
Finished Jul 28 07:35:49 PM PDT 24
Peak memory 209640 kb
Host smart-55bee15b-9c8c-4d57-bf28-d8a2018dc92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010570341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1010570341
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1839288692
Short name T381
Test name
Test status
Simulation time 1061601756 ps
CPU time 10.2 seconds
Started Jul 28 07:35:48 PM PDT 24
Finished Jul 28 07:35:58 PM PDT 24
Peak memory 210696 kb
Host smart-c0ed3323-41bd-46cd-9993-e0606359d2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839288692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1839288692
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1494506923
Short name T429
Test name
Test status
Simulation time 8899948 ps
CPU time 0.69 seconds
Started Jul 28 07:37:27 PM PDT 24
Finished Jul 28 07:37:28 PM PDT 24
Peak memory 205792 kb
Host smart-2decf6b7-9ea2-46d5-9210-212085472862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494506923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1494506923
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2982000696
Short name T289
Test name
Test status
Simulation time 48700161 ps
CPU time 2.58 seconds
Started Jul 28 07:37:23 PM PDT 24
Finished Jul 28 07:37:26 PM PDT 24
Peak memory 214824 kb
Host smart-41d31024-339e-4f65-925f-10ee6b6cab0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2982000696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2982000696
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2768472230
Short name T548
Test name
Test status
Simulation time 187042234 ps
CPU time 2.1 seconds
Started Jul 28 07:37:28 PM PDT 24
Finished Jul 28 07:37:31 PM PDT 24
Peak memory 209416 kb
Host smart-5a073565-3779-419f-ada5-06353169d309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768472230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2768472230
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.2821941730
Short name T389
Test name
Test status
Simulation time 71262323 ps
CPU time 1.63 seconds
Started Jul 28 07:37:29 PM PDT 24
Finished Jul 28 07:37:31 PM PDT 24
Peak memory 207408 kb
Host smart-39cbb535-64a5-43b4-ae40-6796f9603e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821941730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2821941730
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3570485162
Short name T226
Test name
Test status
Simulation time 159872303 ps
CPU time 6.04 seconds
Started Jul 28 07:37:27 PM PDT 24
Finished Jul 28 07:37:34 PM PDT 24
Peak memory 220780 kb
Host smart-fb5f5985-eb8e-425d-8513-3b50c7da6aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570485162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3570485162
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3971038289
Short name T241
Test name
Test status
Simulation time 42254865 ps
CPU time 1.95 seconds
Started Jul 28 07:37:30 PM PDT 24
Finished Jul 28 07:37:32 PM PDT 24
Peak memory 220420 kb
Host smart-ab115a65-9531-41c1-b3b4-e5118aa8ea9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971038289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3971038289
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2080836225
Short name T111
Test name
Test status
Simulation time 265250646 ps
CPU time 3.75 seconds
Started Jul 28 07:37:27 PM PDT 24
Finished Jul 28 07:37:31 PM PDT 24
Peak memory 219824 kb
Host smart-f0e05812-c5b3-4e8f-8a2b-8251f19615dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080836225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2080836225
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.4148096821
Short name T878
Test name
Test status
Simulation time 218949739 ps
CPU time 3.38 seconds
Started Jul 28 07:37:23 PM PDT 24
Finished Jul 28 07:37:27 PM PDT 24
Peak memory 207072 kb
Host smart-03aa7fde-5746-4678-b85d-cb7b738e7d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148096821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.4148096821
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1608999490
Short name T680
Test name
Test status
Simulation time 3097731067 ps
CPU time 22.3 seconds
Started Jul 28 07:37:23 PM PDT 24
Finished Jul 28 07:37:46 PM PDT 24
Peak memory 208136 kb
Host smart-def7c952-1e47-4e1c-be98-1307c5cbc2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608999490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1608999490
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1531137053
Short name T819
Test name
Test status
Simulation time 178713953 ps
CPU time 2.79 seconds
Started Jul 28 07:37:24 PM PDT 24
Finished Jul 28 07:37:27 PM PDT 24
Peak memory 206784 kb
Host smart-8e2c886c-92e6-4167-a277-eadc15761c2c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531137053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1531137053
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3629285683
Short name T646
Test name
Test status
Simulation time 131228724 ps
CPU time 3.26 seconds
Started Jul 28 07:37:27 PM PDT 24
Finished Jul 28 07:37:31 PM PDT 24
Peak memory 208524 kb
Host smart-b1eb4a43-9002-4b3e-9b93-916f91472d81
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629285683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3629285683
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1144991718
Short name T598
Test name
Test status
Simulation time 115899147 ps
CPU time 2.81 seconds
Started Jul 28 07:37:24 PM PDT 24
Finished Jul 28 07:37:27 PM PDT 24
Peak memory 208388 kb
Host smart-99adb0a3-d262-47b0-8b47-3413cbb52457
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144991718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1144991718
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1374773012
Short name T748
Test name
Test status
Simulation time 413831681 ps
CPU time 5.37 seconds
Started Jul 28 07:37:30 PM PDT 24
Finished Jul 28 07:37:36 PM PDT 24
Peak memory 209536 kb
Host smart-8b870c36-8a23-45c5-8477-71dd13c50f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374773012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1374773012
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2609109374
Short name T442
Test name
Test status
Simulation time 2947836475 ps
CPU time 13.02 seconds
Started Jul 28 07:37:25 PM PDT 24
Finished Jul 28 07:37:39 PM PDT 24
Peak memory 208388 kb
Host smart-2795abd4-450f-417e-8722-374393889b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609109374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2609109374
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2228534928
Short name T898
Test name
Test status
Simulation time 4994654511 ps
CPU time 32.49 seconds
Started Jul 28 07:37:27 PM PDT 24
Finished Jul 28 07:37:59 PM PDT 24
Peak memory 219308 kb
Host smart-4d769e6c-a1c7-42da-af84-1fb7a9d9f7cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228534928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2228534928
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1745242893
Short name T263
Test name
Test status
Simulation time 7642276423 ps
CPU time 26.77 seconds
Started Jul 28 07:37:31 PM PDT 24
Finished Jul 28 07:37:58 PM PDT 24
Peak memory 208752 kb
Host smart-6083d739-0119-4a9d-989e-660989da741c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745242893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1745242893
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.532511183
Short name T638
Test name
Test status
Simulation time 580527673 ps
CPU time 11.91 seconds
Started Jul 28 07:37:27 PM PDT 24
Finished Jul 28 07:37:40 PM PDT 24
Peak memory 210556 kb
Host smart-c30c7b0e-a973-4e63-ae0e-0a9a9e434415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532511183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.532511183
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.992591415
Short name T499
Test name
Test status
Simulation time 21315402 ps
CPU time 0.87 seconds
Started Jul 28 07:37:31 PM PDT 24
Finished Jul 28 07:37:32 PM PDT 24
Peak memory 205904 kb
Host smart-08c0ead3-639e-4956-bc86-f62d54f95758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992591415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.992591415
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.134926259
Short name T577
Test name
Test status
Simulation time 167651636 ps
CPU time 2.19 seconds
Started Jul 28 07:37:31 PM PDT 24
Finished Jul 28 07:37:34 PM PDT 24
Peak memory 218492 kb
Host smart-774a0e32-030d-4cd6-872f-61d782d73aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134926259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.134926259
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3408571815
Short name T873
Test name
Test status
Simulation time 27858752 ps
CPU time 1.62 seconds
Started Jul 28 07:37:33 PM PDT 24
Finished Jul 28 07:37:35 PM PDT 24
Peak memory 209312 kb
Host smart-77025aad-945f-4ab2-b034-bbc1daba79ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408571815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3408571815
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3959623742
Short name T228
Test name
Test status
Simulation time 249158521 ps
CPU time 6.77 seconds
Started Jul 28 07:37:30 PM PDT 24
Finished Jul 28 07:37:37 PM PDT 24
Peak memory 222272 kb
Host smart-804fbd39-cc2c-4411-9192-d4e159e2497c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959623742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3959623742
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3612837791
Short name T913
Test name
Test status
Simulation time 48623644 ps
CPU time 3.57 seconds
Started Jul 28 07:37:33 PM PDT 24
Finished Jul 28 07:37:37 PM PDT 24
Peak memory 222344 kb
Host smart-358d1e3c-f81a-44c9-b05e-5bbbf98217f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612837791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3612837791
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.793763941
Short name T192
Test name
Test status
Simulation time 67106022 ps
CPU time 3.79 seconds
Started Jul 28 07:37:29 PM PDT 24
Finished Jul 28 07:37:33 PM PDT 24
Peak memory 208936 kb
Host smart-f902fe90-454d-44ef-9c2e-a5fdc0a637da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793763941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.793763941
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2735535471
Short name T328
Test name
Test status
Simulation time 220310569 ps
CPU time 2.8 seconds
Started Jul 28 07:37:30 PM PDT 24
Finished Jul 28 07:37:33 PM PDT 24
Peak memory 206688 kb
Host smart-fb7c62be-9c21-40a2-8dc0-d087ad2f2b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735535471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2735535471
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2324862430
Short name T842
Test name
Test status
Simulation time 258539854 ps
CPU time 5.41 seconds
Started Jul 28 07:37:28 PM PDT 24
Finished Jul 28 07:37:34 PM PDT 24
Peak memory 208468 kb
Host smart-c3c8e249-a45a-4110-9e23-a19f27bb8cd6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324862430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2324862430
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1493263205
Short name T735
Test name
Test status
Simulation time 193207622 ps
CPU time 3.65 seconds
Started Jul 28 07:37:28 PM PDT 24
Finished Jul 28 07:37:31 PM PDT 24
Peak memory 208648 kb
Host smart-70eaa705-45c1-4abb-bc9d-be808b0461c1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493263205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1493263205
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2440112016
Short name T451
Test name
Test status
Simulation time 4441514461 ps
CPU time 23.72 seconds
Started Jul 28 07:37:30 PM PDT 24
Finished Jul 28 07:37:54 PM PDT 24
Peak memory 208184 kb
Host smart-2ff60f64-421e-4836-8ddf-cb7a18a7f6e1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440112016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2440112016
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.3061021981
Short name T553
Test name
Test status
Simulation time 84301683 ps
CPU time 3.24 seconds
Started Jul 28 07:37:28 PM PDT 24
Finished Jul 28 07:37:31 PM PDT 24
Peak memory 209460 kb
Host smart-a4d69379-16f4-4bff-9d2e-a3fd61bb6440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061021981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3061021981
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2062245231
Short name T304
Test name
Test status
Simulation time 160191366 ps
CPU time 3.94 seconds
Started Jul 28 07:37:32 PM PDT 24
Finished Jul 28 07:37:36 PM PDT 24
Peak memory 222220 kb
Host smart-6968421b-19ca-4ca6-812e-cffd89e97563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062245231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2062245231
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.323780059
Short name T905
Test name
Test status
Simulation time 54701135 ps
CPU time 3.14 seconds
Started Jul 28 07:37:30 PM PDT 24
Finished Jul 28 07:37:33 PM PDT 24
Peak memory 210144 kb
Host smart-52a77de9-33af-469f-9a0c-92e354a35f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323780059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.323780059
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.401973857
Short name T486
Test name
Test status
Simulation time 16616339 ps
CPU time 0.95 seconds
Started Jul 28 07:37:32 PM PDT 24
Finished Jul 28 07:37:33 PM PDT 24
Peak memory 206052 kb
Host smart-114fadec-1bed-46cf-967c-397bc5891eb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401973857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.401973857
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2017044912
Short name T107
Test name
Test status
Simulation time 485423161 ps
CPU time 5.11 seconds
Started Jul 28 07:37:33 PM PDT 24
Finished Jul 28 07:37:38 PM PDT 24
Peak memory 215168 kb
Host smart-2c2bb540-e484-4523-b6bd-7a4a7a625aec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2017044912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2017044912
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.890563581
Short name T514
Test name
Test status
Simulation time 217776848 ps
CPU time 4.24 seconds
Started Jul 28 07:37:32 PM PDT 24
Finished Jul 28 07:37:37 PM PDT 24
Peak memory 219540 kb
Host smart-304b15ad-05cf-4708-a9ae-09c880583f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890563581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.890563581
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3083980353
Short name T602
Test name
Test status
Simulation time 217303583 ps
CPU time 1.72 seconds
Started Jul 28 07:37:37 PM PDT 24
Finished Jul 28 07:37:39 PM PDT 24
Peak memory 208624 kb
Host smart-591149c0-0dec-4abf-a73d-31836857bb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083980353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3083980353
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3221353917
Short name T110
Test name
Test status
Simulation time 59988739 ps
CPU time 2.04 seconds
Started Jul 28 07:37:31 PM PDT 24
Finished Jul 28 07:37:34 PM PDT 24
Peak memory 214228 kb
Host smart-76d7c7e5-a9f2-48d8-ae18-1d9a031f739d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221353917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3221353917
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.830234248
Short name T268
Test name
Test status
Simulation time 302449925 ps
CPU time 4.41 seconds
Started Jul 28 07:37:36 PM PDT 24
Finished Jul 28 07:37:41 PM PDT 24
Peak memory 222296 kb
Host smart-2f4e5d45-e749-4953-8bff-8c31560e6a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830234248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.830234248
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3796923567
Short name T540
Test name
Test status
Simulation time 592146334 ps
CPU time 4.12 seconds
Started Jul 28 07:37:35 PM PDT 24
Finished Jul 28 07:37:39 PM PDT 24
Peak memory 209124 kb
Host smart-a7e5e8ea-d69f-4fc5-95df-91905d4b335e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796923567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3796923567
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2751438038
Short name T109
Test name
Test status
Simulation time 87198059 ps
CPU time 2.77 seconds
Started Jul 28 07:37:35 PM PDT 24
Finished Jul 28 07:37:38 PM PDT 24
Peak memory 208072 kb
Host smart-98bf54cc-764f-4f3e-b8ef-e9c56409dfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751438038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2751438038
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.542566068
Short name T585
Test name
Test status
Simulation time 218204682 ps
CPU time 3.53 seconds
Started Jul 28 07:37:30 PM PDT 24
Finished Jul 28 07:37:33 PM PDT 24
Peak memory 206556 kb
Host smart-8164b3d9-cdd1-4f58-b855-9ca5c81f1fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542566068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.542566068
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2324542024
Short name T321
Test name
Test status
Simulation time 507069894 ps
CPU time 4.25 seconds
Started Jul 28 07:37:32 PM PDT 24
Finished Jul 28 07:37:36 PM PDT 24
Peak memory 208432 kb
Host smart-19aab071-a068-4a7f-ac25-bcefddb3f762
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324542024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2324542024
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3146928285
Short name T722
Test name
Test status
Simulation time 60771750 ps
CPU time 2.83 seconds
Started Jul 28 07:37:28 PM PDT 24
Finished Jul 28 07:37:31 PM PDT 24
Peak memory 206812 kb
Host smart-6dfc1430-e185-45da-9c18-c70759b4bdbf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146928285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3146928285
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3570584292
Short name T637
Test name
Test status
Simulation time 249093674 ps
CPU time 3.06 seconds
Started Jul 28 07:37:37 PM PDT 24
Finished Jul 28 07:37:40 PM PDT 24
Peak memory 208636 kb
Host smart-69149383-9044-41c2-a9ab-c59d5db51345
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570584292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3570584292
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.69100104
Short name T679
Test name
Test status
Simulation time 105402379 ps
CPU time 2.38 seconds
Started Jul 28 07:37:34 PM PDT 24
Finished Jul 28 07:37:37 PM PDT 24
Peak memory 207984 kb
Host smart-7b1cd50a-8947-4968-9292-ea412aadd79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69100104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.69100104
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3408636344
Short name T420
Test name
Test status
Simulation time 416496137 ps
CPU time 2.59 seconds
Started Jul 28 07:37:30 PM PDT 24
Finished Jul 28 07:37:33 PM PDT 24
Peak memory 206480 kb
Host smart-08ae5563-9177-4e67-bc85-d0298b22c8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408636344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3408636344
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.329905415
Short name T200
Test name
Test status
Simulation time 120673143 ps
CPU time 4.9 seconds
Started Jul 28 07:37:37 PM PDT 24
Finished Jul 28 07:37:42 PM PDT 24
Peak memory 209564 kb
Host smart-f7963cd4-7b55-4c08-937d-f56d12d068be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329905415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.329905415
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2755398527
Short name T377
Test name
Test status
Simulation time 136719649 ps
CPU time 2.86 seconds
Started Jul 28 07:37:34 PM PDT 24
Finished Jul 28 07:37:37 PM PDT 24
Peak memory 209800 kb
Host smart-3b726c01-1fe1-4195-97f6-4ecc5543ed66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755398527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2755398527
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.2283026075
Short name T422
Test name
Test status
Simulation time 58320659 ps
CPU time 0.94 seconds
Started Jul 28 07:37:36 PM PDT 24
Finished Jul 28 07:37:37 PM PDT 24
Peak memory 205924 kb
Host smart-1d7da7fc-b42e-4246-9b79-a17b8a97b74b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283026075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2283026075
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.4133828031
Short name T375
Test name
Test status
Simulation time 57831134 ps
CPU time 3.03 seconds
Started Jul 28 07:37:38 PM PDT 24
Finished Jul 28 07:37:41 PM PDT 24
Peak memory 210324 kb
Host smart-ecedfcda-bee3-4fbb-8c12-8d5e3385a5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133828031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.4133828031
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2451508631
Short name T566
Test name
Test status
Simulation time 661323276 ps
CPU time 11.6 seconds
Started Jul 28 07:37:38 PM PDT 24
Finished Jul 28 07:37:50 PM PDT 24
Peak memory 208360 kb
Host smart-05dee221-35e0-41d4-84f2-692d0e906a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451508631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2451508631
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.4023914877
Short name T612
Test name
Test status
Simulation time 89279218 ps
CPU time 3.23 seconds
Started Jul 28 07:37:35 PM PDT 24
Finished Jul 28 07:37:39 PM PDT 24
Peak memory 222132 kb
Host smart-e6bb8eee-f093-4d7a-b1db-996300d4116d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023914877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.4023914877
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3711932814
Short name T907
Test name
Test status
Simulation time 222059160 ps
CPU time 2.61 seconds
Started Jul 28 07:37:34 PM PDT 24
Finished Jul 28 07:37:37 PM PDT 24
Peak memory 222224 kb
Host smart-6a1d65d6-8283-47a6-8900-9adf9c09fb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711932814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3711932814
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1543407119
Short name T851
Test name
Test status
Simulation time 206969481 ps
CPU time 3.32 seconds
Started Jul 28 07:37:33 PM PDT 24
Finished Jul 28 07:37:37 PM PDT 24
Peak memory 209540 kb
Host smart-b38fbb1f-eb8d-486b-bfea-b74b6d522ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543407119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1543407119
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2665469473
Short name T395
Test name
Test status
Simulation time 5159819843 ps
CPU time 29.58 seconds
Started Jul 28 07:37:43 PM PDT 24
Finished Jul 28 07:38:13 PM PDT 24
Peak memory 209100 kb
Host smart-17cac9b8-a44e-4e73-be0a-aa6b8f3c3ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665469473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2665469473
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3209961579
Short name T311
Test name
Test status
Simulation time 1052635884 ps
CPU time 8.34 seconds
Started Jul 28 07:37:34 PM PDT 24
Finished Jul 28 07:37:43 PM PDT 24
Peak memory 208588 kb
Host smart-0ab4cf64-318c-4bb0-b699-5417694b1c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209961579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3209961579
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2677529005
Short name T330
Test name
Test status
Simulation time 619932251 ps
CPU time 2.51 seconds
Started Jul 28 07:37:33 PM PDT 24
Finished Jul 28 07:37:36 PM PDT 24
Peak memory 206892 kb
Host smart-6f96f316-5dfb-44e2-928d-078a105327a1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677529005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2677529005
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2774871749
Short name T492
Test name
Test status
Simulation time 1432608063 ps
CPU time 35.42 seconds
Started Jul 28 07:37:32 PM PDT 24
Finished Jul 28 07:38:08 PM PDT 24
Peak memory 208720 kb
Host smart-f409eba7-69ea-477e-9ca3-bf1d2e109f31
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774871749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2774871749
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1395152732
Short name T396
Test name
Test status
Simulation time 205584680 ps
CPU time 4.18 seconds
Started Jul 28 07:37:34 PM PDT 24
Finished Jul 28 07:37:38 PM PDT 24
Peak memory 208296 kb
Host smart-1037bbbc-c315-446a-ba7c-a916ff087eb9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395152732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1395152732
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.693423830
Short name T799
Test name
Test status
Simulation time 72073446 ps
CPU time 2.08 seconds
Started Jul 28 07:37:43 PM PDT 24
Finished Jul 28 07:37:46 PM PDT 24
Peak memory 209324 kb
Host smart-daad2aea-1cd7-4c52-8df8-b3721387882c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693423830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.693423830
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2969951623
Short name T501
Test name
Test status
Simulation time 156331558 ps
CPU time 2.65 seconds
Started Jul 28 07:37:34 PM PDT 24
Finished Jul 28 07:37:37 PM PDT 24
Peak memory 208424 kb
Host smart-c5832a42-8fa4-4892-b66c-e76180e93cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969951623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2969951623
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.943384974
Short name T191
Test name
Test status
Simulation time 203124340 ps
CPU time 5.16 seconds
Started Jul 28 07:37:34 PM PDT 24
Finished Jul 28 07:37:39 PM PDT 24
Peak memory 207788 kb
Host smart-90bdcc28-09de-4f9d-9a22-d9dde7b923a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943384974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.943384974
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.2728509668
Short name T693
Test name
Test status
Simulation time 330587068 ps
CPU time 8.31 seconds
Started Jul 28 07:37:35 PM PDT 24
Finished Jul 28 07:37:43 PM PDT 24
Peak memory 222372 kb
Host smart-9eaec113-3847-4c06-8d95-33a869fdd357
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728509668 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.2728509668
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.831204468
Short name T784
Test name
Test status
Simulation time 146487161 ps
CPU time 5.72 seconds
Started Jul 28 07:37:43 PM PDT 24
Finished Jul 28 07:37:49 PM PDT 24
Peak memory 208332 kb
Host smart-2403ab9e-2874-4437-8b95-a0aac1cebfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831204468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.831204468
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1569745966
Short name T546
Test name
Test status
Simulation time 118789865 ps
CPU time 2.08 seconds
Started Jul 28 07:37:47 PM PDT 24
Finished Jul 28 07:37:49 PM PDT 24
Peak memory 209984 kb
Host smart-3d690ecf-aaae-47ac-9bcc-7432ba0b0c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569745966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1569745966
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3291840275
Short name T461
Test name
Test status
Simulation time 12255778 ps
CPU time 0.76 seconds
Started Jul 28 07:37:43 PM PDT 24
Finished Jul 28 07:37:44 PM PDT 24
Peak memory 205820 kb
Host smart-50221d3a-ed49-4848-9119-d64f29153ab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291840275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3291840275
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2869588292
Short name T121
Test name
Test status
Simulation time 54572688 ps
CPU time 3.83 seconds
Started Jul 28 07:37:48 PM PDT 24
Finished Jul 28 07:37:52 PM PDT 24
Peak memory 214112 kb
Host smart-f0469c70-f071-4f50-9fa5-5e8fe2efcea8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2869588292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2869588292
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2050789021
Short name T673
Test name
Test status
Simulation time 22979330 ps
CPU time 1.43 seconds
Started Jul 28 07:37:45 PM PDT 24
Finished Jul 28 07:37:46 PM PDT 24
Peak memory 207724 kb
Host smart-fda100b4-ff90-4a6e-b2eb-bc2d1ac19140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050789021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2050789021
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3746679186
Short name T332
Test name
Test status
Simulation time 148018077 ps
CPU time 2.66 seconds
Started Jul 28 07:37:40 PM PDT 24
Finished Jul 28 07:37:43 PM PDT 24
Peak memory 214164 kb
Host smart-61e0fba6-4171-44ec-9423-c62b0918c938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746679186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3746679186
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3802045337
Short name T827
Test name
Test status
Simulation time 68975963 ps
CPU time 3.24 seconds
Started Jul 28 07:37:38 PM PDT 24
Finished Jul 28 07:37:41 PM PDT 24
Peak memory 214156 kb
Host smart-93f8f760-db9f-4cca-b5ed-251f148dc3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802045337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3802045337
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2171550426
Short name T214
Test name
Test status
Simulation time 523812556 ps
CPU time 8.13 seconds
Started Jul 28 07:37:46 PM PDT 24
Finished Jul 28 07:37:54 PM PDT 24
Peak memory 219024 kb
Host smart-ce2e54e9-57a4-44bf-abd2-53f02bda7135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171550426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2171550426
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.3684910919
Short name T773
Test name
Test status
Simulation time 210150785 ps
CPU time 5.2 seconds
Started Jul 28 07:37:38 PM PDT 24
Finished Jul 28 07:37:44 PM PDT 24
Peak memory 209864 kb
Host smart-6a1169e7-a03e-4b9e-bb5d-e9634accdc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684910919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3684910919
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3899314278
Short name T911
Test name
Test status
Simulation time 507075785 ps
CPU time 10.3 seconds
Started Jul 28 07:37:47 PM PDT 24
Finished Jul 28 07:37:58 PM PDT 24
Peak memory 208288 kb
Host smart-5e85b2a0-9d61-40a7-8b25-55c8f46a9958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899314278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3899314278
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.2394825701
Short name T805
Test name
Test status
Simulation time 2257921090 ps
CPU time 5.6 seconds
Started Jul 28 07:37:43 PM PDT 24
Finished Jul 28 07:37:48 PM PDT 24
Peak memory 207896 kb
Host smart-9bc04233-8a8f-4a8a-868b-869f3083982a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394825701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.2394825701
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.360011047
Short name T841
Test name
Test status
Simulation time 165711877 ps
CPU time 2.75 seconds
Started Jul 28 07:37:39 PM PDT 24
Finished Jul 28 07:37:42 PM PDT 24
Peak memory 208480 kb
Host smart-cb4eabef-bd06-4ca8-a7b0-6bf48df8bb6f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360011047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.360011047
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3563974816
Short name T880
Test name
Test status
Simulation time 403963299 ps
CPU time 4.59 seconds
Started Jul 28 07:37:39 PM PDT 24
Finished Jul 28 07:37:44 PM PDT 24
Peak memory 208224 kb
Host smart-328ec5d5-42b0-4693-960a-fd7d2774c3b7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563974816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3563974816
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.2773088118
Short name T643
Test name
Test status
Simulation time 79730830 ps
CPU time 1.76 seconds
Started Jul 28 07:37:38 PM PDT 24
Finished Jul 28 07:37:40 PM PDT 24
Peak memory 207852 kb
Host smart-be1789c6-f7fd-48a8-824c-1995d30f1a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773088118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2773088118
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2326783623
Short name T419
Test name
Test status
Simulation time 439272374 ps
CPU time 8.06 seconds
Started Jul 28 07:37:35 PM PDT 24
Finished Jul 28 07:37:43 PM PDT 24
Peak memory 207912 kb
Host smart-cdec6b69-a9dd-417b-b3cf-4bafd88b77ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326783623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2326783623
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1985719716
Short name T183
Test name
Test status
Simulation time 1280113097 ps
CPU time 9.66 seconds
Started Jul 28 07:37:40 PM PDT 24
Finished Jul 28 07:37:50 PM PDT 24
Peak memory 222320 kb
Host smart-e06503dd-588f-4167-a5aa-9a4511164c1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985719716 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.1985719716
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2909144349
Short name T684
Test name
Test status
Simulation time 407406959 ps
CPU time 5.47 seconds
Started Jul 28 07:37:41 PM PDT 24
Finished Jul 28 07:37:47 PM PDT 24
Peak memory 207056 kb
Host smart-becfc0bf-2c09-48fe-92cd-79c32d63de6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909144349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2909144349
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3708986157
Short name T896
Test name
Test status
Simulation time 121219698 ps
CPU time 3.18 seconds
Started Jul 28 07:37:38 PM PDT 24
Finished Jul 28 07:37:42 PM PDT 24
Peak memory 209576 kb
Host smart-6e8c4ca5-a8dc-4c5b-a226-d90ba6ff62d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708986157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3708986157
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2201814882
Short name T782
Test name
Test status
Simulation time 82031277 ps
CPU time 0.86 seconds
Started Jul 28 07:37:46 PM PDT 24
Finished Jul 28 07:37:47 PM PDT 24
Peak memory 205840 kb
Host smart-f3c78bde-22b1-453f-b496-16a80b675613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201814882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2201814882
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3465588372
Short name T413
Test name
Test status
Simulation time 48354870 ps
CPU time 3.67 seconds
Started Jul 28 07:37:38 PM PDT 24
Finished Jul 28 07:37:42 PM PDT 24
Peak memory 215156 kb
Host smart-d5719c16-cedb-4be3-9e68-c2561ea5b69e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3465588372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3465588372
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2436515119
Short name T179
Test name
Test status
Simulation time 112363181 ps
CPU time 1.72 seconds
Started Jul 28 07:37:38 PM PDT 24
Finished Jul 28 07:37:40 PM PDT 24
Peak memory 216188 kb
Host smart-1a51eb04-52cb-48e5-bdea-f097bedcd4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436515119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2436515119
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3464176420
Short name T538
Test name
Test status
Simulation time 173356303 ps
CPU time 2.2 seconds
Started Jul 28 07:37:37 PM PDT 24
Finished Jul 28 07:37:40 PM PDT 24
Peak memory 207456 kb
Host smart-b6ff6279-f513-4016-89c0-bd61e4b30105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464176420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3464176420
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.2324323916
Short name T354
Test name
Test status
Simulation time 77835167 ps
CPU time 2.23 seconds
Started Jul 28 07:37:39 PM PDT 24
Finished Jul 28 07:37:41 PM PDT 24
Peak memory 214044 kb
Host smart-27c4ec58-c672-4aea-94ef-cb2b14a7aebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324323916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2324323916
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_random.2960984077
Short name T823
Test name
Test status
Simulation time 142447697 ps
CPU time 4.92 seconds
Started Jul 28 07:37:42 PM PDT 24
Finished Jul 28 07:37:47 PM PDT 24
Peak memory 222276 kb
Host smart-3dd02024-bd92-443a-a893-364c97f74eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960984077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2960984077
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2156653551
Short name T587
Test name
Test status
Simulation time 2378199146 ps
CPU time 37.63 seconds
Started Jul 28 07:37:45 PM PDT 24
Finished Jul 28 07:38:23 PM PDT 24
Peak memory 208192 kb
Host smart-01ddd873-8184-40b1-8ff7-df9098e70735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156653551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2156653551
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.17713510
Short name T473
Test name
Test status
Simulation time 3180416141 ps
CPU time 39.73 seconds
Started Jul 28 07:37:38 PM PDT 24
Finished Jul 28 07:38:18 PM PDT 24
Peak memory 207840 kb
Host smart-1d48c435-0828-45c1-ad5b-52b5ac239c15
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17713510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.17713510
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.274153848
Short name T83
Test name
Test status
Simulation time 243237479 ps
CPU time 4.92 seconds
Started Jul 28 07:37:39 PM PDT 24
Finished Jul 28 07:37:44 PM PDT 24
Peak memory 207764 kb
Host smart-f7382e9a-1b9a-45a3-8d0f-679cdffa20cc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274153848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.274153848
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.374086142
Short name T426
Test name
Test status
Simulation time 36316267 ps
CPU time 2.32 seconds
Started Jul 28 07:37:43 PM PDT 24
Finished Jul 28 07:37:45 PM PDT 24
Peak memory 206656 kb
Host smart-3822765c-b078-4636-bba8-c1217f0ce08f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374086142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.374086142
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.4099028139
Short name T137
Test name
Test status
Simulation time 506719176 ps
CPU time 2.58 seconds
Started Jul 28 07:37:38 PM PDT 24
Finished Jul 28 07:37:41 PM PDT 24
Peak memory 218164 kb
Host smart-4c902fd7-71a8-46b5-ad0d-4ed884e12a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099028139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.4099028139
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2326209415
Short name T398
Test name
Test status
Simulation time 263137638 ps
CPU time 3.51 seconds
Started Jul 28 07:37:40 PM PDT 24
Finished Jul 28 07:37:43 PM PDT 24
Peak memory 208096 kb
Host smart-48cf1f5b-2266-4aa5-adb5-acda0c12440c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326209415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2326209415
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2792062181
Short name T76
Test name
Test status
Simulation time 465466257 ps
CPU time 23.14 seconds
Started Jul 28 07:37:40 PM PDT 24
Finished Jul 28 07:38:03 PM PDT 24
Peak memory 222348 kb
Host smart-945a4340-8a67-4831-9352-96ed475e186b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792062181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2792062181
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2966293877
Short name T818
Test name
Test status
Simulation time 1142373869 ps
CPU time 17.64 seconds
Started Jul 28 07:37:37 PM PDT 24
Finished Jul 28 07:37:55 PM PDT 24
Peak memory 222380 kb
Host smart-e79fbb83-b755-4936-a077-efca99e2cf22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966293877 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2966293877
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3753444766
Short name T720
Test name
Test status
Simulation time 221728413 ps
CPU time 4.98 seconds
Started Jul 28 07:37:47 PM PDT 24
Finished Jul 28 07:37:52 PM PDT 24
Peak memory 210368 kb
Host smart-45817a33-1552-4908-82f3-06094222e6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753444766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3753444766
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3319177422
Short name T874
Test name
Test status
Simulation time 148965541 ps
CPU time 2.29 seconds
Started Jul 28 07:37:52 PM PDT 24
Finished Jul 28 07:37:54 PM PDT 24
Peak memory 209852 kb
Host smart-ccbab539-2a12-424c-ac7d-c32f09d71354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319177422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3319177422
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.4183909728
Short name T777
Test name
Test status
Simulation time 47481683 ps
CPU time 0.69 seconds
Started Jul 28 07:37:42 PM PDT 24
Finished Jul 28 07:37:43 PM PDT 24
Peak memory 205896 kb
Host smart-5572f753-36dc-4a8f-9900-d2fa3c2b7adc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183909728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.4183909728
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2630296052
Short name T761
Test name
Test status
Simulation time 41138155 ps
CPU time 2.74 seconds
Started Jul 28 07:37:44 PM PDT 24
Finished Jul 28 07:37:47 PM PDT 24
Peak memory 214084 kb
Host smart-4854152d-048d-4e03-a220-99524e67d19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630296052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2630296052
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3893688120
Short name T73
Test name
Test status
Simulation time 120073142 ps
CPU time 1.82 seconds
Started Jul 28 07:37:49 PM PDT 24
Finished Jul 28 07:37:51 PM PDT 24
Peak memory 207612 kb
Host smart-525cf800-7911-4fe2-9a9e-601e98b61623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893688120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3893688120
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2152170213
Short name T313
Test name
Test status
Simulation time 142004040 ps
CPU time 3.47 seconds
Started Jul 28 07:37:45 PM PDT 24
Finished Jul 28 07:37:49 PM PDT 24
Peak memory 216944 kb
Host smart-b1268f85-8928-4b75-aca1-36adbd7efb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152170213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2152170213
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3375729559
Short name T727
Test name
Test status
Simulation time 165172814 ps
CPU time 4.74 seconds
Started Jul 28 07:37:45 PM PDT 24
Finished Jul 28 07:37:50 PM PDT 24
Peak memory 219704 kb
Host smart-4e0d8722-89aa-4016-abcd-7be71043ddc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375729559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3375729559
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1395569928
Short name T465
Test name
Test status
Simulation time 41388995 ps
CPU time 2.85 seconds
Started Jul 28 07:37:52 PM PDT 24
Finished Jul 28 07:37:55 PM PDT 24
Peak memory 214128 kb
Host smart-76bc400d-3185-4939-9b99-1adad3cc1ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395569928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1395569928
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3267122377
Short name T4
Test name
Test status
Simulation time 163757045 ps
CPU time 2.54 seconds
Started Jul 28 07:37:50 PM PDT 24
Finished Jul 28 07:37:53 PM PDT 24
Peak memory 207032 kb
Host smart-6eda01f0-7452-4a6f-9f8c-9a9d98352c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267122377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3267122377
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.59656798
Short name T394
Test name
Test status
Simulation time 1046883705 ps
CPU time 4 seconds
Started Jul 28 07:37:45 PM PDT 24
Finished Jul 28 07:37:49 PM PDT 24
Peak memory 206820 kb
Host smart-acfe3900-4386-4704-be86-ebe3e85f5bc9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59656798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.59656798
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1586925239
Short name T297
Test name
Test status
Simulation time 195433545 ps
CPU time 5.4 seconds
Started Jul 28 07:37:48 PM PDT 24
Finished Jul 28 07:37:54 PM PDT 24
Peak memory 208800 kb
Host smart-52f915f9-874e-47c0-89f1-3ac904884e8c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586925239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1586925239
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1622885
Short name T624
Test name
Test status
Simulation time 72935114 ps
CPU time 2.57 seconds
Started Jul 28 07:37:44 PM PDT 24
Finished Jul 28 07:37:47 PM PDT 24
Peak memory 208740 kb
Host smart-db2c681b-5501-4d12-a24d-36f37ab1e976
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1622885
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2289995658
Short name T522
Test name
Test status
Simulation time 35390004 ps
CPU time 2.16 seconds
Started Jul 28 07:37:43 PM PDT 24
Finished Jul 28 07:37:45 PM PDT 24
Peak memory 214248 kb
Host smart-fe5249a1-7576-4c31-b536-c1e51bd0e48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289995658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2289995658
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2863165573
Short name T796
Test name
Test status
Simulation time 159712384 ps
CPU time 3.48 seconds
Started Jul 28 07:37:47 PM PDT 24
Finished Jul 28 07:37:51 PM PDT 24
Peak memory 207144 kb
Host smart-50a5fecc-5273-445c-9a1f-71a54028189d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863165573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2863165573
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2397732406
Short name T215
Test name
Test status
Simulation time 13967321980 ps
CPU time 152.18 seconds
Started Jul 28 07:37:47 PM PDT 24
Finished Jul 28 07:40:20 PM PDT 24
Peak memory 217420 kb
Host smart-9d432185-6e2f-4ef3-b244-a93cc91f4afb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397732406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2397732406
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.699618727
Short name T184
Test name
Test status
Simulation time 528179060 ps
CPU time 19.06 seconds
Started Jul 28 07:37:50 PM PDT 24
Finished Jul 28 07:38:09 PM PDT 24
Peak memory 222332 kb
Host smart-c6cf45d8-311b-45c5-a213-e63a0b3e481c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699618727 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.699618727
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1671817943
Short name T854
Test name
Test status
Simulation time 721081646 ps
CPU time 9.08 seconds
Started Jul 28 07:37:49 PM PDT 24
Finished Jul 28 07:37:58 PM PDT 24
Peak memory 208552 kb
Host smart-74d98efa-3ed1-45a5-81b9-a9dd18cd9668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671817943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1671817943
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.4083955250
Short name T64
Test name
Test status
Simulation time 51182734 ps
CPU time 2.6 seconds
Started Jul 28 07:37:48 PM PDT 24
Finished Jul 28 07:37:51 PM PDT 24
Peak memory 210176 kb
Host smart-792c369c-081f-4aec-a527-ab2928101b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083955250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.4083955250
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.127127436
Short name T105
Test name
Test status
Simulation time 66916768 ps
CPU time 0.76 seconds
Started Jul 28 07:37:47 PM PDT 24
Finished Jul 28 07:37:48 PM PDT 24
Peak memory 205856 kb
Host smart-445dae37-e5b3-4e3e-89d0-2783e13669ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127127436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.127127436
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1656561043
Short name T415
Test name
Test status
Simulation time 4081480395 ps
CPU time 54.25 seconds
Started Jul 28 07:37:54 PM PDT 24
Finished Jul 28 07:38:48 PM PDT 24
Peak memory 214208 kb
Host smart-ca0ab4ec-5d35-4d4e-814e-47847e873a20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1656561043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1656561043
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1527958947
Short name T31
Test name
Test status
Simulation time 128283353 ps
CPU time 1.83 seconds
Started Jul 28 07:37:51 PM PDT 24
Finished Jul 28 07:37:53 PM PDT 24
Peak memory 214404 kb
Host smart-fb5ea22f-071a-4354-944d-23910beb8c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527958947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1527958947
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1299307131
Short name T46
Test name
Test status
Simulation time 722979969 ps
CPU time 4.98 seconds
Started Jul 28 07:37:50 PM PDT 24
Finished Jul 28 07:37:55 PM PDT 24
Peak memory 209592 kb
Host smart-8ca263e2-7dc0-4052-9bec-f938d834da39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299307131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1299307131
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.900863996
Short name T811
Test name
Test status
Simulation time 384280315 ps
CPU time 4.54 seconds
Started Jul 28 07:37:52 PM PDT 24
Finished Jul 28 07:37:57 PM PDT 24
Peak memory 214212 kb
Host smart-13867fa0-ca22-4198-8666-1c61390868cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900863996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.900863996
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.441441228
Short name T574
Test name
Test status
Simulation time 241706166 ps
CPU time 4.71 seconds
Started Jul 28 07:37:49 PM PDT 24
Finished Jul 28 07:37:54 PM PDT 24
Peak memory 222280 kb
Host smart-3b241071-c639-4dfb-a681-ed6f6c4a9aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441441228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.441441228
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2091485851
Short name T44
Test name
Test status
Simulation time 408963621 ps
CPU time 4.04 seconds
Started Jul 28 07:37:48 PM PDT 24
Finished Jul 28 07:37:52 PM PDT 24
Peak memory 220072 kb
Host smart-e7d8e777-467b-4d4e-b5a6-344c73828785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091485851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2091485851
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1537830970
Short name T882
Test name
Test status
Simulation time 841044575 ps
CPU time 4.64 seconds
Started Jul 28 07:37:47 PM PDT 24
Finished Jul 28 07:37:52 PM PDT 24
Peak memory 207820 kb
Host smart-8afc0555-af4a-442e-98c8-e9478daaeb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537830970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1537830970
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.666398735
Short name T194
Test name
Test status
Simulation time 974072677 ps
CPU time 22.76 seconds
Started Jul 28 07:37:47 PM PDT 24
Finished Jul 28 07:38:10 PM PDT 24
Peak memory 207960 kb
Host smart-f33ce302-24ac-42a8-8cd4-fe0b53695a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666398735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.666398735
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2406049017
Short name T202
Test name
Test status
Simulation time 253575435 ps
CPU time 2.67 seconds
Started Jul 28 07:37:47 PM PDT 24
Finished Jul 28 07:37:49 PM PDT 24
Peak memory 206712 kb
Host smart-3b2be8a1-54b6-4d3f-a70a-07a298a00f4f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406049017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2406049017
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2678657120
Short name T32
Test name
Test status
Simulation time 1173397568 ps
CPU time 36.56 seconds
Started Jul 28 07:37:46 PM PDT 24
Finished Jul 28 07:38:23 PM PDT 24
Peak memory 208220 kb
Host smart-bcc47b11-201b-4952-bb36-54f977c9691a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678657120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2678657120
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.759514518
Short name T665
Test name
Test status
Simulation time 31411084 ps
CPU time 2.23 seconds
Started Jul 28 07:37:49 PM PDT 24
Finished Jul 28 07:37:52 PM PDT 24
Peak memory 208444 kb
Host smart-3be0a263-31a9-42d8-9183-783ff2486b33
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759514518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.759514518
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1051855060
Short name T615
Test name
Test status
Simulation time 220522620 ps
CPU time 4.39 seconds
Started Jul 28 07:37:50 PM PDT 24
Finished Jul 28 07:37:54 PM PDT 24
Peak memory 208312 kb
Host smart-104bfa5d-c1fd-467f-b807-08213b165d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051855060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1051855060
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3548146196
Short name T855
Test name
Test status
Simulation time 1205882060 ps
CPU time 20.12 seconds
Started Jul 28 07:37:50 PM PDT 24
Finished Jul 28 07:38:11 PM PDT 24
Peak memory 207924 kb
Host smart-1af147dc-eff9-4602-82a1-0d5c709d49ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548146196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3548146196
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2249711047
Short name T650
Test name
Test status
Simulation time 114977459 ps
CPU time 3.97 seconds
Started Jul 28 07:37:53 PM PDT 24
Finished Jul 28 07:37:58 PM PDT 24
Peak memory 220068 kb
Host smart-d3092f9a-1b00-428b-a913-72e20a19ea0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249711047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2249711047
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.1857072353
Short name T318
Test name
Test status
Simulation time 1330425034 ps
CPU time 22.48 seconds
Started Jul 28 07:37:56 PM PDT 24
Finished Jul 28 07:38:18 PM PDT 24
Peak memory 222280 kb
Host smart-ebc5c6de-f87f-4318-838e-dbe839ddb61f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857072353 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.1857072353
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.3079518756
Short name T627
Test name
Test status
Simulation time 1745367424 ps
CPU time 5.59 seconds
Started Jul 28 07:37:44 PM PDT 24
Finished Jul 28 07:37:50 PM PDT 24
Peak memory 218128 kb
Host smart-a0fde469-9b4a-4512-9541-687e2c900134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079518756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3079518756
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1128294413
Short name T887
Test name
Test status
Simulation time 84470665 ps
CPU time 2.8 seconds
Started Jul 28 07:37:53 PM PDT 24
Finished Jul 28 07:37:56 PM PDT 24
Peak memory 209960 kb
Host smart-44ceb943-496a-4a6e-a5e1-6b911de4be90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128294413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1128294413
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2694684442
Short name T843
Test name
Test status
Simulation time 16508031 ps
CPU time 0.86 seconds
Started Jul 28 07:37:54 PM PDT 24
Finished Jul 28 07:37:55 PM PDT 24
Peak memory 205884 kb
Host smart-8e97b205-8087-4fc9-8096-a3941193bd93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694684442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2694684442
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.4219390943
Short name T280
Test name
Test status
Simulation time 55761504 ps
CPU time 3.81 seconds
Started Jul 28 07:37:51 PM PDT 24
Finished Jul 28 07:37:55 PM PDT 24
Peak memory 214132 kb
Host smart-38efa1a0-8b7d-4cff-b159-d7c0b40406e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4219390943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.4219390943
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3044185037
Short name T705
Test name
Test status
Simulation time 152890359 ps
CPU time 2.55 seconds
Started Jul 28 07:37:50 PM PDT 24
Finished Jul 28 07:37:53 PM PDT 24
Peak memory 208208 kb
Host smart-a5f24148-cc5c-46fa-8740-398b3cb8c138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044185037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3044185037
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1892149946
Short name T506
Test name
Test status
Simulation time 181029832 ps
CPU time 1.72 seconds
Started Jul 28 07:37:52 PM PDT 24
Finished Jul 28 07:37:54 PM PDT 24
Peak memory 218104 kb
Host smart-bc016bbb-4df7-4c02-af22-853803b45836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892149946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1892149946
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.649402520
Short name T98
Test name
Test status
Simulation time 6615599157 ps
CPU time 52.49 seconds
Started Jul 28 07:37:55 PM PDT 24
Finished Jul 28 07:38:48 PM PDT 24
Peak memory 214208 kb
Host smart-dbea8456-1608-47bb-ae8f-3e7d9406503c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649402520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.649402520
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2867762023
Short name T491
Test name
Test status
Simulation time 55433665 ps
CPU time 2 seconds
Started Jul 28 07:37:54 PM PDT 24
Finished Jul 28 07:37:56 PM PDT 24
Peak memory 214076 kb
Host smart-e843c675-aac8-4d3a-ae19-7277f755d429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867762023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2867762023
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1420103887
Short name T667
Test name
Test status
Simulation time 58754064 ps
CPU time 2.03 seconds
Started Jul 28 07:37:52 PM PDT 24
Finished Jul 28 07:37:55 PM PDT 24
Peak memory 214164 kb
Host smart-60837f48-8c33-418c-be61-a95afdf671f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420103887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1420103887
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.407354267
Short name T325
Test name
Test status
Simulation time 38536899 ps
CPU time 2.72 seconds
Started Jul 28 07:37:53 PM PDT 24
Finished Jul 28 07:37:56 PM PDT 24
Peak memory 209832 kb
Host smart-0fdc78de-119e-409f-9fc8-5741cab602a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407354267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.407354267
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1802681145
Short name T812
Test name
Test status
Simulation time 64617647 ps
CPU time 2.53 seconds
Started Jul 28 07:37:51 PM PDT 24
Finished Jul 28 07:37:54 PM PDT 24
Peak memory 206660 kb
Host smart-595b5fed-6a0c-4145-b2cc-79c965cab544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802681145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1802681145
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.617744309
Short name T597
Test name
Test status
Simulation time 434908173 ps
CPU time 5.54 seconds
Started Jul 28 07:37:51 PM PDT 24
Finished Jul 28 07:37:57 PM PDT 24
Peak memory 208440 kb
Host smart-a717be37-69e0-4940-8937-0d1d5d30d6bb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617744309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.617744309
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2654563208
Short name T657
Test name
Test status
Simulation time 358099035 ps
CPU time 4.9 seconds
Started Jul 28 07:37:51 PM PDT 24
Finished Jul 28 07:37:56 PM PDT 24
Peak memory 208484 kb
Host smart-e6dad04c-ff68-4150-a45a-0b05c024047f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654563208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2654563208
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.1631326389
Short name T688
Test name
Test status
Simulation time 81616452 ps
CPU time 1.85 seconds
Started Jul 28 07:37:51 PM PDT 24
Finished Jul 28 07:37:53 PM PDT 24
Peak memory 206820 kb
Host smart-008d841f-6b01-462b-a49c-157982b805ee
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631326389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1631326389
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3919485186
Short name T837
Test name
Test status
Simulation time 823889470 ps
CPU time 12.49 seconds
Started Jul 28 07:37:51 PM PDT 24
Finished Jul 28 07:38:04 PM PDT 24
Peak memory 208472 kb
Host smart-8da6ab6e-f987-46e6-88e7-550f09866c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919485186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3919485186
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.91419098
Short name T493
Test name
Test status
Simulation time 120526463 ps
CPU time 2.68 seconds
Started Jul 28 07:37:52 PM PDT 24
Finished Jul 28 07:37:55 PM PDT 24
Peak memory 208524 kb
Host smart-17395c1f-c9bd-4da5-aec1-3db0ed3ab565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91419098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.91419098
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.84530798
Short name T859
Test name
Test status
Simulation time 217572677 ps
CPU time 10.55 seconds
Started Jul 28 07:37:51 PM PDT 24
Finished Jul 28 07:38:02 PM PDT 24
Peak memory 222376 kb
Host smart-b5c62c8d-d9f2-40a6-afdd-a3e235093f5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84530798 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.84530798
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.920756340
Short name T300
Test name
Test status
Simulation time 142278709 ps
CPU time 4.6 seconds
Started Jul 28 07:37:49 PM PDT 24
Finished Jul 28 07:37:53 PM PDT 24
Peak memory 208420 kb
Host smart-2ddb67e3-f3fc-4f17-b8c0-cd98ed684fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920756340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.920756340
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.592002700
Short name T434
Test name
Test status
Simulation time 13561522 ps
CPU time 0.72 seconds
Started Jul 28 07:37:53 PM PDT 24
Finished Jul 28 07:37:54 PM PDT 24
Peak memory 205864 kb
Host smart-b55587f9-b65b-4fe0-b7e6-3049ab27a146
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592002700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.592002700
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1954390281
Short name T401
Test name
Test status
Simulation time 237164176 ps
CPU time 12.09 seconds
Started Jul 28 07:37:52 PM PDT 24
Finished Jul 28 07:38:04 PM PDT 24
Peak memory 214248 kb
Host smart-7f779c15-b25a-46df-b8f4-7453d867c077
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1954390281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1954390281
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3964389044
Short name T209
Test name
Test status
Simulation time 161076610 ps
CPU time 4.24 seconds
Started Jul 28 07:37:54 PM PDT 24
Finished Jul 28 07:37:59 PM PDT 24
Peak memory 221124 kb
Host smart-b422315e-ae4c-4987-8414-dba0f06e391b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964389044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3964389044
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2129371511
Short name T714
Test name
Test status
Simulation time 80002952 ps
CPU time 1.78 seconds
Started Jul 28 07:37:55 PM PDT 24
Finished Jul 28 07:37:57 PM PDT 24
Peak memory 206960 kb
Host smart-933838f5-6c27-4ae1-b255-2f6c45ffb00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129371511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2129371511
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1008077754
Short name T742
Test name
Test status
Simulation time 37702079 ps
CPU time 2.28 seconds
Started Jul 28 07:37:57 PM PDT 24
Finished Jul 28 07:37:59 PM PDT 24
Peak memory 214024 kb
Host smart-0c41d268-3a47-4f36-a6ce-2502c54b1f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008077754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1008077754
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.347786047
Short name T213
Test name
Test status
Simulation time 130927304 ps
CPU time 3.29 seconds
Started Jul 28 07:37:53 PM PDT 24
Finished Jul 28 07:37:56 PM PDT 24
Peak memory 209716 kb
Host smart-162b60b6-0558-48ab-8e5a-8e8c098c9546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347786047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.347786047
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3427521827
Short name T633
Test name
Test status
Simulation time 371694764 ps
CPU time 4.71 seconds
Started Jul 28 07:37:53 PM PDT 24
Finished Jul 28 07:37:58 PM PDT 24
Peak memory 207252 kb
Host smart-f02affed-83f4-444d-a536-fbd654776e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427521827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3427521827
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3859163661
Short name T648
Test name
Test status
Simulation time 756419749 ps
CPU time 5.43 seconds
Started Jul 28 07:37:53 PM PDT 24
Finished Jul 28 07:37:59 PM PDT 24
Peak memory 207832 kb
Host smart-5d3088a6-50c7-48a5-9065-362f2313f450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859163661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3859163661
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1875801449
Short name T788
Test name
Test status
Simulation time 272787603 ps
CPU time 5.84 seconds
Started Jul 28 07:37:53 PM PDT 24
Finished Jul 28 07:37:59 PM PDT 24
Peak memory 207788 kb
Host smart-22818965-ff33-4331-aee6-bc7d690fde82
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875801449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1875801449
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3279693882
Short name T654
Test name
Test status
Simulation time 95484524 ps
CPU time 2.61 seconds
Started Jul 28 07:37:53 PM PDT 24
Finished Jul 28 07:37:56 PM PDT 24
Peak memory 206648 kb
Host smart-093a12dc-3cc7-4a1c-8039-9e38fd2fd174
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279693882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3279693882
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.1200351481
Short name T543
Test name
Test status
Simulation time 141433043 ps
CPU time 3.91 seconds
Started Jul 28 07:37:55 PM PDT 24
Finished Jul 28 07:37:59 PM PDT 24
Peak memory 208196 kb
Host smart-75a220d6-f458-4793-83fa-d3df4bc02551
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200351481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1200351481
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1967738629
Short name T257
Test name
Test status
Simulation time 52099395 ps
CPU time 2.32 seconds
Started Jul 28 07:37:57 PM PDT 24
Finished Jul 28 07:37:59 PM PDT 24
Peak memory 208004 kb
Host smart-eb85ab42-1eb9-40ea-ba2f-932792e61b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967738629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1967738629
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.348701112
Short name T853
Test name
Test status
Simulation time 291620984 ps
CPU time 2.84 seconds
Started Jul 28 07:37:52 PM PDT 24
Finished Jul 28 07:37:55 PM PDT 24
Peak memory 206664 kb
Host smart-28bb9095-066a-4675-a081-5b1cf8d41bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348701112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.348701112
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.2320217101
Short name T247
Test name
Test status
Simulation time 364603989 ps
CPU time 12.29 seconds
Started Jul 28 07:37:54 PM PDT 24
Finished Jul 28 07:38:06 PM PDT 24
Peak memory 222432 kb
Host smart-13167f5b-8879-4776-ab42-aae962581a23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320217101 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.2320217101
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3149835139
Short name T407
Test name
Test status
Simulation time 68943713 ps
CPU time 3.32 seconds
Started Jul 28 07:37:55 PM PDT 24
Finished Jul 28 07:37:58 PM PDT 24
Peak memory 208932 kb
Host smart-99e7c511-1806-499f-abaa-49d3354c264a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149835139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3149835139
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3218361226
Short name T134
Test name
Test status
Simulation time 214513998 ps
CPU time 2 seconds
Started Jul 28 07:37:53 PM PDT 24
Finished Jul 28 07:37:56 PM PDT 24
Peak memory 210020 kb
Host smart-48c4d137-3f7b-4251-847f-05f5552d1abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218361226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3218361226
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2381985473
Short name T762
Test name
Test status
Simulation time 34201942 ps
CPU time 0.81 seconds
Started Jul 28 07:35:48 PM PDT 24
Finished Jul 28 07:35:49 PM PDT 24
Peak memory 205832 kb
Host smart-e4c0b19f-9083-4019-9ae1-663fa3e150a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381985473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2381985473
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2079690373
Short name T238
Test name
Test status
Simulation time 401703979 ps
CPU time 3.16 seconds
Started Jul 28 07:35:44 PM PDT 24
Finished Jul 28 07:35:47 PM PDT 24
Peak memory 214144 kb
Host smart-9ae41a2f-851a-4463-a49f-8af1ade7c10c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2079690373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2079690373
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1725839248
Short name T19
Test name
Test status
Simulation time 102238170 ps
CPU time 1.61 seconds
Started Jul 28 07:35:42 PM PDT 24
Finished Jul 28 07:35:44 PM PDT 24
Peak memory 208552 kb
Host smart-761711c2-09ed-439b-a6bf-b08d6fec9d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725839248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1725839248
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2183238511
Short name T778
Test name
Test status
Simulation time 2007742903 ps
CPU time 6.74 seconds
Started Jul 28 07:35:43 PM PDT 24
Finished Jul 28 07:35:50 PM PDT 24
Peak memory 208552 kb
Host smart-ba1b4691-3786-4d19-abff-ab3e75d090ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183238511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2183238511
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3380259740
Short name T676
Test name
Test status
Simulation time 171571914 ps
CPU time 3.58 seconds
Started Jul 28 07:35:44 PM PDT 24
Finished Jul 28 07:35:48 PM PDT 24
Peak memory 209748 kb
Host smart-315fff28-048b-4408-ade8-aa5c4da31557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380259740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3380259740
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.599319834
Short name T34
Test name
Test status
Simulation time 277113746 ps
CPU time 5.41 seconds
Started Jul 28 07:35:45 PM PDT 24
Finished Jul 28 07:35:50 PM PDT 24
Peak memory 214072 kb
Host smart-b0dfac7a-ff2e-4d36-91e4-b006a68959f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599319834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.599319834
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2823145077
Short name T361
Test name
Test status
Simulation time 422128251 ps
CPU time 7.76 seconds
Started Jul 28 07:35:47 PM PDT 24
Finished Jul 28 07:35:55 PM PDT 24
Peak memory 214152 kb
Host smart-6a9be0fe-1f18-4c2b-aa85-3d63c13cabed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823145077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2823145077
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2690408303
Short name T816
Test name
Test status
Simulation time 3357650111 ps
CPU time 19.23 seconds
Started Jul 28 07:35:47 PM PDT 24
Finished Jul 28 07:36:06 PM PDT 24
Peak memory 214244 kb
Host smart-d599b7c7-4ae9-451f-8e24-721c832ab556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690408303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2690408303
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.4126732280
Short name T883
Test name
Test status
Simulation time 52591280 ps
CPU time 2.36 seconds
Started Jul 28 07:35:49 PM PDT 24
Finished Jul 28 07:35:52 PM PDT 24
Peak memory 207036 kb
Host smart-44a0c5c4-a596-448b-b86f-0f5353518dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126732280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.4126732280
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2512545037
Short name T564
Test name
Test status
Simulation time 701050826 ps
CPU time 5.03 seconds
Started Jul 28 07:35:42 PM PDT 24
Finished Jul 28 07:35:47 PM PDT 24
Peak memory 208508 kb
Host smart-309db0fa-e4a3-483c-85ec-f6de357036ca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512545037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2512545037
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.784331268
Short name T661
Test name
Test status
Simulation time 112090406 ps
CPU time 4.35 seconds
Started Jul 28 07:35:44 PM PDT 24
Finished Jul 28 07:35:48 PM PDT 24
Peak memory 208788 kb
Host smart-acf0d5ab-f023-4796-a857-52dad264527e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784331268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.784331268
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3796158353
Short name T490
Test name
Test status
Simulation time 259989282 ps
CPU time 3.43 seconds
Started Jul 28 07:35:46 PM PDT 24
Finished Jul 28 07:35:50 PM PDT 24
Peak memory 208808 kb
Host smart-6edcddb1-709c-4f36-a01c-95152a21baab
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796158353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3796158353
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1548567430
Short name T822
Test name
Test status
Simulation time 31776103 ps
CPU time 1.69 seconds
Started Jul 28 07:35:47 PM PDT 24
Finished Jul 28 07:35:48 PM PDT 24
Peak memory 207684 kb
Host smart-84be70e1-0a34-4b76-bb59-3b7168ee6566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548567430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1548567430
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1291389867
Short name T417
Test name
Test status
Simulation time 143411118 ps
CPU time 3.33 seconds
Started Jul 28 07:35:42 PM PDT 24
Finished Jul 28 07:35:46 PM PDT 24
Peak memory 207620 kb
Host smart-c487adb3-de56-4bbe-bcb0-3cf2dd2e469d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291389867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1291389867
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.2554477213
Short name T793
Test name
Test status
Simulation time 419310458 ps
CPU time 11.32 seconds
Started Jul 28 07:35:52 PM PDT 24
Finished Jul 28 07:36:03 PM PDT 24
Peak memory 222308 kb
Host smart-fcfbebc6-ac77-4815-8a36-e7816a85d551
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554477213 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.2554477213
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.4025946979
Short name T567
Test name
Test status
Simulation time 65047305 ps
CPU time 0.73 seconds
Started Jul 28 07:35:52 PM PDT 24
Finished Jul 28 07:35:53 PM PDT 24
Peak memory 205900 kb
Host smart-b2dfb9cd-ec8f-4f81-9655-6febf434a97a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025946979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.4025946979
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3565834523
Short name T387
Test name
Test status
Simulation time 88962302 ps
CPU time 3.46 seconds
Started Jul 28 07:35:52 PM PDT 24
Finished Jul 28 07:35:55 PM PDT 24
Peak memory 214144 kb
Host smart-852c13fc-fa90-4a51-9980-229687afed49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3565834523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3565834523
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3726652631
Short name T6
Test name
Test status
Simulation time 58819718 ps
CPU time 2.58 seconds
Started Jul 28 07:35:51 PM PDT 24
Finished Jul 28 07:35:54 PM PDT 24
Peak memory 209908 kb
Host smart-6965730b-671a-41cf-a2cf-13b343d87d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726652631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3726652631
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3879890335
Short name T850
Test name
Test status
Simulation time 118316432 ps
CPU time 3.5 seconds
Started Jul 28 07:35:48 PM PDT 24
Finished Jul 28 07:35:52 PM PDT 24
Peak memory 208384 kb
Host smart-844a1b31-c743-421b-8429-deac374532f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879890335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3879890335
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2862925711
Short name T355
Test name
Test status
Simulation time 525198303 ps
CPU time 3.31 seconds
Started Jul 28 07:35:49 PM PDT 24
Finished Jul 28 07:35:52 PM PDT 24
Peak memory 214280 kb
Host smart-388bc03c-3826-45ee-b15d-bb18c12232d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862925711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2862925711
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.7140564
Short name T393
Test name
Test status
Simulation time 145845755 ps
CPU time 4.94 seconds
Started Jul 28 07:35:50 PM PDT 24
Finished Jul 28 07:35:55 PM PDT 24
Peak memory 209224 kb
Host smart-2aa7af6c-5689-4042-8e1d-b744e32d4956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7140564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.7140564
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.2474445960
Short name T350
Test name
Test status
Simulation time 979761356 ps
CPU time 9.69 seconds
Started Jul 28 07:35:53 PM PDT 24
Finished Jul 28 07:36:03 PM PDT 24
Peak memory 210044 kb
Host smart-d9329ac7-1161-4ad4-9b0e-7ecf37f87781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474445960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2474445960
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3752692677
Short name T390
Test name
Test status
Simulation time 55407492 ps
CPU time 2.54 seconds
Started Jul 28 07:35:53 PM PDT 24
Finished Jul 28 07:35:55 PM PDT 24
Peak memory 206764 kb
Host smart-cdb07256-3530-4956-be38-5f94cf96ced8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752692677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3752692677
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3283632941
Short name T435
Test name
Test status
Simulation time 801919997 ps
CPU time 3.7 seconds
Started Jul 28 07:35:53 PM PDT 24
Finished Jul 28 07:35:57 PM PDT 24
Peak memory 208300 kb
Host smart-075e2384-2c9d-4896-847b-21b26f7cc345
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283632941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3283632941
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1474036903
Short name T424
Test name
Test status
Simulation time 60298563 ps
CPU time 3.36 seconds
Started Jul 28 07:35:49 PM PDT 24
Finished Jul 28 07:35:52 PM PDT 24
Peak memory 208516 kb
Host smart-8965240e-f6c2-42a2-9f8a-1b9405f8678d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474036903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1474036903
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.1872774264
Short name T890
Test name
Test status
Simulation time 1305365351 ps
CPU time 4.92 seconds
Started Jul 28 07:35:50 PM PDT 24
Finished Jul 28 07:35:55 PM PDT 24
Peak memory 206936 kb
Host smart-66b39447-a570-467a-91b9-d82214b137be
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872774264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1872774264
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.4075001048
Short name T198
Test name
Test status
Simulation time 121139502 ps
CPU time 2.32 seconds
Started Jul 28 07:35:50 PM PDT 24
Finished Jul 28 07:35:52 PM PDT 24
Peak memory 207980 kb
Host smart-be2bef6b-df5a-4bd3-a155-dd91c235b2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075001048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.4075001048
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1151014359
Short name T750
Test name
Test status
Simulation time 341578102 ps
CPU time 1.84 seconds
Started Jul 28 07:35:48 PM PDT 24
Finished Jul 28 07:35:50 PM PDT 24
Peak memory 208516 kb
Host smart-3529d95b-9fb2-4309-8c5c-4521964cbf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151014359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1151014359
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.435189608
Short name T674
Test name
Test status
Simulation time 6396249768 ps
CPU time 92.34 seconds
Started Jul 28 07:35:54 PM PDT 24
Finished Jul 28 07:37:27 PM PDT 24
Peak memory 216180 kb
Host smart-fcc26ef3-32fe-48ec-b5de-0535e033a22f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435189608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.435189608
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2490838272
Short name T579
Test name
Test status
Simulation time 2178589457 ps
CPU time 21.78 seconds
Started Jul 28 07:35:49 PM PDT 24
Finished Jul 28 07:36:11 PM PDT 24
Peak memory 209184 kb
Host smart-2b5ff9fe-9e46-4f47-89a0-a3651bdf0e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490838272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2490838272
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.1175469460
Short name T604
Test name
Test status
Simulation time 125307244 ps
CPU time 1.92 seconds
Started Jul 28 07:35:50 PM PDT 24
Finished Jul 28 07:35:52 PM PDT 24
Peak memory 209864 kb
Host smart-4644d05e-c9e4-4c9d-b353-fbdf9e027c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175469460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.1175469460
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.455454120
Short name T703
Test name
Test status
Simulation time 14230741 ps
CPU time 0.88 seconds
Started Jul 28 07:35:55 PM PDT 24
Finished Jul 28 07:35:56 PM PDT 24
Peak memory 205868 kb
Host smart-5cf98e90-f8cb-4b07-871b-c18b92b5865a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455454120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.455454120
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3562534499
Short name T205
Test name
Test status
Simulation time 70693514 ps
CPU time 3.24 seconds
Started Jul 28 07:35:52 PM PDT 24
Finished Jul 28 07:35:56 PM PDT 24
Peak memory 208068 kb
Host smart-535cb8dd-9730-4bfa-87a5-70093cc42265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562534499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3562534499
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2050792548
Short name T528
Test name
Test status
Simulation time 101946041 ps
CPU time 1.79 seconds
Started Jul 28 07:35:50 PM PDT 24
Finished Jul 28 07:35:52 PM PDT 24
Peak memory 218144 kb
Host smart-60d742ae-740b-4516-a7b7-ee08d96904ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050792548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2050792548
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2014877469
Short name T269
Test name
Test status
Simulation time 89498009 ps
CPU time 3.94 seconds
Started Jul 28 07:35:47 PM PDT 24
Finished Jul 28 07:35:51 PM PDT 24
Peak memory 214152 kb
Host smart-0fe4e0f2-02e5-433b-8c5d-f8fe2ffadfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014877469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2014877469
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3784671264
Short name T696
Test name
Test status
Simulation time 114061495 ps
CPU time 4.6 seconds
Started Jul 28 07:35:50 PM PDT 24
Finished Jul 28 07:35:55 PM PDT 24
Peak memory 214104 kb
Host smart-75636ba9-4180-40a3-8410-5029e8f2743b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784671264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3784671264
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3158047316
Short name T53
Test name
Test status
Simulation time 77606718 ps
CPU time 2.27 seconds
Started Jul 28 07:35:49 PM PDT 24
Finished Jul 28 07:35:51 PM PDT 24
Peak memory 219664 kb
Host smart-c6dcd9c2-76ff-4593-92c5-591829cb5aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158047316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3158047316
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1456280834
Short name T524
Test name
Test status
Simulation time 77396095 ps
CPU time 4.2 seconds
Started Jul 28 07:35:51 PM PDT 24
Finished Jul 28 07:35:55 PM PDT 24
Peak memory 218336 kb
Host smart-06dea69e-8799-4f3a-a59f-517588e7f790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456280834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1456280834
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.2948870478
Short name T707
Test name
Test status
Simulation time 148862400 ps
CPU time 3.71 seconds
Started Jul 28 07:35:53 PM PDT 24
Finished Jul 28 07:35:56 PM PDT 24
Peak memory 208508 kb
Host smart-8bead7b7-638b-40d7-bdbe-2893259d3589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948870478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2948870478
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3127731455
Short name T776
Test name
Test status
Simulation time 236099110 ps
CPU time 3.5 seconds
Started Jul 28 07:35:54 PM PDT 24
Finished Jul 28 07:35:58 PM PDT 24
Peak memory 206760 kb
Host smart-db456f92-388f-482b-877b-38707fb1b8ca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127731455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3127731455
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2268989322
Short name T298
Test name
Test status
Simulation time 1301659178 ps
CPU time 8.72 seconds
Started Jul 28 07:35:54 PM PDT 24
Finished Jul 28 07:36:03 PM PDT 24
Peak memory 208636 kb
Host smart-5e89c08a-9ce7-4770-a39f-6cbd85b47448
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268989322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2268989322
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2687496520
Short name T847
Test name
Test status
Simulation time 123768513 ps
CPU time 2.39 seconds
Started Jul 28 07:35:48 PM PDT 24
Finished Jul 28 07:35:50 PM PDT 24
Peak memory 206864 kb
Host smart-c16dd2ed-f44c-4575-bf08-40e77bb877b8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687496520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2687496520
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.240277481
Short name T250
Test name
Test status
Simulation time 818548008 ps
CPU time 2.69 seconds
Started Jul 28 07:35:54 PM PDT 24
Finished Jul 28 07:35:57 PM PDT 24
Peak memory 209380 kb
Host smart-dd5d5122-afa4-484e-8a0e-0878dcca17f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240277481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.240277481
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.739948178
Short name T515
Test name
Test status
Simulation time 11044742392 ps
CPU time 22.62 seconds
Started Jul 28 07:35:49 PM PDT 24
Finished Jul 28 07:36:12 PM PDT 24
Peak memory 208140 kb
Host smart-83eb38b4-526b-44a7-8db2-e232e2cacfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739948178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.739948178
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3274423240
Short name T365
Test name
Test status
Simulation time 342678427 ps
CPU time 12.99 seconds
Started Jul 28 07:35:59 PM PDT 24
Finished Jul 28 07:36:12 PM PDT 24
Peak memory 209132 kb
Host smart-7e842914-578c-4181-85f0-2b9eeecccc7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274423240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3274423240
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.1612677991
Short name T323
Test name
Test status
Simulation time 2440347099 ps
CPU time 28.73 seconds
Started Jul 28 07:35:53 PM PDT 24
Finished Jul 28 07:36:22 PM PDT 24
Peak memory 222316 kb
Host smart-2d31580d-87ff-42b8-abfb-382408d5665b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612677991 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.1612677991
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.413212291
Short name T557
Test name
Test status
Simulation time 976207758 ps
CPU time 12.02 seconds
Started Jul 28 07:35:50 PM PDT 24
Finished Jul 28 07:36:03 PM PDT 24
Peak memory 208320 kb
Host smart-e6375878-ac85-4df7-b3c7-944a1585aa32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413212291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.413212291
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1665448756
Short name T376
Test name
Test status
Simulation time 61574721 ps
CPU time 2.2 seconds
Started Jul 28 07:35:50 PM PDT 24
Finished Jul 28 07:35:52 PM PDT 24
Peak memory 209960 kb
Host smart-70c42caa-6239-4079-afec-f85ff407b0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665448756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1665448756
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2191100745
Short name T440
Test name
Test status
Simulation time 15434826 ps
CPU time 0.77 seconds
Started Jul 28 07:35:54 PM PDT 24
Finished Jul 28 07:35:55 PM PDT 24
Peak memory 205896 kb
Host smart-9b8845bc-ecb4-49bb-ad83-c3995d9364e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191100745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2191100745
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2509525125
Short name T342
Test name
Test status
Simulation time 1606829142 ps
CPU time 6.51 seconds
Started Jul 28 07:35:54 PM PDT 24
Finished Jul 28 07:36:01 PM PDT 24
Peak memory 214156 kb
Host smart-e98ff61a-0bc4-4143-aa90-185722792335
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2509525125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2509525125
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2843368387
Short name T560
Test name
Test status
Simulation time 59670095 ps
CPU time 2.74 seconds
Started Jul 28 07:35:58 PM PDT 24
Finished Jul 28 07:36:01 PM PDT 24
Peak memory 209828 kb
Host smart-ec19cb6c-fd28-42a8-afa0-b451ef964d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843368387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2843368387
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.4234244953
Short name T334
Test name
Test status
Simulation time 112191131 ps
CPU time 2.28 seconds
Started Jul 28 07:35:53 PM PDT 24
Finished Jul 28 07:35:55 PM PDT 24
Peak memory 214116 kb
Host smart-2aa60981-0930-490e-accc-a77efa27a1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234244953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.4234244953
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.70044520
Short name T87
Test name
Test status
Simulation time 136721210 ps
CPU time 6.05 seconds
Started Jul 28 07:35:54 PM PDT 24
Finished Jul 28 07:36:00 PM PDT 24
Peak memory 214928 kb
Host smart-d0771211-1e71-4fde-afd8-c6176f3c7770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70044520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.70044520
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1694320771
Short name T485
Test name
Test status
Simulation time 264069676 ps
CPU time 2.96 seconds
Started Jul 28 07:35:57 PM PDT 24
Finished Jul 28 07:36:00 PM PDT 24
Peak memory 208548 kb
Host smart-91074ffa-d779-4615-9503-77c566785342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694320771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1694320771
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_sideload.927838460
Short name T291
Test name
Test status
Simulation time 2743689974 ps
CPU time 11.21 seconds
Started Jul 28 07:35:55 PM PDT 24
Finished Jul 28 07:36:06 PM PDT 24
Peak memory 208060 kb
Host smart-95647029-9dbc-43e0-81f4-fbec7ce12e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927838460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.927838460
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1101523501
Short name T865
Test name
Test status
Simulation time 296436968 ps
CPU time 2.74 seconds
Started Jul 28 07:35:55 PM PDT 24
Finished Jul 28 07:35:58 PM PDT 24
Peak memory 208256 kb
Host smart-b0edd1dd-0fff-468a-999a-e7fe63aae4d5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101523501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1101523501
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.602301364
Short name T740
Test name
Test status
Simulation time 100978229 ps
CPU time 2.8 seconds
Started Jul 28 07:35:56 PM PDT 24
Finished Jul 28 07:35:59 PM PDT 24
Peak memory 206684 kb
Host smart-324d4449-e605-4d45-a83d-c6de0883d4d9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602301364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.602301364
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2561835152
Short name T500
Test name
Test status
Simulation time 597738405 ps
CPU time 5.05 seconds
Started Jul 28 07:35:55 PM PDT 24
Finished Jul 28 07:36:00 PM PDT 24
Peak memory 208836 kb
Host smart-0390d319-db47-452b-a137-8cf210e7906c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561835152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2561835152
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.4116844557
Short name T133
Test name
Test status
Simulation time 679606097 ps
CPU time 2.64 seconds
Started Jul 28 07:35:57 PM PDT 24
Finished Jul 28 07:36:00 PM PDT 24
Peak memory 218264 kb
Host smart-459555ca-1bb3-443c-8ce7-3089215dc968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116844557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.4116844557
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.539099824
Short name T668
Test name
Test status
Simulation time 230747369 ps
CPU time 4.41 seconds
Started Jul 28 07:35:58 PM PDT 24
Finished Jul 28 07:36:03 PM PDT 24
Peak memory 207876 kb
Host smart-00faeda7-36e5-4203-93d0-64819a595fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539099824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.539099824
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3514062434
Short name T787
Test name
Test status
Simulation time 313061567 ps
CPU time 3.6 seconds
Started Jul 28 07:35:57 PM PDT 24
Finished Jul 28 07:36:01 PM PDT 24
Peak memory 218272 kb
Host smart-3ba6b5c0-5ff9-41e1-988d-f01d687143d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514062434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3514062434
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.896171783
Short name T131
Test name
Test status
Simulation time 2310327180 ps
CPU time 23.18 seconds
Started Jul 28 07:35:56 PM PDT 24
Finished Jul 28 07:36:19 PM PDT 24
Peak memory 222416 kb
Host smart-ab1e5706-8ae5-4928-aeb0-2f49a8f30f16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896171783 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.896171783
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3699850537
Short name T719
Test name
Test status
Simulation time 669282333 ps
CPU time 7.39 seconds
Started Jul 28 07:35:56 PM PDT 24
Finished Jul 28 07:36:04 PM PDT 24
Peak memory 209340 kb
Host smart-70eaa713-9f82-42b5-9592-161ba32ce63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699850537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3699850537
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3402907110
Short name T774
Test name
Test status
Simulation time 351778376 ps
CPU time 2.24 seconds
Started Jul 28 07:35:55 PM PDT 24
Finished Jul 28 07:35:57 PM PDT 24
Peak memory 209996 kb
Host smart-736b55d0-eeea-4fed-8a4b-a3f0dfbe0f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402907110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3402907110
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2610811850
Short name T749
Test name
Test status
Simulation time 15850919 ps
CPU time 0.93 seconds
Started Jul 28 07:36:00 PM PDT 24
Finished Jul 28 07:36:01 PM PDT 24
Peak memory 205928 kb
Host smart-3eb737bd-33a8-4720-8f2b-18bda09ed2fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610811850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2610811850
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3695413263
Short name T141
Test name
Test status
Simulation time 301698775 ps
CPU time 4.56 seconds
Started Jul 28 07:35:56 PM PDT 24
Finished Jul 28 07:36:01 PM PDT 24
Peak memory 215056 kb
Host smart-c9236d38-dc4a-4eec-a799-6723b9b36f59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3695413263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3695413263
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3027825226
Short name T803
Test name
Test status
Simulation time 625647857 ps
CPU time 2.75 seconds
Started Jul 28 07:36:00 PM PDT 24
Finished Jul 28 07:36:03 PM PDT 24
Peak memory 214104 kb
Host smart-ed064d54-efa6-45c9-941f-8bcb949cb0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027825226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3027825226
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.714008630
Short name T57
Test name
Test status
Simulation time 291791506 ps
CPU time 3.17 seconds
Started Jul 28 07:35:58 PM PDT 24
Finished Jul 28 07:36:01 PM PDT 24
Peak memory 218344 kb
Host smart-655c8db9-70e2-4849-a140-d6722a7f3711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714008630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.714008630
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.91222070
Short name T552
Test name
Test status
Simulation time 254986292 ps
CPU time 2.83 seconds
Started Jul 28 07:36:04 PM PDT 24
Finished Jul 28 07:36:06 PM PDT 24
Peak memory 214152 kb
Host smart-7b86dd3f-7279-4d5c-b30f-755352526ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91222070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.91222070
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2984853643
Short name T240
Test name
Test status
Simulation time 253363585 ps
CPU time 2.77 seconds
Started Jul 28 07:36:00 PM PDT 24
Finished Jul 28 07:36:03 PM PDT 24
Peak memory 221672 kb
Host smart-f86d53b7-41ec-4821-92f1-5c23964f1ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984853643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2984853643
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2334806903
Short name T556
Test name
Test status
Simulation time 152038836 ps
CPU time 2.74 seconds
Started Jul 28 07:35:55 PM PDT 24
Finished Jul 28 07:35:58 PM PDT 24
Peak memory 206788 kb
Host smart-bf02b9d2-dd2b-4823-b589-ec0305163588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334806903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2334806903
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1355780852
Short name T655
Test name
Test status
Simulation time 43497223 ps
CPU time 3.17 seconds
Started Jul 28 07:35:57 PM PDT 24
Finished Jul 28 07:36:01 PM PDT 24
Peak memory 218336 kb
Host smart-8bdc4141-93de-4fb3-864f-68b085e47756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355780852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1355780852
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1761132390
Short name T672
Test name
Test status
Simulation time 3084364430 ps
CPU time 5.66 seconds
Started Jul 28 07:35:58 PM PDT 24
Finished Jul 28 07:36:04 PM PDT 24
Peak memory 208504 kb
Host smart-4c6e0b47-fbfd-4427-996b-1777b7e82f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761132390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1761132390
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3234036092
Short name T886
Test name
Test status
Simulation time 136717454 ps
CPU time 4.85 seconds
Started Jul 28 07:35:58 PM PDT 24
Finished Jul 28 07:36:03 PM PDT 24
Peak memory 207896 kb
Host smart-a64c76ae-d4cd-47f2-a25e-3e9b613b6c0e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234036092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3234036092
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3224168286
Short name T432
Test name
Test status
Simulation time 134620800 ps
CPU time 4.91 seconds
Started Jul 28 07:35:55 PM PDT 24
Finished Jul 28 07:36:00 PM PDT 24
Peak memory 207808 kb
Host smart-7deb9c50-a296-4c7f-a279-2efa5e3e1f7b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224168286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3224168286
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.171021083
Short name T618
Test name
Test status
Simulation time 260219229 ps
CPU time 3.68 seconds
Started Jul 28 07:35:59 PM PDT 24
Finished Jul 28 07:36:03 PM PDT 24
Peak memory 208704 kb
Host smart-1f449204-eab8-4e5d-9cfa-81dc2e50f79d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171021083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.171021083
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1365524194
Short name T833
Test name
Test status
Simulation time 103562811 ps
CPU time 2.29 seconds
Started Jul 28 07:36:01 PM PDT 24
Finished Jul 28 07:36:03 PM PDT 24
Peak memory 215840 kb
Host smart-222fe52c-416a-46ba-b79b-ced5e78ef164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365524194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1365524194
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3592933877
Short name T910
Test name
Test status
Simulation time 3707383087 ps
CPU time 32.19 seconds
Started Jul 28 07:35:53 PM PDT 24
Finished Jul 28 07:36:25 PM PDT 24
Peak memory 208256 kb
Host smart-19b1e6b1-c943-4b39-afed-4eea44dec528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592933877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3592933877
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1622630235
Short name T726
Test name
Test status
Simulation time 214649910 ps
CPU time 6.79 seconds
Started Jul 28 07:36:01 PM PDT 24
Finished Jul 28 07:36:08 PM PDT 24
Peak memory 206920 kb
Host smart-e8f9d932-685d-4192-9a47-a841886037a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622630235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1622630235
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.3490172875
Short name T483
Test name
Test status
Simulation time 89616329 ps
CPU time 1.56 seconds
Started Jul 28 07:35:58 PM PDT 24
Finished Jul 28 07:36:00 PM PDT 24
Peak memory 209308 kb
Host smart-d57e39a5-dd70-4c34-83b1-b99e2d351c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490172875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3490172875
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%