Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
71.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	17	32	65.31

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	16	19	54.29	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	41	1			T29	2		T48	1		T5	1
auto[OpGenId]	11	1			T17	1		T220	1		T35	1
auto[OpGenSwOut]	16	1			T15	1		T55	1		T49	1
auto[OpGenHwOut]	17	1			T4	1		T6	1		T21	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1756	1			T29	3		T111	2		T10	180
auto[StInit]	87	1			T1	1		T15	1		T39	1
auto[StCreatorRootKey]	64	1			T55	1		T56	1		T49	2
auto[StOwnerIntKey]	45	1			T44	1		T60	1		T113	1
auto[StOwnerKey]	37	1			T17	1		T65	1		T66	1
auto[StDisabled]	461	1			T29	7		T111	3		T114	1
auto[StInvalid]	49	1			T13	1		T40	1		T51	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3496

1

T1

2

T2

1

T3

1

auto[1]

85

1

T15

1

T17

1

T29

2

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1752	1			T29	2		T111	2		T10	180
auto[StReset]	auto[1]	4	1			T29	1		T52	1		T53	1
auto[StInit]	auto[0]	47	1			T1	1		T39	1		T29	1
auto[StInit]	auto[1]	40	1			T15	1		T29	1		T4	1
auto[StCreatorRootKey]	auto[0]	49	1			T56	1		T49	1		T20	1
auto[StCreatorRootKey]	auto[1]	15	1			T55	1		T49	1		T220	1
auto[StOwnerIntKey]	auto[0]	33	1			T44	1		T60	1		T113	1
auto[StOwnerIntKey]	auto[1]	12	1			T6	1		T62	1		T228	1
auto[StOwnerKey]	auto[0]	30	1			T65	1		T66	1		T67	1
auto[StOwnerKey]	auto[1]	7	1			T17	1		T50	1		T229	1
auto[StDisabled]	auto[0]	454	1			T29	7		T111	3		T114	1
auto[StDisabled]	auto[1]	7	1			T230	1		T163	1		T231	1
auto[StInvalid]	auto[0]	49	1			T13	1		T40	1		T51	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	16	19	54.29	16

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	4
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[StOwnerKey]]	[auto[OpGenSwOut]]	0	1	1
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpGenId]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	4	1			T29	1		T52	1		T53	1
auto[StInit]	auto[OpAdvance]	19	1			T29	1		T48	1		T5	1
auto[StInit]	auto[OpGenId]	5	1			T35	1		T50	1		T155	1
auto[StInit]	auto[OpGenSwOut]	9	1			T15	1		T49	1		T220	1
auto[StInit]	auto[OpGenHwOut]	7	1			T4	1		T62	1		T141	1
auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T49	1		T232	1		T233	1
auto[StCreatorRootKey]	auto[OpGenId]	3	1			T220	1		T234	1		T43	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T55	1		T82	1		T235	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	2	1			T21	1		T236	1		-	-
auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T237	1		T238	1		T239	1
auto[StOwnerIntKey]	auto[OpGenId]	1	1			T62	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T186	1		T240	1		T241	1
auto[StOwnerIntKey]	auto[OpGenHwOut]	5	1			T6	1		T228	1		T242	1
auto[StOwnerKey]	auto[OpAdvance]	3	1			T243	1		T242	1		T244	1
auto[StOwnerKey]	auto[OpGenId]	2	1			T17	1		T245	1		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	2	1			T50	1		T229	1		-	-
auto[StDisabled]	auto[OpAdvance]	5	1			T230	1		T163	1		T231	1
auto[StDisabled]	auto[OpGenSwOut]	1	1			T246	1		-	-		-	-
auto[StDisabled]	auto[OpGenHwOut]	1	1			T247	1		-	-		-	-