Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.58	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	74	256	77.58

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	55	225	80.36	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4876

1

T2

8

T3

3

T13

2

auto[1]

534

1

T16

4

T18

1

T19

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4876

1

T2

8

T3

3

T13

2

auto[1]

534

1

T16

4

T18

1

T19

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4794

1

T2

8

T3

3

T13

2

auto[1]

616

1

T14

1

T18

2

T47

4

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4794

1

T2

8

T3

3

T13

2

auto[1]

616

1

T14

1

T18

2

T47

4

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	399	1			T2	2		T19	1		T85	2
auto[OpGenId]	1150	1			T2	3		T3	1		T13	1
auto[OpGenSwOut]	1164	1			T2	2		T3	1		T14	2
auto[OpGenHwOut]	2616	1			T2	1		T3	1		T13	1
auto[OpDisable]	81	1			T14	1		T29	1		T112	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	399	1			T2	2		T19	1		T85	2
auto[OpGenId]	1150	1			T2	3		T3	1		T13	1
auto[OpGenSwOut]	1164	1			T2	2		T3	1		T14	2
auto[OpGenHwOut]	2616	1			T2	1		T3	1		T13	1
auto[OpDisable]	81	1			T14	1		T29	1		T112	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4835

1

T2

8

T3

3

T13

2

auto[1]

575

1

T18

2

T28

1

T45

3

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4835

1

T2

8

T3

3

T13

2

auto[1]

575

1

T18

2

T28

1

T45

3

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5149

1

T2

5

T3

3

T13

2

auto[1]

261

1

T2

3

T19

3

T85

4

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1827	1			T2	1		T3	1		T13	1
auto[1]	743	1			T2	1		T13	1		T16	1
auto[2]	710	1			T16	3		T38	1		T85	1
auto[3]	708	1			T15	1		T17	1		T19	1
auto[4]	371	1			T2	1		T47	2		T29	1
auto[5]	374	1			T2	5		T17	1		T19	2
auto[6]	345	1			T3	1		T16	2		T19	3
auto[7]	332	1			T3	1		T14	1		T45	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1422	1			T2	6		T3	2		T14	1
clear_one[1]	743	1			T2	1		T13	1		T16	1
clear_one[2]	710	1			T16	3		T38	1		T85	1
clear_one[3]	708	1			T15	1		T17	1		T19	1
clear_none	1827	1			T2	1		T3	1		T13	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1073	1			T15	2		T19	1		T38	2
auto[StInit]	662	1			T3	1		T14	1		T16	1
auto[StCreatorRootKey]	593	1			T2	1		T3	1		T14	1
auto[StOwnerIntKey]	525	1			T2	1		T16	1		T17	1
auto[StOwnerKey]	434	1			T16	1		T85	2		T47	1
auto[StDisabled]	1860	1			T2	6		T3	1		T14	1
auto[StInvalid]	263	1			T13	2		T40	4		T51	2

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1073	1			T15	2		T19	1		T38	2
auto[StInit]	662	1			T3	1		T14	1		T16	1
auto[StCreatorRootKey]	593	1			T2	1		T3	1		T14	1
auto[StOwnerIntKey]	525	1			T2	1		T16	1		T17	1
auto[StOwnerKey]	434	1			T16	1		T85	2		T47	1
auto[StDisabled]	1860	1			T2	6		T3	1		T14	1
auto[StInvalid]	263	1			T13	2		T40	4		T51	2

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	7
[auto[1] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	7
[auto[1] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	28
[auto[1] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	7

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	1	1			T248	1		-	-		-	-
auto[0]	auto[StReset]	auto[OpGenId]	160	1			T15	1		T19	1		T4	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	147	1			T29	2		T203	2		T4	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	291	1			T38	1		T85	1		T47	1
auto[0]	auto[StInit]	auto[OpAdvance]	40	1			T139	1		T101	1		T71	1
auto[0]	auto[StInit]	auto[OpGenId]	92	1			T17	1		T29	1		T32	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	100	1			T3	1		T14	1		T85	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	187	1			T16	1		T85	1		T29	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	14	1			T28	1		T111	1		T114	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	47	1			T112	1		T113	1		T49	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	52	1			T14	1		T139	1		T111	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	87	1			T2	1		T219	1		T216	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	15	1			T30	1		T204	1		T140	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	27	1			T29	1		T207	1		T249	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	27	1			T29	1		T71	1		T64	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	47	1			T47	1		T45	1		T250	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T251	1		T76	1		T141	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	17	1			T114	1		T101	1		T205	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T204	1		T205	1		T141	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	44	1			T28	1		T45	1		T219	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	17	1			T139	2		T252	2		T209	1
auto[0]	auto[StDisabled]	auto[OpGenId]	60	1			T29	1		T111	2		T114	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	63	1			T18	1		T19	1		T139	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	175	1			T16	1		T28	1		T223	1
auto[0]	auto[StDisabled]	auto[OpDisable]	27	1			T141	2		T194	1		T78	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	10	1			T93	1		T253	1		T254	1
auto[0]	auto[StInvalid]	auto[OpGenId]	21	1			T13	1		T110	1		T255	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	17	1			T51	1		T90	1		T256	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	22	1			T40	1		T90	1		T110	2
auto[1]	auto[StReset]	auto[OpGenId]	20	1			T29	1		T30	1		T57	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	26	1			T152	1		T205	1		T76	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	57	1			T38	1		T196	1		T249	1
auto[1]	auto[StInit]	auto[OpAdvance]	4	1			T230	1		T257	1		T258	1
auto[1]	auto[StInit]	auto[OpGenId]	10	1			T152	1		T141	1		T25	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	17	1			T139	1		T57	1		T6	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	19	1			T204	1		T221	1		T259	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	11	1			T205	1		T50	1		T260	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T203	1		T212	1		T209	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	18	1			T116	1		T261	1		T62	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	38	1			T16	1		T114	1		T101	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T262	1		T263	1		T237	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T2	1		T114	1		T112	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	19	1			T116	1		T264	1		T62	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	43	1			T219	1		T211	1		T265	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T112	1		T26	1		T266	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	15	1			T249	1		T252	1		T267	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T47	1		T113	1		T252	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	28	1			T215	1		T222	1		T268	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	24	1			T72	1		T62	1		T269	1
auto[1]	auto[StDisabled]	auto[OpGenId]	70	1			T29	1		T208	1		T114	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	65	1			T18	1		T217	1		T211	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	163	1			T47	1		T45	1		T219	1
auto[1]	auto[StDisabled]	auto[OpDisable]	10	1			T6	1		T50	1		T76	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	5	1			T257	1		T270	1		T271	1
auto[1]	auto[StInvalid]	auto[OpGenId]	10	1			T54	1		T93	1		T256	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T57	1		T272	1		T89	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T13	1		T54	1		T273	1
auto[2]	auto[StReset]	auto[OpGenId]	23	1			T119	1		T195	1		T50	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	24	1			T203	1		T57	1		T274	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	50	1			T47	1		T223	1		T251	1
auto[2]	auto[StInit]	auto[OpAdvance]	5	1			T251	1		T275	1		T226	1
auto[2]	auto[StInit]	auto[OpGenId]	6	1			T205	1		T267	1		T141	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	15	1			T220	1		T205	1		T269	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	20	1			T268	1		T205	1		T6	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T152	1		T163	1		T240	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T152	1		T276	1		T277	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	17	1			T153	1		T49	2		T238	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	32	1			T119	1		T268	1		T6	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	13	1			T203	1		T251	1		T76	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	17	1			T101	1		T214	1		T49	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	13	1			T152	1		T49	1		T121	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	50	1			T16	1		T218	1		T223	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T251	1		T220	1		T6	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	11	1			T207	1		T205	1		T277	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T211	1		T49	1		T50	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T16	1		T218	1		T223	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	20	1			T85	1		T278	1		T279	1
auto[2]	auto[StDisabled]	auto[OpGenId]	64	1			T38	1		T113	1		T49	2
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	69	1			T204	1		T112	1		T153	2
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	140	1			T16	1		T219	2		T216	1
auto[2]	auto[StDisabled]	auto[OpDisable]	9	1			T50	2		T141	1		T84	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	7	1			T57	1		T255	1		T270	1
auto[2]	auto[StInvalid]	auto[OpGenId]	12	1			T54	1		T273	1		T280	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T54	1		T281	1		T88	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T272	1		T282	1		T283	1
auto[3]	auto[StReset]	auto[OpGenId]	26	1			T220	2		T205	1		T284	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	21	1			T29	1		T30	1		T205	3
auto[3]	auto[StReset]	auto[OpGenHwOut]	61	1			T15	1		T47	1		T223	1
auto[3]	auto[StInit]	auto[OpAdvance]	2	1			T113	1		T285	1		-	-
auto[3]	auto[StInit]	auto[OpGenId]	19	1			T38	1		T49	1		T220	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	8	1			T50	1		T286	1		T287	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	33	1			T45	1		T223	1		T265	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T204	1		T50	1		T288	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	18	1			T205	1		T6	1		T289	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	21	1			T6	1		T72	1		T50	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	38	1			T265	1		T220	1		T205	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T113	1		T290	1		T291	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T220	1		T142	1		T292	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T49	1		T293	1		T294	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	37	1			T17	1		T215	1		T221	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T152	1		T121	1		T295	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	10	1			T49	1		T230	1		T296	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T50	1		T297	1		T298	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	38	1			T216	1		T217	1		T112	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	17	1			T85	1		T220	1		T72	1
auto[3]	auto[StDisabled]	auto[OpGenId]	50	1			T19	1		T47	1		T212	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	45	1			T203	1		T114	1		T197	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	150	1			T45	1		T29	1		T219	1
auto[3]	auto[StDisabled]	auto[OpDisable]	10	1			T75	1		T50	1		T76	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	12	1			T57	1		T254	1		T272	1
auto[3]	auto[StInvalid]	auto[OpGenId]	12	1			T93	1		T95	1		T92	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T95	1		T257	1		T299	3
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	12	1			T54	1		T95	1		T68	1
auto[4]	auto[StReset]	auto[OpGenId]	11	1			T204	1		T196	1		T205	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	12	1			T47	1		T230	1		T300	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	22	1			T203	1		T57	1		T49	1
auto[4]	auto[StInit]	auto[OpAdvance]	3	1			T301	1		T302	2		-	-
auto[4]	auto[StInit]	auto[OpGenId]	3	1			T49	1		T303	1		T304	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	6	1			T210	1		T305	1		T306	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	12	1			T307	1		T25	1		T308	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T62	1		T297	1		T309	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T47	1		T220	1		T76	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T91	1		T306	1		T310	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	15	1			T311	1		T301	1		T312	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T313	1		T314	1		T315	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T301	1		T316	1		T317	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T220	1		T62	1		T141	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T311	1		T76	1		T318	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T140	3		T319	1		T99	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	8	1			T301	1		T230	1		T320	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T212	1		T205	1		T321	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	24	1			T111	1		T91	1		T259	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	15	1			T2	1		T29	1		T76	1
auto[4]	auto[StDisabled]	auto[OpGenId]	25	1			T217	1		T114	1		T77	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T111	1		T112	1		T214	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	74	1			T218	1		T204	1		T215	2
auto[4]	auto[StDisabled]	auto[OpDisable]	9	1			T112	1		T6	1		T84	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	2	1			T322	1		T323	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	5	1			T51	1		T253	1		T324	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T90	1		T325	1		T326	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T110	1		T255	1		T327	1
auto[5]	auto[StReset]	auto[OpGenId]	12	1			T205	1		T328	1		T50	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	9	1			T210	1		T6	1		T76	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	24	1			T45	1		T223	1		T265	1
auto[5]	auto[StInit]	auto[OpAdvance]	3	1			T220	1		T241	1		T329	1
auto[5]	auto[StInit]	auto[OpGenId]	5	1			T49	1		T330	1		T331	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	7	1			T112	1		T209	1		T76	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	7	1			T332	1		T50	1		T333	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T153	1		T334	1		T245	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T17	1		T85	1		T113	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T335	1		T194	1		T336	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	22	1			T45	1		T59	1		T6	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T62	1		T314	1		T337	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T338	1		T141	1		T339	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T85	1		T29	1		T139	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	25	1			T216	1		T118	1		T153	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T340	1		T275	1		T341	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	12	1			T139	1		T49	1		T293	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T85	2		T76	1		T63	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	12	1			T221	1		T342	1		T307	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	15	1			T2	1		T203	1		T153	2
auto[5]	auto[StDisabled]	auto[OpGenId]	32	1			T2	2		T220	1		T278	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	28	1			T2	2		T19	2		T203	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	81	1			T45	1		T216	1		T338	1
auto[5]	auto[StDisabled]	auto[OpDisable]	4	1			T77	1		T343	1		T344	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	4	1			T256	1		T345	1		T346	1
auto[5]	auto[StInvalid]	auto[OpGenId]	7	1			T40	1		T255	1		T347	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T40	1		T346	1		T271	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T57	1		T253	1		T348	1
auto[6]	auto[StReset]	auto[OpGenId]	10	1			T141	1		T82	1		T238	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	11	1			T205	1		T349	1		T350	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	20	1			T351	1		T220	1		T205	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T76	1		T352	1		-	-
auto[6]	auto[StInit]	auto[OpGenId]	2	1			T163	1		T238	1		-	-
auto[6]	auto[StInit]	auto[OpGenSwOut]	4	1			T353	1		T354	1		T355	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	5	1			T230	1		T356	1		T357	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T76	1		T269	1		T230	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T3	1		T50	1		T358	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T19	1		T49	1		T50	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T19	1		T223	1		T250	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T19	1		T49	2		T84	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T209	1		T205	1		T133	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T359	1		T319	1		T360	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T112	1		T332	1		T361	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T362	1		T363	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	5	1			T310	1		T102	1		T364	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T112	1		T49	1		T87	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	28	1			T111	1		T265	1		T311	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	14	1			T101	1		T112	1		T278	1
auto[6]	auto[StDisabled]	auto[OpGenId]	27	1			T101	1		T112	1		T153	2
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	21	1			T71	1		T153	1		T6	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	75	1			T16	2		T223	1		T215	1
auto[6]	auto[StDisabled]	auto[OpDisable]	5	1			T29	1		T365	1		T310	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	4	1			T281	1		T366	1		T367	1
auto[6]	auto[StInvalid]	auto[OpGenId]	4	1			T255	1		T368	1		T369	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T256	1		T299	1		T280	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T283	1		T370	1		-	-
auto[7]	auto[StReset]	auto[OpGenId]	6	1			T195	1		T62	1		T141	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	6	1			T220	1		T371	1		T372	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	23	1			T30	1		T265	1		T351	1
auto[7]	auto[StInit]	auto[OpAdvance]	4	1			T267	1		T373	1		T374	1
auto[7]	auto[StInit]	auto[OpGenId]	4	1			T119	1		T375	1		T331	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	3	1			T20	1		T336	1		T376	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	15	1			T351	1		T76	1		T377	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T378	1		T379	1		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T380	1		T238	1		T331	2
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T249	1		T267	2		T279	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T221	1		T332	1		T342	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T381	1		-	-		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	3	1			T251	1		T372	1		T275	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T238	1		T382	1		T379	3
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T59	1		T91	1		T62	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T205	1		-	-		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	5	1			T220	1		T383	1		T242	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T274	1		T63	1		T103	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T118	1		T68	1		T192	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	8	1			T140	1		T261	1		T103	1
auto[7]	auto[StDisabled]	auto[OpGenId]	28	1			T204	1		T71	1		T112	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	36	1			T112	1		T205	1		T50	2
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	76	1			T3	1		T45	1		T118	2
auto[7]	auto[StDisabled]	auto[OpDisable]	7	1			T14	1		T76	1		T321	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	3	1			T92	1		T272	1		T366	1
auto[7]	auto[StInvalid]	auto[OpGenId]	3	1			T384	1		T385	1		T355	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T95	1		T273	1		T282	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T40	1		T347	1		T386	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1422

1

T2

6

T3

2

T14

1

clear_one[1]

auto[0]

auto[0]

auto[0]

416

1

T2

1

T13

1

T16

1

clear_one[1]

auto[0]

auto[0]

auto[1]

129

1

T45

1

T219

2

T218

1

clear_one[1]

auto[0]

auto[1]

auto[0]

150

1

T47

2

T30

1

T217

1

clear_one[1]

auto[0]

auto[1]

auto[1]

48

1

T18

1

T112

3

T267

2

clear_one[2]

auto[0]

auto[0]

auto[0]

435

1

T38

1

T85

1

T47

1

clear_one[2]

auto[0]

auto[0]

auto[1]

122

1

T219

2

T218

4

T223

3

clear_one[2]

auto[1]

auto[0]

auto[0]

124

1

T16

3

T216

1

T113

1

clear_one[2]

auto[1]

auto[0]

auto[1]

29

1

T208

1

T49

2

T50

1

clear_one[3]

auto[0]

auto[0]

auto[0]

416

1

T15

1

T17

1

T19

1

clear_one[3]

auto[0]

auto[1]

auto[0]

143

1

T47

1

T30

1

T221

1

clear_one[3]

auto[1]

auto[0]

auto[0]

106

1

T29

1

T216

1

T215

1

clear_one[3]

auto[1]

auto[1]

auto[0]

43

1

T111

1

T197

1

T6

2

clear_none

auto[0]

auto[0]

auto[0]

1291

1

T2

1

T3

1

T13

1

clear_none

auto[0]

auto[0]

auto[1]

140

1

T45

2

T219

2

T218

1

clear_none

auto[0]

auto[1]

auto[0]

123

1

T14

1

T47

1

T28

1

clear_none

auto[0]

auto[1]

auto[1]

41

1

T152

3

T252

1

T49

1

clear_none

auto[1]

auto[0]

auto[0]

135

1

T16

1

T19

1

T29

1

clear_none

auto[1]

auto[0]

auto[1]

29

1

T71

1

T251

2

T91

1

clear_none

auto[1]

auto[1]

auto[0]

31

1

T207

1

T205

1

T6

3

clear_none

auto[1]

auto[1]

auto[1]

37

1

T18

1

T28

1

T114

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1344	1			T2	3		T3	2		T14	1
clear_all	auto[1]	78	1			T2	3		T19	3		T85	2
clear_one[1]	auto[0]	692	1			T2	1		T13	1		T16	1
clear_one[1]	auto[1]	51	1			T252	1		T267	1		T142	1
clear_one[2]	auto[0]	674	1			T16	3		T38	1		T85	1
clear_one[2]	auto[1]	36	1			T152	3		T153	1		T251	1
clear_one[3]	auto[0]	672	1			T15	1		T17	1		T19	1
clear_one[3]	auto[1]	36	1			T85	1		T140	1		T387	8
clear_none	auto[0]	1767	1			T2	1		T3	1		T13	1
clear_none	auto[1]	60	1			T85	1		T139	3		T152	5