Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11342

1

T1

3

T2

7

T3

5

auto[Attestation]

7707

1

T1

1

T2

11

T3

5

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2780	1			T1	3		T2	5		T3	3
auto[Aes]	3359	1			T2	2		T3	1		T14	2
auto[Kmac]	3458	1			T2	2		T3	2		T14	5
auto[Otbn]	3510	1			T1	1		T3	1		T14	3

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7713	1			T1	1		T2	8		T3	3
auto[OpGenId]	5942	1			T2	9		T3	3		T14	2
auto[OpGenSwOut]	5947	1			T1	1		T2	5		T3	5
auto[OpGenHwOut]	7160	1			T1	3		T2	4		T3	2
auto[OpDisable]	151	1			T3	1		T14	1		T29	3

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10715

1

T1

1

T2

10

T3

10

auto[OpDoneFail]

16198

1

T1

4

T2

16

T3

4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6659	1			T1	1		T2	1		T3	1
auto[StInit]	3733	1			T1	4		T2	6		T3	2
auto[StCreatorRootKey]	3214	1			T2	2		T3	3		T14	4
auto[StOwnerIntKey]	2828	1			T2	3		T3	5		T16	2
auto[StOwnerKey]	2436	1			T2	3		T16	2		T17	2
auto[StDisabled]	8043	1			T2	11		T3	3		T14	4

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	350	1			T17	1		T203	1		T30	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	97	1			T1	1		T3	1		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	71	1			T111	2		T114	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	84	1			T3	1		T85	1		T139	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	61	1			T85	1		T29	1		T204	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	219	1			T18	1		T19	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	319	1			T47	1		T203	3		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	100	1			T18	1		T112	2		T205	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	94	1			T3	1		T17	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	59	1			T85	1		T28	1		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	62	1			T18	1		T206	1		T29	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	195	1			T18	1		T85	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	308	1			T47	1		T206	1		T203	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	112	1			T14	1		T85	1		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	79	1			T86	1		T29	1		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	94	1			T3	1		T18	1		T85	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	71	1			T2	1		T17	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	203	1			T29	1		T204	1		T207	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	328	1			T38	1		T47	1		T206	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	87	1			T19	1		T208	1		T59	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	95	1			T14	1		T19	1		T139	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	64	1			T17	1		T29	1		T111	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	61	1			T111	2		T112	1		T209	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	249	1			T14	1		T28	1		T206	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	87	1			T29	5		T57	1		T113	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	109	1			T18	1		T28	1		T29	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	89	1			T29	1		T101	1		T112	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	68	1			T3	1		T29	1		T112	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	62	1			T2	1		T29	1		T204	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	216	1			T2	1		T19	1		T29	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	93	1			T29	3		T57	3		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	104	1			T206	1		T40	1		T210	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	96	1			T18	1		T29	1		T116	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	69	1			T2	1		T210	1		T197	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	62	1			T18	1		T85	1		T211	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	238	1			T18	1		T38	1		T28	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	74	1			T29	1		T112	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	93	1			T14	1		T40	1		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	81	1			T85	1		T197	1		T112	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	72	1			T17	1		T38	1		T85	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	56	1			T212	1		T112	1		T213	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	212	1			T2	1		T14	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	91	1			T29	5		T57	1		T113	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	98	1			T15	1		T85	1		T29	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	74	1			T30	1		T56	1		T111	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	79	1			T206	1		T29	3		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	45	1			T28	1		T29	1		T114	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	217	1			T18	2		T19	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	294	1			T14	1		T15	1		T47	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	86	1			T1	2		T2	1		T207	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	75	1			T19	1		T85	1		T197	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	55	1			T18	1		T111	1		T65	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	49	1			T207	1		T111	1		T214	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	193	1			T2	1		T18	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	433	1			T14	2		T15	2		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	106	1			T16	1		T85	1		T111	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	106	1			T16	1		T18	1		T101	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	96	1			T85	1		T215	1		T111	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	96	1			T18	1		T216	1		T111	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	276	1			T16	4		T28	2		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	506	1			T14	1		T19	3		T38	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	116	1			T106	1		T44	1		T152	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	106	1			T14	1		T210	1		T56	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	119	1			T111	1		T197	1		T112	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	98	1			T28	2		T111	3		T118	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	304	1			T3	1		T29	1		T217	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	553	1			T15	6		T17	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	132	1			T30	1		T218	1		T217	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	98	1			T19	1		T45	1		T30	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	110	1			T45	1		T218	1		T139	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	87	1			T219	1		T218	1		T217	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	285	1			T18	1		T28	1		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	59	1			T29	3		T220	3		T205	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	87	1			T29	1		T204	1		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	80	1			T2	1		T111	1		T71	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	57	1			T207	1		T113	3		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	61	1			T19	1		T29	1		T207	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	171	1			T38	1		T85	1		T30	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	62	1			T49	1		T220	3		T205	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	133	1			T2	1		T203	1		T216	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	96	1			T85	1		T29	1		T216	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	103	1			T16	1		T29	1		T216	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	92	1			T16	1		T18	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	269	1			T19	1		T47	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	71	1			T29	1		T57	2		T49	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	101	1			T118	1		T112	2		T221	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	110	1			T18	1		T29	1		T30	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	91	1			T47	1		T118	1		T152	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	90	1			T139	1		T114	1		T222	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	291	1			T19	2		T28	1		T30	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	55	1			T29	3		T112	1		T113	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	129	1			T1	1		T45	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	111	1			T219	1		T30	1		T223	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	93	1			T3	1		T17	1		T219	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	75	1			T45	1		T30	1		T65	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	294	1			T14	1		T18	1		T45	3

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	200	1			T3	1		T85	2		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	682	1			T1	1		T3	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	201	1			T3	1		T17	1		T18	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	628	1			T18	2		T85	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	226	1			T2	1		T3	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	641	1			T14	1		T85	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	206	1			T14	1		T17	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	678	1			T14	1		T19	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	204	1			T2	1		T3	1		T29	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	427	1			T2	1		T18	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	207	1			T2	1		T18	2		T85	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	455	1			T18	1		T38	1		T28	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	194	1			T17	1		T38	1		T85	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	394	1			T2	1		T14	2		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	183	1			T28	1		T206	1		T29	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	421	1			T15	1		T18	2		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	167	1			T18	1		T19	1		T85	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	585	1			T1	2		T2	2		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	277	1			T16	1		T18	2		T85	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	836	1			T14	2		T15	2		T16	5
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	304	1			T14	1		T28	2		T210	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	945	1			T3	1		T14	1		T19	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	272	1			T19	1		T45	2		T219	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	993	1			T15	6		T17	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	184	1			T2	1		T19	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	331	1			T38	1		T85	1		T29	4
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	284	1			T16	2		T18	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	471	1			T2	1		T19	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	277	1			T18	1		T47	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	477	1			T19	2		T28	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	265	1			T3	1		T17	1		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	492	1			T1	1		T14	1		T18	1