Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32794

1

T1

6

T2

32

T3

17

auto[1]

251

1

T2

2

T19

2

T85

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32800	1			T1	6		T2	32		T3	17
auto[134217728:268435455]	10	1			T19	1		T152	1		T140	1
auto[268435456:402653183]	7	1			T19	1		T301	1		T379	1
auto[402653184:536870911]	11	1			T85	1		T252	1		T267	1
auto[536870912:671088639]	8	1			T153	1		T387	1		T263	1
auto[671088640:805306367]	10	1			T252	2		T405	2		T319	1
auto[805306368:939524095]	16	1			T301	1		T387	1		T393	2
auto[939524096:1073741823]	6	1			T85	1		T406	1		T379	1
auto[1073741824:1207959551]	6	1			T393	1		T406	1		T379	1
auto[1207959552:1342177279]	7	1			T139	1		T140	1		T407	1
auto[1342177280:1476395007]	10	1			T301	1		T407	2		T408	3
auto[1476395008:1610612735]	5	1			T85	1		T152	1		T409	1
auto[1610612736:1744830463]	6	1			T140	1		T387	1		T320	1
auto[1744830464:1879048191]	5	1			T139	1		T408	1		T410	1
auto[1879048192:2013265919]	9	1			T301	1		T263	1		T295	1
auto[2013265920:2147483647]	8	1			T153	1		T267	1		T140	1
auto[2147483648:2281701375]	6	1			T152	1		T405	1		T334	1
auto[2281701376:2415919103]	9	1			T2	1		T392	2		T409	1
auto[2415919104:2550136831]	8	1			T152	2		T252	3		T140	1
auto[2550136832:2684354559]	6	1			T294	1		T391	1		T411	1
auto[2684354560:2818572287]	12	1			T152	1		T267	1		T140	1
auto[2818572288:2952790015]	8	1			T252	1		T387	1		T392	1
auto[2952790016:3087007743]	6	1			T267	1		T140	1		T409	1
auto[3087007744:3221225471]	4	1			T152	1		T262	1		T263	1
auto[3221225472:3355443199]	10	1			T267	1		T140	1		T294	1
auto[3355443200:3489660927]	3	1			T85	1		T153	1		T387	1
auto[3489660928:3623878655]	6	1			T267	1		T393	1		T392	1
auto[3623878656:3758096383]	6	1			T85	1		T409	1		T408	1
auto[3758096384:3892314111]	9	1			T2	1		T252	1		T140	1
auto[3892314112:4026531839]	10	1			T405	1		T295	1		T319	1
auto[4026531840:4160749567]	9	1			T152	1		T140	1		T392	1
auto[4160749568:4294967295]	9	1			T393	1		T392	1		T334	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32794	1			T1	6		T2	32		T3	17
auto[0:134217727]	auto[1]	6	1			T393	1		T379	1		T362	1
auto[134217728:268435455]	auto[1]	10	1			T19	1		T152	1		T140	1
auto[268435456:402653183]	auto[1]	7	1			T19	1		T301	1		T379	1
auto[402653184:536870911]	auto[1]	11	1			T85	1		T252	1		T267	1
auto[536870912:671088639]	auto[1]	8	1			T153	1		T387	1		T263	1
auto[671088640:805306367]	auto[1]	10	1			T252	2		T405	2		T319	1
auto[805306368:939524095]	auto[1]	16	1			T301	1		T387	1		T393	2
auto[939524096:1073741823]	auto[1]	6	1			T85	1		T406	1		T379	1
auto[1073741824:1207959551]	auto[1]	6	1			T393	1		T406	1		T379	1
auto[1207959552:1342177279]	auto[1]	7	1			T139	1		T140	1		T407	1
auto[1342177280:1476395007]	auto[1]	10	1			T301	1		T407	2		T408	3
auto[1476395008:1610612735]	auto[1]	5	1			T85	1		T152	1		T409	1
auto[1610612736:1744830463]	auto[1]	6	1			T140	1		T387	1		T320	1
auto[1744830464:1879048191]	auto[1]	5	1			T139	1		T408	1		T410	1
auto[1879048192:2013265919]	auto[1]	9	1			T301	1		T263	1		T295	1
auto[2013265920:2147483647]	auto[1]	8	1			T153	1		T267	1		T140	1
auto[2147483648:2281701375]	auto[1]	6	1			T152	1		T405	1		T334	1
auto[2281701376:2415919103]	auto[1]	9	1			T2	1		T392	2		T409	1
auto[2415919104:2550136831]	auto[1]	8	1			T152	2		T252	3		T140	1
auto[2550136832:2684354559]	auto[1]	6	1			T294	1		T391	1		T411	1
auto[2684354560:2818572287]	auto[1]	12	1			T152	1		T267	1		T140	1
auto[2818572288:2952790015]	auto[1]	8	1			T252	1		T387	1		T392	1
auto[2952790016:3087007743]	auto[1]	6	1			T267	1		T140	1		T409	1
auto[3087007744:3221225471]	auto[1]	4	1			T152	1		T262	1		T263	1
auto[3221225472:3355443199]	auto[1]	10	1			T267	1		T140	1		T294	1
auto[3355443200:3489660927]	auto[1]	3	1			T85	1		T153	1		T387	1
auto[3489660928:3623878655]	auto[1]	6	1			T267	1		T393	1		T392	1
auto[3623878656:3758096383]	auto[1]	6	1			T85	1		T409	1		T408	1
auto[3758096384:3892314111]	auto[1]	9	1			T2	1		T252	1		T140	1
auto[3892314112:4026531839]	auto[1]	10	1			T405	1		T295	1		T319	1
auto[4026531840:4160749567]	auto[1]	9	1			T152	1		T140	1		T392	1
auto[4160749568:4294967295]	auto[1]	9	1			T393	1		T392	1		T334	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1535

1

T2

1

T3

3

T13

4

auto[1]

1851

1

T2

1

T3

1

T13

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T17	1		T29	1		T51	2
auto[134217728:268435455]	102	1			T13	1		T29	1		T152	1
auto[268435456:402653183]	109	1			T17	1		T85	1		T28	1
auto[402653184:536870911]	112	1			T3	1		T13	1		T15	1
auto[536870912:671088639]	131	1			T3	1		T17	1		T29	1
auto[671088640:805306367]	103	1			T203	1		T152	1		T112	1
auto[805306368:939524095]	98	1			T30	1		T4	1		T54	1
auto[939524096:1073741823]	102	1			T18	1		T29	1		T56	1
auto[1073741824:1207959551]	107	1			T40	1		T29	1		T4	1
auto[1207959552:1342177279]	102	1			T29	2		T48	1		T204	1
auto[1342177280:1476395007]	105	1			T29	1		T203	1		T30	1
auto[1476395008:1610612735]	109	1			T13	1		T17	1		T112	2
auto[1610612736:1744830463]	105	1			T14	1		T29	1		T204	1
auto[1744830464:1879048191]	95	1			T85	1		T29	1		T48	1
auto[1879048192:2013265919]	100	1			T15	1		T17	1		T29	2
auto[2013265920:2147483647]	108	1			T29	1		T30	1		T4	1
auto[2147483648:2281701375]	111	1			T17	1		T29	1		T210	1
auto[2281701376:2415919103]	114	1			T2	1		T19	1		T29	3
auto[2415919104:2550136831]	101	1			T3	1		T29	1		T4	1
auto[2550136832:2684354559]	102	1			T51	1		T210	1		T111	2
auto[2684354560:2818572287]	133	1			T40	1		T203	1		T56	1
auto[2818572288:2952790015]	113	1			T29	1		T204	2		T54	1
auto[2952790016:3087007743]	95	1			T29	2		T56	1		T114	1
auto[3087007744:3221225471]	112	1			T2	1		T15	1		T29	3
auto[3221225472:3355443199]	111	1			T15	1		T17	1		T18	1
auto[3355443200:3489660927]	101	1			T15	1		T19	1		T40	1
auto[3489660928:3623878655]	107	1			T18	1		T85	1		T203	2
auto[3623878656:3758096383]	94	1			T207	1		T71	2		T57	1
auto[3758096384:3892314111]	101	1			T13	2		T29	1		T30	1
auto[3892314112:4026531839]	105	1			T17	1		T29	2		T55	1
auto[4026531840:4160749567]	104	1			T17	1		T40	1		T29	2
auto[4160749568:4294967295]	89	1			T3	1		T19	1		T29	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T29	1		T51	2		T4	1
auto[0:134217727]	auto[1]	49	1			T17	1		T114	1		T250	1
auto[134217728:268435455]	auto[0]	56	1			T29	1		T112	2		T153	1
auto[134217728:268435455]	auto[1]	46	1			T13	1		T152	1		T267	1
auto[268435456:402653183]	auto[0]	50	1			T17	1		T29	1		T56	1
auto[268435456:402653183]	auto[1]	59	1			T85	1		T28	1		T114	1
auto[402653184:536870911]	auto[0]	52	1			T3	1		T13	1		T15	1
auto[402653184:536870911]	auto[1]	60	1			T203	2		T56	1		T5	1
auto[536870912:671088639]	auto[0]	61	1			T3	1		T17	1		T30	1
auto[536870912:671088639]	auto[1]	70	1			T29	1		T222	1		T49	1
auto[671088640:805306367]	auto[0]	46	1			T267	1		T6	2		T230	1
auto[671088640:805306367]	auto[1]	57	1			T203	1		T152	1		T112	1
auto[805306368:939524095]	auto[0]	33	1			T4	1		T54	1		T5	1
auto[805306368:939524095]	auto[1]	65	1			T30	1		T114	1		T57	1
auto[939524096:1073741823]	auto[0]	55	1			T29	1		T56	1		T112	1
auto[939524096:1073741823]	auto[1]	47	1			T18	1		T251	1		T220	1
auto[1073741824:1207959551]	auto[0]	51	1			T4	1		T114	1		T197	1
auto[1073741824:1207959551]	auto[1]	56	1			T40	1		T29	1		T111	2
auto[1207959552:1342177279]	auto[0]	46	1			T29	1		T204	1		T251	1
auto[1207959552:1342177279]	auto[1]	56	1			T29	1		T48	1		T112	1
auto[1342177280:1476395007]	auto[0]	42	1			T29	1		T54	1		T114	1
auto[1342177280:1476395007]	auto[1]	63	1			T203	1		T30	1		T111	1
auto[1476395008:1610612735]	auto[0]	50	1			T13	1		T17	1		T205	1
auto[1476395008:1610612735]	auto[1]	59	1			T112	2		T49	2		T6	1
auto[1610612736:1744830463]	auto[0]	46	1			T14	1		T90	1		T49	1
auto[1610612736:1744830463]	auto[1]	59	1			T29	1		T204	1		T119	1
auto[1744830464:1879048191]	auto[0]	42	1			T93	1		T49	1		T220	2
auto[1744830464:1879048191]	auto[1]	53	1			T85	1		T29	1		T48	1
auto[1879048192:2013265919]	auto[0]	43	1			T15	1		T17	1		T29	1
auto[1879048192:2013265919]	auto[1]	57	1			T29	1		T208	1		T93	1
auto[2013265920:2147483647]	auto[0]	52	1			T29	1		T4	1		T220	2
auto[2013265920:2147483647]	auto[1]	56	1			T30	1		T208	1		T197	1
auto[2147483648:2281701375]	auto[0]	55	1			T17	1		T29	1		T210	1
auto[2147483648:2281701375]	auto[1]	56	1			T152	1		T112	1		T113	1
auto[2281701376:2415919103]	auto[0]	49	1			T29	2		T55	2		T111	2
auto[2281701376:2415919103]	auto[1]	65	1			T2	1		T19	1		T29	1
auto[2415919104:2550136831]	auto[0]	41	1			T3	1		T4	1		T250	1
auto[2415919104:2550136831]	auto[1]	60	1			T29	1		T139	1		T197	1
auto[2550136832:2684354559]	auto[0]	45	1			T51	1		T111	1		T90	1
auto[2550136832:2684354559]	auto[1]	57	1			T210	1		T111	1		T220	1
auto[2684354560:2818572287]	auto[0]	59	1			T40	1		T203	1		T57	1
auto[2684354560:2818572287]	auto[1]	74	1			T56	1		T111	1		T112	2
auto[2818572288:2952790015]	auto[0]	53	1			T204	1		T54	1		T56	1
auto[2818572288:2952790015]	auto[1]	60	1			T29	1		T204	1		T59	1
auto[2952790016:3087007743]	auto[0]	35	1			T29	1		T56	1		T114	1
auto[2952790016:3087007743]	auto[1]	60	1			T29	1		T152	1		T338	1
auto[3087007744:3221225471]	auto[0]	49	1			T2	1		T15	1		T29	2
auto[3087007744:3221225471]	auto[1]	63	1			T29	1		T55	1		T197	2
auto[3221225472:3355443199]	auto[0]	44	1			T15	1		T17	1		T204	1
auto[3221225472:3355443199]	auto[1]	67	1			T18	1		T19	1		T101	1
auto[3355443200:3489660927]	auto[0]	43	1			T15	1		T19	1		T40	1
auto[3355443200:3489660927]	auto[1]	58	1			T29	1		T30	1		T204	1
auto[3489660928:3623878655]	auto[0]	53	1			T203	2		T51	1		T4	1
auto[3489660928:3623878655]	auto[1]	54	1			T18	1		T85	1		T111	1
auto[3623878656:3758096383]	auto[0]	46	1			T71	1		T57	1		T205	1
auto[3623878656:3758096383]	auto[1]	48	1			T207	1		T71	1		T251	1
auto[3758096384:3892314111]	auto[0]	41	1			T13	2		T29	1		T4	1
auto[3758096384:3892314111]	auto[1]	60	1			T30	1		T210	1		T139	1
auto[3892314112:4026531839]	auto[0]	49	1			T29	1		T112	2		T251	1
auto[3892314112:4026531839]	auto[1]	56	1			T17	1		T29	1		T55	1
auto[4026531840:4160749567]	auto[0]	44	1			T17	1		T40	1		T29	1
auto[4026531840:4160749567]	auto[1]	60	1			T29	1		T51	1		T32	1
auto[4160749568:4294967295]	auto[0]	48	1			T113	1		T49	1		T220	1
auto[4160749568:4294967295]	auto[1]	41	1			T3	1		T19	1		T29	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1545

1

T2

1

T3

2

T13

4

auto[1]

1841

1

T2

1

T3

2

T13

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	102	1			T17	1		T40	1		T29	1
auto[134217728:268435455]	110	1			T19	1		T85	1		T28	1
auto[268435456:402653183]	109	1			T29	2		T30	1		T4	2
auto[402653184:536870911]	104	1			T15	1		T18	1		T4	1
auto[536870912:671088639]	102	1			T17	1		T203	1		T54	1
auto[671088640:805306367]	82	1			T48	1		T112	1		T220	2
auto[805306368:939524095]	109	1			T15	2		T17	1		T29	2
auto[939524096:1073741823]	100	1			T17	1		T4	2		T56	1
auto[1073741824:1207959551]	99	1			T3	1		T29	1		T203	1
auto[1207959552:1342177279]	107	1			T3	1		T85	1		T40	1
auto[1342177280:1476395007]	103	1			T17	1		T29	1		T4	1
auto[1476395008:1610612735]	121	1			T29	2		T30	1		T51	1
auto[1610612736:1744830463]	122	1			T13	1		T18	1		T203	1
auto[1744830464:1879048191]	106	1			T2	1		T13	1		T29	2
auto[1879048192:2013265919]	100	1			T19	1		T54	1		T55	1
auto[2013265920:2147483647]	122	1			T15	1		T17	1		T204	1
auto[2147483648:2281701375]	106	1			T203	1		T197	2		T112	1
auto[2281701376:2415919103]	109	1			T29	2		T32	1		T204	1
auto[2415919104:2550136831]	118	1			T13	1		T14	1		T19	1
auto[2550136832:2684354559]	145	1			T40	1		T30	1		T51	1
auto[2684354560:2818572287]	97	1			T3	1		T17	1		T29	2
auto[2818572288:2952790015]	91	1			T56	1		T119	1		T114	1
auto[2952790016:3087007743]	90	1			T13	1		T18	1		T29	2
auto[3087007744:3221225471]	108	1			T207	1		T111	1		T93	1
auto[3221225472:3355443199]	109	1			T2	1		T13	1		T17	1
auto[3355443200:3489660927]	104	1			T19	1		T29	1		T139	1
auto[3489660928:3623878655]	107	1			T15	1		T29	1		T93	1
auto[3623878656:3758096383]	99	1			T3	1		T30	1		T4	1
auto[3758096384:3892314111]	92	1			T29	2		T139	1		T208	1
auto[3892314112:4026531839]	100	1			T203	1		T210	1		T139	1
auto[4026531840:4160749567]	99	1			T17	1		T29	2		T54	2
auto[4160749568:4294967295]	114	1			T85	1		T29	3		T203	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T40	1		T111	1		T220	1
auto[0:134217727]	auto[1]	59	1			T17	1		T29	1		T111	1
auto[134217728:268435455]	auto[0]	54	1			T28	1		T40	2		T30	1
auto[134217728:268435455]	auto[1]	56	1			T19	1		T85	1		T29	1
auto[268435456:402653183]	auto[0]	47	1			T29	1		T4	2		T56	1
auto[268435456:402653183]	auto[1]	62	1			T29	1		T30	1		T204	1
auto[402653184:536870911]	auto[0]	50	1			T15	1		T4	1		T207	1
auto[402653184:536870911]	auto[1]	54	1			T18	1		T210	1		T56	1
auto[536870912:671088639]	auto[0]	46	1			T203	1		T90	2		T251	1
auto[536870912:671088639]	auto[1]	56	1			T17	1		T54	1		T57	1
auto[671088640:805306367]	auto[0]	43	1			T220	2		T140	1		T6	1
auto[671088640:805306367]	auto[1]	39	1			T48	1		T112	1		T347	1
auto[805306368:939524095]	auto[0]	58	1			T15	1		T17	1		T29	1
auto[805306368:939524095]	auto[1]	51	1			T15	1		T29	1		T111	1
auto[939524096:1073741823]	auto[0]	41	1			T17	1		T4	2		T56	1
auto[939524096:1073741823]	auto[1]	59	1			T114	2		T338	1		T209	1
auto[1073741824:1207959551]	auto[0]	53	1			T3	1		T29	1		T197	1
auto[1073741824:1207959551]	auto[1]	46	1			T203	1		T57	1		T205	1
auto[1207959552:1342177279]	auto[0]	60	1			T85	1		T40	1		T29	1
auto[1207959552:1342177279]	auto[1]	47	1			T3	1		T29	1		T30	1
auto[1342177280:1476395007]	auto[0]	42	1			T17	1		T4	1		T152	1
auto[1342177280:1476395007]	auto[1]	61	1			T29	1		T214	1		T49	1
auto[1476395008:1610612735]	auto[0]	52	1			T29	2		T30	1		T51	1
auto[1476395008:1610612735]	auto[1]	69	1			T49	1		T220	1		T6	1
auto[1610612736:1744830463]	auto[0]	57	1			T13	1		T203	1		T114	1
auto[1610612736:1744830463]	auto[1]	65	1			T18	1		T210	1		T205	1
auto[1744830464:1879048191]	auto[0]	47	1			T2	1		T13	1		T29	1
auto[1744830464:1879048191]	auto[1]	59	1			T29	1		T30	1		T55	1
auto[1879048192:2013265919]	auto[0]	46	1			T54	1		T55	1		T112	2
auto[1879048192:2013265919]	auto[1]	54	1			T19	1		T113	1		T220	1
auto[2013265920:2147483647]	auto[0]	56	1			T15	1		T17	1		T57	1
auto[2013265920:2147483647]	auto[1]	66	1			T204	1		T207	1		T111	1
auto[2147483648:2281701375]	auto[0]	50	1			T197	1		T90	1		T64	1
auto[2147483648:2281701375]	auto[1]	56	1			T203	1		T197	1		T112	1
auto[2281701376:2415919103]	auto[0]	55	1			T29	1		T56	1		T49	1
auto[2281701376:2415919103]	auto[1]	54	1			T29	1		T32	1		T204	1
auto[2415919104:2550136831]	auto[0]	63	1			T13	1		T29	2		T209	1
auto[2415919104:2550136831]	auto[1]	55	1			T14	1		T19	1		T29	1
auto[2550136832:2684354559]	auto[0]	57	1			T30	1		T204	2		T113	1
auto[2550136832:2684354559]	auto[1]	88	1			T40	1		T51	1		T139	1
auto[2684354560:2818572287]	auto[0]	42	1			T17	1		T29	1		T203	1
auto[2684354560:2818572287]	auto[1]	55	1			T3	1		T29	1		T114	1
auto[2818572288:2952790015]	auto[0]	37	1			T56	1		T114	1		T251	1
auto[2818572288:2952790015]	auto[1]	54	1			T119	1		T152	1		T112	1
auto[2952790016:3087007743]	auto[0]	28	1			T13	1		T29	1		T51	1
auto[2952790016:3087007743]	auto[1]	62	1			T18	1		T29	1		T56	1
auto[3087007744:3221225471]	auto[0]	44	1			T111	1		T195	2		T50	2
auto[3087007744:3221225471]	auto[1]	64	1			T207	1		T93	1		T222	1
auto[3221225472:3355443199]	auto[0]	50	1			T17	1		T29	1		T112	1
auto[3221225472:3355443199]	auto[1]	59	1			T2	1		T13	1		T112	1
auto[3355443200:3489660927]	auto[0]	44	1			T29	1		T49	1		T220	1
auto[3355443200:3489660927]	auto[1]	60	1			T19	1		T139	1		T101	1
auto[3489660928:3623878655]	auto[0]	45	1			T15	1		T29	1		T112	2
auto[3489660928:3623878655]	auto[1]	62	1			T93	1		T153	1		T220	1
auto[3623878656:3758096383]	auto[0]	43	1			T3	1		T4	1		T56	1
auto[3623878656:3758096383]	auto[1]	56	1			T30	1		T112	1		T57	1
auto[3758096384:3892314111]	auto[0]	36	1			T29	1		T139	1		T56	1
auto[3758096384:3892314111]	auto[1]	56	1			T29	1		T208	1		T114	1
auto[3892314112:4026531839]	auto[0]	54	1			T203	1		T210	1		T251	1
auto[3892314112:4026531839]	auto[1]	46	1			T139	1		T112	1		T49	1
auto[4026531840:4160749567]	auto[0]	55	1			T17	1		T29	1		T54	2
auto[4026531840:4160749567]	auto[1]	44	1			T29	1		T114	1		T93	1
auto[4160749568:4294967295]	auto[0]	47	1			T29	1		T203	1		T51	1
auto[4160749568:4294967295]	auto[1]	67	1			T85	1		T29	2		T208	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1526

1

T2

1

T3

3

T13

4

auto[1]

1860

1

T2

1

T3

1

T13

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	112	1			T3	1		T40	1		T29	1
auto[134217728:268435455]	92	1			T2	1		T17	1		T4	1
auto[268435456:402653183]	106	1			T13	1		T29	1		T204	1
auto[402653184:536870911]	109	1			T17	1		T32	1		T114	1
auto[536870912:671088639]	98	1			T3	1		T29	2		T203	1
auto[671088640:805306367]	121	1			T14	1		T17	1		T85	1
auto[805306368:939524095]	115	1			T2	1		T15	1		T29	1
auto[939524096:1073741823]	113	1			T3	1		T13	1		T19	1
auto[1073741824:1207959551]	100	1			T19	1		T29	2		T30	1
auto[1207959552:1342177279]	104	1			T18	1		T40	1		T29	1
auto[1342177280:1476395007]	97	1			T17	1		T29	3		T51	2
auto[1476395008:1610612735]	89	1			T29	1		T203	2		T210	1
auto[1610612736:1744830463]	113	1			T29	1		T203	1		T54	1
auto[1744830464:1879048191]	108	1			T15	1		T17	1		T29	2
auto[1879048192:2013265919]	91	1			T15	1		T17	1		T40	1
auto[2013265920:2147483647]	86	1			T40	1		T29	3		T204	1
auto[2147483648:2281701375]	117	1			T15	1		T203	1		T51	1
auto[2281701376:2415919103]	104	1			T119	1		T112	1		T57	1
auto[2415919104:2550136831]	116	1			T29	1		T4	1		T111	2
auto[2550136832:2684354559]	117	1			T15	1		T17	2		T18	1
auto[2684354560:2818572287]	100	1			T40	1		T30	1		T139	1
auto[2818572288:2952790015]	104	1			T28	1		T29	2		T48	1
auto[2952790016:3087007743]	119	1			T85	1		T51	1		T204	1
auto[3087007744:3221225471]	117	1			T3	1		T19	1		T85	1
auto[3221225472:3355443199]	106	1			T13	1		T18	1		T29	1
auto[3355443200:3489660927]	105	1			T13	1		T29	1		T250	1
auto[3489660928:3623878655]	100	1			T29	1		T30	1		T4	1
auto[3623878656:3758096383]	84	1			T203	1		T112	1		T250	2
auto[3758096384:3892314111]	103	1			T29	2		T30	1		T210	1
auto[3892314112:4026531839]	118	1			T17	1		T204	1		T56	1
auto[4026531840:4160749567]	111	1			T29	1		T30	1		T139	1
auto[4160749568:4294967295]	111	1			T13	1		T203	1		T48	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T3	1		T40	1		T56	1
auto[0:134217727]	auto[1]	69	1			T29	1		T30	1		T139	1
auto[134217728:268435455]	auto[0]	39	1			T2	1		T4	1		T90	1
auto[134217728:268435455]	auto[1]	53	1			T17	1		T114	1		T112	1
auto[268435456:402653183]	auto[0]	42	1			T207	1		T209	1		T220	1
auto[268435456:402653183]	auto[1]	64	1			T13	1		T29	1		T204	1
auto[402653184:536870911]	auto[0]	51	1			T17	1		T114	1		T197	1
auto[402653184:536870911]	auto[1]	58	1			T32	1		T49	1		T261	1
auto[536870912:671088639]	auto[0]	47	1			T3	1		T203	1		T4	1
auto[536870912:671088639]	auto[1]	51	1			T29	2		T59	1		T49	1
auto[671088640:805306367]	auto[0]	63	1			T14	1		T17	1		T29	2
auto[671088640:805306367]	auto[1]	58	1			T85	1		T49	1		T205	1
auto[805306368:939524095]	auto[0]	53	1			T15	1		T29	1		T210	1
auto[805306368:939524095]	auto[1]	62	1			T2	1		T111	1		T93	1
auto[939524096:1073741823]	auto[0]	48	1			T13	1		T4	1		T54	1
auto[939524096:1073741823]	auto[1]	65	1			T3	1		T19	1		T29	2
auto[1073741824:1207959551]	auto[0]	39	1			T29	2		T30	1		T56	1
auto[1073741824:1207959551]	auto[1]	61	1			T19	1		T208	1		T220	1
auto[1207959552:1342177279]	auto[0]	46	1			T40	1		T251	1		T195	1
auto[1207959552:1342177279]	auto[1]	58	1			T18	1		T29	1		T114	1
auto[1342177280:1476395007]	auto[0]	47	1			T17	1		T29	2		T51	2
auto[1342177280:1476395007]	auto[1]	50	1			T29	1		T111	1		T112	1
auto[1476395008:1610612735]	auto[0]	34	1			T29	1		T203	1		T210	1
auto[1476395008:1610612735]	auto[1]	55	1			T203	1		T112	1		T252	1
auto[1610612736:1744830463]	auto[0]	49	1			T203	1		T54	1		T55	1
auto[1610612736:1744830463]	auto[1]	64	1			T29	1		T152	1		T112	1
auto[1744830464:1879048191]	auto[0]	45	1			T15	1		T17	1		T203	1
auto[1744830464:1879048191]	auto[1]	63	1			T29	2		T55	1		T93	1
auto[1879048192:2013265919]	auto[0]	38	1			T15	1		T4	1		T93	1
auto[1879048192:2013265919]	auto[1]	53	1			T17	1		T40	1		T208	1
auto[2013265920:2147483647]	auto[0]	43	1			T40	1		T29	3		T49	1
auto[2013265920:2147483647]	auto[1]	43	1			T204	1		T197	1		T59	1
auto[2147483648:2281701375]	auto[0]	57	1			T15	1		T203	1		T51	1
auto[2147483648:2281701375]	auto[1]	60	1			T54	1		T152	1		T59	1
auto[2281701376:2415919103]	auto[0]	44	1			T112	1		T57	1		T209	1
auto[2281701376:2415919103]	auto[1]	60	1			T119	1		T49	2		T6	4
auto[2415919104:2550136831]	auto[0]	54	1			T4	1		T111	1		T114	1
auto[2415919104:2550136831]	auto[1]	62	1			T29	1		T111	1		T152	1
auto[2550136832:2684354559]	auto[0]	50	1			T17	1		T19	1		T29	1
auto[2550136832:2684354559]	auto[1]	67	1			T15	1		T17	1		T18	1
auto[2684354560:2818572287]	auto[0]	43	1			T40	1		T30	1		T56	1
auto[2684354560:2818572287]	auto[1]	57	1			T139	1		T101	1		T93	1
auto[2818572288:2952790015]	auto[0]	49	1			T29	1		T54	1		T220	3
auto[2818572288:2952790015]	auto[1]	55	1			T28	1		T29	1		T48	1
auto[2952790016:3087007743]	auto[0]	54	1			T51	1		T71	1		T112	1
auto[2952790016:3087007743]	auto[1]	65	1			T85	1		T204	1		T55	1
auto[3087007744:3221225471]	auto[0]	55	1			T3	1		T85	1		T29	1
auto[3087007744:3221225471]	auto[1]	62	1			T19	1		T51	1		T112	1
auto[3221225472:3355443199]	auto[0]	47	1			T13	1		T139	1		T56	1
auto[3221225472:3355443199]	auto[1]	59	1			T18	1		T29	1		T49	1
auto[3355443200:3489660927]	auto[0]	53	1			T13	1		T29	1		T90	1
auto[3355443200:3489660927]	auto[1]	52	1			T250	1		T49	1		T220	1
auto[3489660928:3623878655]	auto[0]	43	1			T29	1		T56	1		T338	1
auto[3489660928:3623878655]	auto[1]	57	1			T30	1		T4	1		T210	1
auto[3623878656:3758096383]	auto[0]	40	1			T250	1		T49	1		T220	1
auto[3623878656:3758096383]	auto[1]	44	1			T203	1		T112	1		T250	1
auto[3758096384:3892314111]	auto[0]	45	1			T29	1		T55	1		T101	1
auto[3758096384:3892314111]	auto[1]	58	1			T29	1		T30	1		T210	1
auto[3892314112:4026531839]	auto[0]	56	1			T17	1		T56	1		T112	2
auto[3892314112:4026531839]	auto[1]	62	1			T204	1		T111	1		T93	1
auto[4026531840:4160749567]	auto[0]	49	1			T29	1		T139	1		T204	1
auto[4026531840:4160749567]	auto[1]	62	1			T30	1		T111	1		T114	1
auto[4160749568:4294967295]	auto[0]	60	1			T13	1		T203	1		T197	1
auto[4160749568:4294967295]	auto[1]	51	1			T48	1		T204	1		T209	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1551

1

T2

1

T3

3

T13

4

auto[1]

1835

1

T2

1

T3

1

T13

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	114	1			T55	1		T112	2		T209	1
auto[134217728:268435455]	103	1			T17	1		T19	1		T29	3
auto[268435456:402653183]	86	1			T29	1		T48	1		T139	1
auto[402653184:536870911]	109	1			T204	1		T207	1		T54	1
auto[536870912:671088639]	110	1			T13	1		T29	1		T203	1
auto[671088640:805306367]	106	1			T29	2		T111	1		T114	1
auto[805306368:939524095]	113	1			T2	1		T17	1		T85	1
auto[939524096:1073741823]	123	1			T15	1		T85	1		T29	1
auto[1073741824:1207959551]	126	1			T17	1		T40	1		T29	1
auto[1207959552:1342177279]	109	1			T85	1		T29	2		T114	1
auto[1342177280:1476395007]	91	1			T13	1		T28	1		T30	1
auto[1476395008:1610612735]	91	1			T40	1		T208	1		T204	1
auto[1610612736:1744830463]	108	1			T15	1		T18	1		T29	1
auto[1744830464:1879048191]	108	1			T71	1		T5	1		T250	1
auto[1879048192:2013265919]	101	1			T19	1		T29	2		T203	1
auto[2013265920:2147483647]	119	1			T3	1		T13	1		T17	1
auto[2147483648:2281701375]	108	1			T13	1		T29	2		T30	1
auto[2281701376:2415919103]	106	1			T3	1		T18	1		T29	1
auto[2415919104:2550136831]	93	1			T15	1		T40	1		T29	1
auto[2550136832:2684354559]	116	1			T29	5		T4	1		T111	1
auto[2684354560:2818572287]	113	1			T3	1		T13	1		T15	1
auto[2818572288:2952790015]	87	1			T17	1		T29	1		T208	1
auto[2952790016:3087007743]	90	1			T15	1		T29	1		T4	1
auto[3087007744:3221225471]	118	1			T203	1		T30	1		T210	2
auto[3221225472:3355443199]	110	1			T2	1		T19	1		T29	1
auto[3355443200:3489660927]	115	1			T17	1		T40	1		T29	2
auto[3489660928:3623878655]	112	1			T17	2		T203	1		T197	1
auto[3623878656:3758096383]	112	1			T17	1		T18	1		T30	1
auto[3758096384:3892314111]	92	1			T14	1		T203	2		T111	2
auto[3892314112:4026531839]	94	1			T3	1		T29	2		T30	1
auto[4026531840:4160749567]	98	1			T29	1		T204	1		T111	1
auto[4160749568:4294967295]	105	1			T40	1		T54	1		T152	1