Unified Coverage Report :: Group Instance : salt_6

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3023

1

T2

2

T3

4

T13

5

auto[1]

288

1

T2

8

T85

7

T139

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T40	1		T203	1		T71	1
auto[134217728:268435455]	79	1			T29	1		T203	1		T51	1
auto[268435456:402653183]	106	1			T2	2		T85	2		T203	1
auto[402653184:536870911]	105	1			T15	1		T19	1		T139	1
auto[536870912:671088639]	95	1			T40	1		T29	1		T152	1
auto[671088640:805306367]	110	1			T2	1		T29	1		T139	1
auto[805306368:939524095]	114	1			T29	1		T203	2		T114	1
auto[939524096:1073741823]	124	1			T3	1		T85	1		T29	1
auto[1073741824:1207959551]	110	1			T2	1		T19	1		T29	1
auto[1207959552:1342177279]	90	1			T29	1		T51	1		T210	1
auto[1342177280:1476395007]	113	1			T15	1		T19	1		T85	1
auto[1476395008:1610612735]	98	1			T14	1		T40	1		T29	1
auto[1610612736:1744830463]	89	1			T2	1		T18	1		T30	1
auto[1744830464:1879048191]	106	1			T29	2		T111	1		T114	2
auto[1879048192:2013265919]	104	1			T30	1		T51	1		T4	1
auto[2013265920:2147483647]	100	1			T13	2		T203	1		T210	1
auto[2147483648:2281701375]	98	1			T111	2		T101	1		T93	1
auto[2281701376:2415919103]	99	1			T17	1		T85	1		T28	1
auto[2415919104:2550136831]	102	1			T19	1		T29	1		T30	1
auto[2550136832:2684354559]	103	1			T2	1		T13	2		T17	1
auto[2684354560:2818572287]	118	1			T15	1		T18	1		T203	1
auto[2818572288:2952790015]	94	1			T15	1		T18	1		T54	1
auto[2952790016:3087007743]	100	1			T2	1		T85	1		T204	1
auto[3087007744:3221225471]	123	1			T3	1		T17	1		T29	2
auto[3221225472:3355443199]	104	1			T2	1		T40	1		T29	1
auto[3355443200:3489660927]	113	1			T15	1		T85	1		T203	1
auto[3489660928:3623878655]	103	1			T29	2		T111	1		T114	2
auto[3623878656:3758096383]	119	1			T2	1		T17	1		T30	1
auto[3758096384:3892314111]	93	1			T13	1		T139	1		T204	1
auto[3892314112:4026531839]	103	1			T2	1		T85	1		T40	1
auto[4026531840:4160749567]	86	1			T3	1		T93	1		T152	1
auto[4160749568:4294967295]	101	1			T3	1		T85	2		T29	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	97	1			T40	1		T203	1		T71	1
auto[0:134217727]	auto[1]	12	1			T152	1		T153	1		T252	1
auto[134217728:268435455]	auto[0]	75	1			T29	1		T203	1		T51	1
auto[134217728:268435455]	auto[1]	4	1			T252	1		T392	1		T414	1
auto[268435456:402653183]	auto[0]	91	1			T85	1		T203	1		T56	1
auto[268435456:402653183]	auto[1]	15	1			T2	2		T85	1		T267	3
auto[402653184:536870911]	auto[0]	97	1			T15	1		T19	1		T139	1
auto[402653184:536870911]	auto[1]	8	1			T152	1		T267	1		T301	1
auto[536870912:671088639]	auto[0]	86	1			T40	1		T29	1		T152	1
auto[536870912:671088639]	auto[1]	9	1			T267	1		T140	1		T387	2
auto[671088640:805306367]	auto[0]	96	1			T29	1		T112	1		T251	1
auto[671088640:805306367]	auto[1]	14	1			T2	1		T139	1		T153	1
auto[805306368:939524095]	auto[0]	102	1			T29	1		T203	2		T114	1
auto[805306368:939524095]	auto[1]	12	1			T152	1		T301	1		T387	2
auto[939524096:1073741823]	auto[0]	112	1			T3	1		T29	1		T56	1
auto[939524096:1073741823]	auto[1]	12	1			T85	1		T294	1		T393	1
auto[1073741824:1207959551]	auto[0]	96	1			T2	1		T19	1		T29	1
auto[1073741824:1207959551]	auto[1]	14	1			T153	3		T267	2		T387	1
auto[1207959552:1342177279]	auto[0]	81	1			T29	1		T51	1		T210	1
auto[1207959552:1342177279]	auto[1]	9	1			T152	1		T252	1		T294	1
auto[1342177280:1476395007]	auto[0]	106	1			T15	1		T19	1		T29	1
auto[1342177280:1476395007]	auto[1]	7	1			T85	1		T152	1		T417	1
auto[1476395008:1610612735]	auto[0]	87	1			T14	1		T40	1		T29	1
auto[1476395008:1610612735]	auto[1]	11	1			T152	2		T387	1		T320	1
auto[1610612736:1744830463]	auto[0]	77	1			T18	1		T30	1		T5	1
auto[1610612736:1744830463]	auto[1]	12	1			T2	1		T152	1		T267	1
auto[1744830464:1879048191]	auto[0]	99	1			T29	2		T111	1		T114	2
auto[1744830464:1879048191]	auto[1]	7	1			T152	1		T153	1		T408	1
auto[1879048192:2013265919]	auto[0]	98	1			T30	1		T51	1		T4	1
auto[1879048192:2013265919]	auto[1]	6	1			T252	1		T142	1		T415	2
auto[2013265920:2147483647]	auto[0]	96	1			T13	2		T203	1		T210	1
auto[2013265920:2147483647]	auto[1]	4	1			T392	1		T391	1		T314	2
auto[2147483648:2281701375]	auto[0]	87	1			T111	2		T101	1		T93	1
auto[2147483648:2281701375]	auto[1]	11	1			T152	1		T267	1		T393	1
auto[2281701376:2415919103]	auto[0]	88	1			T17	1		T28	1		T29	1
auto[2281701376:2415919103]	auto[1]	11	1			T85	1		T153	1		T387	2
auto[2415919104:2550136831]	auto[0]	93	1			T19	1		T29	1		T30	1
auto[2415919104:2550136831]	auto[1]	9	1			T252	1		T387	1		T405	1
auto[2550136832:2684354559]	auto[0]	96	1			T13	2		T17	1		T111	1
auto[2550136832:2684354559]	auto[1]	7	1			T2	1		T387	1		T393	2
auto[2684354560:2818572287]	auto[0]	110	1			T15	1		T18	1		T203	1
auto[2684354560:2818572287]	auto[1]	8	1			T153	1		T267	1		T393	1
auto[2818572288:2952790015]	auto[0]	89	1			T15	1		T18	1		T54	1
auto[2818572288:2952790015]	auto[1]	5	1			T301	1		T263	1		T411	1
auto[2952790016:3087007743]	auto[0]	93	1			T204	1		T111	2		T5	1
auto[2952790016:3087007743]	auto[1]	7	1			T2	1		T85	1		T320	1
auto[3087007744:3221225471]	auto[0]	117	1			T3	1		T17	1		T29	2
auto[3087007744:3221225471]	auto[1]	6	1			T153	1		T405	1		T319	1
auto[3221225472:3355443199]	auto[0]	95	1			T40	1		T29	1		T30	1
auto[3221225472:3355443199]	auto[1]	9	1			T2	1		T252	2		T263	1
auto[3355443200:3489660927]	auto[0]	104	1			T15	1		T203	1		T111	1
auto[3355443200:3489660927]	auto[1]	9	1			T85	1		T153	1		T252	1
auto[3489660928:3623878655]	auto[0]	94	1			T29	2		T111	1		T114	2
auto[3489660928:3623878655]	auto[1]	9	1			T267	1		T393	1		T392	1
auto[3623878656:3758096383]	auto[0]	110	1			T2	1		T17	1		T30	1
auto[3623878656:3758096383]	auto[1]	9	1			T267	1		T392	1		T319	1
auto[3758096384:3892314111]	auto[0]	85	1			T13	1		T139	1		T204	1
auto[3758096384:3892314111]	auto[1]	8	1			T140	3		T320	1		T319	1
auto[3892314112:4026531839]	auto[0]	90	1			T40	1		T51	1		T210	1
auto[3892314112:4026531839]	auto[1]	13	1			T2	1		T85	1		T152	1
auto[4026531840:4160749567]	auto[0]	81	1			T3	1		T93	1		T112	1
auto[4026531840:4160749567]	auto[1]	5	1			T152	1		T406	2		T419	1
auto[4160749568:4294967295]	auto[0]	95	1			T3	1		T85	2		T29	1
auto[4160749568:4294967295]	auto[1]	6	1			T140	1		T295	1		T414	3