Unified Coverage Report :: Group Instance : sealing_sw_binding_4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1550

1

T2

1

T3

3

T13

4

auto[1]

1836

1

T2

1

T3

1

T13

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	115	1			T17	1		T29	1		T203	1
auto[134217728:268435455]	92	1			T29	1		T48	1		T54	1
auto[268435456:402653183]	110	1			T3	1		T17	1		T4	1
auto[402653184:536870911]	97	1			T40	1		T29	1		T4	1
auto[536870912:671088639]	91	1			T17	1		T29	2		T203	1
auto[671088640:805306367]	94	1			T17	1		T85	1		T29	1
auto[805306368:939524095]	94	1			T15	1		T29	2		T203	1
auto[939524096:1073741823]	114	1			T4	1		T111	1		T112	1
auto[1073741824:1207959551]	109	1			T13	1		T17	1		T29	1
auto[1207959552:1342177279]	102	1			T85	1		T40	1		T4	1
auto[1342177280:1476395007]	84	1			T19	2		T85	1		T29	1
auto[1476395008:1610612735]	101	1			T3	1		T29	2		T51	1
auto[1610612736:1744830463]	101	1			T30	1		T139	1		T56	1
auto[1744830464:1879048191]	110	1			T19	1		T29	1		T4	1
auto[1879048192:2013265919]	100	1			T13	2		T15	1		T28	1
auto[2013265920:2147483647]	110	1			T2	1		T15	1		T54	1
auto[2147483648:2281701375]	99	1			T139	1		T93	1		T71	1
auto[2281701376:2415919103]	111	1			T15	1		T18	1		T29	2
auto[2415919104:2550136831]	101	1			T14	1		T40	1		T29	1
auto[2550136832:2684354559]	104	1			T29	2		T203	1		T210	1
auto[2684354560:2818572287]	122	1			T29	1		T203	1		T56	1
auto[2818572288:2952790015]	133	1			T40	1		T29	2		T30	1
auto[2952790016:3087007743]	109	1			T2	1		T3	1		T18	1
auto[3087007744:3221225471]	115	1			T3	1		T29	3		T55	1
auto[3221225472:3355443199]	115	1			T29	1		T30	1		T114	1
auto[3355443200:3489660927]	109	1			T13	1		T17	1		T29	3
auto[3489660928:3623878655]	93	1			T30	1		T93	1		T49	1
auto[3623878656:3758096383]	109	1			T18	1		T203	1		T207	1
auto[3758096384:3892314111]	114	1			T17	1		T29	1		T208	1
auto[3892314112:4026531839]	127	1			T15	1		T17	1		T29	2
auto[4026531840:4160749567]	110	1			T17	1		T29	1		T4	1
auto[4160749568:4294967295]	91	1			T13	1		T54	1		T56	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T17	1		T203	1		T51	1
auto[0:134217727]	auto[1]	62	1			T29	1		T207	1		T59	1
auto[134217728:268435455]	auto[0]	46	1			T29	1		T6	1		T76	1
auto[134217728:268435455]	auto[1]	46	1			T48	1		T54	1		T49	1
auto[268435456:402653183]	auto[0]	44	1			T3	1		T17	1		T4	1
auto[268435456:402653183]	auto[1]	66	1			T210	1		T197	1		T152	1
auto[402653184:536870911]	auto[0]	53	1			T40	1		T4	1		T152	1
auto[402653184:536870911]	auto[1]	44	1			T29	1		T210	1		T139	1
auto[536870912:671088639]	auto[0]	41	1			T17	1		T29	1		T203	1
auto[536870912:671088639]	auto[1]	50	1			T29	1		T152	1		T49	2
auto[671088640:805306367]	auto[0]	44	1			T4	1		T57	1		T251	1
auto[671088640:805306367]	auto[1]	50	1			T17	1		T85	1		T29	1
auto[805306368:939524095]	auto[0]	39	1			T15	1		T29	1		T338	1
auto[805306368:939524095]	auto[1]	55	1			T29	1		T203	1		T112	1
auto[939524096:1073741823]	auto[0]	59	1			T4	1		T112	1		T220	1
auto[939524096:1073741823]	auto[1]	55	1			T111	1		T209	1		T49	1
auto[1073741824:1207959551]	auto[0]	51	1			T29	1		T203	1		T30	1
auto[1073741824:1207959551]	auto[1]	58	1			T13	1		T17	1		T93	1
auto[1207959552:1342177279]	auto[0]	51	1			T40	1		T4	1		T56	1
auto[1207959552:1342177279]	auto[1]	51	1			T85	1		T111	1		T49	1
auto[1342177280:1476395007]	auto[0]	32	1			T55	1		T113	1		T76	1
auto[1342177280:1476395007]	auto[1]	52	1			T19	2		T85	1		T29	1
auto[1476395008:1610612735]	auto[0]	45	1			T3	1		T51	1		T55	1
auto[1476395008:1610612735]	auto[1]	56	1			T29	2		T101	1		T214	1
auto[1610612736:1744830463]	auto[0]	43	1			T56	1		T71	1		T220	1
auto[1610612736:1744830463]	auto[1]	58	1			T30	1		T139	1		T112	2
auto[1744830464:1879048191]	auto[0]	54	1			T19	1		T29	1		T4	1
auto[1744830464:1879048191]	auto[1]	56	1			T48	1		T111	1		T112	1
auto[1879048192:2013265919]	auto[0]	50	1			T13	2		T15	1		T28	1
auto[1879048192:2013265919]	auto[1]	50	1			T30	1		T204	1		T56	1
auto[2013265920:2147483647]	auto[0]	49	1			T2	1		T15	1		T54	1
auto[2013265920:2147483647]	auto[1]	61	1			T93	1		T197	1		T153	1
auto[2147483648:2281701375]	auto[0]	46	1			T71	1		T57	1		T205	1
auto[2147483648:2281701375]	auto[1]	53	1			T139	1		T93	1		T205	1
auto[2281701376:2415919103]	auto[0]	49	1			T15	1		T29	1		T51	1
auto[2281701376:2415919103]	auto[1]	62	1			T18	1		T29	1		T112	2
auto[2415919104:2550136831]	auto[0]	47	1			T29	1		T112	1		T209	2
auto[2415919104:2550136831]	auto[1]	54	1			T14	1		T40	1		T56	1
auto[2550136832:2684354559]	auto[0]	58	1			T29	2		T203	1		T210	1
auto[2550136832:2684354559]	auto[1]	46	1			T75	1		T50	2		T62	1
auto[2684354560:2818572287]	auto[0]	50	1			T29	1		T56	1		T112	1
auto[2684354560:2818572287]	auto[1]	72	1			T203	1		T111	1		T112	1
auto[2818572288:2952790015]	auto[0]	46	1			T210	1		T197	1		T112	1
auto[2818572288:2952790015]	auto[1]	87	1			T40	1		T29	2		T30	1
auto[2952790016:3087007743]	auto[0]	47	1			T3	1		T203	1		T49	2
auto[2952790016:3087007743]	auto[1]	62	1			T2	1		T18	1		T19	1
auto[3087007744:3221225471]	auto[0]	53	1			T29	3		T55	1		T114	1
auto[3087007744:3221225471]	auto[1]	62	1			T3	1		T114	1		T71	1
auto[3221225472:3355443199]	auto[0]	60	1			T30	1		T114	1		T250	1
auto[3221225472:3355443199]	auto[1]	55	1			T29	1		T214	1		T49	1
auto[3355443200:3489660927]	auto[0]	51	1			T13	1		T17	1		T29	1
auto[3355443200:3489660927]	auto[1]	58	1			T29	2		T250	1		T57	1
auto[3489660928:3623878655]	auto[0]	36	1			T93	1		T49	1		T6	2
auto[3489660928:3623878655]	auto[1]	57	1			T30	1		T220	1		T6	3
auto[3623878656:3758096383]	auto[0]	45	1			T203	1		T6	2		T301	1
auto[3623878656:3758096383]	auto[1]	64	1			T18	1		T207	1		T114	1
auto[3758096384:3892314111]	auto[0]	50	1			T17	1		T111	1		T197	1
auto[3758096384:3892314111]	auto[1]	64	1			T29	1		T208	1		T204	1
auto[3892314112:4026531839]	auto[0]	60	1			T15	1		T17	1		T29	2
auto[3892314112:4026531839]	auto[1]	67	1			T204	1		T55	1		T119	1
auto[4026531840:4160749567]	auto[0]	53	1			T17	1		T29	1		T4	1
auto[4026531840:4160749567]	auto[1]	57	1			T208	1		T55	1		T112	1
auto[4160749568:4294967295]	auto[0]	45	1			T13	1		T54	1		T56	1
auto[4160749568:4294967295]	auto[1]	46	1			T250	1		T49	1		T220	1