SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
97.74 | 99.04 | 98.03 | 98.58 | 100.00 | 99.02 | 98.41 | 91.09 |
T179 | /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.4080925692 | Jul 29 06:20:34 PM PDT 24 | Jul 29 06:20:37 PM PDT 24 | 800293978 ps | ||
T1008 | /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2581620808 | Jul 29 06:20:17 PM PDT 24 | Jul 29 06:20:18 PM PDT 24 | 77693921 ps | ||
T1009 | /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2814617998 | Jul 29 06:20:34 PM PDT 24 | Jul 29 06:20:35 PM PDT 24 | 45021033 ps | ||
T1010 | /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.4046834442 | Jul 29 06:20:37 PM PDT 24 | Jul 29 06:20:50 PM PDT 24 | 2002189681 ps | ||
T1011 | /workspace/coverage/cover_reg_top/45.keymgr_intr_test.18681798 | Jul 29 06:20:33 PM PDT 24 | Jul 29 06:20:34 PM PDT 24 | 10976517 ps | ||
T1012 | /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3024910996 | Jul 29 06:20:15 PM PDT 24 | Jul 29 06:20:16 PM PDT 24 | 32609111 ps | ||
T170 | /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.859666035 | Jul 29 06:20:16 PM PDT 24 | Jul 29 06:20:19 PM PDT 24 | 219135361 ps | ||
T1013 | /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.4138329599 | Jul 29 06:20:14 PM PDT 24 | Jul 29 06:20:18 PM PDT 24 | 130835094 ps | ||
T1014 | /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1408734638 | Jul 29 06:20:30 PM PDT 24 | Jul 29 06:20:31 PM PDT 24 | 37153585 ps | ||
T178 | /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3916145142 | Jul 29 06:20:42 PM PDT 24 | Jul 29 06:20:52 PM PDT 24 | 1184053448 ps | ||
T1015 | /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2291492768 | Jul 29 06:20:41 PM PDT 24 | Jul 29 06:20:41 PM PDT 24 | 9978556 ps | ||
T1016 | /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1185297531 | Jul 29 06:20:15 PM PDT 24 | Jul 29 06:20:16 PM PDT 24 | 57085675 ps | ||
T1017 | /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.4047831784 | Jul 29 06:20:41 PM PDT 24 | Jul 29 06:20:42 PM PDT 24 | 19594278 ps | ||
T1018 | /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3874403724 | Jul 29 06:20:14 PM PDT 24 | Jul 29 06:20:18 PM PDT 24 | 509946796 ps | ||
T1019 | /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2378208128 | Jul 29 06:20:15 PM PDT 24 | Jul 29 06:20:20 PM PDT 24 | 280941783 ps | ||
T1020 | /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1657820591 | Jul 29 06:20:48 PM PDT 24 | Jul 29 06:20:49 PM PDT 24 | 23297402 ps | ||
T1021 | /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3253155345 | Jul 29 06:20:04 PM PDT 24 | Jul 29 06:20:05 PM PDT 24 | 52252728 ps | ||
T1022 | /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2044751352 | Jul 29 06:20:15 PM PDT 24 | Jul 29 06:20:24 PM PDT 24 | 483464225 ps | ||
T1023 | /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.628936721 | Jul 29 06:20:08 PM PDT 24 | Jul 29 06:20:16 PM PDT 24 | 777625774 ps | ||
T1024 | /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3196083306 | Jul 29 06:20:12 PM PDT 24 | Jul 29 06:20:14 PM PDT 24 | 117999660 ps | ||
T1025 | /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1222831841 | Jul 29 06:20:23 PM PDT 24 | Jul 29 06:20:28 PM PDT 24 | 573883655 ps | ||
T1026 | /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1288783641 | Jul 29 06:20:34 PM PDT 24 | Jul 29 06:20:35 PM PDT 24 | 22454045 ps | ||
T1027 | /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1581914487 | Jul 29 06:20:07 PM PDT 24 | Jul 29 06:20:09 PM PDT 24 | 115535523 ps | ||
T1028 | /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2904176946 | Jul 29 06:20:14 PM PDT 24 | Jul 29 06:20:15 PM PDT 24 | 28161973 ps | ||
T1029 | /workspace/coverage/cover_reg_top/3.keymgr_intr_test.105369110 | Jul 29 06:20:12 PM PDT 24 | Jul 29 06:20:13 PM PDT 24 | 27021115 ps | ||
T1030 | /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2090049811 | Jul 29 06:20:40 PM PDT 24 | Jul 29 06:20:48 PM PDT 24 | 2273352806 ps | ||
T1031 | /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3879490556 | Jul 29 06:20:36 PM PDT 24 | Jul 29 06:20:36 PM PDT 24 | 37391904 ps | ||
T1032 | /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3670875140 | Jul 29 06:20:44 PM PDT 24 | Jul 29 06:20:45 PM PDT 24 | 13299227 ps | ||
T1033 | /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3805058333 | Jul 29 06:20:07 PM PDT 24 | Jul 29 06:20:10 PM PDT 24 | 332145756 ps | ||
T1034 | /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3204049047 | Jul 29 06:20:47 PM PDT 24 | Jul 29 06:20:50 PM PDT 24 | 70633311 ps | ||
T1035 | /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3065218714 | Jul 29 06:20:09 PM PDT 24 | Jul 29 06:20:10 PM PDT 24 | 60712054 ps | ||
T1036 | /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2315582827 | Jul 29 06:20:43 PM PDT 24 | Jul 29 06:20:44 PM PDT 24 | 18047679 ps | ||
T1037 | /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1121230944 | Jul 29 06:20:37 PM PDT 24 | Jul 29 06:20:39 PM PDT 24 | 23076387 ps | ||
T1038 | /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2545278032 | Jul 29 06:20:21 PM PDT 24 | Jul 29 06:20:30 PM PDT 24 | 427273420 ps | ||
T177 | /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1774181787 | Jul 29 06:20:15 PM PDT 24 | Jul 29 06:20:21 PM PDT 24 | 142519366 ps | ||
T1039 | /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.273652316 | Jul 29 06:20:51 PM PDT 24 | Jul 29 06:20:53 PM PDT 24 | 16991200 ps | ||
T1040 | /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2368023544 | Jul 29 06:20:42 PM PDT 24 | Jul 29 06:20:46 PM PDT 24 | 185199453 ps | ||
T1041 | /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.378072466 | Jul 29 06:20:06 PM PDT 24 | Jul 29 06:20:08 PM PDT 24 | 34684751 ps | ||
T1042 | /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1831167691 | Jul 29 06:20:48 PM PDT 24 | Jul 29 06:20:49 PM PDT 24 | 11168275 ps | ||
T1043 | /workspace/coverage/cover_reg_top/10.keymgr_intr_test.687875628 | Jul 29 06:20:19 PM PDT 24 | Jul 29 06:20:20 PM PDT 24 | 21034235 ps | ||
T1044 | /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.726057179 | Jul 29 06:20:14 PM PDT 24 | Jul 29 06:20:16 PM PDT 24 | 64933057 ps | ||
T1045 | /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3326388809 | Jul 29 06:20:47 PM PDT 24 | Jul 29 06:20:50 PM PDT 24 | 1435130828 ps | ||
T1046 | /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.747026217 | Jul 29 06:20:18 PM PDT 24 | Jul 29 06:20:19 PM PDT 24 | 82897050 ps | ||
T1047 | /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.4285039586 | Jul 29 06:20:40 PM PDT 24 | Jul 29 06:20:41 PM PDT 24 | 22885095 ps | ||
T171 | /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.796064466 | Jul 29 06:20:05 PM PDT 24 | Jul 29 06:20:11 PM PDT 24 | 401329374 ps | ||
T1048 | /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1843148071 | Jul 29 06:20:32 PM PDT 24 | Jul 29 06:20:41 PM PDT 24 | 393218318 ps | ||
T1049 | /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2996073316 | Jul 29 06:20:39 PM PDT 24 | Jul 29 06:20:49 PM PDT 24 | 443091669 ps | ||
T1050 | /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1257741714 | Jul 29 06:20:16 PM PDT 24 | Jul 29 06:20:19 PM PDT 24 | 86713378 ps | ||
T1051 | /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2303732800 | Jul 29 06:20:37 PM PDT 24 | Jul 29 06:20:39 PM PDT 24 | 183088329 ps | ||
T1052 | /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1657082835 | Jul 29 06:20:12 PM PDT 24 | Jul 29 06:20:13 PM PDT 24 | 10671304 ps | ||
T1053 | /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1854158861 | Jul 29 06:20:26 PM PDT 24 | Jul 29 06:20:29 PM PDT 24 | 135838960 ps | ||
T1054 | /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1558232692 | Jul 29 06:20:37 PM PDT 24 | Jul 29 06:20:38 PM PDT 24 | 42761080 ps | ||
T172 | /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3810951403 | Jul 29 06:20:11 PM PDT 24 | Jul 29 06:20:16 PM PDT 24 | 110482078 ps | ||
T1055 | /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2034707434 | Jul 29 06:20:07 PM PDT 24 | Jul 29 06:20:12 PM PDT 24 | 189618383 ps | ||
T1056 | /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.841895396 | Jul 29 06:20:24 PM PDT 24 | Jul 29 06:20:26 PM PDT 24 | 98682514 ps | ||
T1057 | /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2818317740 | Jul 29 06:20:24 PM PDT 24 | Jul 29 06:20:25 PM PDT 24 | 110006859 ps | ||
T1058 | /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1376760559 | Jul 29 06:20:49 PM PDT 24 | Jul 29 06:20:50 PM PDT 24 | 31925064 ps | ||
T1059 | /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.4218276067 | Jul 29 06:20:25 PM PDT 24 | Jul 29 06:20:33 PM PDT 24 | 309686337 ps | ||
T1060 | /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3938879513 | Jul 29 06:20:20 PM PDT 24 | Jul 29 06:20:21 PM PDT 24 | 30095422 ps | ||
T1061 | /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2205035640 | Jul 29 06:20:14 PM PDT 24 | Jul 29 06:20:15 PM PDT 24 | 20186370 ps | ||
T1062 | /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.4218499138 | Jul 29 06:20:32 PM PDT 24 | Jul 29 06:20:34 PM PDT 24 | 136108676 ps | ||
T1063 | /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.919982145 | Jul 29 06:20:19 PM PDT 24 | Jul 29 06:20:21 PM PDT 24 | 79909749 ps | ||
T1064 | /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3901929935 | Jul 29 06:20:49 PM PDT 24 | Jul 29 06:20:50 PM PDT 24 | 14015406 ps | ||
T1065 | /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1466377530 | Jul 29 06:20:37 PM PDT 24 | Jul 29 06:20:40 PM PDT 24 | 149891841 ps | ||
T1066 | /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2087449184 | Jul 29 06:20:43 PM PDT 24 | Jul 29 06:20:44 PM PDT 24 | 35062546 ps | ||
T1067 | /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2561899855 | Jul 29 06:20:17 PM PDT 24 | Jul 29 06:20:19 PM PDT 24 | 66181955 ps | ||
T1068 | /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3125991965 | Jul 29 06:20:33 PM PDT 24 | Jul 29 06:20:35 PM PDT 24 | 90618988 ps | ||
T1069 | /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1621535529 | Jul 29 06:20:43 PM PDT 24 | Jul 29 06:20:44 PM PDT 24 | 14812262 ps | ||
T1070 | /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3738175794 | Jul 29 06:20:46 PM PDT 24 | Jul 29 06:20:47 PM PDT 24 | 19237663 ps | ||
T1071 | /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2055490898 | Jul 29 06:20:17 PM PDT 24 | Jul 29 06:20:19 PM PDT 24 | 690049048 ps | ||
T1072 | /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2440574561 | Jul 29 06:20:40 PM PDT 24 | Jul 29 06:20:52 PM PDT 24 | 1180312970 ps | ||
T1073 | /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.289901472 | Jul 29 06:20:30 PM PDT 24 | Jul 29 06:20:36 PM PDT 24 | 164372124 ps | ||
T1074 | /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1985033136 | Jul 29 06:20:41 PM PDT 24 | Jul 29 06:20:42 PM PDT 24 | 44590392 ps | ||
T1075 | /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2671168249 | Jul 29 06:20:25 PM PDT 24 | Jul 29 06:20:29 PM PDT 24 | 150326431 ps | ||
T1076 | /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3360755805 | Jul 29 06:20:18 PM PDT 24 | Jul 29 06:20:20 PM PDT 24 | 118856723 ps | ||
T1077 | /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1633328457 | Jul 29 06:20:37 PM PDT 24 | Jul 29 06:20:40 PM PDT 24 | 80732168 ps | ||
T1078 | /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2887074025 | Jul 29 06:20:10 PM PDT 24 | Jul 29 06:20:12 PM PDT 24 | 30682199 ps | ||
T1079 | /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2457035249 | Jul 29 06:20:49 PM PDT 24 | Jul 29 06:20:49 PM PDT 24 | 109676399 ps | ||
T180 | /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2969490307 | Jul 29 06:20:24 PM PDT 24 | Jul 29 06:20:30 PM PDT 24 | 302836626 ps | ||
T1080 | /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.4047144616 | Jul 29 06:20:19 PM PDT 24 | Jul 29 06:20:21 PM PDT 24 | 113566104 ps | ||
T1081 | /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2908733383 | Jul 29 06:20:11 PM PDT 24 | Jul 29 06:20:16 PM PDT 24 | 144244862 ps | ||
T1082 | /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2509993938 | Jul 29 06:20:05 PM PDT 24 | Jul 29 06:20:06 PM PDT 24 | 33384871 ps |
Test location | /workspace/coverage/default/19.keymgr_lc_disable.2789629337 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 383787516 ps |
CPU time | 6.04 seconds |
Started | Jul 29 07:35:11 PM PDT 24 |
Finished | Jul 29 07:35:18 PM PDT 24 |
Peak memory | 210140 kb |
Host | smart-b3428433-881e-4925-9147-5ce93aa0a71b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789629337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2789629337 |
Directory | /workspace/19.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/4.keymgr_stress_all.3599130641 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 1557812030 ps |
CPU time | 36.17 seconds |
Started | Jul 29 07:34:44 PM PDT 24 |
Finished | Jul 29 07:35:20 PM PDT 24 |
Peak memory | 220620 kb |
Host | smart-f89c837e-f84c-41bb-a197-e8694f57b957 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599130641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3599130641 |
Directory | /workspace/4.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/31.keymgr_stress_all.1422658802 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 3688096543 ps |
CPU time | 50.86 seconds |
Started | Jul 29 07:35:58 PM PDT 24 |
Finished | Jul 29 07:36:49 PM PDT 24 |
Peak memory | 222500 kb |
Host | smart-98275341-6f14-4a08-9eca-6693016ef674 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422658802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1422658802 |
Directory | /workspace/31.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/0.keymgr_sec_cm.1559555744 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 1428829382 ps |
CPU time | 12.33 seconds |
Started | Jul 29 07:34:39 PM PDT 24 |
Finished | Jul 29 07:34:51 PM PDT 24 |
Peak memory | 238212 kb |
Host | smart-af6741cd-2247-44a0-8e9a-1929928637e6 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559555744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1559555744 |
Directory | /workspace/0.keymgr_sec_cm/latest |
Test location | /workspace/coverage/default/36.keymgr_stress_all.3326331769 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 24949757425 ps |
CPU time | 66.11 seconds |
Started | Jul 29 07:36:08 PM PDT 24 |
Finished | Jul 29 07:37:14 PM PDT 24 |
Peak memory | 215976 kb |
Host | smart-abf05b78-7223-453d-9af7-3e9c136b218c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326331769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3326331769 |
Directory | /workspace/36.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.1989539525 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 1246289845 ps |
CPU time | 24.42 seconds |
Started | Jul 29 07:35:03 PM PDT 24 |
Finished | Jul 29 07:35:28 PM PDT 24 |
Peak memory | 222572 kb |
Host | smart-16781f6b-2b4b-4c00-8337-b11ef0f7d1b8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989539525 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.1989539525 |
Directory | /workspace/12.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/31.keymgr_cfg_regwen.4163654217 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 107307275 ps |
CPU time | 3.77 seconds |
Started | Jul 29 07:35:51 PM PDT 24 |
Finished | Jul 29 07:35:55 PM PDT 24 |
Peak memory | 214300 kb |
Host | smart-243d80bc-3277-401f-8740-060349dccf63 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4163654217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.4163654217 |
Directory | /workspace/31.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/10.keymgr_stress_all.488133512 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 34739004876 ps |
CPU time | 199.01 seconds |
Started | Jul 29 07:35:03 PM PDT 24 |
Finished | Jul 29 07:38:22 PM PDT 24 |
Peak memory | 218932 kb |
Host | smart-0486ea23-0c6e-4f99-9e9e-73d04fe6c001 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488133512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.488133512 |
Directory | /workspace/10.keymgr_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2854413986 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 344949229 ps |
CPU time | 12.81 seconds |
Started | Jul 29 06:20:13 PM PDT 24 |
Finished | Jul 29 06:20:26 PM PDT 24 |
Peak memory | 214556 kb |
Host | smart-56dab2a3-8ce3-40f9-930b-1019fe1a78ab |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854413986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. keymgr_shadow_reg_errors_with_csr_rw.2854413986 |
Directory | /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/default/32.keymgr_cfg_regwen.2255814023 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 4047963273 ps |
CPU time | 51.04 seconds |
Started | Jul 29 07:35:59 PM PDT 24 |
Finished | Jul 29 07:36:51 PM PDT 24 |
Peak memory | 216088 kb |
Host | smart-a1b5fe56-a164-4039-9b96-cf4745463bac |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2255814023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2255814023 |
Directory | /workspace/32.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/14.keymgr_custom_cm.3027390963 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 225265645 ps |
CPU time | 2.35 seconds |
Started | Jul 29 07:35:04 PM PDT 24 |
Finished | Jul 29 07:35:06 PM PDT 24 |
Peak memory | 218820 kb |
Host | smart-939374df-b7fe-44e3-8f34-2982c16e45d5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3027390963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3027390963 |
Directory | /workspace/14.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/11.keymgr_cfg_regwen.2668146614 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 541478620 ps |
CPU time | 15.23 seconds |
Started | Jul 29 07:35:03 PM PDT 24 |
Finished | Jul 29 07:35:18 PM PDT 24 |
Peak memory | 215036 kb |
Host | smart-851a202b-c529-44d5-a56f-38c3c6a6675f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2668146614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2668146614 |
Directory | /workspace/11.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.4075794547 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 1415849519 ps |
CPU time | 9.77 seconds |
Started | Jul 29 07:34:55 PM PDT 24 |
Finished | Jul 29 07:35:05 PM PDT 24 |
Peak memory | 222460 kb |
Host | smart-10ae6254-d9b0-43e9-9a95-cfd0df4e9b1e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075794547 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.4075794547 |
Directory | /workspace/5.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/25.keymgr_stress_all.4171233173 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 3179814706 ps |
CPU time | 34.47 seconds |
Started | Jul 29 07:35:53 PM PDT 24 |
Finished | Jul 29 07:36:28 PM PDT 24 |
Peak memory | 222516 kb |
Host | smart-015e6b68-8440-4182-aed4-caee4523ed53 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171233173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.4171233173 |
Directory | /workspace/25.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/1.keymgr_cfg_regwen.3935201685 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 237706593 ps |
CPU time | 13.3 seconds |
Started | Jul 29 07:34:36 PM PDT 24 |
Finished | Jul 29 07:34:49 PM PDT 24 |
Peak memory | 215460 kb |
Host | smart-ec86001d-8f8c-40c6-9906-2d5ef7a76512 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3935201685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3935201685 |
Directory | /workspace/1.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/17.keymgr_custom_cm.2902508692 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 174086586 ps |
CPU time | 4.03 seconds |
Started | Jul 29 07:35:20 PM PDT 24 |
Finished | Jul 29 07:35:25 PM PDT 24 |
Peak memory | 210548 kb |
Host | smart-fce38c68-aa62-4eba-8443-65958d45808f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2902508692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2902508692 |
Directory | /workspace/17.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3473540159 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 798611537 ps |
CPU time | 3.09 seconds |
Started | Jul 29 07:35:58 PM PDT 24 |
Finished | Jul 29 07:36:02 PM PDT 24 |
Peak memory | 208636 kb |
Host | smart-88575b6d-d18c-4a0b-95da-7407c1437279 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3473540159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3473540159 |
Directory | /workspace/36.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.1326439360 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 4864772527 ps |
CPU time | 20.17 seconds |
Started | Jul 29 07:34:56 PM PDT 24 |
Finished | Jul 29 07:35:17 PM PDT 24 |
Peak memory | 222584 kb |
Host | smart-45303869-07be-454e-a848-f5d168cbbeaa |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326439360 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.1326439360 |
Directory | /workspace/8.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/42.keymgr_stress_all.3325945621 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 3005484965 ps |
CPU time | 37.9 seconds |
Started | Jul 29 07:36:41 PM PDT 24 |
Finished | Jul 29 07:37:19 PM PDT 24 |
Peak memory | 222540 kb |
Host | smart-81574725-59c9-4052-af13-0baaf9d08dfc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325945621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3325945621 |
Directory | /workspace/42.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/43.keymgr_cfg_regwen.3422970185 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 164203786 ps |
CPU time | 6.53 seconds |
Started | Jul 29 07:36:19 PM PDT 24 |
Finished | Jul 29 07:36:25 PM PDT 24 |
Peak memory | 222392 kb |
Host | smart-595cc41d-6c58-4258-99fc-e36f2f8f4cde |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3422970185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3422970185 |
Directory | /workspace/43.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3117433617 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 1652731454 ps |
CPU time | 14.55 seconds |
Started | Jul 29 07:34:56 PM PDT 24 |
Finished | Jul 29 07:35:10 PM PDT 24 |
Peak memory | 210988 kb |
Host | smart-2605907d-301c-4da1-b446-450d23479464 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3117433617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3117433617 |
Directory | /workspace/7.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/23.keymgr_cfg_regwen.3641452372 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 16905042654 ps |
CPU time | 89.2 seconds |
Started | Jul 29 07:35:37 PM PDT 24 |
Finished | Jul 29 07:37:07 PM PDT 24 |
Peak memory | 219968 kb |
Host | smart-3fddd4e4-7c6c-4464-ad04-3a37a58623b8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3641452372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3641452372 |
Directory | /workspace/23.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/39.keymgr_stress_all.720160943 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 10234080921 ps |
CPU time | 34.75 seconds |
Started | Jul 29 07:36:18 PM PDT 24 |
Finished | Jul 29 07:36:53 PM PDT 24 |
Peak memory | 216800 kb |
Host | smart-038deb9a-c283-4d27-94c2-ca71047143fa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720160943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.720160943 |
Directory | /workspace/39.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3125786685 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 135222266 ps |
CPU time | 3.83 seconds |
Started | Jul 29 07:36:34 PM PDT 24 |
Finished | Jul 29 07:36:38 PM PDT 24 |
Peak memory | 214828 kb |
Host | smart-698abc28-b39d-4474-a715-e5b13e5430af |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3125786685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3125786685 |
Directory | /workspace/43.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/2.keymgr_custom_cm.1648760600 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 167657987 ps |
CPU time | 2.22 seconds |
Started | Jul 29 07:34:35 PM PDT 24 |
Finished | Jul 29 07:34:37 PM PDT 24 |
Peak memory | 209096 kb |
Host | smart-3eed1d48-3ab6-42d9-81b4-be55077247ce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1648760600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1648760600 |
Directory | /workspace/2.keymgr_custom_cm/latest |
Test location | /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1835593167 |
Short name | T938 |
Test name | |
Test status | |
Simulation time | 85796661 ps |
CPU time | 2.87 seconds |
Started | Jul 29 06:20:20 PM PDT 24 |
Finished | Jul 29 06:20:23 PM PDT 24 |
Peak memory | 214732 kb |
Host | smart-6fee9c8b-46da-4a3e-be0b-3cc5e0d66484 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835593167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado w_reg_errors.1835593167 |
Directory | /workspace/5.keymgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/default/3.keymgr_cfg_regwen.1823888834 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 463261358 ps |
CPU time | 4.51 seconds |
Started | Jul 29 07:34:40 PM PDT 24 |
Finished | Jul 29 07:34:45 PM PDT 24 |
Peak memory | 214356 kb |
Host | smart-322cd479-91cc-4834-8207-20a0ca2b791f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1823888834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1823888834 |
Directory | /workspace/3.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/45.keymgr_custom_cm.2306141715 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 69091827 ps |
CPU time | 2.96 seconds |
Started | Jul 29 07:36:42 PM PDT 24 |
Finished | Jul 29 07:36:45 PM PDT 24 |
Peak memory | 209380 kb |
Host | smart-cf32d842-27ff-4398-a8fc-5f418069fcc7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2306141715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2306141715 |
Directory | /workspace/45.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/5.keymgr_cfg_regwen.2947364479 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 85306076 ps |
CPU time | 5.14 seconds |
Started | Jul 29 07:34:43 PM PDT 24 |
Finished | Jul 29 07:34:48 PM PDT 24 |
Peak memory | 215804 kb |
Host | smart-d9671978-e5a4-42d6-90ec-eda1c6707698 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2947364479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2947364479 |
Directory | /workspace/5.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/12.keymgr_custom_cm.3407126094 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 725625801 ps |
CPU time | 3.5 seconds |
Started | Jul 29 07:35:05 PM PDT 24 |
Finished | Jul 29 07:35:09 PM PDT 24 |
Peak memory | 217304 kb |
Host | smart-d73cb3d0-6df1-4c7d-92ca-f4ea56f1be78 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3407126094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3407126094 |
Directory | /workspace/12.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/32.keymgr_hwsw_invalid_input.435206347 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 172999255 ps |
CPU time | 5.14 seconds |
Started | Jul 29 07:36:04 PM PDT 24 |
Finished | Jul 29 07:36:09 PM PDT 24 |
Peak memory | 220844 kb |
Host | smart-d3a0d21a-b0cb-46e7-9c09-72856154c779 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=435206347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.435206347 |
Directory | /workspace/32.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/23.keymgr_custom_cm.2026873804 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 48430575 ps |
CPU time | 2.53 seconds |
Started | Jul 29 07:35:37 PM PDT 24 |
Finished | Jul 29 07:35:40 PM PDT 24 |
Peak memory | 208612 kb |
Host | smart-d4c2da88-360c-4bb8-a21b-46062d3f0e8c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2026873804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2026873804 |
Directory | /workspace/23.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/15.keymgr_cfg_regwen.639212753 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 1311566564 ps |
CPU time | 68.67 seconds |
Started | Jul 29 07:35:11 PM PDT 24 |
Finished | Jul 29 07:36:20 PM PDT 24 |
Peak memory | 214260 kb |
Host | smart-39b802dd-a76a-4071-9b6e-9dda5442ac4a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=639212753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.639212753 |
Directory | /workspace/15.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/20.keymgr_stress_all.831134123 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 11738368768 ps |
CPU time | 28.99 seconds |
Started | Jul 29 07:35:23 PM PDT 24 |
Finished | Jul 29 07:35:52 PM PDT 24 |
Peak memory | 222548 kb |
Host | smart-8874ca8c-a302-4068-beb9-d184e6cab0cf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831134123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.831134123 |
Directory | /workspace/20.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/11.keymgr_alert_test.2700238123 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 22296250 ps |
CPU time | 0.82 seconds |
Started | Jul 29 07:35:03 PM PDT 24 |
Finished | Jul 29 07:35:04 PM PDT 24 |
Peak memory | 205964 kb |
Host | smart-d1099209-f35a-449e-b739-22ce0daa5129 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700238123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2700238123 |
Directory | /workspace/11.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/31.keymgr_kmac_rsp_err.1132883038 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 177256849 ps |
CPU time | 5.08 seconds |
Started | Jul 29 07:36:00 PM PDT 24 |
Finished | Jul 29 07:36:05 PM PDT 24 |
Peak memory | 214380 kb |
Host | smart-3f04a0be-9294-4263-883e-efa1f6c811ab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1132883038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1132883038 |
Directory | /workspace/31.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/1.keymgr_stress_all.3136728086 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 1807110394 ps |
CPU time | 36.08 seconds |
Started | Jul 29 07:34:37 PM PDT 24 |
Finished | Jul 29 07:35:14 PM PDT 24 |
Peak memory | 222456 kb |
Host | smart-855eb890-a751-43d9-8a22-a2d18825df15 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136728086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3136728086 |
Directory | /workspace/1.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/28.keymgr_cfg_regwen.1770136557 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 13937831737 ps |
CPU time | 124.67 seconds |
Started | Jul 29 07:35:46 PM PDT 24 |
Finished | Jul 29 07:37:51 PM PDT 24 |
Peak memory | 220060 kb |
Host | smart-7a6b1535-c76c-4c63-9090-8e5c5d90a04e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1770136557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1770136557 |
Directory | /workspace/28.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/7.keymgr_cfg_regwen.2390772038 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 65353546 ps |
CPU time | 4.32 seconds |
Started | Jul 29 07:34:57 PM PDT 24 |
Finished | Jul 29 07:35:01 PM PDT 24 |
Peak memory | 215296 kb |
Host | smart-5c212a47-190b-43f5-af71-a0e8c82002e5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2390772038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2390772038 |
Directory | /workspace/7.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/7.keymgr_sideload_otbn.2512333648 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 87466732 ps |
CPU time | 3.34 seconds |
Started | Jul 29 07:34:57 PM PDT 24 |
Finished | Jul 29 07:35:01 PM PDT 24 |
Peak memory | 208512 kb |
Host | smart-72b467a7-010f-445a-82dc-31014fcf17d0 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512333648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2512333648 |
Directory | /workspace/7.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.4080925692 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 800293978 ps |
CPU time | 2.52 seconds |
Started | Jul 29 06:20:34 PM PDT 24 |
Finished | Jul 29 06:20:37 PM PDT 24 |
Peak memory | 206076 kb |
Host | smart-f7783e49-0c71-4437-be14-2cba9e18fb91 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080925692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er r.4080925692 |
Directory | /workspace/16.keymgr_tl_intg_err/latest |
Test location | /workspace/coverage/default/28.keymgr_sync_async_fault_cross.4128441552 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 47139953 ps |
CPU time | 2.46 seconds |
Started | Jul 29 07:35:58 PM PDT 24 |
Finished | Jul 29 07:36:01 PM PDT 24 |
Peak memory | 210060 kb |
Host | smart-53fcec80-c391-41e2-9f7d-69854420caaf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4128441552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.4128441552 |
Directory | /workspace/28.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/38.keymgr_hwsw_invalid_input.801776966 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 137914815 ps |
CPU time | 5.52 seconds |
Started | Jul 29 07:36:05 PM PDT 24 |
Finished | Jul 29 07:36:11 PM PDT 24 |
Peak memory | 215488 kb |
Host | smart-0d48b0db-d43f-45b6-8e9d-6e87ccf1311e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=801776966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.801776966 |
Directory | /workspace/38.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1652865295 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 1049401891 ps |
CPU time | 9.29 seconds |
Started | Jul 29 06:20:48 PM PDT 24 |
Finished | Jul 29 06:20:58 PM PDT 24 |
Peak memory | 214216 kb |
Host | smart-8457bcfb-bcb7-475b-acde-020aafb94497 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652865295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er r.1652865295 |
Directory | /workspace/17.keymgr_tl_intg_err/latest |
Test location | /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3476497546 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 48433362 ps |
CPU time | 2.26 seconds |
Started | Jul 29 07:34:46 PM PDT 24 |
Finished | Jul 29 07:34:48 PM PDT 24 |
Peak memory | 214588 kb |
Host | smart-0bc09ee4-f3c0-42b0-8699-f3c9a771b797 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3476497546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3476497546 |
Directory | /workspace/5.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/3.keymgr_custom_cm.869432654 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 116994151 ps |
CPU time | 2.88 seconds |
Started | Jul 29 07:34:41 PM PDT 24 |
Finished | Jul 29 07:34:44 PM PDT 24 |
Peak memory | 222724 kb |
Host | smart-1986cf29-3b82-4ad2-b69f-abddf2f6ed48 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=869432654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.869432654 |
Directory | /workspace/3.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/4.keymgr_kmac_rsp_err.727999777 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 158175646 ps |
CPU time | 3.15 seconds |
Started | Jul 29 07:34:43 PM PDT 24 |
Finished | Jul 29 07:34:47 PM PDT 24 |
Peak memory | 214248 kb |
Host | smart-b72004df-1ab0-4a5a-9917-fc3832a4b059 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=727999777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.727999777 |
Directory | /workspace/4.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/44.keymgr_custom_cm.3744834773 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 121370927 ps |
CPU time | 4.48 seconds |
Started | Jul 29 07:36:33 PM PDT 24 |
Finished | Jul 29 07:36:37 PM PDT 24 |
Peak memory | 217604 kb |
Host | smart-292ab2b5-c42b-4b21-8417-e1cc58566e81 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3744834773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3744834773 |
Directory | /workspace/44.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/14.keymgr_stress_all.3603806097 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 10787548736 ps |
CPU time | 54.58 seconds |
Started | Jul 29 07:35:15 PM PDT 24 |
Finished | Jul 29 07:36:10 PM PDT 24 |
Peak memory | 222468 kb |
Host | smart-6f31c957-e606-4be8-9ee0-55e533ad6230 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603806097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3603806097 |
Directory | /workspace/14.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/21.keymgr_cfg_regwen.531833940 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 1534102376 ps |
CPU time | 7.92 seconds |
Started | Jul 29 07:35:34 PM PDT 24 |
Finished | Jul 29 07:35:42 PM PDT 24 |
Peak memory | 214468 kb |
Host | smart-71eb2f36-c347-4f63-b822-dff0ce68c3d7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=531833940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.531833940 |
Directory | /workspace/21.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/40.keymgr_stress_all.4162150006 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 4182899706 ps |
CPU time | 65.8 seconds |
Started | Jul 29 07:36:13 PM PDT 24 |
Finished | Jul 29 07:37:19 PM PDT 24 |
Peak memory | 217112 kb |
Host | smart-6b64aa35-c587-4b98-a878-6557f27d5d93 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162150006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.4162150006 |
Directory | /workspace/40.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/49.keymgr_cfg_regwen.1715603523 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 66221706 ps |
CPU time | 4.09 seconds |
Started | Jul 29 07:37:01 PM PDT 24 |
Finished | Jul 29 07:37:05 PM PDT 24 |
Peak memory | 214284 kb |
Host | smart-b179475c-7711-4a03-9c91-dafc6d710980 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1715603523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1715603523 |
Directory | /workspace/49.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1731018358 |
Short name | T949 |
Test name | |
Test status | |
Simulation time | 186229705 ps |
CPU time | 1.78 seconds |
Started | Jul 29 06:20:26 PM PDT 24 |
Finished | Jul 29 06:20:33 PM PDT 24 |
Peak memory | 214780 kb |
Host | smart-0a31358f-2dd6-49b1-bf48-23101e044234 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731018358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad ow_reg_errors.1731018358 |
Directory | /workspace/11.keymgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2969490307 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 302836626 ps |
CPU time | 5.87 seconds |
Started | Jul 29 06:20:24 PM PDT 24 |
Finished | Jul 29 06:20:30 PM PDT 24 |
Peak memory | 214404 kb |
Host | smart-8c18df8c-4366-4f52-97ef-2b7821e694c8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969490307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er r.2969490307 |
Directory | /workspace/11.keymgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1373764913 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 98892822 ps |
CPU time | 5.02 seconds |
Started | Jul 29 06:20:27 PM PDT 24 |
Finished | Jul 29 06:20:32 PM PDT 24 |
Peak memory | 214436 kb |
Host | smart-6ff79c42-601c-4630-8e61-22a210ef0444 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373764913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er r.1373764913 |
Directory | /workspace/13.keymgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3916145142 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 1184053448 ps |
CPU time | 9.98 seconds |
Started | Jul 29 06:20:42 PM PDT 24 |
Finished | Jul 29 06:20:52 PM PDT 24 |
Peak memory | 214348 kb |
Host | smart-29eeca76-5286-4d7c-b017-18cc0dde9bb9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916145142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er r.3916145142 |
Directory | /workspace/19.keymgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3810951403 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 110482078 ps |
CPU time | 4.74 seconds |
Started | Jul 29 06:20:11 PM PDT 24 |
Finished | Jul 29 06:20:16 PM PDT 24 |
Peak memory | 214304 kb |
Host | smart-9259cac4-d40b-4194-b0dc-74f48c122fa2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810951403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err .3810951403 |
Directory | /workspace/2.keymgr_tl_intg_err/latest |
Test location | /workspace/coverage/default/1.keymgr_custom_cm.2159963293 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 172142470 ps |
CPU time | 2.75 seconds |
Started | Jul 29 07:34:35 PM PDT 24 |
Finished | Jul 29 07:34:38 PM PDT 24 |
Peak memory | 217368 kb |
Host | smart-fe78679c-efb0-4ed0-b4df-8ddd55643e61 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2159963293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2159963293 |
Directory | /workspace/1.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/5.keymgr_custom_cm.2657174075 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 674135442 ps |
CPU time | 5.67 seconds |
Started | Jul 29 07:34:55 PM PDT 24 |
Finished | Jul 29 07:35:01 PM PDT 24 |
Peak memory | 218140 kb |
Host | smart-e056024f-7731-4349-a683-2e520cbef89b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2657174075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2657174075 |
Directory | /workspace/5.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3425032996 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 31790868108 ps |
CPU time | 88.69 seconds |
Started | Jul 29 07:34:38 PM PDT 24 |
Finished | Jul 29 07:36:07 PM PDT 24 |
Peak memory | 214400 kb |
Host | smart-2d6eaa1a-6e13-43bc-ac54-56f9439359ec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3425032996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3425032996 |
Directory | /workspace/0.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/12.keymgr_hwsw_invalid_input.509788297 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 152337703 ps |
CPU time | 5.41 seconds |
Started | Jul 29 07:35:00 PM PDT 24 |
Finished | Jul 29 07:35:05 PM PDT 24 |
Peak memory | 214288 kb |
Host | smart-6c2911b0-30d8-42dc-9faf-efbc13c7e8ee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=509788297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.509788297 |
Directory | /workspace/12.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/28.keymgr_stress_all.3870307576 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 2450411230 ps |
CPU time | 37.07 seconds |
Started | Jul 29 07:35:56 PM PDT 24 |
Finished | Jul 29 07:36:33 PM PDT 24 |
Peak memory | 222636 kb |
Host | smart-e5d59843-8292-4dda-968f-c07aedec6eef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870307576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3870307576 |
Directory | /workspace/28.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/40.keymgr_kmac_rsp_err.2437102260 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 231661444 ps |
CPU time | 2.7 seconds |
Started | Jul 29 07:36:17 PM PDT 24 |
Finished | Jul 29 07:36:20 PM PDT 24 |
Peak memory | 214176 kb |
Host | smart-1d4fb482-4045-43b6-934b-dd363247fe62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2437102260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2437102260 |
Directory | /workspace/40.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2705743915 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 39511193 ps |
CPU time | 1.82 seconds |
Started | Jul 29 07:35:01 PM PDT 24 |
Finished | Jul 29 07:35:03 PM PDT 24 |
Peak memory | 209972 kb |
Host | smart-eecf8f48-b603-4908-92bb-9229250d54e4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2705743915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2705743915 |
Directory | /workspace/10.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2624940334 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 241424916 ps |
CPU time | 2.93 seconds |
Started | Jul 29 07:35:37 PM PDT 24 |
Finished | Jul 29 07:35:40 PM PDT 24 |
Peak memory | 209896 kb |
Host | smart-e5ed6453-829c-41d6-a5bb-00adfab9039d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2624940334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2624940334 |
Directory | /workspace/25.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.440691700 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 2777743579 ps |
CPU time | 22.89 seconds |
Started | Jul 29 07:35:54 PM PDT 24 |
Finished | Jul 29 07:36:17 PM PDT 24 |
Peak memory | 222600 kb |
Host | smart-81277eeb-a26a-4576-8679-5bc3c8df013e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440691700 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.440691700 |
Directory | /workspace/28.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/21.keymgr_custom_cm.918116752 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 7264369648 ps |
CPU time | 51.63 seconds |
Started | Jul 29 07:35:20 PM PDT 24 |
Finished | Jul 29 07:36:12 PM PDT 24 |
Peak memory | 221476 kb |
Host | smart-dfb12316-3e97-49eb-a395-396558fc14ec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=918116752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.918116752 |
Directory | /workspace/21.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/34.keymgr_custom_cm.4213309464 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 404691870 ps |
CPU time | 5.65 seconds |
Started | Jul 29 07:36:01 PM PDT 24 |
Finished | Jul 29 07:36:06 PM PDT 24 |
Peak memory | 222652 kb |
Host | smart-fbbe4dee-aa4b-4e81-92d0-5a90bd1e0f4c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4213309464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.4213309464 |
Directory | /workspace/34.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/4.keymgr_custom_cm.1255621906 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 89073895 ps |
CPU time | 3.83 seconds |
Started | Jul 29 07:34:47 PM PDT 24 |
Finished | Jul 29 07:34:51 PM PDT 24 |
Peak memory | 218160 kb |
Host | smart-cf6e57c3-ba77-4d4d-9446-8c3206df1d66 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1255621906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1255621906 |
Directory | /workspace/4.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/1.keymgr_direct_to_disabled.2768857597 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 145450867 ps |
CPU time | 2.39 seconds |
Started | Jul 29 07:34:39 PM PDT 24 |
Finished | Jul 29 07:34:41 PM PDT 24 |
Peak memory | 207892 kb |
Host | smart-a7dabb10-1739-40c5-953f-b4bb117d6c15 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2768857597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2768857597 |
Directory | /workspace/1.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/1.keymgr_sideload_aes.2605356891 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 153443360 ps |
CPU time | 4.83 seconds |
Started | Jul 29 07:34:39 PM PDT 24 |
Finished | Jul 29 07:34:44 PM PDT 24 |
Peak memory | 208640 kb |
Host | smart-bc514e0d-2ea8-4b38-98da-b2e5242730d1 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605356891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2605356891 |
Directory | /workspace/1.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/11.keymgr_kmac_rsp_err.1672687734 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 59747683 ps |
CPU time | 2.21 seconds |
Started | Jul 29 07:35:07 PM PDT 24 |
Finished | Jul 29 07:35:09 PM PDT 24 |
Peak memory | 214276 kb |
Host | smart-9df47a5d-ad5f-4309-ae10-81ce358dc7e8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1672687734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1672687734 |
Directory | /workspace/11.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/17.keymgr_cfg_regwen.1951440037 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 115602217 ps |
CPU time | 2.7 seconds |
Started | Jul 29 07:35:13 PM PDT 24 |
Finished | Jul 29 07:35:16 PM PDT 24 |
Peak memory | 215232 kb |
Host | smart-e405d0a8-db3f-4ee7-a845-a52f452e1e19 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1951440037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1951440037 |
Directory | /workspace/17.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2826569028 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 130814202 ps |
CPU time | 3.59 seconds |
Started | Jul 29 07:35:15 PM PDT 24 |
Finished | Jul 29 07:35:19 PM PDT 24 |
Peak memory | 215152 kb |
Host | smart-6a289447-5ecf-4c66-a932-e2b0ad1bee6d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2826569028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2826569028 |
Directory | /workspace/17.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/2.keymgr_stress_all.3132474871 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 1769136135 ps |
CPU time | 58.28 seconds |
Started | Jul 29 07:34:36 PM PDT 24 |
Finished | Jul 29 07:35:35 PM PDT 24 |
Peak memory | 220468 kb |
Host | smart-c34fad32-3194-4411-8256-45a8e10bf2f1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132474871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3132474871 |
Directory | /workspace/2.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/34.keymgr_cfg_regwen.572867215 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 47703100 ps |
CPU time | 3.45 seconds |
Started | Jul 29 07:36:02 PM PDT 24 |
Finished | Jul 29 07:36:06 PM PDT 24 |
Peak memory | 214136 kb |
Host | smart-289d5e5f-99e8-4089-80a0-001bba49f0a2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=572867215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.572867215 |
Directory | /workspace/34.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/41.keymgr_hwsw_invalid_input.680928530 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 231924163 ps |
CPU time | 2.35 seconds |
Started | Jul 29 07:36:10 PM PDT 24 |
Finished | Jul 29 07:36:12 PM PDT 24 |
Peak memory | 209764 kb |
Host | smart-5b8ce05f-de66-49e6-84ee-25a8b6c34e9c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=680928530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.680928530 |
Directory | /workspace/41.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/5.keymgr_kmac_rsp_err.1803666428 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 144275975 ps |
CPU time | 1.96 seconds |
Started | Jul 29 07:34:45 PM PDT 24 |
Finished | Jul 29 07:34:47 PM PDT 24 |
Peak memory | 214348 kb |
Host | smart-6de8ec22-2b5e-44a2-8115-a61eae3c0738 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1803666428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1803666428 |
Directory | /workspace/5.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/6.keymgr_stress_all.2260268176 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 4808659534 ps |
CPU time | 45.67 seconds |
Started | Jul 29 07:34:55 PM PDT 24 |
Finished | Jul 29 07:35:41 PM PDT 24 |
Peak memory | 222608 kb |
Host | smart-8a2a54f5-1186-4f60-afb5-9d88b3f43bde |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260268176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2260268176 |
Directory | /workspace/6.keymgr_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2321179098 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 240293479 ps |
CPU time | 7.56 seconds |
Started | Jul 29 06:20:39 PM PDT 24 |
Finished | Jul 29 06:20:47 PM PDT 24 |
Peak memory | 215764 kb |
Host | smart-8c331646-e3f2-4f31-a5f9-a906fbe4964d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321179098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er r.2321179098 |
Directory | /workspace/18.keymgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1774181787 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 142519366 ps |
CPU time | 5.89 seconds |
Started | Jul 29 06:20:15 PM PDT 24 |
Finished | Jul 29 06:20:21 PM PDT 24 |
Peak memory | 214396 kb |
Host | smart-bc75799f-f63b-40ce-bf49-4e0c5342a12b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774181787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err .1774181787 |
Directory | /workspace/4.keymgr_tl_intg_err/latest |
Test location | /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2305995443 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 88298067 ps |
CPU time | 4.2 seconds |
Started | Jul 29 07:35:04 PM PDT 24 |
Finished | Jul 29 07:35:08 PM PDT 24 |
Peak memory | 209804 kb |
Host | smart-30bdd19f-5558-4a05-ac02-40b5ef575dcd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2305995443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2305995443 |
Directory | /workspace/10.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2933883940 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 183801745 ps |
CPU time | 4.87 seconds |
Started | Jul 29 07:36:13 PM PDT 24 |
Finished | Jul 29 07:36:18 PM PDT 24 |
Peak memory | 210100 kb |
Host | smart-eeb062d8-83de-4d35-97ec-8d9c901011b5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2933883940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2933883940 |
Directory | /workspace/38.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/32.keymgr_custom_cm.2396223323 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 338876021 ps |
CPU time | 3.72 seconds |
Started | Jul 29 07:35:59 PM PDT 24 |
Finished | Jul 29 07:36:03 PM PDT 24 |
Peak memory | 222776 kb |
Host | smart-15e3077c-4822-471a-9643-5af717332df4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2396223323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2396223323 |
Directory | /workspace/32.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/39.keymgr_custom_cm.4043539243 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 334876905 ps |
CPU time | 3.6 seconds |
Started | Jul 29 07:36:23 PM PDT 24 |
Finished | Jul 29 07:36:26 PM PDT 24 |
Peak memory | 222616 kb |
Host | smart-4111a5f3-1d5a-4d6a-99d8-e31941069211 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4043539243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.4043539243 |
Directory | /workspace/39.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/0.keymgr_kmac_rsp_err.2860496507 |
Short name | T898 |
Test name | |
Test status | |
Simulation time | 55696389 ps |
CPU time | 2.24 seconds |
Started | Jul 29 07:34:37 PM PDT 24 |
Finished | Jul 29 07:34:39 PM PDT 24 |
Peak memory | 206060 kb |
Host | smart-c1e4f182-8cb4-472f-9c84-25951af4a3d4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2860496507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2860496507 |
Directory | /workspace/0.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/0.keymgr_lc_disable.4209588526 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 86215147 ps |
CPU time | 2.89 seconds |
Started | Jul 29 07:34:35 PM PDT 24 |
Finished | Jul 29 07:34:38 PM PDT 24 |
Peak memory | 208504 kb |
Host | smart-7d3aa051-caf4-4d23-b04c-328d23a4916a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4209588526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.4209588526 |
Directory | /workspace/0.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/0.keymgr_sideload_aes.3910622732 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 851039787 ps |
CPU time | 5.97 seconds |
Started | Jul 29 07:34:34 PM PDT 24 |
Finished | Jul 29 07:34:40 PM PDT 24 |
Peak memory | 208164 kb |
Host | smart-319644ca-35fa-4751-af68-93ab1a3210d5 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910622732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3910622732 |
Directory | /workspace/0.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3375279676 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 103695913 ps |
CPU time | 3.41 seconds |
Started | Jul 29 07:34:36 PM PDT 24 |
Finished | Jul 29 07:34:40 PM PDT 24 |
Peak memory | 214324 kb |
Host | smart-d8920694-9822-4a35-938f-86b64d836b64 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3375279676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3375279676 |
Directory | /workspace/1.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/12.keymgr_stress_all.757424813 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 240923355 ps |
CPU time | 9.6 seconds |
Started | Jul 29 07:35:02 PM PDT 24 |
Finished | Jul 29 07:35:11 PM PDT 24 |
Peak memory | 222232 kb |
Host | smart-d9909ad7-bfec-43f8-84a9-2c4441eb80aa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757424813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.757424813 |
Directory | /workspace/12.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/17.keymgr_lc_disable.1757458104 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 73692159 ps |
CPU time | 3.37 seconds |
Started | Jul 29 07:35:13 PM PDT 24 |
Finished | Jul 29 07:35:17 PM PDT 24 |
Peak memory | 214288 kb |
Host | smart-e2481224-4138-4b10-9fd2-e2dcefd65eb9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1757458104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1757458104 |
Directory | /workspace/17.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/17.keymgr_stress_all.3121682622 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 20407943587 ps |
CPU time | 124.19 seconds |
Started | Jul 29 07:35:11 PM PDT 24 |
Finished | Jul 29 07:37:16 PM PDT 24 |
Peak memory | 217508 kb |
Host | smart-9ae1df82-af08-4d18-b983-ceb2567872c3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121682622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3121682622 |
Directory | /workspace/17.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/17.keymgr_sw_invalid_input.3242776716 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 73276134 ps |
CPU time | 3.78 seconds |
Started | Jul 29 07:35:13 PM PDT 24 |
Finished | Jul 29 07:35:17 PM PDT 24 |
Peak memory | 207908 kb |
Host | smart-5b7a5657-fab3-4b31-8d33-753178a2e037 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3242776716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3242776716 |
Directory | /workspace/17.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/18.keymgr_kmac_rsp_err.3794483813 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 1014752166 ps |
CPU time | 9.79 seconds |
Started | Jul 29 07:35:17 PM PDT 24 |
Finished | Jul 29 07:35:27 PM PDT 24 |
Peak memory | 214336 kb |
Host | smart-28d9f884-3826-4868-99dc-97c8d7785794 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3794483813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3794483813 |
Directory | /workspace/18.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/19.keymgr_stress_all.4211012410 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 726691492 ps |
CPU time | 6.35 seconds |
Started | Jul 29 07:35:35 PM PDT 24 |
Finished | Jul 29 07:35:42 PM PDT 24 |
Peak memory | 210448 kb |
Host | smart-5bb91ee3-22fd-47bf-a295-2c603e159338 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211012410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.4211012410 |
Directory | /workspace/19.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/24.keymgr_lc_disable.1572032587 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 123044579 ps |
CPU time | 5.75 seconds |
Started | Jul 29 07:35:43 PM PDT 24 |
Finished | Jul 29 07:35:48 PM PDT 24 |
Peak memory | 220256 kb |
Host | smart-9129740d-7d27-4c85-a80c-a2a87ecfe9f7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1572032587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1572032587 |
Directory | /workspace/24.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/24.keymgr_stress_all.4072893700 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 950744884 ps |
CPU time | 24.11 seconds |
Started | Jul 29 07:35:52 PM PDT 24 |
Finished | Jul 29 07:36:17 PM PDT 24 |
Peak memory | 221972 kb |
Host | smart-b0454d78-6d2d-4155-9100-de7c7b831d9e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072893700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.4072893700 |
Directory | /workspace/24.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/25.keymgr_cfg_regwen.1039324039 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 355652508 ps |
CPU time | 9.63 seconds |
Started | Jul 29 07:35:52 PM PDT 24 |
Finished | Jul 29 07:36:02 PM PDT 24 |
Peak memory | 214288 kb |
Host | smart-63d6e1b6-f71a-41ef-8a8a-dcb81cffa1a1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1039324039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1039324039 |
Directory | /workspace/25.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/28.keymgr_kmac_rsp_err.3520515991 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 50996699 ps |
CPU time | 3.26 seconds |
Started | Jul 29 07:35:50 PM PDT 24 |
Finished | Jul 29 07:35:54 PM PDT 24 |
Peak memory | 221380 kb |
Host | smart-de7392e5-7c09-4e52-813d-f446d2bd196d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3520515991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3520515991 |
Directory | /workspace/28.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/29.keymgr_sideload_otbn.728762467 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 117491938 ps |
CPU time | 3.69 seconds |
Started | Jul 29 07:35:50 PM PDT 24 |
Finished | Jul 29 07:35:54 PM PDT 24 |
Peak memory | 208848 kb |
Host | smart-3fc2127f-10bc-4536-8b3c-2b2d526336fb |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728762467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.728762467 |
Directory | /workspace/29.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/29.keymgr_stress_all.3583794869 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 869669447 ps |
CPU time | 21.66 seconds |
Started | Jul 29 07:35:57 PM PDT 24 |
Finished | Jul 29 07:36:19 PM PDT 24 |
Peak memory | 216508 kb |
Host | smart-bc52c5ce-4a6e-4163-a90e-490124b2c0c9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583794869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3583794869 |
Directory | /workspace/29.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/3.keymgr_lc_disable.4285263667 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 77923589 ps |
CPU time | 2.6 seconds |
Started | Jul 29 07:34:47 PM PDT 24 |
Finished | Jul 29 07:34:50 PM PDT 24 |
Peak memory | 209104 kb |
Host | smart-21f7e59e-381b-4faf-85ce-8c8b777ecead |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4285263667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.4285263667 |
Directory | /workspace/3.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/5.keymgr_stress_all.3724441 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 159460949 ps |
CPU time | 8.63 seconds |
Started | Jul 29 07:34:54 PM PDT 24 |
Finished | Jul 29 07:35:03 PM PDT 24 |
Peak memory | 217068 kb |
Host | smart-9da70948-0d15-4e71-b18b-d0b5f705ea27 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3724441 |
Directory | /workspace/5.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/1.keymgr_sec_cm.2576959710 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 976972528 ps |
CPU time | 12.62 seconds |
Started | Jul 29 07:34:37 PM PDT 24 |
Finished | Jul 29 07:34:50 PM PDT 24 |
Peak memory | 232072 kb |
Host | smart-ede836a2-6599-4937-ac59-ad7bd02e603a |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576959710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2576959710 |
Directory | /workspace/1.keymgr_sec_cm/latest |
Test location | /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.4190463085 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 70035839 ps |
CPU time | 3.77 seconds |
Started | Jul 29 06:20:07 PM PDT 24 |
Finished | Jul 29 06:20:11 PM PDT 24 |
Peak memory | 206176 kb |
Host | smart-ecdb29d4-a3fd-4738-9456-2ea5e85b7cf9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190463085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.4 190463085 |
Directory | /workspace/0.keymgr_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3282727703 |
Short name | T921 |
Test name | |
Test status | |
Simulation time | 136963243 ps |
CPU time | 7.82 seconds |
Started | Jul 29 06:20:12 PM PDT 24 |
Finished | Jul 29 06:20:20 PM PDT 24 |
Peak memory | 206076 kb |
Host | smart-f65512df-ec03-47d5-b8da-b596087e7c64 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282727703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3 282727703 |
Directory | /workspace/0.keymgr_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3334653098 |
Short name | T932 |
Test name | |
Test status | |
Simulation time | 44731124 ps |
CPU time | 1.01 seconds |
Started | Jul 29 06:20:13 PM PDT 24 |
Finished | Jul 29 06:20:14 PM PDT 24 |
Peak memory | 206304 kb |
Host | smart-12e5b43c-6b2e-4499-a547-451a45b7767e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334653098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3 334653098 |
Directory | /workspace/0.keymgr_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1870515364 |
Short name | T946 |
Test name | |
Test status | |
Simulation time | 34496088 ps |
CPU time | 1.3 seconds |
Started | Jul 29 06:20:04 PM PDT 24 |
Finished | Jul 29 06:20:06 PM PDT 24 |
Peak memory | 214444 kb |
Host | smart-6795cca6-de2f-4997-8264-9d2ac7af2047 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870515364 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1870515364 |
Directory | /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2722563427 |
Short name | T941 |
Test name | |
Test status | |
Simulation time | 17539167 ps |
CPU time | 0.93 seconds |
Started | Jul 29 06:20:01 PM PDT 24 |
Finished | Jul 29 06:20:02 PM PDT 24 |
Peak memory | 205984 kb |
Host | smart-af1e4e9b-bc11-466e-88db-2702d41e00dd |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722563427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2722563427 |
Directory | /workspace/0.keymgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.keymgr_intr_test.765703189 |
Short name | T980 |
Test name | |
Test status | |
Simulation time | 45637116 ps |
CPU time | 0.86 seconds |
Started | Jul 29 06:20:06 PM PDT 24 |
Finished | Jul 29 06:20:07 PM PDT 24 |
Peak memory | 205844 kb |
Host | smart-b63ceb6f-27cb-4b99-9f81-4849768910c8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765703189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.765703189 |
Directory | /workspace/0.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2607940322 |
Short name | T976 |
Test name | |
Test status | |
Simulation time | 89106161 ps |
CPU time | 2.45 seconds |
Started | Jul 29 06:20:11 PM PDT 24 |
Finished | Jul 29 06:20:13 PM PDT 24 |
Peak memory | 206148 kb |
Host | smart-a10062a9-bcb0-484c-8a4f-2c423d694a5f |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607940322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa me_csr_outstanding.2607940322 |
Directory | /workspace/0.keymgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3805058333 |
Short name | T1033 |
Test name | |
Test status | |
Simulation time | 332145756 ps |
CPU time | 3.75 seconds |
Started | Jul 29 06:20:07 PM PDT 24 |
Finished | Jul 29 06:20:10 PM PDT 24 |
Peak memory | 214720 kb |
Host | smart-580b341e-8c41-4a22-a433-284710270b7b |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805058333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado w_reg_errors.3805058333 |
Directory | /workspace/0.keymgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.628936721 |
Short name | T1023 |
Test name | |
Test status | |
Simulation time | 777625774 ps |
CPU time | 7.58 seconds |
Started | Jul 29 06:20:08 PM PDT 24 |
Finished | Jul 29 06:20:16 PM PDT 24 |
Peak memory | 214848 kb |
Host | smart-513474a5-252d-428e-8ecc-0021f1ee97ec |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628936721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST _SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k eymgr_shadow_reg_errors_with_csr_rw.628936721 |
Directory | /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.378072466 |
Short name | T1041 |
Test name | |
Test status | |
Simulation time | 34684751 ps |
CPU time | 1.59 seconds |
Started | Jul 29 06:20:06 PM PDT 24 |
Finished | Jul 29 06:20:08 PM PDT 24 |
Peak memory | 214420 kb |
Host | smart-65d2db05-0afb-4359-b8a3-131d27a7e99a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378072466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.378072466 |
Directory | /workspace/0.keymgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.796064466 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 401329374 ps |
CPU time | 6.27 seconds |
Started | Jul 29 06:20:05 PM PDT 24 |
Finished | Jul 29 06:20:11 PM PDT 24 |
Peak memory | 214380 kb |
Host | smart-187d3aae-00ce-48ba-bc5b-d6936553b0c9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796064466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err. 796064466 |
Directory | /workspace/0.keymgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2908733383 |
Short name | T1081 |
Test name | |
Test status | |
Simulation time | 144244862 ps |
CPU time | 4.46 seconds |
Started | Jul 29 06:20:11 PM PDT 24 |
Finished | Jul 29 06:20:16 PM PDT 24 |
Peak memory | 206188 kb |
Host | smart-412f2dff-e75c-4cb3-9bee-e059aa4dccb8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908733383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2 908733383 |
Directory | /workspace/1.keymgr_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.531456017 |
Short name | T957 |
Test name | |
Test status | |
Simulation time | 7926183905 ps |
CPU time | 15.22 seconds |
Started | Jul 29 06:20:06 PM PDT 24 |
Finished | Jul 29 06:20:21 PM PDT 24 |
Peak memory | 206244 kb |
Host | smart-d7d85eff-7179-4f24-b317-685138f3077a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531456017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.531456017 |
Directory | /workspace/1.keymgr_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2887074025 |
Short name | T1078 |
Test name | |
Test status | |
Simulation time | 30682199 ps |
CPU time | 0.97 seconds |
Started | Jul 29 06:20:10 PM PDT 24 |
Finished | Jul 29 06:20:12 PM PDT 24 |
Peak memory | 205992 kb |
Host | smart-48d1efd4-a8f2-45bf-8f87-eef79ba1e299 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887074025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2 887074025 |
Directory | /workspace/1.keymgr_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.879138984 |
Short name | T942 |
Test name | |
Test status | |
Simulation time | 35107000 ps |
CPU time | 1.21 seconds |
Started | Jul 29 06:20:08 PM PDT 24 |
Finished | Jul 29 06:20:09 PM PDT 24 |
Peak memory | 206164 kb |
Host | smart-a44185a8-7f7a-4f6b-a089-59baaf50d9d1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879138984 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.879138984 |
Directory | /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3840695391 |
Short name | T947 |
Test name | |
Test status | |
Simulation time | 14006687 ps |
CPU time | 1.03 seconds |
Started | Jul 29 06:20:11 PM PDT 24 |
Finished | Jul 29 06:20:12 PM PDT 24 |
Peak memory | 206148 kb |
Host | smart-232e5d7a-8052-49f9-96af-3174da905e2a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840695391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3840695391 |
Directory | /workspace/1.keymgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3461473142 |
Short name | T915 |
Test name | |
Test status | |
Simulation time | 24029785 ps |
CPU time | 0.9 seconds |
Started | Jul 29 06:20:12 PM PDT 24 |
Finished | Jul 29 06:20:13 PM PDT 24 |
Peak memory | 205868 kb |
Host | smart-451b7d07-8aab-4683-9b07-3f6908ff83ac |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461473142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3461473142 |
Directory | /workspace/1.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3065218714 |
Short name | T1035 |
Test name | |
Test status | |
Simulation time | 60712054 ps |
CPU time | 1.37 seconds |
Started | Jul 29 06:20:09 PM PDT 24 |
Finished | Jul 29 06:20:10 PM PDT 24 |
Peak memory | 206156 kb |
Host | smart-c584d267-a8af-4c41-8da0-7b4a2084f2b3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065218714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa me_csr_outstanding.3065218714 |
Directory | /workspace/1.keymgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3253155345 |
Short name | T1021 |
Test name | |
Test status | |
Simulation time | 52252728 ps |
CPU time | 1.34 seconds |
Started | Jul 29 06:20:04 PM PDT 24 |
Finished | Jul 29 06:20:05 PM PDT 24 |
Peak memory | 206252 kb |
Host | smart-fa608884-b384-4ddd-811a-8dc9b95d38c5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253155345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado w_reg_errors.3253155345 |
Directory | /workspace/1.keymgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1581914487 |
Short name | T1027 |
Test name | |
Test status | |
Simulation time | 115535523 ps |
CPU time | 2.21 seconds |
Started | Jul 29 06:20:07 PM PDT 24 |
Finished | Jul 29 06:20:09 PM PDT 24 |
Peak memory | 217504 kb |
Host | smart-1214938d-0c9f-494b-b234-73deb8154e89 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581914487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1581914487 |
Directory | /workspace/1.keymgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2893356575 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 590729501 ps |
CPU time | 4.14 seconds |
Started | Jul 29 06:20:02 PM PDT 24 |
Finished | Jul 29 06:20:06 PM PDT 24 |
Peak memory | 215184 kb |
Host | smart-7fc34ac6-6c0d-4bdc-9bef-dcac064cf1a2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893356575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err .2893356575 |
Directory | /workspace/1.keymgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.4218499138 |
Short name | T1062 |
Test name | |
Test status | |
Simulation time | 136108676 ps |
CPU time | 2.11 seconds |
Started | Jul 29 06:20:32 PM PDT 24 |
Finished | Jul 29 06:20:34 PM PDT 24 |
Peak memory | 214328 kb |
Host | smart-b7c627e7-d81f-4a0f-85f4-f7ea83957efe |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218499138 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.4218499138 |
Directory | /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3938879513 |
Short name | T1060 |
Test name | |
Test status | |
Simulation time | 30095422 ps |
CPU time | 0.89 seconds |
Started | Jul 29 06:20:20 PM PDT 24 |
Finished | Jul 29 06:20:21 PM PDT 24 |
Peak memory | 206004 kb |
Host | smart-1a22f0c2-3331-4f3b-a9a6-92fb1d38b27a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938879513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3938879513 |
Directory | /workspace/10.keymgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.keymgr_intr_test.687875628 |
Short name | T1043 |
Test name | |
Test status | |
Simulation time | 21034235 ps |
CPU time | 0.7 seconds |
Started | Jul 29 06:20:19 PM PDT 24 |
Finished | Jul 29 06:20:20 PM PDT 24 |
Peak memory | 205928 kb |
Host | smart-3c612c7d-703f-4eb3-bed8-0bb1e10009d8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687875628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.687875628 |
Directory | /workspace/10.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2561899855 |
Short name | T1067 |
Test name | |
Test status | |
Simulation time | 66181955 ps |
CPU time | 1.86 seconds |
Started | Jul 29 06:20:17 PM PDT 24 |
Finished | Jul 29 06:20:19 PM PDT 24 |
Peak memory | 206156 kb |
Host | smart-a3bb798d-f4a2-40c7-94ed-2635bab9e816 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561899855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s ame_csr_outstanding.2561899855 |
Directory | /workspace/10.keymgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.919982145 |
Short name | T1063 |
Test name | |
Test status | |
Simulation time | 79909749 ps |
CPU time | 1.89 seconds |
Started | Jul 29 06:20:19 PM PDT 24 |
Finished | Jul 29 06:20:21 PM PDT 24 |
Peak memory | 214676 kb |
Host | smart-e59337d0-2f97-433d-80ba-fdea803b0b68 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919982145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado w_reg_errors.919982145 |
Directory | /workspace/10.keymgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.4046834442 |
Short name | T1010 |
Test name | |
Test status | |
Simulation time | 2002189681 ps |
CPU time | 13.01 seconds |
Started | Jul 29 06:20:37 PM PDT 24 |
Finished | Jul 29 06:20:50 PM PDT 24 |
Peak memory | 214932 kb |
Host | smart-231686fd-a5ce-40f5-87a4-1764e667c180 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046834442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .keymgr_shadow_reg_errors_with_csr_rw.4046834442 |
Directory | /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1222831841 |
Short name | T1025 |
Test name | |
Test status | |
Simulation time | 573883655 ps |
CPU time | 5.35 seconds |
Started | Jul 29 06:20:23 PM PDT 24 |
Finished | Jul 29 06:20:28 PM PDT 24 |
Peak memory | 214420 kb |
Host | smart-dd692210-8ad3-4bba-b42b-eb2c1618dd62 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222831841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1222831841 |
Directory | /workspace/10.keymgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.502826547 |
Short name | T995 |
Test name | |
Test status | |
Simulation time | 304190833 ps |
CPU time | 5.71 seconds |
Started | Jul 29 06:20:18 PM PDT 24 |
Finished | Jul 29 06:20:24 PM PDT 24 |
Peak memory | 214320 kb |
Host | smart-8286bb35-54ad-45bf-a17f-4867a4c4a3d9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502826547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err .502826547 |
Directory | /workspace/10.keymgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2818317740 |
Short name | T1057 |
Test name | |
Test status | |
Simulation time | 110006859 ps |
CPU time | 1.29 seconds |
Started | Jul 29 06:20:24 PM PDT 24 |
Finished | Jul 29 06:20:25 PM PDT 24 |
Peak memory | 214408 kb |
Host | smart-8f9644d3-6ebf-45e7-9350-4a66d91ca39e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818317740 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2818317740 |
Directory | /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.93129940 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 19405268 ps |
CPU time | 1.35 seconds |
Started | Jul 29 06:20:26 PM PDT 24 |
Finished | Jul 29 06:20:28 PM PDT 24 |
Peak memory | 206276 kb |
Host | smart-66a5abaa-97fc-46c9-aa9c-7bcad1b510a0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93129940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.93129940 |
Directory | /workspace/11.keymgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3924710672 |
Short name | T965 |
Test name | |
Test status | |
Simulation time | 18485195 ps |
CPU time | 0.89 seconds |
Started | Jul 29 06:20:21 PM PDT 24 |
Finished | Jul 29 06:20:22 PM PDT 24 |
Peak memory | 206112 kb |
Host | smart-6ea293c7-f646-46eb-b502-de19d54e900f |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924710672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3924710672 |
Directory | /workspace/11.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1854158861 |
Short name | T1053 |
Test name | |
Test status | |
Simulation time | 135838960 ps |
CPU time | 2.67 seconds |
Started | Jul 29 06:20:26 PM PDT 24 |
Finished | Jul 29 06:20:29 PM PDT 24 |
Peak memory | 206096 kb |
Host | smart-1b101ece-49b2-49ef-8c93-83db86d505d5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854158861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s ame_csr_outstanding.1854158861 |
Directory | /workspace/11.keymgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.399831492 |
Short name | T931 |
Test name | |
Test status | |
Simulation time | 1639987968 ps |
CPU time | 9.39 seconds |
Started | Jul 29 06:20:24 PM PDT 24 |
Finished | Jul 29 06:20:34 PM PDT 24 |
Peak memory | 214684 kb |
Host | smart-9c897474-21f7-4d51-a225-9d32dc4a0493 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399831492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST _SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. keymgr_shadow_reg_errors_with_csr_rw.399831492 |
Directory | /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3492653492 |
Short name | T969 |
Test name | |
Test status | |
Simulation time | 18769082 ps |
CPU time | 1.29 seconds |
Started | Jul 29 06:20:42 PM PDT 24 |
Finished | Jul 29 06:20:44 PM PDT 24 |
Peak memory | 206140 kb |
Host | smart-a131b1e0-8890-4679-b7a8-bb3c2bbf782e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492653492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3492653492 |
Directory | /workspace/11.keymgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3335768409 |
Short name | T929 |
Test name | |
Test status | |
Simulation time | 29749585 ps |
CPU time | 1.13 seconds |
Started | Jul 29 06:20:43 PM PDT 24 |
Finished | Jul 29 06:20:45 PM PDT 24 |
Peak memory | 206236 kb |
Host | smart-9178527a-a2ab-4564-8294-596dc637e8d4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335768409 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3335768409 |
Directory | /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1736718703 |
Short name | T978 |
Test name | |
Test status | |
Simulation time | 38907888 ps |
CPU time | 1.07 seconds |
Started | Jul 29 06:20:33 PM PDT 24 |
Finished | Jul 29 06:20:34 PM PDT 24 |
Peak memory | 206060 kb |
Host | smart-f1d63872-e536-4f94-b3b3-09d78b7b5ee1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736718703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1736718703 |
Directory | /workspace/12.keymgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2291492768 |
Short name | T1015 |
Test name | |
Test status | |
Simulation time | 9978556 ps |
CPU time | 0.71 seconds |
Started | Jul 29 06:20:41 PM PDT 24 |
Finished | Jul 29 06:20:41 PM PDT 24 |
Peak memory | 205896 kb |
Host | smart-0e9e82f8-d939-442c-bf7f-c72c09f5fc3a |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291492768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2291492768 |
Directory | /workspace/12.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2849183087 |
Short name | T986 |
Test name | |
Test status | |
Simulation time | 73125935 ps |
CPU time | 2.25 seconds |
Started | Jul 29 06:20:36 PM PDT 24 |
Finished | Jul 29 06:20:38 PM PDT 24 |
Peak memory | 206156 kb |
Host | smart-35a25953-51bb-4830-9a0d-745bf106db23 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849183087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s ame_csr_outstanding.2849183087 |
Directory | /workspace/12.keymgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2055490898 |
Short name | T1071 |
Test name | |
Test status | |
Simulation time | 690049048 ps |
CPU time | 2.02 seconds |
Started | Jul 29 06:20:17 PM PDT 24 |
Finished | Jul 29 06:20:19 PM PDT 24 |
Peak memory | 214644 kb |
Host | smart-a7d7a5ef-fd8f-4bff-af88-75d70ee351a5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055490898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad ow_reg_errors.2055490898 |
Directory | /workspace/12.keymgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1843148071 |
Short name | T1048 |
Test name | |
Test status | |
Simulation time | 393218318 ps |
CPU time | 9 seconds |
Started | Jul 29 06:20:32 PM PDT 24 |
Finished | Jul 29 06:20:41 PM PDT 24 |
Peak memory | 222864 kb |
Host | smart-8d555db6-92de-4cf9-be14-24e0e063c051 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843148071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12 .keymgr_shadow_reg_errors_with_csr_rw.1843148071 |
Directory | /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1812686624 |
Short name | T1004 |
Test name | |
Test status | |
Simulation time | 557210310 ps |
CPU time | 3.55 seconds |
Started | Jul 29 06:20:46 PM PDT 24 |
Finished | Jul 29 06:20:50 PM PDT 24 |
Peak memory | 214336 kb |
Host | smart-6487e5e2-4947-429d-9fe0-fc8fb236d45b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812686624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1812686624 |
Directory | /workspace/12.keymgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2078945180 |
Short name | T930 |
Test name | |
Test status | |
Simulation time | 138151132 ps |
CPU time | 3.42 seconds |
Started | Jul 29 06:20:38 PM PDT 24 |
Finished | Jul 29 06:20:41 PM PDT 24 |
Peak memory | 206380 kb |
Host | smart-e35d304f-da6c-4957-96df-dcd8b3236062 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078945180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er r.2078945180 |
Directory | /workspace/12.keymgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.955716739 |
Short name | T993 |
Test name | |
Test status | |
Simulation time | 162011879 ps |
CPU time | 1.81 seconds |
Started | Jul 29 06:20:34 PM PDT 24 |
Finished | Jul 29 06:20:36 PM PDT 24 |
Peak memory | 214536 kb |
Host | smart-6f42f7ec-d73c-4b8f-b8dc-c2d78f0a03f1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955716739 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.955716739 |
Directory | /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3236266366 |
Short name | T982 |
Test name | |
Test status | |
Simulation time | 31581728 ps |
CPU time | 0.91 seconds |
Started | Jul 29 06:20:33 PM PDT 24 |
Finished | Jul 29 06:20:34 PM PDT 24 |
Peak memory | 205980 kb |
Host | smart-2ee5157c-ef65-49a6-b14e-afae4aa72eee |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236266366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3236266366 |
Directory | /workspace/13.keymgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1408734638 |
Short name | T1014 |
Test name | |
Test status | |
Simulation time | 37153585 ps |
CPU time | 0.83 seconds |
Started | Jul 29 06:20:30 PM PDT 24 |
Finished | Jul 29 06:20:31 PM PDT 24 |
Peak memory | 205956 kb |
Host | smart-2e345af0-677f-487f-9f3b-379a18d707c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408734638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1408734638 |
Directory | /workspace/13.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3068922217 |
Short name | T979 |
Test name | |
Test status | |
Simulation time | 22149534 ps |
CPU time | 1.67 seconds |
Started | Jul 29 06:20:31 PM PDT 24 |
Finished | Jul 29 06:20:33 PM PDT 24 |
Peak memory | 206320 kb |
Host | smart-7da4839a-4a51-4cef-a259-89349b50b895 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068922217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s ame_csr_outstanding.3068922217 |
Directory | /workspace/13.keymgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.518929423 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 2785506991 ps |
CPU time | 4.72 seconds |
Started | Jul 29 06:20:33 PM PDT 24 |
Finished | Jul 29 06:20:38 PM PDT 24 |
Peak memory | 214728 kb |
Host | smart-f05cf14d-3b80-4d02-bca2-93ef1c807731 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518929423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado w_reg_errors.518929423 |
Directory | /workspace/13.keymgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2671168249 |
Short name | T1075 |
Test name | |
Test status | |
Simulation time | 150326431 ps |
CPU time | 4.18 seconds |
Started | Jul 29 06:20:25 PM PDT 24 |
Finished | Jul 29 06:20:29 PM PDT 24 |
Peak memory | 214660 kb |
Host | smart-283be872-c89e-4231-b7b2-9592c83996d4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671168249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .keymgr_shadow_reg_errors_with_csr_rw.2671168249 |
Directory | /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.843277881 |
Short name | T914 |
Test name | |
Test status | |
Simulation time | 139795860 ps |
CPU time | 3.55 seconds |
Started | Jul 29 06:20:45 PM PDT 24 |
Finished | Jul 29 06:20:49 PM PDT 24 |
Peak memory | 214344 kb |
Host | smart-1e4006b4-e479-4e28-8b25-5ca4a63d6b90 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843277881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.843277881 |
Directory | /workspace/13.keymgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3891975329 |
Short name | T955 |
Test name | |
Test status | |
Simulation time | 214021974 ps |
CPU time | 1.78 seconds |
Started | Jul 29 06:20:39 PM PDT 24 |
Finished | Jul 29 06:20:41 PM PDT 24 |
Peak memory | 214408 kb |
Host | smart-8a3da08c-8e8e-4915-bfd3-a940093a66a7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891975329 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3891975329 |
Directory | /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2303732800 |
Short name | T1051 |
Test name | |
Test status | |
Simulation time | 183088329 ps |
CPU time | 0.99 seconds |
Started | Jul 29 06:20:37 PM PDT 24 |
Finished | Jul 29 06:20:39 PM PDT 24 |
Peak memory | 205932 kb |
Host | smart-8d235f7c-f43b-4939-a557-69a39d7a5f2d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303732800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2303732800 |
Directory | /workspace/14.keymgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2805064775 |
Short name | T999 |
Test name | |
Test status | |
Simulation time | 12731718 ps |
CPU time | 0.75 seconds |
Started | Jul 29 06:20:32 PM PDT 24 |
Finished | Jul 29 06:20:33 PM PDT 24 |
Peak memory | 205944 kb |
Host | smart-ca21db8c-38e4-49df-9e68-641da3f2d735 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805064775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2805064775 |
Directory | /workspace/14.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1985033136 |
Short name | T1074 |
Test name | |
Test status | |
Simulation time | 44590392 ps |
CPU time | 1.53 seconds |
Started | Jul 29 06:20:41 PM PDT 24 |
Finished | Jul 29 06:20:42 PM PDT 24 |
Peak memory | 206128 kb |
Host | smart-98b336a8-e13d-4fb9-b728-303691b1b17b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985033136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s ame_csr_outstanding.1985033136 |
Directory | /workspace/14.keymgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2227151896 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 153620650 ps |
CPU time | 1.75 seconds |
Started | Jul 29 06:20:36 PM PDT 24 |
Finished | Jul 29 06:20:37 PM PDT 24 |
Peak memory | 214732 kb |
Host | smart-d577c7c5-05e2-4156-8efb-38a687d3cf91 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227151896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad ow_reg_errors.2227151896 |
Directory | /workspace/14.keymgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2090049811 |
Short name | T1030 |
Test name | |
Test status | |
Simulation time | 2273352806 ps |
CPU time | 8.03 seconds |
Started | Jul 29 06:20:40 PM PDT 24 |
Finished | Jul 29 06:20:48 PM PDT 24 |
Peak memory | 214648 kb |
Host | smart-10a15c4d-4b2c-421d-bde6-9ae2059f04f0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090049811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14 .keymgr_shadow_reg_errors_with_csr_rw.2090049811 |
Directory | /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3745806890 |
Short name | T1006 |
Test name | |
Test status | |
Simulation time | 110553088 ps |
CPU time | 2.44 seconds |
Started | Jul 29 06:20:32 PM PDT 24 |
Finished | Jul 29 06:20:34 PM PDT 24 |
Peak memory | 217476 kb |
Host | smart-ee613c35-7e82-4b37-9d77-fdb4d6bce0e3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745806890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3745806890 |
Directory | /workspace/14.keymgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1563173683 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 142171940 ps |
CPU time | 4.54 seconds |
Started | Jul 29 06:20:28 PM PDT 24 |
Finished | Jul 29 06:20:33 PM PDT 24 |
Peak memory | 214288 kb |
Host | smart-4cde32ed-38e7-4c35-ad33-ce1e9726e24e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563173683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er r.1563173683 |
Directory | /workspace/14.keymgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3035208332 |
Short name | T924 |
Test name | |
Test status | |
Simulation time | 95168342 ps |
CPU time | 1.63 seconds |
Started | Jul 29 06:20:42 PM PDT 24 |
Finished | Jul 29 06:20:44 PM PDT 24 |
Peak memory | 214496 kb |
Host | smart-c3b184ff-d296-40df-badb-8107acf3ecb3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035208332 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3035208332 |
Directory | /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.273652316 |
Short name | T1039 |
Test name | |
Test status | |
Simulation time | 16991200 ps |
CPU time | 1.35 seconds |
Started | Jul 29 06:20:51 PM PDT 24 |
Finished | Jul 29 06:20:53 PM PDT 24 |
Peak memory | 206224 kb |
Host | smart-2363c2d3-fd94-4b9c-85be-43a0adf60b1b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273652316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.273652316 |
Directory | /workspace/15.keymgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1648535546 |
Short name | T956 |
Test name | |
Test status | |
Simulation time | 23475802 ps |
CPU time | 0.7 seconds |
Started | Jul 29 06:20:33 PM PDT 24 |
Finished | Jul 29 06:20:34 PM PDT 24 |
Peak memory | 205980 kb |
Host | smart-e6614cd6-4200-408c-8df2-268dcc039159 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648535546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1648535546 |
Directory | /workspace/15.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1861673962 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 89087978 ps |
CPU time | 1.51 seconds |
Started | Jul 29 06:20:42 PM PDT 24 |
Finished | Jul 29 06:20:43 PM PDT 24 |
Peak memory | 206108 kb |
Host | smart-43a94b15-bd1a-4167-bd8c-f300fcb3035f |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861673962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s ame_csr_outstanding.1861673962 |
Directory | /workspace/15.keymgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.844171115 |
Short name | T987 |
Test name | |
Test status | |
Simulation time | 332736431 ps |
CPU time | 2.81 seconds |
Started | Jul 29 06:20:45 PM PDT 24 |
Finished | Jul 29 06:20:48 PM PDT 24 |
Peak memory | 219432 kb |
Host | smart-fc56ea0c-8a6c-4ef8-b8a9-df44f92e348a |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844171115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado w_reg_errors.844171115 |
Directory | /workspace/15.keymgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.289901472 |
Short name | T1073 |
Test name | |
Test status | |
Simulation time | 164372124 ps |
CPU time | 5.67 seconds |
Started | Jul 29 06:20:30 PM PDT 24 |
Finished | Jul 29 06:20:36 PM PDT 24 |
Peak memory | 214700 kb |
Host | smart-2720197d-eb15-4773-88da-6d23efc6ad49 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289901472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST _SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. keymgr_shadow_reg_errors_with_csr_rw.289901472 |
Directory | /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1194209886 |
Short name | T926 |
Test name | |
Test status | |
Simulation time | 87696108 ps |
CPU time | 2.02 seconds |
Started | Jul 29 06:20:45 PM PDT 24 |
Finished | Jul 29 06:20:47 PM PDT 24 |
Peak memory | 214492 kb |
Host | smart-c55ef66e-cf82-44e6-8e6a-89c1ce537893 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194209886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1194209886 |
Directory | /workspace/15.keymgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1662093730 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 209559321 ps |
CPU time | 8.78 seconds |
Started | Jul 29 06:20:33 PM PDT 24 |
Finished | Jul 29 06:20:42 PM PDT 24 |
Peak memory | 214328 kb |
Host | smart-a848503a-2209-46f2-b639-8d4fbee7f20f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662093730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er r.1662093730 |
Directory | /workspace/15.keymgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2057333235 |
Short name | T984 |
Test name | |
Test status | |
Simulation time | 172495496 ps |
CPU time | 1.55 seconds |
Started | Jul 29 06:20:35 PM PDT 24 |
Finished | Jul 29 06:20:37 PM PDT 24 |
Peak memory | 214372 kb |
Host | smart-86157224-65e4-4a00-aca3-04a2fc786e33 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057333235 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2057333235 |
Directory | /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3733347449 |
Short name | T1003 |
Test name | |
Test status | |
Simulation time | 59240853 ps |
CPU time | 1.08 seconds |
Started | Jul 29 06:20:33 PM PDT 24 |
Finished | Jul 29 06:20:34 PM PDT 24 |
Peak memory | 206124 kb |
Host | smart-c778bd93-8811-4c65-bc2c-f078c7143a04 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733347449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3733347449 |
Directory | /workspace/16.keymgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1922908998 |
Short name | T943 |
Test name | |
Test status | |
Simulation time | 13595100 ps |
CPU time | 0.73 seconds |
Started | Jul 29 06:20:34 PM PDT 24 |
Finished | Jul 29 06:20:35 PM PDT 24 |
Peak memory | 205980 kb |
Host | smart-a9007612-3f04-468a-a31d-b4523522c2df |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922908998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1922908998 |
Directory | /workspace/16.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3204049047 |
Short name | T1034 |
Test name | |
Test status | |
Simulation time | 70633311 ps |
CPU time | 2.47 seconds |
Started | Jul 29 06:20:47 PM PDT 24 |
Finished | Jul 29 06:20:50 PM PDT 24 |
Peak memory | 206092 kb |
Host | smart-cbbe118a-2aa2-4ee1-9f6e-69ba1f161a05 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204049047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s ame_csr_outstanding.3204049047 |
Directory | /workspace/16.keymgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2829695080 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 81153882 ps |
CPU time | 2.42 seconds |
Started | Jul 29 06:20:24 PM PDT 24 |
Finished | Jul 29 06:20:27 PM PDT 24 |
Peak memory | 219208 kb |
Host | smart-2d1d454a-12c1-4e65-ae0e-f89083db06c9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829695080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad ow_reg_errors.2829695080 |
Directory | /workspace/16.keymgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2996073316 |
Short name | T1049 |
Test name | |
Test status | |
Simulation time | 443091669 ps |
CPU time | 9.7 seconds |
Started | Jul 29 06:20:39 PM PDT 24 |
Finished | Jul 29 06:20:49 PM PDT 24 |
Peak memory | 214744 kb |
Host | smart-39bb858f-99bb-4720-8e9a-72caa7caa36d |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996073316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16 .keymgr_shadow_reg_errors_with_csr_rw.2996073316 |
Directory | /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1684065407 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 221988844 ps |
CPU time | 4.92 seconds |
Started | Jul 29 06:20:34 PM PDT 24 |
Finished | Jul 29 06:20:39 PM PDT 24 |
Peak memory | 214424 kb |
Host | smart-5fffd80a-cec9-435f-ba17-1f8be20998d8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684065407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1684065407 |
Directory | /workspace/16.keymgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.396914659 |
Short name | T927 |
Test name | |
Test status | |
Simulation time | 90353433 ps |
CPU time | 1.53 seconds |
Started | Jul 29 06:20:49 PM PDT 24 |
Finished | Jul 29 06:20:51 PM PDT 24 |
Peak memory | 219244 kb |
Host | smart-cf0fd5ae-2ee1-4afb-9b26-84184404c408 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396914659 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.396914659 |
Directory | /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1541312082 |
Short name | T918 |
Test name | |
Test status | |
Simulation time | 17359697 ps |
CPU time | 1.09 seconds |
Started | Jul 29 06:20:37 PM PDT 24 |
Finished | Jul 29 06:20:39 PM PDT 24 |
Peak memory | 206084 kb |
Host | smart-19b48c0c-33c5-4df7-a4e8-6aed5376fe2d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541312082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1541312082 |
Directory | /workspace/17.keymgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1288783641 |
Short name | T1026 |
Test name | |
Test status | |
Simulation time | 22454045 ps |
CPU time | 0.89 seconds |
Started | Jul 29 06:20:34 PM PDT 24 |
Finished | Jul 29 06:20:35 PM PDT 24 |
Peak memory | 206112 kb |
Host | smart-0ce8fd65-6bab-494c-816c-1d12d8f48b41 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288783641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1288783641 |
Directory | /workspace/17.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3844174413 |
Short name | T983 |
Test name | |
Test status | |
Simulation time | 820236230 ps |
CPU time | 2.51 seconds |
Started | Jul 29 06:20:40 PM PDT 24 |
Finished | Jul 29 06:20:42 PM PDT 24 |
Peak memory | 206164 kb |
Host | smart-9e45ea9a-704a-4ac3-9480-98f2a29c16ab |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844174413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s ame_csr_outstanding.3844174413 |
Directory | /workspace/17.keymgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2802959896 |
Short name | T974 |
Test name | |
Test status | |
Simulation time | 2994496046 ps |
CPU time | 3.38 seconds |
Started | Jul 29 06:20:44 PM PDT 24 |
Finished | Jul 29 06:20:48 PM PDT 24 |
Peak memory | 214668 kb |
Host | smart-77ce5c6d-fa34-4b40-8c49-21a6f4afb93b |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802959896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad ow_reg_errors.2802959896 |
Directory | /workspace/17.keymgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2440574561 |
Short name | T1072 |
Test name | |
Test status | |
Simulation time | 1180312970 ps |
CPU time | 11.74 seconds |
Started | Jul 29 06:20:40 PM PDT 24 |
Finished | Jul 29 06:20:52 PM PDT 24 |
Peak memory | 214672 kb |
Host | smart-9dc2b185-a34e-45bd-a1b2-c9c6cb4ab94f |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440574561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .keymgr_shadow_reg_errors_with_csr_rw.2440574561 |
Directory | /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1633328457 |
Short name | T1077 |
Test name | |
Test status | |
Simulation time | 80732168 ps |
CPU time | 3.09 seconds |
Started | Jul 29 06:20:37 PM PDT 24 |
Finished | Jul 29 06:20:40 PM PDT 24 |
Peak memory | 214384 kb |
Host | smart-dc068986-62f5-404d-a257-2c13a09b25a5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633328457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1633328457 |
Directory | /workspace/17.keymgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3125991965 |
Short name | T1068 |
Test name | |
Test status | |
Simulation time | 90618988 ps |
CPU time | 1.11 seconds |
Started | Jul 29 06:20:33 PM PDT 24 |
Finished | Jul 29 06:20:35 PM PDT 24 |
Peak memory | 206208 kb |
Host | smart-47bcc0ad-63cc-45ac-8786-099509b6cc68 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125991965 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.3125991965 |
Directory | /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.4285039586 |
Short name | T1047 |
Test name | |
Test status | |
Simulation time | 22885095 ps |
CPU time | 1.28 seconds |
Started | Jul 29 06:20:40 PM PDT 24 |
Finished | Jul 29 06:20:41 PM PDT 24 |
Peak memory | 206232 kb |
Host | smart-71c5efb9-eaa5-4c82-810c-d9027ac38e99 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285039586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.4285039586 |
Directory | /workspace/18.keymgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1921109030 |
Short name | T962 |
Test name | |
Test status | |
Simulation time | 23095220 ps |
CPU time | 0.75 seconds |
Started | Jul 29 06:20:53 PM PDT 24 |
Finished | Jul 29 06:20:54 PM PDT 24 |
Peak memory | 205888 kb |
Host | smart-a11db111-05cd-4c6d-b4d9-e6db0bca203e |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921109030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1921109030 |
Directory | /workspace/18.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.4047831784 |
Short name | T1017 |
Test name | |
Test status | |
Simulation time | 19594278 ps |
CPU time | 1.52 seconds |
Started | Jul 29 06:20:41 PM PDT 24 |
Finished | Jul 29 06:20:42 PM PDT 24 |
Peak memory | 206188 kb |
Host | smart-2ce6b276-afce-4304-96c3-a1d2f5114507 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047831784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s ame_csr_outstanding.4047831784 |
Directory | /workspace/18.keymgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3326388809 |
Short name | T1045 |
Test name | |
Test status | |
Simulation time | 1435130828 ps |
CPU time | 1.91 seconds |
Started | Jul 29 06:20:47 PM PDT 24 |
Finished | Jul 29 06:20:50 PM PDT 24 |
Peak memory | 214676 kb |
Host | smart-92e809af-3c80-487f-9d5c-53a1f102f093 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326388809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad ow_reg_errors.3326388809 |
Directory | /workspace/18.keymgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3810456470 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 314135380 ps |
CPU time | 6.76 seconds |
Started | Jul 29 06:20:42 PM PDT 24 |
Finished | Jul 29 06:20:49 PM PDT 24 |
Peak memory | 214656 kb |
Host | smart-13c057d1-eaa6-495e-a2a0-7d4434d0bbe0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810456470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .keymgr_shadow_reg_errors_with_csr_rw.3810456470 |
Directory | /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2368023544 |
Short name | T1040 |
Test name | |
Test status | |
Simulation time | 185199453 ps |
CPU time | 3.18 seconds |
Started | Jul 29 06:20:42 PM PDT 24 |
Finished | Jul 29 06:20:46 PM PDT 24 |
Peak memory | 214432 kb |
Host | smart-6d346054-a97c-4580-9663-d68e7fc4884a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368023544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2368023544 |
Directory | /workspace/18.keymgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3781454600 |
Short name | T963 |
Test name | |
Test status | |
Simulation time | 39076593 ps |
CPU time | 1.32 seconds |
Started | Jul 29 06:20:38 PM PDT 24 |
Finished | Jul 29 06:20:40 PM PDT 24 |
Peak memory | 214432 kb |
Host | smart-518b7c9f-9b2a-4f30-be45-37d3759b849c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781454600 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3781454600 |
Directory | /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.651965856 |
Short name | T972 |
Test name | |
Test status | |
Simulation time | 14972610 ps |
CPU time | 1 seconds |
Started | Jul 29 06:20:36 PM PDT 24 |
Finished | Jul 29 06:20:37 PM PDT 24 |
Peak memory | 206028 kb |
Host | smart-4875d7d6-498d-4213-9548-2b8896ec5eb6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651965856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.651965856 |
Directory | /workspace/19.keymgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3738175794 |
Short name | T1070 |
Test name | |
Test status | |
Simulation time | 19237663 ps |
CPU time | 0.78 seconds |
Started | Jul 29 06:20:46 PM PDT 24 |
Finished | Jul 29 06:20:47 PM PDT 24 |
Peak memory | 205724 kb |
Host | smart-0cca0134-7839-47fb-9cb2-9a0d8a823a96 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738175794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3738175794 |
Directory | /workspace/19.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1121230944 |
Short name | T1037 |
Test name | |
Test status | |
Simulation time | 23076387 ps |
CPU time | 1.44 seconds |
Started | Jul 29 06:20:37 PM PDT 24 |
Finished | Jul 29 06:20:39 PM PDT 24 |
Peak memory | 206172 kb |
Host | smart-a5950dd3-27b6-4f5f-9bcb-b91c21cba951 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121230944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s ame_csr_outstanding.1121230944 |
Directory | /workspace/19.keymgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1466377530 |
Short name | T1065 |
Test name | |
Test status | |
Simulation time | 149891841 ps |
CPU time | 2.75 seconds |
Started | Jul 29 06:20:37 PM PDT 24 |
Finished | Jul 29 06:20:40 PM PDT 24 |
Peak memory | 214660 kb |
Host | smart-a2764f0d-73d9-45f1-b563-49efd18d6c2e |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466377530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad ow_reg_errors.1466377530 |
Directory | /workspace/19.keymgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1158069026 |
Short name | T954 |
Test name | |
Test status | |
Simulation time | 175923551 ps |
CPU time | 4.09 seconds |
Started | Jul 29 06:20:48 PM PDT 24 |
Finished | Jul 29 06:20:53 PM PDT 24 |
Peak memory | 214684 kb |
Host | smart-82681cc5-2305-4770-910e-67602cde5502 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158069026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19 .keymgr_shadow_reg_errors_with_csr_rw.1158069026 |
Directory | /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2958480888 |
Short name | T1002 |
Test name | |
Test status | |
Simulation time | 35351044 ps |
CPU time | 2.32 seconds |
Started | Jul 29 06:20:48 PM PDT 24 |
Finished | Jul 29 06:20:51 PM PDT 24 |
Peak memory | 214300 kb |
Host | smart-99992a3b-551b-4876-8b0f-b236ce971ea1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958480888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2958480888 |
Directory | /workspace/19.keymgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2034707434 |
Short name | T1055 |
Test name | |
Test status | |
Simulation time | 189618383 ps |
CPU time | 4.89 seconds |
Started | Jul 29 06:20:07 PM PDT 24 |
Finished | Jul 29 06:20:12 PM PDT 24 |
Peak memory | 206244 kb |
Host | smart-db142e6f-3180-4001-9ed5-00c96a2f3cad |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034707434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2 034707434 |
Directory | /workspace/2.keymgr_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3855165849 |
Short name | T988 |
Test name | |
Test status | |
Simulation time | 253321735 ps |
CPU time | 12.53 seconds |
Started | Jul 29 06:20:11 PM PDT 24 |
Finished | Jul 29 06:20:24 PM PDT 24 |
Peak memory | 206128 kb |
Host | smart-06ab8e0c-06d9-4e41-a15b-0090c4a97c1e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855165849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3 855165849 |
Directory | /workspace/2.keymgr_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1657082835 |
Short name | T1052 |
Test name | |
Test status | |
Simulation time | 10671304 ps |
CPU time | 0.91 seconds |
Started | Jul 29 06:20:12 PM PDT 24 |
Finished | Jul 29 06:20:13 PM PDT 24 |
Peak memory | 206180 kb |
Host | smart-56e12b46-32a6-4670-940d-96e0a5575559 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657082835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1 657082835 |
Directory | /workspace/2.keymgr_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.4255238833 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 137127506 ps |
CPU time | 1.73 seconds |
Started | Jul 29 06:20:12 PM PDT 24 |
Finished | Jul 29 06:20:14 PM PDT 24 |
Peak memory | 214300 kb |
Host | smart-2292dcec-778c-41a9-8ed3-f73bb9ec6c36 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255238833 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.4255238833 |
Directory | /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2883331690 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 20942171 ps |
CPU time | 0.98 seconds |
Started | Jul 29 06:20:05 PM PDT 24 |
Finished | Jul 29 06:20:06 PM PDT 24 |
Peak memory | 205980 kb |
Host | smart-91df564a-fdfe-42b8-8562-625e0d8ee2e4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883331690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2883331690 |
Directory | /workspace/2.keymgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2509993938 |
Short name | T1082 |
Test name | |
Test status | |
Simulation time | 33384871 ps |
CPU time | 0.76 seconds |
Started | Jul 29 06:20:05 PM PDT 24 |
Finished | Jul 29 06:20:06 PM PDT 24 |
Peak memory | 205904 kb |
Host | smart-353e8a5b-6a67-4ff3-aa35-69e0a15fca60 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509993938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2509993938 |
Directory | /workspace/2.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.830751729 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 363948515 ps |
CPU time | 3.08 seconds |
Started | Jul 29 06:20:10 PM PDT 24 |
Finished | Jul 29 06:20:13 PM PDT 24 |
Peak memory | 206212 kb |
Host | smart-0c8bd6db-076b-4829-bb08-6332424d3114 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830751729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam e_csr_outstanding.830751729 |
Directory | /workspace/2.keymgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3486936846 |
Short name | T940 |
Test name | |
Test status | |
Simulation time | 151992680 ps |
CPU time | 2.72 seconds |
Started | Jul 29 06:20:06 PM PDT 24 |
Finished | Jul 29 06:20:09 PM PDT 24 |
Peak memory | 214624 kb |
Host | smart-60efcb4a-d573-44a9-8362-2fd309bb8156 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486936846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado w_reg_errors.3486936846 |
Directory | /workspace/2.keymgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.574798320 |
Short name | T977 |
Test name | |
Test status | |
Simulation time | 228500532 ps |
CPU time | 5.12 seconds |
Started | Jul 29 06:20:11 PM PDT 24 |
Finished | Jul 29 06:20:17 PM PDT 24 |
Peak memory | 214704 kb |
Host | smart-59a1fb67-ce74-4b37-a697-54ef4a945a08 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574798320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST _SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k eymgr_shadow_reg_errors_with_csr_rw.574798320 |
Directory | /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3208917060 |
Short name | T992 |
Test name | |
Test status | |
Simulation time | 494051898 ps |
CPU time | 3.55 seconds |
Started | Jul 29 06:20:07 PM PDT 24 |
Finished | Jul 29 06:20:10 PM PDT 24 |
Peak memory | 214324 kb |
Host | smart-32888750-55cc-4fc5-9c52-ed3a00c70cfd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208917060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3208917060 |
Directory | /workspace/2.keymgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/20.keymgr_intr_test.4232727599 |
Short name | T917 |
Test name | |
Test status | |
Simulation time | 19312224 ps |
CPU time | 0.7 seconds |
Started | Jul 29 06:20:37 PM PDT 24 |
Finished | Jul 29 06:20:38 PM PDT 24 |
Peak memory | 205936 kb |
Host | smart-26e20f3e-7f87-4431-94af-8a4db71aa281 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232727599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.4232727599 |
Directory | /workspace/20.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1376760559 |
Short name | T1058 |
Test name | |
Test status | |
Simulation time | 31925064 ps |
CPU time | 0.71 seconds |
Started | Jul 29 06:20:49 PM PDT 24 |
Finished | Jul 29 06:20:50 PM PDT 24 |
Peak memory | 205912 kb |
Host | smart-5d5fa187-7b41-46b3-ada4-43e4460024d8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376760559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1376760559 |
Directory | /workspace/21.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2830623787 |
Short name | T939 |
Test name | |
Test status | |
Simulation time | 38062079 ps |
CPU time | 0.69 seconds |
Started | Jul 29 06:20:41 PM PDT 24 |
Finished | Jul 29 06:20:41 PM PDT 24 |
Peak memory | 205940 kb |
Host | smart-bc17fc46-6caf-412f-aeed-4fe76926975f |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830623787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2830623787 |
Directory | /workspace/22.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1621535529 |
Short name | T1069 |
Test name | |
Test status | |
Simulation time | 14812262 ps |
CPU time | 0.89 seconds |
Started | Jul 29 06:20:43 PM PDT 24 |
Finished | Jul 29 06:20:44 PM PDT 24 |
Peak memory | 206000 kb |
Host | smart-b798596e-26af-41a6-a191-0ec6ece4872a |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621535529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1621535529 |
Directory | /workspace/23.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3895738411 |
Short name | T935 |
Test name | |
Test status | |
Simulation time | 17346137 ps |
CPU time | 0.74 seconds |
Started | Jul 29 06:20:46 PM PDT 24 |
Finished | Jul 29 06:20:47 PM PDT 24 |
Peak memory | 205960 kb |
Host | smart-2908646e-8cd6-4ef4-9d3c-8c8972ed3ccb |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895738411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3895738411 |
Directory | /workspace/24.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3901929935 |
Short name | T1064 |
Test name | |
Test status | |
Simulation time | 14015406 ps |
CPU time | 0.88 seconds |
Started | Jul 29 06:20:49 PM PDT 24 |
Finished | Jul 29 06:20:50 PM PDT 24 |
Peak memory | 206088 kb |
Host | smart-9dea1c6a-6c20-4054-b6c8-c0c6a3afbbc4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901929935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3901929935 |
Directory | /workspace/25.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1558232692 |
Short name | T1054 |
Test name | |
Test status | |
Simulation time | 42761080 ps |
CPU time | 0.79 seconds |
Started | Jul 29 06:20:37 PM PDT 24 |
Finished | Jul 29 06:20:38 PM PDT 24 |
Peak memory | 205976 kb |
Host | smart-0e4ea0e9-94fb-4b78-a399-d40fde78a4e3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558232692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1558232692 |
Directory | /workspace/26.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/27.keymgr_intr_test.476604817 |
Short name | T967 |
Test name | |
Test status | |
Simulation time | 32198708 ps |
CPU time | 0.69 seconds |
Started | Jul 29 06:20:48 PM PDT 24 |
Finished | Jul 29 06:20:49 PM PDT 24 |
Peak memory | 205932 kb |
Host | smart-726a3a79-c52b-4b91-960e-f39d042705a1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476604817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.476604817 |
Directory | /workspace/27.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1882093007 |
Short name | T975 |
Test name | |
Test status | |
Simulation time | 32137028 ps |
CPU time | 0.79 seconds |
Started | Jul 29 06:20:39 PM PDT 24 |
Finished | Jul 29 06:20:40 PM PDT 24 |
Peak memory | 205916 kb |
Host | smart-577961e2-6e4c-46f9-a141-8f0af29fde76 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882093007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1882093007 |
Directory | /workspace/28.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2457035249 |
Short name | T1079 |
Test name | |
Test status | |
Simulation time | 109676399 ps |
CPU time | 0.74 seconds |
Started | Jul 29 06:20:49 PM PDT 24 |
Finished | Jul 29 06:20:49 PM PDT 24 |
Peak memory | 205912 kb |
Host | smart-43ee2220-f5ff-47ca-9d9a-82b12f17f260 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457035249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2457035249 |
Directory | /workspace/29.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.4215127430 |
Short name | T1005 |
Test name | |
Test status | |
Simulation time | 1243715015 ps |
CPU time | 6.38 seconds |
Started | Jul 29 06:20:14 PM PDT 24 |
Finished | Jul 29 06:20:21 PM PDT 24 |
Peak memory | 206188 kb |
Host | smart-32c84999-d00e-4abe-9e3c-dec31b92a16f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215127430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.4 215127430 |
Directory | /workspace/3.keymgr_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1740442204 |
Short name | T970 |
Test name | |
Test status | |
Simulation time | 4019424564 ps |
CPU time | 16.45 seconds |
Started | Jul 29 06:20:19 PM PDT 24 |
Finished | Jul 29 06:20:35 PM PDT 24 |
Peak memory | 206200 kb |
Host | smart-16e326e8-7ca7-4459-a7df-1237fe064e17 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740442204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1 740442204 |
Directory | /workspace/3.keymgr_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.842857127 |
Short name | T961 |
Test name | |
Test status | |
Simulation time | 137159026 ps |
CPU time | 1.44 seconds |
Started | Jul 29 06:20:07 PM PDT 24 |
Finished | Jul 29 06:20:08 PM PDT 24 |
Peak memory | 206228 kb |
Host | smart-d9432f65-6cdf-434f-8285-740af98bf0a0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842857127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.842857127 |
Directory | /workspace/3.keymgr_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3196083306 |
Short name | T1024 |
Test name | |
Test status | |
Simulation time | 117999660 ps |
CPU time | 1.16 seconds |
Started | Jul 29 06:20:12 PM PDT 24 |
Finished | Jul 29 06:20:14 PM PDT 24 |
Peak memory | 214496 kb |
Host | smart-45de989a-0546-4108-961c-d8bfb43607da |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196083306 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3196083306 |
Directory | /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1187707347 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 27244670 ps |
CPU time | 1.13 seconds |
Started | Jul 29 06:20:16 PM PDT 24 |
Finished | Jul 29 06:20:17 PM PDT 24 |
Peak memory | 206224 kb |
Host | smart-b73d4657-d2e0-442d-aee6-e7c506abf161 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187707347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1187707347 |
Directory | /workspace/3.keymgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.keymgr_intr_test.105369110 |
Short name | T1029 |
Test name | |
Test status | |
Simulation time | 27021115 ps |
CPU time | 0.78 seconds |
Started | Jul 29 06:20:12 PM PDT 24 |
Finished | Jul 29 06:20:13 PM PDT 24 |
Peak memory | 205888 kb |
Host | smart-d89c8944-43f9-4d9b-84c2-d578609469d7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105369110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.105369110 |
Directory | /workspace/3.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2040384686 |
Short name | T951 |
Test name | |
Test status | |
Simulation time | 82031919 ps |
CPU time | 1.45 seconds |
Started | Jul 29 06:20:17 PM PDT 24 |
Finished | Jul 29 06:20:18 PM PDT 24 |
Peak memory | 206120 kb |
Host | smart-4fe8c240-56d4-4d8f-96e8-109b9f318bd1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040384686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa me_csr_outstanding.2040384686 |
Directory | /workspace/3.keymgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2758034081 |
Short name | T973 |
Test name | |
Test status | |
Simulation time | 285571053 ps |
CPU time | 3.18 seconds |
Started | Jul 29 06:20:09 PM PDT 24 |
Finished | Jul 29 06:20:12 PM PDT 24 |
Peak memory | 214584 kb |
Host | smart-d124d3d9-614f-415e-8fb6-b1a9f831870b |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758034081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado w_reg_errors.2758034081 |
Directory | /workspace/3.keymgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2078859863 |
Short name | T991 |
Test name | |
Test status | |
Simulation time | 370548084 ps |
CPU time | 8.54 seconds |
Started | Jul 29 06:20:08 PM PDT 24 |
Finished | Jul 29 06:20:16 PM PDT 24 |
Peak memory | 214576 kb |
Host | smart-b312ee9c-139b-4b00-b406-fbbb36f1209f |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078859863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. keymgr_shadow_reg_errors_with_csr_rw.2078859863 |
Directory | /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1286436665 |
Short name | T960 |
Test name | |
Test status | |
Simulation time | 104062843 ps |
CPU time | 3.89 seconds |
Started | Jul 29 06:20:09 PM PDT 24 |
Finished | Jul 29 06:20:13 PM PDT 24 |
Peak memory | 214340 kb |
Host | smart-f37d1489-befa-4566-bd32-0c33bbfbfb5e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286436665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1286436665 |
Directory | /workspace/3.keymgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.797363312 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 210942876 ps |
CPU time | 3.46 seconds |
Started | Jul 29 06:20:11 PM PDT 24 |
Finished | Jul 29 06:20:15 PM PDT 24 |
Peak memory | 215556 kb |
Host | smart-56ea8304-2ac0-4f90-b03b-8c5891deab90 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797363312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err. 797363312 |
Directory | /workspace/3.keymgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1592684612 |
Short name | T989 |
Test name | |
Test status | |
Simulation time | 19819390 ps |
CPU time | 0.7 seconds |
Started | Jul 29 06:20:48 PM PDT 24 |
Finished | Jul 29 06:20:49 PM PDT 24 |
Peak memory | 205844 kb |
Host | smart-45703650-2b6a-4efb-8460-e0cc598e139e |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592684612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1592684612 |
Directory | /workspace/30.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1831167691 |
Short name | T1042 |
Test name | |
Test status | |
Simulation time | 11168275 ps |
CPU time | 0.74 seconds |
Started | Jul 29 06:20:48 PM PDT 24 |
Finished | Jul 29 06:20:49 PM PDT 24 |
Peak memory | 205880 kb |
Host | smart-c06f3a67-03ce-4e96-a893-97e438df4410 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831167691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1831167691 |
Directory | /workspace/31.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2200527353 |
Short name | T1000 |
Test name | |
Test status | |
Simulation time | 44200525 ps |
CPU time | 0.83 seconds |
Started | Jul 29 06:20:41 PM PDT 24 |
Finished | Jul 29 06:20:42 PM PDT 24 |
Peak memory | 205912 kb |
Host | smart-fb33d562-9211-44fd-9bb1-8c03c00a1213 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200527353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2200527353 |
Directory | /workspace/32.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2315582827 |
Short name | T1036 |
Test name | |
Test status | |
Simulation time | 18047679 ps |
CPU time | 0.81 seconds |
Started | Jul 29 06:20:43 PM PDT 24 |
Finished | Jul 29 06:20:44 PM PDT 24 |
Peak memory | 205888 kb |
Host | smart-1603c68b-0d54-41cb-ba4f-35fa5f7fce65 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315582827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2315582827 |
Directory | /workspace/33.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1657820591 |
Short name | T1020 |
Test name | |
Test status | |
Simulation time | 23297402 ps |
CPU time | 0.74 seconds |
Started | Jul 29 06:20:48 PM PDT 24 |
Finished | Jul 29 06:20:49 PM PDT 24 |
Peak memory | 205924 kb |
Host | smart-7df11ca3-f6d6-4742-b750-312563b2a583 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657820591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1657820591 |
Directory | /workspace/34.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2814617998 |
Short name | T1009 |
Test name | |
Test status | |
Simulation time | 45021033 ps |
CPU time | 0.84 seconds |
Started | Jul 29 06:20:34 PM PDT 24 |
Finished | Jul 29 06:20:35 PM PDT 24 |
Peak memory | 205896 kb |
Host | smart-1f533c29-fecf-465e-852d-97fcb90ef9c0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814617998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2814617998 |
Directory | /workspace/35.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/36.keymgr_intr_test.4148107295 |
Short name | T953 |
Test name | |
Test status | |
Simulation time | 20988752 ps |
CPU time | 0.71 seconds |
Started | Jul 29 06:20:41 PM PDT 24 |
Finished | Jul 29 06:20:42 PM PDT 24 |
Peak memory | 205796 kb |
Host | smart-73689752-7efa-4d05-bd86-ace6c6bbd268 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148107295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.4148107295 |
Directory | /workspace/36.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2230005086 |
Short name | T948 |
Test name | |
Test status | |
Simulation time | 9350483 ps |
CPU time | 0.7 seconds |
Started | Jul 29 06:20:47 PM PDT 24 |
Finished | Jul 29 06:20:47 PM PDT 24 |
Peak memory | 205976 kb |
Host | smart-d90c24db-12dc-4b30-b3e0-0d1541d6e14a |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230005086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2230005086 |
Directory | /workspace/37.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3879490556 |
Short name | T1031 |
Test name | |
Test status | |
Simulation time | 37391904 ps |
CPU time | 0.72 seconds |
Started | Jul 29 06:20:36 PM PDT 24 |
Finished | Jul 29 06:20:36 PM PDT 24 |
Peak memory | 205820 kb |
Host | smart-63c32883-3095-449c-98c7-e091f18f5b71 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879490556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3879490556 |
Directory | /workspace/38.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2087449184 |
Short name | T1066 |
Test name | |
Test status | |
Simulation time | 35062546 ps |
CPU time | 0.84 seconds |
Started | Jul 29 06:20:43 PM PDT 24 |
Finished | Jul 29 06:20:44 PM PDT 24 |
Peak memory | 205864 kb |
Host | smart-2b4c64a7-7307-4d91-a1f4-aefe159347b9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087449184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2087449184 |
Directory | /workspace/39.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3009781216 |
Short name | T922 |
Test name | |
Test status | |
Simulation time | 297692408 ps |
CPU time | 6.39 seconds |
Started | Jul 29 06:20:13 PM PDT 24 |
Finished | Jul 29 06:20:20 PM PDT 24 |
Peak memory | 206204 kb |
Host | smart-a77ac583-8f90-4b2f-b16b-bee2ee2d014c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009781216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3 009781216 |
Directory | /workspace/4.keymgr_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3746163628 |
Short name | T937 |
Test name | |
Test status | |
Simulation time | 2628532078 ps |
CPU time | 31.42 seconds |
Started | Jul 29 06:20:16 PM PDT 24 |
Finished | Jul 29 06:20:48 PM PDT 24 |
Peak memory | 206292 kb |
Host | smart-fe7a5c3b-cbd8-4b75-bb42-083985ad2834 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746163628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3 746163628 |
Directory | /workspace/4.keymgr_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2904176946 |
Short name | T1028 |
Test name | |
Test status | |
Simulation time | 28161973 ps |
CPU time | 0.95 seconds |
Started | Jul 29 06:20:14 PM PDT 24 |
Finished | Jul 29 06:20:15 PM PDT 24 |
Peak memory | 205936 kb |
Host | smart-8ffb944d-8541-40bb-8314-37e31ecb3713 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904176946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2 904176946 |
Directory | /workspace/4.keymgr_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1738487879 |
Short name | T994 |
Test name | |
Test status | |
Simulation time | 841853727 ps |
CPU time | 1.86 seconds |
Started | Jul 29 06:20:11 PM PDT 24 |
Finished | Jul 29 06:20:13 PM PDT 24 |
Peak memory | 214428 kb |
Host | smart-50a879d8-c0b7-4ae8-9e79-dc4aebf3e399 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738487879 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1738487879 |
Directory | /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.890758684 |
Short name | T985 |
Test name | |
Test status | |
Simulation time | 38217153 ps |
CPU time | 1.07 seconds |
Started | Jul 29 06:20:15 PM PDT 24 |
Finished | Jul 29 06:20:16 PM PDT 24 |
Peak memory | 205992 kb |
Host | smart-e8cad1fc-84ae-4267-9282-f8b07758c65a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890758684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.890758684 |
Directory | /workspace/4.keymgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1795396556 |
Short name | T958 |
Test name | |
Test status | |
Simulation time | 31402765 ps |
CPU time | 0.97 seconds |
Started | Jul 29 06:20:14 PM PDT 24 |
Finished | Jul 29 06:20:15 PM PDT 24 |
Peak memory | 205940 kb |
Host | smart-a859b04b-4af9-4e73-b5da-d0696023dcd7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795396556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1795396556 |
Directory | /workspace/4.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2378208128 |
Short name | T1019 |
Test name | |
Test status | |
Simulation time | 280941783 ps |
CPU time | 4.61 seconds |
Started | Jul 29 06:20:15 PM PDT 24 |
Finished | Jul 29 06:20:20 PM PDT 24 |
Peak memory | 206196 kb |
Host | smart-03dcc7a2-9b30-40e9-8f0e-3cf827c711a0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378208128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa me_csr_outstanding.2378208128 |
Directory | /workspace/4.keymgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1185297531 |
Short name | T1016 |
Test name | |
Test status | |
Simulation time | 57085675 ps |
CPU time | 1.6 seconds |
Started | Jul 29 06:20:15 PM PDT 24 |
Finished | Jul 29 06:20:16 PM PDT 24 |
Peak memory | 214600 kb |
Host | smart-8848b2a7-096e-4188-803b-abc717ade3c7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185297531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado w_reg_errors.1185297531 |
Directory | /workspace/4.keymgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.168508462 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 4977837296 ps |
CPU time | 10.21 seconds |
Started | Jul 29 06:20:17 PM PDT 24 |
Finished | Jul 29 06:20:27 PM PDT 24 |
Peak memory | 214772 kb |
Host | smart-05ac95ff-9662-4e56-9bc7-a8a218a336e6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168508462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST _SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k eymgr_shadow_reg_errors_with_csr_rw.168508462 |
Directory | /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.392434480 |
Short name | T966 |
Test name | |
Test status | |
Simulation time | 173860324 ps |
CPU time | 2.84 seconds |
Started | Jul 29 06:20:15 PM PDT 24 |
Finished | Jul 29 06:20:17 PM PDT 24 |
Peak memory | 214448 kb |
Host | smart-c94a1989-e076-4f2f-872b-95203057742d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392434480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.392434480 |
Directory | /workspace/4.keymgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/40.keymgr_intr_test.331307370 |
Short name | T913 |
Test name | |
Test status | |
Simulation time | 102671072 ps |
CPU time | 0.79 seconds |
Started | Jul 29 06:20:40 PM PDT 24 |
Finished | Jul 29 06:20:41 PM PDT 24 |
Peak memory | 205956 kb |
Host | smart-ac8d8b30-1e2b-461c-bd41-7495ff406682 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331307370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.331307370 |
Directory | /workspace/40.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3670875140 |
Short name | T1032 |
Test name | |
Test status | |
Simulation time | 13299227 ps |
CPU time | 0.86 seconds |
Started | Jul 29 06:20:44 PM PDT 24 |
Finished | Jul 29 06:20:45 PM PDT 24 |
Peak memory | 205932 kb |
Host | smart-c8204edf-32fb-40d7-a6a5-4e10d1ea1d5f |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670875140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3670875140 |
Directory | /workspace/41.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2304650539 |
Short name | T952 |
Test name | |
Test status | |
Simulation time | 12896169 ps |
CPU time | 0.8 seconds |
Started | Jul 29 06:20:38 PM PDT 24 |
Finished | Jul 29 06:20:39 PM PDT 24 |
Peak memory | 205928 kb |
Host | smart-3bc1d4eb-2b8a-49a9-a517-b82844cf3e60 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304650539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2304650539 |
Directory | /workspace/42.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1672905720 |
Short name | T934 |
Test name | |
Test status | |
Simulation time | 14015946 ps |
CPU time | 0.92 seconds |
Started | Jul 29 06:20:40 PM PDT 24 |
Finished | Jul 29 06:20:41 PM PDT 24 |
Peak memory | 206260 kb |
Host | smart-d33d9bdc-d458-4551-88a6-4d77d40f73a9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672905720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1672905720 |
Directory | /workspace/43.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3863938807 |
Short name | T997 |
Test name | |
Test status | |
Simulation time | 29129810 ps |
CPU time | 0.73 seconds |
Started | Jul 29 06:20:37 PM PDT 24 |
Finished | Jul 29 06:20:38 PM PDT 24 |
Peak memory | 205912 kb |
Host | smart-45e1f88f-a9f8-467b-939e-d699392c5ddd |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863938807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3863938807 |
Directory | /workspace/44.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/45.keymgr_intr_test.18681798 |
Short name | T1011 |
Test name | |
Test status | |
Simulation time | 10976517 ps |
CPU time | 0.74 seconds |
Started | Jul 29 06:20:33 PM PDT 24 |
Finished | Jul 29 06:20:34 PM PDT 24 |
Peak memory | 205888 kb |
Host | smart-e69c7e4a-2bdc-4a90-9997-961a3d0facd4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18681798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.18681798 |
Directory | /workspace/45.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/46.keymgr_intr_test.420173736 |
Short name | T944 |
Test name | |
Test status | |
Simulation time | 38920024 ps |
CPU time | 0.86 seconds |
Started | Jul 29 06:20:52 PM PDT 24 |
Finished | Jul 29 06:20:53 PM PDT 24 |
Peak memory | 205912 kb |
Host | smart-23533748-5160-4500-a55a-4a7d5110d0c8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420173736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.420173736 |
Directory | /workspace/46.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/47.keymgr_intr_test.61702995 |
Short name | T971 |
Test name | |
Test status | |
Simulation time | 38140626 ps |
CPU time | 0.68 seconds |
Started | Jul 29 06:20:39 PM PDT 24 |
Finished | Jul 29 06:20:40 PM PDT 24 |
Peak memory | 205840 kb |
Host | smart-5587569e-9013-4f2d-a7f9-3b6b8723ca17 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61702995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.61702995 |
Directory | /workspace/47.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/48.keymgr_intr_test.4090626747 |
Short name | T1001 |
Test name | |
Test status | |
Simulation time | 9911201 ps |
CPU time | 0.74 seconds |
Started | Jul 29 06:20:38 PM PDT 24 |
Finished | Jul 29 06:20:39 PM PDT 24 |
Peak memory | 205940 kb |
Host | smart-81c5c83c-83d4-460e-bad5-a9586744e0a1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090626747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.4090626747 |
Directory | /workspace/48.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1095448893 |
Short name | T990 |
Test name | |
Test status | |
Simulation time | 7618583 ps |
CPU time | 0.77 seconds |
Started | Jul 29 06:20:47 PM PDT 24 |
Finished | Jul 29 06:20:48 PM PDT 24 |
Peak memory | 205924 kb |
Host | smart-ca7f4ec8-96b2-40f5-ab5e-83e5a53f0f56 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095448893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1095448893 |
Directory | /workspace/49.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.726057179 |
Short name | T1044 |
Test name | |
Test status | |
Simulation time | 64933057 ps |
CPU time | 1.46 seconds |
Started | Jul 29 06:20:14 PM PDT 24 |
Finished | Jul 29 06:20:16 PM PDT 24 |
Peak memory | 214404 kb |
Host | smart-022a1cc5-f346-4601-a471-5bf794b27118 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726057179 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.726057179 |
Directory | /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1542815196 |
Short name | T968 |
Test name | |
Test status | |
Simulation time | 20375206 ps |
CPU time | 1.23 seconds |
Started | Jul 29 06:20:15 PM PDT 24 |
Finished | Jul 29 06:20:16 PM PDT 24 |
Peak memory | 206232 kb |
Host | smart-a552c2ec-8169-4897-88bc-a2a1a6404314 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542815196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1542815196 |
Directory | /workspace/5.keymgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2205035640 |
Short name | T1061 |
Test name | |
Test status | |
Simulation time | 20186370 ps |
CPU time | 0.71 seconds |
Started | Jul 29 06:20:14 PM PDT 24 |
Finished | Jul 29 06:20:15 PM PDT 24 |
Peak memory | 205956 kb |
Host | smart-67149c30-5aec-41b1-ba8a-46d88403464b |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205035640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2205035640 |
Directory | /workspace/5.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.4047144616 |
Short name | T1080 |
Test name | |
Test status | |
Simulation time | 113566104 ps |
CPU time | 1.78 seconds |
Started | Jul 29 06:20:19 PM PDT 24 |
Finished | Jul 29 06:20:21 PM PDT 24 |
Peak memory | 206052 kb |
Host | smart-f498dad7-e614-4bc8-9ebc-b49d37232215 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047144616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa me_csr_outstanding.4047144616 |
Directory | /workspace/5.keymgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3128461593 |
Short name | T936 |
Test name | |
Test status | |
Simulation time | 319393496 ps |
CPU time | 3.86 seconds |
Started | Jul 29 06:20:17 PM PDT 24 |
Finished | Jul 29 06:20:21 PM PDT 24 |
Peak memory | 214732 kb |
Host | smart-42bb49dd-73ce-4d1f-b2a5-f42c01df933d |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128461593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. keymgr_shadow_reg_errors_with_csr_rw.3128461593 |
Directory | /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3360755805 |
Short name | T1076 |
Test name | |
Test status | |
Simulation time | 118856723 ps |
CPU time | 2.09 seconds |
Started | Jul 29 06:20:18 PM PDT 24 |
Finished | Jul 29 06:20:20 PM PDT 24 |
Peak memory | 216524 kb |
Host | smart-57118010-9bf5-4cff-9bd6-0726aed32c09 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360755805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3360755805 |
Directory | /workspace/5.keymgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1565045702 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 807557892 ps |
CPU time | 5.93 seconds |
Started | Jul 29 06:20:17 PM PDT 24 |
Finished | Jul 29 06:20:23 PM PDT 24 |
Peak memory | 214332 kb |
Host | smart-2d693c54-2b63-41c2-b803-5a75177fe217 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565045702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err .1565045702 |
Directory | /workspace/5.keymgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.84377649 |
Short name | T925 |
Test name | |
Test status | |
Simulation time | 33598769 ps |
CPU time | 1.62 seconds |
Started | Jul 29 06:20:14 PM PDT 24 |
Finished | Jul 29 06:20:15 PM PDT 24 |
Peak memory | 214344 kb |
Host | smart-08535b0a-44c9-4b21-813a-b1403d14c42a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84377649 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.84377649 |
Directory | /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3487216059 |
Short name | T920 |
Test name | |
Test status | |
Simulation time | 26197544 ps |
CPU time | 1.1 seconds |
Started | Jul 29 06:20:19 PM PDT 24 |
Finished | Jul 29 06:20:20 PM PDT 24 |
Peak memory | 206116 kb |
Host | smart-4370d3e5-4b99-4a14-9aa4-f970275f5d83 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487216059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3487216059 |
Directory | /workspace/6.keymgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.keymgr_intr_test.4235989255 |
Short name | T964 |
Test name | |
Test status | |
Simulation time | 28658732 ps |
CPU time | 0.95 seconds |
Started | Jul 29 06:20:15 PM PDT 24 |
Finished | Jul 29 06:20:16 PM PDT 24 |
Peak memory | 206012 kb |
Host | smart-d8e635a2-7f0a-4122-8fe5-b097158847d2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235989255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.4235989255 |
Directory | /workspace/6.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.711978403 |
Short name | T933 |
Test name | |
Test status | |
Simulation time | 233562255 ps |
CPU time | 2.23 seconds |
Started | Jul 29 06:20:13 PM PDT 24 |
Finished | Jul 29 06:20:16 PM PDT 24 |
Peak memory | 206216 kb |
Host | smart-5cb2aad6-2cc5-41a1-968c-18ed6e6d8527 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711978403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam e_csr_outstanding.711978403 |
Directory | /workspace/6.keymgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.4138329599 |
Short name | T1013 |
Test name | |
Test status | |
Simulation time | 130835094 ps |
CPU time | 3.67 seconds |
Started | Jul 29 06:20:14 PM PDT 24 |
Finished | Jul 29 06:20:18 PM PDT 24 |
Peak memory | 218908 kb |
Host | smart-0c960bd6-c2fe-4567-a652-fac48bea0a5b |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138329599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado w_reg_errors.4138329599 |
Directory | /workspace/6.keymgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1108215330 |
Short name | T950 |
Test name | |
Test status | |
Simulation time | 3695442309 ps |
CPU time | 9.51 seconds |
Started | Jul 29 06:20:19 PM PDT 24 |
Finished | Jul 29 06:20:28 PM PDT 24 |
Peak memory | 214792 kb |
Host | smart-d2f49aba-ccdd-41d1-88c2-379b1ba89c27 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108215330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. keymgr_shadow_reg_errors_with_csr_rw.1108215330 |
Directory | /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3715270010 |
Short name | T1007 |
Test name | |
Test status | |
Simulation time | 587165275 ps |
CPU time | 5.43 seconds |
Started | Jul 29 06:20:21 PM PDT 24 |
Finished | Jul 29 06:20:26 PM PDT 24 |
Peak memory | 217488 kb |
Host | smart-e9db0d50-b69a-4912-8bcd-00ea384002e7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715270010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3715270010 |
Directory | /workspace/6.keymgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1265820355 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 195615898 ps |
CPU time | 3.21 seconds |
Started | Jul 29 06:20:18 PM PDT 24 |
Finished | Jul 29 06:20:22 PM PDT 24 |
Peak memory | 214256 kb |
Host | smart-c4994edb-8623-4014-95c9-d8f6ca68751f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265820355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err .1265820355 |
Directory | /workspace/6.keymgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2247279722 |
Short name | T919 |
Test name | |
Test status | |
Simulation time | 72662140 ps |
CPU time | 2.25 seconds |
Started | Jul 29 06:20:32 PM PDT 24 |
Finished | Jul 29 06:20:34 PM PDT 24 |
Peak memory | 219080 kb |
Host | smart-bb69fc72-88dd-458f-ae98-dbe9813b341d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247279722 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2247279722 |
Directory | /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3024910996 |
Short name | T1012 |
Test name | |
Test status | |
Simulation time | 32609111 ps |
CPU time | 1.16 seconds |
Started | Jul 29 06:20:15 PM PDT 24 |
Finished | Jul 29 06:20:16 PM PDT 24 |
Peak memory | 206108 kb |
Host | smart-607b4073-51a0-49e9-b72a-56a638e10592 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024910996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3024910996 |
Directory | /workspace/7.keymgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3375491148 |
Short name | T923 |
Test name | |
Test status | |
Simulation time | 14791754 ps |
CPU time | 0.7 seconds |
Started | Jul 29 06:20:16 PM PDT 24 |
Finished | Jul 29 06:20:16 PM PDT 24 |
Peak memory | 205836 kb |
Host | smart-4cb927e6-981d-491d-b89a-26c3ef15e881 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375491148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3375491148 |
Directory | /workspace/7.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2945631937 |
Short name | T959 |
Test name | |
Test status | |
Simulation time | 147902266 ps |
CPU time | 2.5 seconds |
Started | Jul 29 06:20:14 PM PDT 24 |
Finished | Jul 29 06:20:22 PM PDT 24 |
Peak memory | 206112 kb |
Host | smart-0e89b0c6-3edf-419e-aa30-9f1060ef53c6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945631937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa me_csr_outstanding.2945631937 |
Directory | /workspace/7.keymgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.4215737615 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 107232709 ps |
CPU time | 2.32 seconds |
Started | Jul 29 06:20:29 PM PDT 24 |
Finished | Jul 29 06:20:32 PM PDT 24 |
Peak memory | 214584 kb |
Host | smart-d05b5322-9a8e-44d3-903f-ac31cd018d50 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215737615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado w_reg_errors.4215737615 |
Directory | /workspace/7.keymgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2545278032 |
Short name | T1038 |
Test name | |
Test status | |
Simulation time | 427273420 ps |
CPU time | 8.67 seconds |
Started | Jul 29 06:20:21 PM PDT 24 |
Finished | Jul 29 06:20:30 PM PDT 24 |
Peak memory | 214676 kb |
Host | smart-8ff6715f-e0f5-4415-a664-e2b2f50ddab8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545278032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7. keymgr_shadow_reg_errors_with_csr_rw.2545278032 |
Directory | /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3874403724 |
Short name | T1018 |
Test name | |
Test status | |
Simulation time | 509946796 ps |
CPU time | 4.68 seconds |
Started | Jul 29 06:20:14 PM PDT 24 |
Finished | Jul 29 06:20:18 PM PDT 24 |
Peak memory | 222644 kb |
Host | smart-614c976a-d88d-4ffe-aa17-88759794934f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874403724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3874403724 |
Directory | /workspace/7.keymgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2349387144 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 2084915588 ps |
CPU time | 9.47 seconds |
Started | Jul 29 06:20:15 PM PDT 24 |
Finished | Jul 29 06:20:25 PM PDT 24 |
Peak memory | 214268 kb |
Host | smart-619fe1dd-9717-42dc-830b-a91fa7746d88 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349387144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err .2349387144 |
Directory | /workspace/7.keymgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.960482863 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 346860915 ps |
CPU time | 1.71 seconds |
Started | Jul 29 06:20:23 PM PDT 24 |
Finished | Jul 29 06:20:25 PM PDT 24 |
Peak memory | 214544 kb |
Host | smart-693f83e1-0d52-4988-99b8-ad8d263d3c2a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960482863 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.960482863 |
Directory | /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1467961043 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 36785271 ps |
CPU time | 0.97 seconds |
Started | Jul 29 06:20:22 PM PDT 24 |
Finished | Jul 29 06:20:23 PM PDT 24 |
Peak memory | 205908 kb |
Host | smart-7407f5b4-dc27-420d-9aa1-804803f7575f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467961043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1467961043 |
Directory | /workspace/8.keymgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.keymgr_intr_test.4048547232 |
Short name | T928 |
Test name | |
Test status | |
Simulation time | 43676726 ps |
CPU time | 0.8 seconds |
Started | Jul 29 06:20:18 PM PDT 24 |
Finished | Jul 29 06:20:19 PM PDT 24 |
Peak memory | 205948 kb |
Host | smart-80e96503-02ea-41c7-ab69-1ed1ea5ad92b |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048547232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.4048547232 |
Directory | /workspace/8.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1479200641 |
Short name | T998 |
Test name | |
Test status | |
Simulation time | 44425073 ps |
CPU time | 1.39 seconds |
Started | Jul 29 06:20:23 PM PDT 24 |
Finished | Jul 29 06:20:25 PM PDT 24 |
Peak memory | 206168 kb |
Host | smart-9e33f062-8e5b-43be-9394-2e0d1a8539cc |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479200641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa me_csr_outstanding.1479200641 |
Directory | /workspace/8.keymgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2823150305 |
Short name | T981 |
Test name | |
Test status | |
Simulation time | 176293639 ps |
CPU time | 4.83 seconds |
Started | Jul 29 06:20:14 PM PDT 24 |
Finished | Jul 29 06:20:19 PM PDT 24 |
Peak memory | 214568 kb |
Host | smart-7f603680-a760-4ea0-9b36-982fd2df2f09 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823150305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado w_reg_errors.2823150305 |
Directory | /workspace/8.keymgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3321615763 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 305952644 ps |
CPU time | 8.49 seconds |
Started | Jul 29 06:20:19 PM PDT 24 |
Finished | Jul 29 06:20:28 PM PDT 24 |
Peak memory | 220728 kb |
Host | smart-842f7acf-cc79-4e14-a700-2aeb571f1e81 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321615763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. keymgr_shadow_reg_errors_with_csr_rw.3321615763 |
Directory | /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1257741714 |
Short name | T1050 |
Test name | |
Test status | |
Simulation time | 86713378 ps |
CPU time | 2.13 seconds |
Started | Jul 29 06:20:16 PM PDT 24 |
Finished | Jul 29 06:20:19 PM PDT 24 |
Peak memory | 215356 kb |
Host | smart-e03584cb-e29e-47a8-9e2d-7bda6e110ca6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257741714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1257741714 |
Directory | /workspace/8.keymgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.859666035 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 219135361 ps |
CPU time | 3.01 seconds |
Started | Jul 29 06:20:16 PM PDT 24 |
Finished | Jul 29 06:20:19 PM PDT 24 |
Peak memory | 214432 kb |
Host | smart-89cb3bae-5c4e-41d5-bbb5-9176a998c41a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859666035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err. 859666035 |
Directory | /workspace/8.keymgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2581620808 |
Short name | T1008 |
Test name | |
Test status | |
Simulation time | 77693921 ps |
CPU time | 1.51 seconds |
Started | Jul 29 06:20:17 PM PDT 24 |
Finished | Jul 29 06:20:18 PM PDT 24 |
Peak memory | 214388 kb |
Host | smart-cc3a9cb1-8825-4bdb-8ede-fc93061ab6da |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581620808 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2581620808 |
Directory | /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.841895396 |
Short name | T1056 |
Test name | |
Test status | |
Simulation time | 98682514 ps |
CPU time | 1.51 seconds |
Started | Jul 29 06:20:24 PM PDT 24 |
Finished | Jul 29 06:20:26 PM PDT 24 |
Peak memory | 206156 kb |
Host | smart-e150a7f9-c22c-40aa-8016-6d9354f6ce29 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841895396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.841895396 |
Directory | /workspace/9.keymgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.keymgr_intr_test.4168832348 |
Short name | T916 |
Test name | |
Test status | |
Simulation time | 34080058 ps |
CPU time | 0.77 seconds |
Started | Jul 29 06:20:21 PM PDT 24 |
Finished | Jul 29 06:20:22 PM PDT 24 |
Peak memory | 205836 kb |
Host | smart-eee555b3-4f6a-4046-82fd-3142d26fef36 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168832348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.4168832348 |
Directory | /workspace/9.keymgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.747026217 |
Short name | T1046 |
Test name | |
Test status | |
Simulation time | 82897050 ps |
CPU time | 1.45 seconds |
Started | Jul 29 06:20:18 PM PDT 24 |
Finished | Jul 29 06:20:19 PM PDT 24 |
Peak memory | 206168 kb |
Host | smart-c8d041c7-a1e0-4383-8e03-ad6d50a5f1c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747026217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam e_csr_outstanding.747026217 |
Directory | /workspace/9.keymgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1943490540 |
Short name | T996 |
Test name | |
Test status | |
Simulation time | 652990154 ps |
CPU time | 5.07 seconds |
Started | Jul 29 06:20:24 PM PDT 24 |
Finished | Jul 29 06:20:29 PM PDT 24 |
Peak memory | 214664 kb |
Host | smart-0721beb7-e83c-4344-9b84-882c5244e552 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943490540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado w_reg_errors.1943490540 |
Directory | /workspace/9.keymgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2044751352 |
Short name | T1022 |
Test name | |
Test status | |
Simulation time | 483464225 ps |
CPU time | 8.79 seconds |
Started | Jul 29 06:20:15 PM PDT 24 |
Finished | Jul 29 06:20:24 PM PDT 24 |
Peak memory | 220672 kb |
Host | smart-ee7b1700-24a2-4429-a965-29e74bf071d6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044751352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. keymgr_shadow_reg_errors_with_csr_rw.2044751352 |
Directory | /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.89982138 |
Short name | T945 |
Test name | |
Test status | |
Simulation time | 323342690 ps |
CPU time | 3.2 seconds |
Started | Jul 29 06:20:21 PM PDT 24 |
Finished | Jul 29 06:20:24 PM PDT 24 |
Peak memory | 214596 kb |
Host | smart-78c26955-4e22-444b-9fed-411039b3da1c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89982138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.89982138 |
Directory | /workspace/9.keymgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.4218276067 |
Short name | T1059 |
Test name | |
Test status | |
Simulation time | 309686337 ps |
CPU time | 8.42 seconds |
Started | Jul 29 06:20:25 PM PDT 24 |
Finished | Jul 29 06:20:33 PM PDT 24 |
Peak memory | 215604 kb |
Host | smart-118f7957-f020-4425-9b00-0ac4c3de4c4d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218276067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err .4218276067 |
Directory | /workspace/9.keymgr_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.keymgr_alert_test.984092973 |
Short name | T796 |
Test name | |
Test status | |
Simulation time | 13997364 ps |
CPU time | 0.89 seconds |
Started | Jul 29 07:34:35 PM PDT 24 |
Finished | Jul 29 07:34:36 PM PDT 24 |
Peak memory | 206236 kb |
Host | smart-13d76b67-1c01-4fcd-ac50-50d02bba046f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984092973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.984092973 |
Directory | /workspace/0.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/0.keymgr_cfg_regwen.1251581082 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 119749930 ps |
CPU time | 4.85 seconds |
Started | Jul 29 07:34:37 PM PDT 24 |
Finished | Jul 29 07:34:42 PM PDT 24 |
Peak memory | 214328 kb |
Host | smart-429a4909-4815-4fa3-a4f0-c1399f4f3cb9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1251581082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1251581082 |
Directory | /workspace/0.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/0.keymgr_custom_cm.2376395705 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 1627637799 ps |
CPU time | 5.58 seconds |
Started | Jul 29 07:34:40 PM PDT 24 |
Finished | Jul 29 07:34:46 PM PDT 24 |
Peak memory | 218212 kb |
Host | smart-4bbc4494-287d-413b-926d-f0e9a05fe4c6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2376395705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2376395705 |
Directory | /workspace/0.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/0.keymgr_direct_to_disabled.2127200244 |
Short name | T712 |
Test name | |
Test status | |
Simulation time | 271231411 ps |
CPU time | 3.21 seconds |
Started | Jul 29 07:34:39 PM PDT 24 |
Finished | Jul 29 07:34:42 PM PDT 24 |
Peak memory | 210176 kb |
Host | smart-6764e69f-3c65-4a64-80ef-7016429064fc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2127200244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2127200244 |
Directory | /workspace/0.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/0.keymgr_random.3953622353 |
Short name | T894 |
Test name | |
Test status | |
Simulation time | 5632752228 ps |
CPU time | 15.11 seconds |
Started | Jul 29 07:34:36 PM PDT 24 |
Finished | Jul 29 07:34:52 PM PDT 24 |
Peak memory | 209240 kb |
Host | smart-5c72d4a5-6065-4a8e-9f1f-5cad9a2c69c2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3953622353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3953622353 |
Directory | /workspace/0.keymgr_random/latest |
Test location | /workspace/coverage/default/0.keymgr_sideload.1946074682 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 295513595 ps |
CPU time | 3.66 seconds |
Started | Jul 29 07:34:39 PM PDT 24 |
Finished | Jul 29 07:34:43 PM PDT 24 |
Peak memory | 208632 kb |
Host | smart-0e293b4c-b1ef-49fa-bf47-f94daea1cf5d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1946074682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1946074682 |
Directory | /workspace/0.keymgr_sideload/latest |
Test location | /workspace/coverage/default/0.keymgr_sideload_kmac.3295013544 |
Short name | T658 |
Test name | |
Test status | |
Simulation time | 145740806 ps |
CPU time | 4.65 seconds |
Started | Jul 29 07:34:39 PM PDT 24 |
Finished | Jul 29 07:34:44 PM PDT 24 |
Peak memory | 208940 kb |
Host | smart-5f5fe9b6-fec7-4382-8fc0-ca08b355fe19 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295013544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3295013544 |
Directory | /workspace/0.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/0.keymgr_sideload_otbn.3503322420 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 155592356 ps |
CPU time | 2.89 seconds |
Started | Jul 29 07:34:36 PM PDT 24 |
Finished | Jul 29 07:34:39 PM PDT 24 |
Peak memory | 208856 kb |
Host | smart-9f59ca6a-bbbc-42d8-bda1-92ade9afe914 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503322420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3503322420 |
Directory | /workspace/0.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/0.keymgr_sideload_protect.3819110908 |
Short name | T840 |
Test name | |
Test status | |
Simulation time | 40006765 ps |
CPU time | 2.14 seconds |
Started | Jul 29 07:34:38 PM PDT 24 |
Finished | Jul 29 07:34:40 PM PDT 24 |
Peak memory | 206908 kb |
Host | smart-d3e015b3-7264-4e7e-aca6-186074543cdb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3819110908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3819110908 |
Directory | /workspace/0.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/0.keymgr_smoke.1287748591 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 559150834 ps |
CPU time | 3.49 seconds |
Started | Jul 29 07:34:35 PM PDT 24 |
Finished | Jul 29 07:34:39 PM PDT 24 |
Peak memory | 206900 kb |
Host | smart-64253571-ec94-4502-a48b-892269849a64 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1287748591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1287748591 |
Directory | /workspace/0.keymgr_smoke/latest |
Test location | /workspace/coverage/default/0.keymgr_stress_all.2479610042 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 2172983897 ps |
CPU time | 30.81 seconds |
Started | Jul 29 07:34:38 PM PDT 24 |
Finished | Jul 29 07:35:09 PM PDT 24 |
Peak memory | 219596 kb |
Host | smart-1648314f-41ac-44db-99c3-d2fff512bba6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479610042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2479610042 |
Directory | /workspace/0.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/0.keymgr_sw_invalid_input.3213172961 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 5446203745 ps |
CPU time | 55.53 seconds |
Started | Jul 29 07:34:40 PM PDT 24 |
Finished | Jul 29 07:35:36 PM PDT 24 |
Peak memory | 214412 kb |
Host | smart-091f034b-ea64-4a74-a82d-bccc4ecda988 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3213172961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3213172961 |
Directory | /workspace/0.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/0.keymgr_sync_async_fault_cross.467162885 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 94244617 ps |
CPU time | 1.56 seconds |
Started | Jul 29 07:34:35 PM PDT 24 |
Finished | Jul 29 07:34:37 PM PDT 24 |
Peak memory | 209808 kb |
Host | smart-26e98090-fdc2-4734-9f3e-f9a700837aa2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=467162885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.467162885 |
Directory | /workspace/0.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/1.keymgr_alert_test.3545939438 |
Short name | T859 |
Test name | |
Test status | |
Simulation time | 19125037 ps |
CPU time | 0.76 seconds |
Started | Jul 29 07:34:42 PM PDT 24 |
Finished | Jul 29 07:34:43 PM PDT 24 |
Peak memory | 205980 kb |
Host | smart-6cff3ed9-efa5-4341-8f36-d08cc4733c2f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545939438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3545939438 |
Directory | /workspace/1.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/1.keymgr_kmac_rsp_err.758994264 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 126213728 ps |
CPU time | 3.58 seconds |
Started | Jul 29 07:34:35 PM PDT 24 |
Finished | Jul 29 07:34:39 PM PDT 24 |
Peak memory | 214272 kb |
Host | smart-5e4c8c64-3c71-4acc-8bbc-f9992580071f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=758994264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.758994264 |
Directory | /workspace/1.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/1.keymgr_lc_disable.2606458085 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 1353482578 ps |
CPU time | 19.62 seconds |
Started | Jul 29 07:34:37 PM PDT 24 |
Finished | Jul 29 07:34:57 PM PDT 24 |
Peak memory | 222484 kb |
Host | smart-9bcbdee6-8cab-44a9-a81d-64777a7d2886 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2606458085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2606458085 |
Directory | /workspace/1.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/1.keymgr_random.1233796238 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 184373706 ps |
CPU time | 5.3 seconds |
Started | Jul 29 07:34:38 PM PDT 24 |
Finished | Jul 29 07:34:43 PM PDT 24 |
Peak memory | 208812 kb |
Host | smart-29d5e468-ba70-478a-83f8-844a6b40f546 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1233796238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1233796238 |
Directory | /workspace/1.keymgr_random/latest |
Test location | /workspace/coverage/default/1.keymgr_sideload.3484034423 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 41264274 ps |
CPU time | 1.85 seconds |
Started | Jul 29 07:34:36 PM PDT 24 |
Finished | Jul 29 07:34:38 PM PDT 24 |
Peak memory | 206916 kb |
Host | smart-d32bc0f0-7402-40b6-88d3-9b1ce11ff48f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3484034423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3484034423 |
Directory | /workspace/1.keymgr_sideload/latest |
Test location | /workspace/coverage/default/1.keymgr_sideload_kmac.3985793257 |
Short name | T685 |
Test name | |
Test status | |
Simulation time | 1025423436 ps |
CPU time | 20.72 seconds |
Started | Jul 29 07:34:39 PM PDT 24 |
Finished | Jul 29 07:35:00 PM PDT 24 |
Peak memory | 208660 kb |
Host | smart-1b8b3a3f-d7ee-4631-96d1-f37cb25618fd |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985793257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3985793257 |
Directory | /workspace/1.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/1.keymgr_sideload_otbn.3473085876 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 447108437 ps |
CPU time | 3.13 seconds |
Started | Jul 29 07:34:33 PM PDT 24 |
Finished | Jul 29 07:34:37 PM PDT 24 |
Peak memory | 206868 kb |
Host | smart-64fc8769-4b7d-4447-a9e6-371a984a1119 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473085876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3473085876 |
Directory | /workspace/1.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/1.keymgr_sideload_protect.1826115550 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 100486117 ps |
CPU time | 2.25 seconds |
Started | Jul 29 07:34:39 PM PDT 24 |
Finished | Jul 29 07:34:42 PM PDT 24 |
Peak memory | 208640 kb |
Host | smart-cd96f5e9-1688-46f7-8d9f-d6f97f8ae350 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1826115550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1826115550 |
Directory | /workspace/1.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/1.keymgr_smoke.4166953362 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 92259526 ps |
CPU time | 2.59 seconds |
Started | Jul 29 07:34:38 PM PDT 24 |
Finished | Jul 29 07:34:40 PM PDT 24 |
Peak memory | 208156 kb |
Host | smart-dbadfd9b-a05d-406f-a57b-c8e286283482 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4166953362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.4166953362 |
Directory | /workspace/1.keymgr_smoke/latest |
Test location | /workspace/coverage/default/1.keymgr_sw_invalid_input.848512204 |
Short name | T636 |
Test name | |
Test status | |
Simulation time | 114161709 ps |
CPU time | 4.46 seconds |
Started | Jul 29 07:34:35 PM PDT 24 |
Finished | Jul 29 07:34:40 PM PDT 24 |
Peak memory | 208912 kb |
Host | smart-e8ffc367-23bc-47e0-8e79-4dace7b67e37 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=848512204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.848512204 |
Directory | /workspace/1.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1292514067 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 136920495 ps |
CPU time | 1.61 seconds |
Started | Jul 29 07:34:36 PM PDT 24 |
Finished | Jul 29 07:34:37 PM PDT 24 |
Peak memory | 209900 kb |
Host | smart-1780a487-6411-47fe-9771-21f34810fe0c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1292514067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1292514067 |
Directory | /workspace/1.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/10.keymgr_alert_test.3316192064 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 75665490 ps |
CPU time | 0.87 seconds |
Started | Jul 29 07:34:57 PM PDT 24 |
Finished | Jul 29 07:34:58 PM PDT 24 |
Peak memory | 205940 kb |
Host | smart-915d6417-afa5-49bc-aab5-8e5d258a5cfb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316192064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3316192064 |
Directory | /workspace/10.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/10.keymgr_cfg_regwen.2110903245 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 163352501 ps |
CPU time | 8.98 seconds |
Started | Jul 29 07:35:06 PM PDT 24 |
Finished | Jul 29 07:35:15 PM PDT 24 |
Peak memory | 214872 kb |
Host | smart-da96001a-ab8d-4324-bd56-36698309d0d1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2110903245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2110903245 |
Directory | /workspace/10.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/10.keymgr_custom_cm.532720171 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 1116502866 ps |
CPU time | 2.94 seconds |
Started | Jul 29 07:35:02 PM PDT 24 |
Finished | Jul 29 07:35:05 PM PDT 24 |
Peak memory | 220356 kb |
Host | smart-bb67d1ee-92e2-4471-a0b9-b86f66cb80ba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=532720171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.532720171 |
Directory | /workspace/10.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/10.keymgr_direct_to_disabled.905921649 |
Short name | T739 |
Test name | |
Test status | |
Simulation time | 749652307 ps |
CPU time | 16.21 seconds |
Started | Jul 29 07:35:00 PM PDT 24 |
Finished | Jul 29 07:35:17 PM PDT 24 |
Peak memory | 218228 kb |
Host | smart-6521992b-f5eb-427c-842c-318f93a4ad45 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=905921649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.905921649 |
Directory | /workspace/10.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/10.keymgr_kmac_rsp_err.3292398815 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 34338393 ps |
CPU time | 2.49 seconds |
Started | Jul 29 07:35:03 PM PDT 24 |
Finished | Jul 29 07:35:06 PM PDT 24 |
Peak memory | 214348 kb |
Host | smart-0d4f5b07-28bf-47e9-be1b-0929042a0e34 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3292398815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3292398815 |
Directory | /workspace/10.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/10.keymgr_lc_disable.1529160150 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 86229561 ps |
CPU time | 3.52 seconds |
Started | Jul 29 07:34:55 PM PDT 24 |
Finished | Jul 29 07:34:58 PM PDT 24 |
Peak memory | 214304 kb |
Host | smart-0fa042ed-2030-45bd-9974-dd58d48fbe7b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1529160150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1529160150 |
Directory | /workspace/10.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/10.keymgr_random.2862618132 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 121220301 ps |
CPU time | 3.86 seconds |
Started | Jul 29 07:35:02 PM PDT 24 |
Finished | Jul 29 07:35:06 PM PDT 24 |
Peak memory | 207588 kb |
Host | smart-d2afb9b1-dceb-48e8-b99c-1fa74cea2e8b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2862618132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2862618132 |
Directory | /workspace/10.keymgr_random/latest |
Test location | /workspace/coverage/default/10.keymgr_sideload.788923331 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 187618621 ps |
CPU time | 2.59 seconds |
Started | Jul 29 07:35:03 PM PDT 24 |
Finished | Jul 29 07:35:05 PM PDT 24 |
Peak memory | 206872 kb |
Host | smart-46ea0c62-b894-46ba-a1e1-4aed751f91ab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=788923331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.788923331 |
Directory | /workspace/10.keymgr_sideload/latest |
Test location | /workspace/coverage/default/10.keymgr_sideload_aes.2164577613 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 958559226 ps |
CPU time | 5.76 seconds |
Started | Jul 29 07:35:07 PM PDT 24 |
Finished | Jul 29 07:35:13 PM PDT 24 |
Peak memory | 208004 kb |
Host | smart-97465d04-668b-443a-94e7-a541b6109502 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164577613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2164577613 |
Directory | /workspace/10.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/10.keymgr_sideload_kmac.390902174 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 88823291 ps |
CPU time | 4.02 seconds |
Started | Jul 29 07:35:00 PM PDT 24 |
Finished | Jul 29 07:35:04 PM PDT 24 |
Peak memory | 208512 kb |
Host | smart-23475c79-6380-4fe7-9265-ef25a4116d7f |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390902174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.390902174 |
Directory | /workspace/10.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/10.keymgr_sideload_otbn.1006835357 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 47758892 ps |
CPU time | 2.73 seconds |
Started | Jul 29 07:35:06 PM PDT 24 |
Finished | Jul 29 07:35:09 PM PDT 24 |
Peak memory | 207756 kb |
Host | smart-99ef4cd2-bfac-474e-aa86-600b7f70bc7f |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006835357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1006835357 |
Directory | /workspace/10.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/10.keymgr_sideload_protect.1281130391 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 1513520707 ps |
CPU time | 4.4 seconds |
Started | Jul 29 07:35:05 PM PDT 24 |
Finished | Jul 29 07:35:09 PM PDT 24 |
Peak memory | 208896 kb |
Host | smart-029521d6-9ea9-41e6-b1f2-023023545009 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1281130391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1281130391 |
Directory | /workspace/10.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/10.keymgr_smoke.1382347262 |
Short name | T854 |
Test name | |
Test status | |
Simulation time | 166046683 ps |
CPU time | 4.09 seconds |
Started | Jul 29 07:34:55 PM PDT 24 |
Finished | Jul 29 07:34:59 PM PDT 24 |
Peak memory | 208372 kb |
Host | smart-4f72849b-a600-48a9-a893-4df58bf8964d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1382347262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1382347262 |
Directory | /workspace/10.keymgr_smoke/latest |
Test location | /workspace/coverage/default/10.keymgr_sw_invalid_input.1392071338 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 535404831 ps |
CPU time | 6.18 seconds |
Started | Jul 29 07:35:03 PM PDT 24 |
Finished | Jul 29 07:35:09 PM PDT 24 |
Peak memory | 214340 kb |
Host | smart-8416255f-17af-4d98-8fd1-56c01a94cafe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1392071338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1392071338 |
Directory | /workspace/10.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/11.keymgr_custom_cm.826076834 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 459636550 ps |
CPU time | 3.68 seconds |
Started | Jul 29 07:35:07 PM PDT 24 |
Finished | Jul 29 07:35:11 PM PDT 24 |
Peak memory | 221836 kb |
Host | smart-1ac3426e-19e0-4226-b561-2a2e350af5de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=826076834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.826076834 |
Directory | /workspace/11.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/11.keymgr_direct_to_disabled.1633018313 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 138380339 ps |
CPU time | 3.22 seconds |
Started | Jul 29 07:34:58 PM PDT 24 |
Finished | Jul 29 07:35:01 PM PDT 24 |
Peak memory | 214296 kb |
Host | smart-4b213b27-36c6-405c-8e08-81a9097b4913 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1633018313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1633018313 |
Directory | /workspace/11.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/11.keymgr_hwsw_invalid_input.466969661 |
Short name | T881 |
Test name | |
Test status | |
Simulation time | 27108195 ps |
CPU time | 1.81 seconds |
Started | Jul 29 07:35:07 PM PDT 24 |
Finished | Jul 29 07:35:09 PM PDT 24 |
Peak memory | 214336 kb |
Host | smart-7227daf4-4d62-4885-9094-5308bc634fc0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=466969661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.466969661 |
Directory | /workspace/11.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/11.keymgr_lc_disable.2886756461 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 265879018 ps |
CPU time | 4.03 seconds |
Started | Jul 29 07:35:01 PM PDT 24 |
Finished | Jul 29 07:35:05 PM PDT 24 |
Peak memory | 214340 kb |
Host | smart-18f0819e-c2af-468c-907a-d602f4541186 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2886756461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2886756461 |
Directory | /workspace/11.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/11.keymgr_random.3032392809 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 173435701 ps |
CPU time | 3.37 seconds |
Started | Jul 29 07:35:03 PM PDT 24 |
Finished | Jul 29 07:35:07 PM PDT 24 |
Peak memory | 218336 kb |
Host | smart-1e97c32d-250d-48e3-8028-0e175518221b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3032392809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3032392809 |
Directory | /workspace/11.keymgr_random/latest |
Test location | /workspace/coverage/default/11.keymgr_sideload.2516207863 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 357788653 ps |
CPU time | 4.16 seconds |
Started | Jul 29 07:35:02 PM PDT 24 |
Finished | Jul 29 07:35:07 PM PDT 24 |
Peak memory | 208548 kb |
Host | smart-8f91b833-287a-4bdf-80b9-eb580527723f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2516207863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2516207863 |
Directory | /workspace/11.keymgr_sideload/latest |
Test location | /workspace/coverage/default/11.keymgr_sideload_aes.2495130103 |
Short name | T764 |
Test name | |
Test status | |
Simulation time | 37565761 ps |
CPU time | 2.58 seconds |
Started | Jul 29 07:34:54 PM PDT 24 |
Finished | Jul 29 07:34:56 PM PDT 24 |
Peak memory | 208456 kb |
Host | smart-b868b54c-1071-4fe1-81af-bea3bfef65c8 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495130103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2495130103 |
Directory | /workspace/11.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/11.keymgr_sideload_kmac.1916707068 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 4019404168 ps |
CPU time | 39.6 seconds |
Started | Jul 29 07:35:06 PM PDT 24 |
Finished | Jul 29 07:35:46 PM PDT 24 |
Peak memory | 208996 kb |
Host | smart-85977be1-1363-462b-9d9f-aea23c47c028 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916707068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1916707068 |
Directory | /workspace/11.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/11.keymgr_sideload_otbn.881396461 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 5436135255 ps |
CPU time | 34.43 seconds |
Started | Jul 29 07:34:54 PM PDT 24 |
Finished | Jul 29 07:35:28 PM PDT 24 |
Peak memory | 208460 kb |
Host | smart-e3a9902b-0efb-442c-90af-a1e5446a5985 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881396461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.881396461 |
Directory | /workspace/11.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/11.keymgr_sideload_protect.2812930204 |
Short name | T728 |
Test name | |
Test status | |
Simulation time | 108292953 ps |
CPU time | 2.92 seconds |
Started | Jul 29 07:35:00 PM PDT 24 |
Finished | Jul 29 07:35:03 PM PDT 24 |
Peak memory | 215976 kb |
Host | smart-c5cd9a40-a6fa-4f50-a8ad-85b3a2ccaae1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2812930204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2812930204 |
Directory | /workspace/11.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/11.keymgr_smoke.308848300 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 232538591 ps |
CPU time | 2.47 seconds |
Started | Jul 29 07:35:00 PM PDT 24 |
Finished | Jul 29 07:35:03 PM PDT 24 |
Peak memory | 207016 kb |
Host | smart-e2fb826b-54db-43f6-abd5-d97e1061cdfe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=308848300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.308848300 |
Directory | /workspace/11.keymgr_smoke/latest |
Test location | /workspace/coverage/default/11.keymgr_stress_all.4204964953 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 193888762 ps |
CPU time | 5.51 seconds |
Started | Jul 29 07:35:07 PM PDT 24 |
Finished | Jul 29 07:35:12 PM PDT 24 |
Peak memory | 219500 kb |
Host | smart-2a2c52b9-c71f-4504-a597-a19127ed6b5e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204964953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.4204964953 |
Directory | /workspace/11.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/11.keymgr_sw_invalid_input.1798047091 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 1249190061 ps |
CPU time | 14.89 seconds |
Started | Jul 29 07:35:07 PM PDT 24 |
Finished | Jul 29 07:35:22 PM PDT 24 |
Peak memory | 214300 kb |
Host | smart-1ef467b6-44b1-4235-8bab-2193e15d5257 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1798047091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1798047091 |
Directory | /workspace/11.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3492099178 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 41135093 ps |
CPU time | 2.37 seconds |
Started | Jul 29 07:35:07 PM PDT 24 |
Finished | Jul 29 07:35:09 PM PDT 24 |
Peak memory | 209944 kb |
Host | smart-52f2d6e0-fa0b-4f6e-8e91-f5f57fb01d34 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3492099178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3492099178 |
Directory | /workspace/11.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/12.keymgr_alert_test.201915939 |
Short name | T633 |
Test name | |
Test status | |
Simulation time | 42246425 ps |
CPU time | 0.9 seconds |
Started | Jul 29 07:35:07 PM PDT 24 |
Finished | Jul 29 07:35:08 PM PDT 24 |
Peak memory | 205920 kb |
Host | smart-f4a97fcc-b37c-4a30-9dcb-4df1ae133f7b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201915939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.201915939 |
Directory | /workspace/12.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/12.keymgr_cfg_regwen.2202079990 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 52410566 ps |
CPU time | 3.69 seconds |
Started | Jul 29 07:35:06 PM PDT 24 |
Finished | Jul 29 07:35:10 PM PDT 24 |
Peak memory | 214888 kb |
Host | smart-ee3775d2-37f9-4ae6-99f4-a6000206421b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2202079990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2202079990 |
Directory | /workspace/12.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/12.keymgr_direct_to_disabled.2620250963 |
Short name | T727 |
Test name | |
Test status | |
Simulation time | 255674087 ps |
CPU time | 2.75 seconds |
Started | Jul 29 07:35:00 PM PDT 24 |
Finished | Jul 29 07:35:03 PM PDT 24 |
Peak memory | 208212 kb |
Host | smart-b9b9ecf3-158e-4736-a3cd-be8d80d80e82 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2620250963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2620250963 |
Directory | /workspace/12.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/12.keymgr_kmac_rsp_err.2042149416 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 648419500 ps |
CPU time | 4.36 seconds |
Started | Jul 29 07:35:07 PM PDT 24 |
Finished | Jul 29 07:35:12 PM PDT 24 |
Peak memory | 214128 kb |
Host | smart-4f8da176-a273-4ff6-9fea-9679b2597e87 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2042149416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2042149416 |
Directory | /workspace/12.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/12.keymgr_lc_disable.896216973 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 306617175 ps |
CPU time | 3.08 seconds |
Started | Jul 29 07:35:04 PM PDT 24 |
Finished | Jul 29 07:35:07 PM PDT 24 |
Peak memory | 207344 kb |
Host | smart-5c5917f8-23fc-4724-b28f-d14aa1bb14aa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=896216973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.896216973 |
Directory | /workspace/12.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/12.keymgr_random.3800393975 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 143870155 ps |
CPU time | 2.95 seconds |
Started | Jul 29 07:35:05 PM PDT 24 |
Finished | Jul 29 07:35:08 PM PDT 24 |
Peak memory | 207572 kb |
Host | smart-518cec3a-c799-4a03-8610-73243d701bd3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3800393975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3800393975 |
Directory | /workspace/12.keymgr_random/latest |
Test location | /workspace/coverage/default/12.keymgr_sideload.4243289395 |
Short name | T835 |
Test name | |
Test status | |
Simulation time | 262273785 ps |
CPU time | 3.25 seconds |
Started | Jul 29 07:35:02 PM PDT 24 |
Finished | Jul 29 07:35:05 PM PDT 24 |
Peak memory | 208380 kb |
Host | smart-7d5f357c-cf78-4e7e-a3f8-0e0abbaf034f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4243289395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.4243289395 |
Directory | /workspace/12.keymgr_sideload/latest |
Test location | /workspace/coverage/default/12.keymgr_sideload_aes.1340521555 |
Short name | T677 |
Test name | |
Test status | |
Simulation time | 271825813 ps |
CPU time | 3.24 seconds |
Started | Jul 29 07:35:08 PM PDT 24 |
Finished | Jul 29 07:35:11 PM PDT 24 |
Peak memory | 206828 kb |
Host | smart-242d3dde-2e1c-4760-85f6-6be046a0d3c5 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340521555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1340521555 |
Directory | /workspace/12.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/12.keymgr_sideload_kmac.2651454965 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 1718206579 ps |
CPU time | 37.69 seconds |
Started | Jul 29 07:35:07 PM PDT 24 |
Finished | Jul 29 07:35:45 PM PDT 24 |
Peak memory | 208076 kb |
Host | smart-1161bdcb-3a60-4b4a-a280-cb2544bee496 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651454965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2651454965 |
Directory | /workspace/12.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/12.keymgr_sideload_otbn.490124299 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 212762025 ps |
CPU time | 6.15 seconds |
Started | Jul 29 07:34:58 PM PDT 24 |
Finished | Jul 29 07:35:04 PM PDT 24 |
Peak memory | 208732 kb |
Host | smart-b2455169-426f-46ab-9e19-931a8a7e59d1 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490124299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.490124299 |
Directory | /workspace/12.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/12.keymgr_sideload_protect.407372714 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 113074921 ps |
CPU time | 3.72 seconds |
Started | Jul 29 07:35:01 PM PDT 24 |
Finished | Jul 29 07:35:05 PM PDT 24 |
Peak memory | 209936 kb |
Host | smart-e3a1a1a9-b394-4d25-8a04-afb1d9c99c5d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=407372714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.407372714 |
Directory | /workspace/12.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/12.keymgr_smoke.3610793740 |
Short name | T631 |
Test name | |
Test status | |
Simulation time | 91700035 ps |
CPU time | 2.5 seconds |
Started | Jul 29 07:35:05 PM PDT 24 |
Finished | Jul 29 07:35:08 PM PDT 24 |
Peak memory | 208688 kb |
Host | smart-98087d54-c9fa-4292-a9ce-89354724f301 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3610793740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3610793740 |
Directory | /workspace/12.keymgr_smoke/latest |
Test location | /workspace/coverage/default/12.keymgr_sw_invalid_input.409531124 |
Short name | T858 |
Test name | |
Test status | |
Simulation time | 248037504 ps |
CPU time | 3.85 seconds |
Started | Jul 29 07:35:06 PM PDT 24 |
Finished | Jul 29 07:35:10 PM PDT 24 |
Peak memory | 208088 kb |
Host | smart-ad2b5c58-34ef-4e81-a6b8-926b0d4f292b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=409531124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.409531124 |
Directory | /workspace/12.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3662634716 |
Short name | T841 |
Test name | |
Test status | |
Simulation time | 141332459 ps |
CPU time | 2.24 seconds |
Started | Jul 29 07:35:01 PM PDT 24 |
Finished | Jul 29 07:35:04 PM PDT 24 |
Peak memory | 210068 kb |
Host | smart-798095d4-0d72-49a2-8efa-b2c502a87afa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3662634716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3662634716 |
Directory | /workspace/12.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/13.keymgr_alert_test.2200523198 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 12902967 ps |
CPU time | 0.8 seconds |
Started | Jul 29 07:35:07 PM PDT 24 |
Finished | Jul 29 07:35:08 PM PDT 24 |
Peak memory | 205916 kb |
Host | smart-085c6973-f4f1-452a-ab9f-c265c4e2d639 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200523198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2200523198 |
Directory | /workspace/13.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/13.keymgr_cfg_regwen.636589146 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 4234386433 ps |
CPU time | 59.38 seconds |
Started | Jul 29 07:35:03 PM PDT 24 |
Finished | Jul 29 07:36:03 PM PDT 24 |
Peak memory | 215676 kb |
Host | smart-1504ac3c-4229-4822-99fd-dd516c4acc94 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=636589146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.636589146 |
Directory | /workspace/13.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/13.keymgr_custom_cm.390051688 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 133564664 ps |
CPU time | 5.18 seconds |
Started | Jul 29 07:35:06 PM PDT 24 |
Finished | Jul 29 07:35:11 PM PDT 24 |
Peak memory | 214184 kb |
Host | smart-775243bb-b736-4b98-83dd-ef0659ffe123 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=390051688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.390051688 |
Directory | /workspace/13.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/13.keymgr_direct_to_disabled.3716593934 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 1935441324 ps |
CPU time | 6.27 seconds |
Started | Jul 29 07:35:03 PM PDT 24 |
Finished | Jul 29 07:35:10 PM PDT 24 |
Peak memory | 207808 kb |
Host | smart-8ba9c4d2-297e-4e10-84dc-c51ac0956ef0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3716593934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3716593934 |
Directory | /workspace/13.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1496132437 |
Short name | T871 |
Test name | |
Test status | |
Simulation time | 193756470 ps |
CPU time | 5.14 seconds |
Started | Jul 29 07:35:07 PM PDT 24 |
Finished | Jul 29 07:35:13 PM PDT 24 |
Peak memory | 208688 kb |
Host | smart-49de7b51-bfe3-45c6-99a0-e801c1956f4e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1496132437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1496132437 |
Directory | /workspace/13.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/13.keymgr_kmac_rsp_err.2307836568 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 69826444 ps |
CPU time | 1.59 seconds |
Started | Jul 29 07:35:07 PM PDT 24 |
Finished | Jul 29 07:35:08 PM PDT 24 |
Peak memory | 214200 kb |
Host | smart-7399e5b7-0f1c-44a0-9be7-ca2082b45d53 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2307836568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2307836568 |
Directory | /workspace/13.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/13.keymgr_lc_disable.2330889285 |
Short name | T825 |
Test name | |
Test status | |
Simulation time | 277897538 ps |
CPU time | 3.51 seconds |
Started | Jul 29 07:35:06 PM PDT 24 |
Finished | Jul 29 07:35:10 PM PDT 24 |
Peak memory | 210344 kb |
Host | smart-52306b63-28a9-4cdf-acad-5c5908cb15a0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2330889285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2330889285 |
Directory | /workspace/13.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/13.keymgr_random.3621430128 |
Short name | T826 |
Test name | |
Test status | |
Simulation time | 120959057 ps |
CPU time | 4.94 seconds |
Started | Jul 29 07:35:07 PM PDT 24 |
Finished | Jul 29 07:35:13 PM PDT 24 |
Peak memory | 208524 kb |
Host | smart-c599fd9a-9023-4aa7-8461-ac73be0338a6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3621430128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3621430128 |
Directory | /workspace/13.keymgr_random/latest |
Test location | /workspace/coverage/default/13.keymgr_sideload.1882670012 |
Short name | T783 |
Test name | |
Test status | |
Simulation time | 263617106 ps |
CPU time | 3.67 seconds |
Started | Jul 29 07:35:06 PM PDT 24 |
Finished | Jul 29 07:35:10 PM PDT 24 |
Peak memory | 206952 kb |
Host | smart-cb07e9ff-7e1b-486b-87af-f8f0eeae43bd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1882670012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1882670012 |
Directory | /workspace/13.keymgr_sideload/latest |
Test location | /workspace/coverage/default/13.keymgr_sideload_aes.2392686457 |
Short name | T703 |
Test name | |
Test status | |
Simulation time | 246530608 ps |
CPU time | 2.42 seconds |
Started | Jul 29 07:35:04 PM PDT 24 |
Finished | Jul 29 07:35:06 PM PDT 24 |
Peak memory | 206876 kb |
Host | smart-c88392c3-578a-439c-a8b3-0b6cab92e326 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392686457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2392686457 |
Directory | /workspace/13.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/13.keymgr_sideload_kmac.3981469467 |
Short name | T718 |
Test name | |
Test status | |
Simulation time | 59493735 ps |
CPU time | 2.81 seconds |
Started | Jul 29 07:35:01 PM PDT 24 |
Finished | Jul 29 07:35:04 PM PDT 24 |
Peak memory | 206776 kb |
Host | smart-eb2a70c1-b4e4-4a98-9fb8-699f1a7bf131 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981469467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3981469467 |
Directory | /workspace/13.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/13.keymgr_sideload_otbn.4106671864 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 1182625035 ps |
CPU time | 4.32 seconds |
Started | Jul 29 07:35:03 PM PDT 24 |
Finished | Jul 29 07:35:08 PM PDT 24 |
Peak memory | 206948 kb |
Host | smart-a20e6b69-a350-48d9-993a-1f4984e48875 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106671864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.4106671864 |
Directory | /workspace/13.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/13.keymgr_sideload_protect.1834556200 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 85505330 ps |
CPU time | 2.21 seconds |
Started | Jul 29 07:35:03 PM PDT 24 |
Finished | Jul 29 07:35:05 PM PDT 24 |
Peak memory | 208660 kb |
Host | smart-a900aecb-c20d-4bba-aa43-bf32f0ebc54e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1834556200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1834556200 |
Directory | /workspace/13.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/13.keymgr_smoke.3197880853 |
Short name | T795 |
Test name | |
Test status | |
Simulation time | 38502013 ps |
CPU time | 2.02 seconds |
Started | Jul 29 07:35:07 PM PDT 24 |
Finished | Jul 29 07:35:09 PM PDT 24 |
Peak memory | 206872 kb |
Host | smart-12556955-79ef-4619-9056-e3c480bbf77a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3197880853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.3197880853 |
Directory | /workspace/13.keymgr_smoke/latest |
Test location | /workspace/coverage/default/13.keymgr_sw_invalid_input.2749492787 |
Short name | T814 |
Test name | |
Test status | |
Simulation time | 277167362 ps |
CPU time | 5.24 seconds |
Started | Jul 29 07:35:04 PM PDT 24 |
Finished | Jul 29 07:35:09 PM PDT 24 |
Peak memory | 218520 kb |
Host | smart-e287f418-e3ae-4561-8566-9cecb104bb7b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2749492787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2749492787 |
Directory | /workspace/13.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3372973927 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 369324485 ps |
CPU time | 3.36 seconds |
Started | Jul 29 07:35:07 PM PDT 24 |
Finished | Jul 29 07:35:10 PM PDT 24 |
Peak memory | 210132 kb |
Host | smart-b2f0193d-4941-4463-96fb-07b760f528d5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3372973927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3372973927 |
Directory | /workspace/13.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/14.keymgr_alert_test.1007313411 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 36632643 ps |
CPU time | 0.83 seconds |
Started | Jul 29 07:35:03 PM PDT 24 |
Finished | Jul 29 07:35:04 PM PDT 24 |
Peak memory | 205936 kb |
Host | smart-82736701-6708-4dd6-8b6e-af15e8b8568f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007313411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1007313411 |
Directory | /workspace/14.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/14.keymgr_cfg_regwen.3876707919 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 706992521 ps |
CPU time | 36.99 seconds |
Started | Jul 29 07:35:15 PM PDT 24 |
Finished | Jul 29 07:35:52 PM PDT 24 |
Peak memory | 214852 kb |
Host | smart-0d02bc5c-0bb1-4dfb-86d3-c18d07bc97ee |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3876707919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3876707919 |
Directory | /workspace/14.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/14.keymgr_direct_to_disabled.503985960 |
Short name | T689 |
Test name | |
Test status | |
Simulation time | 147897307 ps |
CPU time | 2.54 seconds |
Started | Jul 29 07:35:15 PM PDT 24 |
Finished | Jul 29 07:35:17 PM PDT 24 |
Peak memory | 207548 kb |
Host | smart-bb2215b7-0faa-4239-bc95-3ac45e2dc57a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=503985960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.503985960 |
Directory | /workspace/14.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1890573574 |
Short name | T724 |
Test name | |
Test status | |
Simulation time | 229214596 ps |
CPU time | 5.37 seconds |
Started | Jul 29 07:35:15 PM PDT 24 |
Finished | Jul 29 07:35:21 PM PDT 24 |
Peak memory | 209024 kb |
Host | smart-949fcaf3-9fdf-4751-8787-2b4d8af1c4ca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1890573574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1890573574 |
Directory | /workspace/14.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/14.keymgr_kmac_rsp_err.2695712835 |
Short name | T693 |
Test name | |
Test status | |
Simulation time | 42063429 ps |
CPU time | 2.28 seconds |
Started | Jul 29 07:35:08 PM PDT 24 |
Finished | Jul 29 07:35:11 PM PDT 24 |
Peak memory | 214296 kb |
Host | smart-dd01cb82-5fad-43d2-a9e1-3233e2f8b8d2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2695712835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2695712835 |
Directory | /workspace/14.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/14.keymgr_lc_disable.1217646317 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 95544152 ps |
CPU time | 4.44 seconds |
Started | Jul 29 07:35:00 PM PDT 24 |
Finished | Jul 29 07:35:05 PM PDT 24 |
Peak memory | 210684 kb |
Host | smart-503dc651-ad85-419c-854e-c75a79455a9f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1217646317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1217646317 |
Directory | /workspace/14.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/14.keymgr_random.73395840 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 57475681 ps |
CPU time | 2.36 seconds |
Started | Jul 29 07:35:13 PM PDT 24 |
Finished | Jul 29 07:35:15 PM PDT 24 |
Peak memory | 214324 kb |
Host | smart-e94b0ce1-6d37-4997-8944-0619e12571bf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=73395840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.73395840 |
Directory | /workspace/14.keymgr_random/latest |
Test location | /workspace/coverage/default/14.keymgr_sideload.1758964766 |
Short name | T729 |
Test name | |
Test status | |
Simulation time | 96471458 ps |
CPU time | 2.2 seconds |
Started | Jul 29 07:35:05 PM PDT 24 |
Finished | Jul 29 07:35:07 PM PDT 24 |
Peak memory | 206876 kb |
Host | smart-4460168b-6551-4f11-916d-084935bba93f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1758964766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1758964766 |
Directory | /workspace/14.keymgr_sideload/latest |
Test location | /workspace/coverage/default/14.keymgr_sideload_aes.148643907 |
Short name | T757 |
Test name | |
Test status | |
Simulation time | 1130647412 ps |
CPU time | 6.63 seconds |
Started | Jul 29 07:35:02 PM PDT 24 |
Finished | Jul 29 07:35:09 PM PDT 24 |
Peak memory | 207996 kb |
Host | smart-6603dbcf-0ae4-44f0-801b-58989beaa058 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148643907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.148643907 |
Directory | /workspace/14.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/14.keymgr_sideload_kmac.3852341340 |
Short name | T716 |
Test name | |
Test status | |
Simulation time | 874299164 ps |
CPU time | 19.46 seconds |
Started | Jul 29 07:35:06 PM PDT 24 |
Finished | Jul 29 07:35:26 PM PDT 24 |
Peak memory | 208044 kb |
Host | smart-29a17a95-a3db-4f7b-86ea-c39b05a6bbb6 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852341340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3852341340 |
Directory | /workspace/14.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/14.keymgr_sideload_otbn.3716513215 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 111220765 ps |
CPU time | 3.72 seconds |
Started | Jul 29 07:35:01 PM PDT 24 |
Finished | Jul 29 07:35:05 PM PDT 24 |
Peak memory | 208448 kb |
Host | smart-1dd029a8-cff9-4508-8fd0-af075a3cc1ce |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716513215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3716513215 |
Directory | /workspace/14.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/14.keymgr_sideload_protect.3792810570 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 259145838 ps |
CPU time | 1.82 seconds |
Started | Jul 29 07:35:02 PM PDT 24 |
Finished | Jul 29 07:35:04 PM PDT 24 |
Peak memory | 207220 kb |
Host | smart-ef6d978e-510b-4310-9bc3-b22516aad3c4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3792810570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3792810570 |
Directory | /workspace/14.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/14.keymgr_smoke.2834440217 |
Short name | T848 |
Test name | |
Test status | |
Simulation time | 5205759100 ps |
CPU time | 21.95 seconds |
Started | Jul 29 07:35:06 PM PDT 24 |
Finished | Jul 29 07:35:28 PM PDT 24 |
Peak memory | 208416 kb |
Host | smart-41b82481-8e9f-416d-ac1f-0970cdc32a49 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2834440217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2834440217 |
Directory | /workspace/14.keymgr_smoke/latest |
Test location | /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.172369386 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 500268619 ps |
CPU time | 12.73 seconds |
Started | Jul 29 07:35:02 PM PDT 24 |
Finished | Jul 29 07:35:15 PM PDT 24 |
Peak memory | 222544 kb |
Host | smart-3973da3f-a0b5-4fc3-ac5f-728370438b1b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172369386 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.172369386 |
Directory | /workspace/14.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/14.keymgr_sw_invalid_input.3449842112 |
Short name | T886 |
Test name | |
Test status | |
Simulation time | 1695012352 ps |
CPU time | 11.14 seconds |
Started | Jul 29 07:35:01 PM PDT 24 |
Finished | Jul 29 07:35:13 PM PDT 24 |
Peak memory | 209128 kb |
Host | smart-e14fa25e-48b3-4ab6-bb0b-3cc6aa904814 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3449842112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3449842112 |
Directory | /workspace/14.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/14.keymgr_sync_async_fault_cross.809304230 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 277653922 ps |
CPU time | 3.35 seconds |
Started | Jul 29 07:35:03 PM PDT 24 |
Finished | Jul 29 07:35:07 PM PDT 24 |
Peak memory | 210528 kb |
Host | smart-b3901050-c591-433d-9b78-e41788120014 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=809304230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.809304230 |
Directory | /workspace/14.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/15.keymgr_alert_test.2415451211 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 22255688 ps |
CPU time | 0.82 seconds |
Started | Jul 29 07:35:14 PM PDT 24 |
Finished | Jul 29 07:35:15 PM PDT 24 |
Peak memory | 205984 kb |
Host | smart-42308f8b-df41-4790-afa4-060c8afddd81 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415451211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2415451211 |
Directory | /workspace/15.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/15.keymgr_custom_cm.3800077499 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 164590799 ps |
CPU time | 1.77 seconds |
Started | Jul 29 07:35:15 PM PDT 24 |
Finished | Jul 29 07:35:17 PM PDT 24 |
Peak memory | 214244 kb |
Host | smart-c04bce42-4fc9-4979-8068-51686b573b9d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3800077499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3800077499 |
Directory | /workspace/15.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/15.keymgr_direct_to_disabled.3215435263 |
Short name | T695 |
Test name | |
Test status | |
Simulation time | 146557172 ps |
CPU time | 4.74 seconds |
Started | Jul 29 07:35:04 PM PDT 24 |
Finished | Jul 29 07:35:09 PM PDT 24 |
Peak memory | 222636 kb |
Host | smart-c5d9dc79-c194-4ea4-9e60-e270fa414d0c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3215435263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3215435263 |
Directory | /workspace/15.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3686304851 |
Short name | T675 |
Test name | |
Test status | |
Simulation time | 26352157 ps |
CPU time | 2.41 seconds |
Started | Jul 29 07:35:02 PM PDT 24 |
Finished | Jul 29 07:35:05 PM PDT 24 |
Peak memory | 214420 kb |
Host | smart-e54488b9-4274-4b92-b7c2-ad33c9016ce8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3686304851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3686304851 |
Directory | /workspace/15.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/15.keymgr_kmac_rsp_err.2299626563 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 61900016 ps |
CPU time | 2.89 seconds |
Started | Jul 29 07:35:15 PM PDT 24 |
Finished | Jul 29 07:35:18 PM PDT 24 |
Peak memory | 221740 kb |
Host | smart-d46d39bc-2130-457a-b84d-04e8ab496a3f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2299626563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2299626563 |
Directory | /workspace/15.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/15.keymgr_lc_disable.2226667556 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 2311191829 ps |
CPU time | 17.85 seconds |
Started | Jul 29 07:35:04 PM PDT 24 |
Finished | Jul 29 07:35:22 PM PDT 24 |
Peak memory | 214384 kb |
Host | smart-e401fc94-c835-41f0-80ce-aa20ee43c74a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2226667556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2226667556 |
Directory | /workspace/15.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/15.keymgr_random.3801470604 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 310033542 ps |
CPU time | 6.76 seconds |
Started | Jul 29 07:35:15 PM PDT 24 |
Finished | Jul 29 07:35:22 PM PDT 24 |
Peak memory | 207572 kb |
Host | smart-cf404ee7-7746-482b-aaa1-9968d7799a3b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3801470604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3801470604 |
Directory | /workspace/15.keymgr_random/latest |
Test location | /workspace/coverage/default/15.keymgr_sideload.2604022206 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 8518608104 ps |
CPU time | 36.97 seconds |
Started | Jul 29 07:35:15 PM PDT 24 |
Finished | Jul 29 07:35:52 PM PDT 24 |
Peak memory | 208512 kb |
Host | smart-fa3164c9-16aa-4864-936a-332c76c0813d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2604022206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2604022206 |
Directory | /workspace/15.keymgr_sideload/latest |
Test location | /workspace/coverage/default/15.keymgr_sideload_aes.4068620810 |
Short name | T683 |
Test name | |
Test status | |
Simulation time | 60130139 ps |
CPU time | 3.01 seconds |
Started | Jul 29 07:35:09 PM PDT 24 |
Finished | Jul 29 07:35:12 PM PDT 24 |
Peak memory | 208308 kb |
Host | smart-840820e7-5c84-4078-ac84-49903da67d2a |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068620810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.4068620810 |
Directory | /workspace/15.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/15.keymgr_sideload_kmac.1298747982 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 85112513 ps |
CPU time | 1.73 seconds |
Started | Jul 29 07:35:15 PM PDT 24 |
Finished | Jul 29 07:35:17 PM PDT 24 |
Peak memory | 206888 kb |
Host | smart-b583e95a-8f29-4987-b026-a7cbce74942e |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298747982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1298747982 |
Directory | /workspace/15.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/15.keymgr_sideload_otbn.1708201854 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 28878905 ps |
CPU time | 2.08 seconds |
Started | Jul 29 07:35:15 PM PDT 24 |
Finished | Jul 29 07:35:17 PM PDT 24 |
Peak memory | 208760 kb |
Host | smart-eaeaa267-aa86-4d0f-a4f4-97003bea98a0 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708201854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1708201854 |
Directory | /workspace/15.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/15.keymgr_sideload_protect.1479407560 |
Short name | T759 |
Test name | |
Test status | |
Simulation time | 109353665 ps |
CPU time | 2.43 seconds |
Started | Jul 29 07:35:15 PM PDT 24 |
Finished | Jul 29 07:35:17 PM PDT 24 |
Peak memory | 207944 kb |
Host | smart-4f21732e-e3f4-4249-a897-1194af16e29d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1479407560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1479407560 |
Directory | /workspace/15.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/15.keymgr_smoke.340262277 |
Short name | T691 |
Test name | |
Test status | |
Simulation time | 778832188 ps |
CPU time | 18.53 seconds |
Started | Jul 29 07:35:00 PM PDT 24 |
Finished | Jul 29 07:35:19 PM PDT 24 |
Peak memory | 207900 kb |
Host | smart-f2338e2a-cfdc-4eef-8f0c-52a660fa3060 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=340262277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.340262277 |
Directory | /workspace/15.keymgr_smoke/latest |
Test location | /workspace/coverage/default/15.keymgr_stress_all.1847617502 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 2047484347 ps |
CPU time | 15.12 seconds |
Started | Jul 29 07:35:12 PM PDT 24 |
Finished | Jul 29 07:35:28 PM PDT 24 |
Peak memory | 220076 kb |
Host | smart-120e9335-e358-4d77-bdce-ecad132880cd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847617502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1847617502 |
Directory | /workspace/15.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1298151843 |
Short name | T623 |
Test name | |
Test status | |
Simulation time | 613635511 ps |
CPU time | 11.88 seconds |
Started | Jul 29 07:35:09 PM PDT 24 |
Finished | Jul 29 07:35:21 PM PDT 24 |
Peak memory | 222460 kb |
Host | smart-3e448b7f-0fa2-4d93-898b-2240f8460366 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298151843 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1298151843 |
Directory | /workspace/15.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/15.keymgr_sw_invalid_input.1406029166 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 1125930857 ps |
CPU time | 4.56 seconds |
Started | Jul 29 07:35:02 PM PDT 24 |
Finished | Jul 29 07:35:06 PM PDT 24 |
Peak memory | 207440 kb |
Host | smart-01dc3f08-8e14-4ae1-a163-6384dea20c1d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1406029166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1406029166 |
Directory | /workspace/15.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3504478153 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 367740621 ps |
CPU time | 7.03 seconds |
Started | Jul 29 07:35:07 PM PDT 24 |
Finished | Jul 29 07:35:14 PM PDT 24 |
Peak memory | 210948 kb |
Host | smart-bad86373-0afd-4a27-a5d1-e7f8e0e673c7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3504478153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3504478153 |
Directory | /workspace/15.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/16.keymgr_alert_test.1068720527 |
Short name | T802 |
Test name | |
Test status | |
Simulation time | 143900134 ps |
CPU time | 0.91 seconds |
Started | Jul 29 07:35:13 PM PDT 24 |
Finished | Jul 29 07:35:14 PM PDT 24 |
Peak memory | 206104 kb |
Host | smart-dc0bf029-b6bb-43c1-9c7b-e118cbcf1a03 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068720527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1068720527 |
Directory | /workspace/16.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/16.keymgr_cfg_regwen.33064353 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 469272373 ps |
CPU time | 12.44 seconds |
Started | Jul 29 07:35:13 PM PDT 24 |
Finished | Jul 29 07:35:25 PM PDT 24 |
Peak memory | 214432 kb |
Host | smart-ad2e5cb7-bf4f-454f-975b-098a6440ab22 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=33064353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.33064353 |
Directory | /workspace/16.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/16.keymgr_custom_cm.24294574 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 90516065 ps |
CPU time | 2.51 seconds |
Started | Jul 29 07:35:13 PM PDT 24 |
Finished | Jul 29 07:35:16 PM PDT 24 |
Peak memory | 210160 kb |
Host | smart-3dc88e37-bcf9-4cc6-85b6-9a6719c9a514 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24294574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.24294574 |
Directory | /workspace/16.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/16.keymgr_direct_to_disabled.958010328 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 108890120 ps |
CPU time | 4.56 seconds |
Started | Jul 29 07:35:15 PM PDT 24 |
Finished | Jul 29 07:35:20 PM PDT 24 |
Peak memory | 214316 kb |
Host | smart-ff507464-670a-4713-a821-6c2d38a5e2e3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=958010328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.958010328 |
Directory | /workspace/16.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3369961243 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 2694806633 ps |
CPU time | 24.27 seconds |
Started | Jul 29 07:35:11 PM PDT 24 |
Finished | Jul 29 07:35:35 PM PDT 24 |
Peak memory | 214456 kb |
Host | smart-522c6170-bc02-4f0c-94d4-c084cdabf9b3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3369961243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3369961243 |
Directory | /workspace/16.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/16.keymgr_kmac_rsp_err.3925008119 |
Short name | T836 |
Test name | |
Test status | |
Simulation time | 78516537 ps |
CPU time | 1.7 seconds |
Started | Jul 29 07:35:12 PM PDT 24 |
Finished | Jul 29 07:35:13 PM PDT 24 |
Peak memory | 214260 kb |
Host | smart-14895e24-d510-4cf6-adaa-eb7a6933b03d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3925008119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3925008119 |
Directory | /workspace/16.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/16.keymgr_lc_disable.1931058635 |
Short name | T696 |
Test name | |
Test status | |
Simulation time | 315241752 ps |
CPU time | 4.55 seconds |
Started | Jul 29 07:35:13 PM PDT 24 |
Finished | Jul 29 07:35:18 PM PDT 24 |
Peak memory | 220220 kb |
Host | smart-d64685af-0365-4f87-8a67-068614f4ffa7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1931058635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1931058635 |
Directory | /workspace/16.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/16.keymgr_random.2918809954 |
Short name | T864 |
Test name | |
Test status | |
Simulation time | 130462691 ps |
CPU time | 5.11 seconds |
Started | Jul 29 07:35:21 PM PDT 24 |
Finished | Jul 29 07:35:26 PM PDT 24 |
Peak memory | 209788 kb |
Host | smart-fcc7b371-dea3-4b4c-ad97-21643a458820 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2918809954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2918809954 |
Directory | /workspace/16.keymgr_random/latest |
Test location | /workspace/coverage/default/16.keymgr_sideload.1706544071 |
Short name | T670 |
Test name | |
Test status | |
Simulation time | 2412196250 ps |
CPU time | 17.49 seconds |
Started | Jul 29 07:35:14 PM PDT 24 |
Finished | Jul 29 07:35:32 PM PDT 24 |
Peak memory | 208232 kb |
Host | smart-4d8b5b31-780b-4d1c-b57c-a2da66b44a3b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1706544071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1706544071 |
Directory | /workspace/16.keymgr_sideload/latest |
Test location | /workspace/coverage/default/16.keymgr_sideload_aes.1284427129 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 152062714 ps |
CPU time | 2.58 seconds |
Started | Jul 29 07:35:13 PM PDT 24 |
Finished | Jul 29 07:35:15 PM PDT 24 |
Peak memory | 206944 kb |
Host | smart-78da1bb7-2a8c-451d-8a18-acc77fb5f74b |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284427129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1284427129 |
Directory | /workspace/16.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/16.keymgr_sideload_kmac.3170991428 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 3798063219 ps |
CPU time | 21.7 seconds |
Started | Jul 29 07:35:15 PM PDT 24 |
Finished | Jul 29 07:35:36 PM PDT 24 |
Peak memory | 208044 kb |
Host | smart-eccc1890-9e01-4fb7-abde-3bf40f231acc |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170991428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3170991428 |
Directory | /workspace/16.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/16.keymgr_sideload_otbn.1904611892 |
Short name | T749 |
Test name | |
Test status | |
Simulation time | 415499804 ps |
CPU time | 3.29 seconds |
Started | Jul 29 07:35:21 PM PDT 24 |
Finished | Jul 29 07:35:24 PM PDT 24 |
Peak memory | 208712 kb |
Host | smart-8249a72b-19a3-4860-be2d-7deb9788f65e |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904611892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1904611892 |
Directory | /workspace/16.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/16.keymgr_sideload_protect.3185210826 |
Short name | T704 |
Test name | |
Test status | |
Simulation time | 2482804354 ps |
CPU time | 15.75 seconds |
Started | Jul 29 07:35:17 PM PDT 24 |
Finished | Jul 29 07:35:33 PM PDT 24 |
Peak memory | 210244 kb |
Host | smart-1022fddb-f882-4d3f-a313-0cad11f88963 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3185210826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3185210826 |
Directory | /workspace/16.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/16.keymgr_smoke.1379738648 |
Short name | T815 |
Test name | |
Test status | |
Simulation time | 31768524 ps |
CPU time | 2.11 seconds |
Started | Jul 29 07:35:10 PM PDT 24 |
Finished | Jul 29 07:35:12 PM PDT 24 |
Peak memory | 206696 kb |
Host | smart-21727a62-1043-407e-b8fa-2fdb117155bf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1379738648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1379738648 |
Directory | /workspace/16.keymgr_smoke/latest |
Test location | /workspace/coverage/default/16.keymgr_stress_all.3028642562 |
Short name | T910 |
Test name | |
Test status | |
Simulation time | 869016387 ps |
CPU time | 19.47 seconds |
Started | Jul 29 07:35:16 PM PDT 24 |
Finished | Jul 29 07:35:36 PM PDT 24 |
Peak memory | 215580 kb |
Host | smart-c0e89fe7-c8b7-4723-9546-4e287d81e0e5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028642562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3028642562 |
Directory | /workspace/16.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.777085985 |
Short name | T715 |
Test name | |
Test status | |
Simulation time | 927634797 ps |
CPU time | 10.19 seconds |
Started | Jul 29 07:35:13 PM PDT 24 |
Finished | Jul 29 07:35:23 PM PDT 24 |
Peak memory | 220572 kb |
Host | smart-f55e2804-25e4-4109-9e2c-c11b3d56498e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777085985 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.777085985 |
Directory | /workspace/16.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/16.keymgr_sw_invalid_input.1909675299 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 46691165 ps |
CPU time | 3.49 seconds |
Started | Jul 29 07:35:12 PM PDT 24 |
Finished | Jul 29 07:35:16 PM PDT 24 |
Peak memory | 214268 kb |
Host | smart-72ff94f7-7d6c-4ff0-b7a9-5397407c3b0e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1909675299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1909675299 |
Directory | /workspace/16.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/16.keymgr_sync_async_fault_cross.128796696 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 64475274 ps |
CPU time | 1.16 seconds |
Started | Jul 29 07:35:08 PM PDT 24 |
Finished | Jul 29 07:35:09 PM PDT 24 |
Peak memory | 208672 kb |
Host | smart-225ad038-8dbf-4ab6-9806-e061d6a23ef7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=128796696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.128796696 |
Directory | /workspace/16.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/17.keymgr_alert_test.4132367284 |
Short name | T823 |
Test name | |
Test status | |
Simulation time | 44836781 ps |
CPU time | 0.74 seconds |
Started | Jul 29 07:35:15 PM PDT 24 |
Finished | Jul 29 07:35:16 PM PDT 24 |
Peak memory | 205952 kb |
Host | smart-518f6a41-6ecc-4ae4-84d7-52701bad3621 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132367284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.4132367284 |
Directory | /workspace/17.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/17.keymgr_direct_to_disabled.1162031025 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 57955956 ps |
CPU time | 1.41 seconds |
Started | Jul 29 07:35:09 PM PDT 24 |
Finished | Jul 29 07:35:11 PM PDT 24 |
Peak memory | 207488 kb |
Host | smart-67a73f9e-c8c1-4caf-855b-5d3f6eef47d1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1162031025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1162031025 |
Directory | /workspace/17.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/17.keymgr_kmac_rsp_err.2047251182 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 72597698 ps |
CPU time | 2.3 seconds |
Started | Jul 29 07:35:20 PM PDT 24 |
Finished | Jul 29 07:35:23 PM PDT 24 |
Peak memory | 220396 kb |
Host | smart-9ce0792b-19d6-4a3a-b059-c050d0b19abf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2047251182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2047251182 |
Directory | /workspace/17.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/17.keymgr_random.1449122454 |
Short name | T655 |
Test name | |
Test status | |
Simulation time | 551777193 ps |
CPU time | 5.55 seconds |
Started | Jul 29 07:35:11 PM PDT 24 |
Finished | Jul 29 07:35:17 PM PDT 24 |
Peak memory | 214316 kb |
Host | smart-72eaa780-a1c6-421d-a979-77e72ab088d0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1449122454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1449122454 |
Directory | /workspace/17.keymgr_random/latest |
Test location | /workspace/coverage/default/17.keymgr_sideload.3463170547 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 408836324 ps |
CPU time | 3.6 seconds |
Started | Jul 29 07:35:14 PM PDT 24 |
Finished | Jul 29 07:35:18 PM PDT 24 |
Peak memory | 206760 kb |
Host | smart-fdbc4f51-9adb-416c-9f42-c8e47b3f01c9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3463170547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3463170547 |
Directory | /workspace/17.keymgr_sideload/latest |
Test location | /workspace/coverage/default/17.keymgr_sideload_aes.690280998 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 149370655 ps |
CPU time | 2.28 seconds |
Started | Jul 29 07:35:15 PM PDT 24 |
Finished | Jul 29 07:35:17 PM PDT 24 |
Peak memory | 206964 kb |
Host | smart-c5d72955-b79c-495a-a225-ec0d167d59c9 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690280998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.690280998 |
Directory | /workspace/17.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/17.keymgr_sideload_kmac.2865457947 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 262985894 ps |
CPU time | 7.65 seconds |
Started | Jul 29 07:35:09 PM PDT 24 |
Finished | Jul 29 07:35:17 PM PDT 24 |
Peak memory | 208204 kb |
Host | smart-4dbb06e5-7ee3-418d-9ffb-9f7bd65136cb |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865457947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2865457947 |
Directory | /workspace/17.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/17.keymgr_sideload_otbn.1530948129 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 46957021 ps |
CPU time | 2.31 seconds |
Started | Jul 29 07:35:17 PM PDT 24 |
Finished | Jul 29 07:35:19 PM PDT 24 |
Peak memory | 207100 kb |
Host | smart-52f85ae5-6142-499c-90d3-5200bbc2a68e |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530948129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1530948129 |
Directory | /workspace/17.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/17.keymgr_sideload_protect.2362649252 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 48237076 ps |
CPU time | 3.03 seconds |
Started | Jul 29 07:35:12 PM PDT 24 |
Finished | Jul 29 07:35:15 PM PDT 24 |
Peak memory | 210148 kb |
Host | smart-58a8bad5-ed2d-4c4b-9cdb-fbd0061ae70b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2362649252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2362649252 |
Directory | /workspace/17.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/17.keymgr_smoke.1057702025 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 202953633 ps |
CPU time | 2.44 seconds |
Started | Jul 29 07:35:13 PM PDT 24 |
Finished | Jul 29 07:35:15 PM PDT 24 |
Peak memory | 206712 kb |
Host | smart-8cb9f46f-fe5c-4949-83a0-a21e11281970 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1057702025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1057702025 |
Directory | /workspace/17.keymgr_smoke/latest |
Test location | /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.2705816091 |
Short name | T665 |
Test name | |
Test status | |
Simulation time | 341359463 ps |
CPU time | 11.32 seconds |
Started | Jul 29 07:35:15 PM PDT 24 |
Finished | Jul 29 07:35:27 PM PDT 24 |
Peak memory | 220500 kb |
Host | smart-de0a76d6-54a7-40a6-a465-b758e2ed5013 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705816091 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.2705816091 |
Directory | /workspace/17.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1645011508 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 121406629 ps |
CPU time | 1.85 seconds |
Started | Jul 29 07:35:17 PM PDT 24 |
Finished | Jul 29 07:35:19 PM PDT 24 |
Peak memory | 210260 kb |
Host | smart-b74b60ff-1ee8-41d6-907a-a9825eca9f32 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1645011508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1645011508 |
Directory | /workspace/17.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/18.keymgr_alert_test.476323894 |
Short name | T720 |
Test name | |
Test status | |
Simulation time | 28231393 ps |
CPU time | 0.77 seconds |
Started | Jul 29 07:35:21 PM PDT 24 |
Finished | Jul 29 07:35:22 PM PDT 24 |
Peak memory | 205760 kb |
Host | smart-22bc0376-344d-4414-9083-1dd5a4b4bf9e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476323894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.476323894 |
Directory | /workspace/18.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/18.keymgr_cfg_regwen.2724436986 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 96403339 ps |
CPU time | 3.44 seconds |
Started | Jul 29 07:35:21 PM PDT 24 |
Finished | Jul 29 07:35:24 PM PDT 24 |
Peak memory | 215436 kb |
Host | smart-b2d2408f-5c6a-43c3-b8ba-52bc7dbc6103 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2724436986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2724436986 |
Directory | /workspace/18.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/18.keymgr_custom_cm.2266940662 |
Short name | T649 |
Test name | |
Test status | |
Simulation time | 71874747 ps |
CPU time | 2.78 seconds |
Started | Jul 29 07:35:08 PM PDT 24 |
Finished | Jul 29 07:35:11 PM PDT 24 |
Peak memory | 209128 kb |
Host | smart-400fa769-a580-430a-b1eb-cc881bde83b7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2266940662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2266940662 |
Directory | /workspace/18.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/18.keymgr_direct_to_disabled.3352740400 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 1494499386 ps |
CPU time | 33.62 seconds |
Started | Jul 29 07:35:20 PM PDT 24 |
Finished | Jul 29 07:35:54 PM PDT 24 |
Peak memory | 210628 kb |
Host | smart-289699ed-3e60-41db-9f63-2a3ed98417ed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3352740400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3352740400 |
Directory | /workspace/18.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3968293336 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 104402776 ps |
CPU time | 4.78 seconds |
Started | Jul 29 07:35:17 PM PDT 24 |
Finished | Jul 29 07:35:22 PM PDT 24 |
Peak memory | 214500 kb |
Host | smart-da1b9c25-b26e-414f-b60b-6f5f5d56cd9a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3968293336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3968293336 |
Directory | /workspace/18.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/18.keymgr_lc_disable.3455674524 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 178306530 ps |
CPU time | 3.17 seconds |
Started | Jul 29 07:35:10 PM PDT 24 |
Finished | Jul 29 07:35:14 PM PDT 24 |
Peak memory | 218600 kb |
Host | smart-b5317920-6167-4cd9-80c9-544e696db04b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3455674524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3455674524 |
Directory | /workspace/18.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/18.keymgr_random.1637307662 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 181135510 ps |
CPU time | 4.67 seconds |
Started | Jul 29 07:35:20 PM PDT 24 |
Finished | Jul 29 07:35:25 PM PDT 24 |
Peak memory | 208252 kb |
Host | smart-a1b9ac0d-f4c7-4c9e-a727-3405433015a5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1637307662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1637307662 |
Directory | /workspace/18.keymgr_random/latest |
Test location | /workspace/coverage/default/18.keymgr_sideload.2791266930 |
Short name | T874 |
Test name | |
Test status | |
Simulation time | 147832201 ps |
CPU time | 5.46 seconds |
Started | Jul 29 07:35:10 PM PDT 24 |
Finished | Jul 29 07:35:16 PM PDT 24 |
Peak memory | 207004 kb |
Host | smart-5b33f150-e574-4eef-87ab-d3598d951816 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2791266930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2791266930 |
Directory | /workspace/18.keymgr_sideload/latest |
Test location | /workspace/coverage/default/18.keymgr_sideload_aes.1871538335 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 56789936 ps |
CPU time | 2.69 seconds |
Started | Jul 29 07:35:14 PM PDT 24 |
Finished | Jul 29 07:35:17 PM PDT 24 |
Peak memory | 207748 kb |
Host | smart-ba7fec1b-ef7c-4613-b645-d38acaa604ba |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871538335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1871538335 |
Directory | /workspace/18.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/18.keymgr_sideload_kmac.4265917432 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 534018912 ps |
CPU time | 4.13 seconds |
Started | Jul 29 07:35:13 PM PDT 24 |
Finished | Jul 29 07:35:17 PM PDT 24 |
Peak memory | 207004 kb |
Host | smart-f2ec8184-a621-4888-b61b-3a63da0f459e |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265917432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.4265917432 |
Directory | /workspace/18.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/18.keymgr_sideload_otbn.3832405996 |
Short name | T694 |
Test name | |
Test status | |
Simulation time | 1111240438 ps |
CPU time | 23.59 seconds |
Started | Jul 29 07:35:16 PM PDT 24 |
Finished | Jul 29 07:35:40 PM PDT 24 |
Peak memory | 208372 kb |
Host | smart-86535673-53f0-48cd-8fdb-c466558d2097 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832405996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3832405996 |
Directory | /workspace/18.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/18.keymgr_sideload_protect.2244774720 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 56900777 ps |
CPU time | 1.89 seconds |
Started | Jul 29 07:35:20 PM PDT 24 |
Finished | Jul 29 07:35:22 PM PDT 24 |
Peak memory | 209140 kb |
Host | smart-d0495d78-1c1b-44bb-9548-84a32295d93c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2244774720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2244774720 |
Directory | /workspace/18.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/18.keymgr_smoke.3236139614 |
Short name | T756 |
Test name | |
Test status | |
Simulation time | 190891107 ps |
CPU time | 2.86 seconds |
Started | Jul 29 07:35:11 PM PDT 24 |
Finished | Jul 29 07:35:14 PM PDT 24 |
Peak memory | 206820 kb |
Host | smart-51fae585-080c-4912-add7-7e48ca90ed47 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3236139614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3236139614 |
Directory | /workspace/18.keymgr_smoke/latest |
Test location | /workspace/coverage/default/18.keymgr_stress_all.3686332349 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 254654420 ps |
CPU time | 10.31 seconds |
Started | Jul 29 07:35:20 PM PDT 24 |
Finished | Jul 29 07:35:31 PM PDT 24 |
Peak memory | 216540 kb |
Host | smart-6262b480-1a37-445d-97cf-17265058cb89 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686332349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3686332349 |
Directory | /workspace/18.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/18.keymgr_sw_invalid_input.4013529144 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 322794830 ps |
CPU time | 8.42 seconds |
Started | Jul 29 07:35:20 PM PDT 24 |
Finished | Jul 29 07:35:29 PM PDT 24 |
Peak memory | 207320 kb |
Host | smart-28456360-6798-4252-b23a-984df277d2f9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4013529144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.4013529144 |
Directory | /workspace/18.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/18.keymgr_sync_async_fault_cross.386497965 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 337740899 ps |
CPU time | 3.03 seconds |
Started | Jul 29 07:35:20 PM PDT 24 |
Finished | Jul 29 07:35:23 PM PDT 24 |
Peak memory | 210444 kb |
Host | smart-63f65c22-1192-4bc7-9e1c-05bb2dd4eae2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=386497965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.386497965 |
Directory | /workspace/18.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/19.keymgr_alert_test.1646843379 |
Short name | T797 |
Test name | |
Test status | |
Simulation time | 8926383 ps |
CPU time | 0.83 seconds |
Started | Jul 29 07:35:18 PM PDT 24 |
Finished | Jul 29 07:35:24 PM PDT 24 |
Peak memory | 205960 kb |
Host | smart-a740baa3-44f7-4dec-bd0d-2327f41499f0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646843379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1646843379 |
Directory | /workspace/19.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/19.keymgr_cfg_regwen.1574585994 |
Short name | T850 |
Test name | |
Test status | |
Simulation time | 55198811 ps |
CPU time | 2.58 seconds |
Started | Jul 29 07:35:11 PM PDT 24 |
Finished | Jul 29 07:35:14 PM PDT 24 |
Peak memory | 214348 kb |
Host | smart-c5f90dd9-0181-4cb9-9570-1c062afe3a5e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1574585994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1574585994 |
Directory | /workspace/19.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/19.keymgr_custom_cm.1542821599 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 396681116 ps |
CPU time | 5.6 seconds |
Started | Jul 29 07:35:29 PM PDT 24 |
Finished | Jul 29 07:35:35 PM PDT 24 |
Peak memory | 210588 kb |
Host | smart-fca9e007-210c-4330-b309-191a740389c4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1542821599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1542821599 |
Directory | /workspace/19.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/19.keymgr_direct_to_disabled.1699826725 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 154548362 ps |
CPU time | 3.59 seconds |
Started | Jul 29 07:35:20 PM PDT 24 |
Finished | Jul 29 07:35:24 PM PDT 24 |
Peak memory | 214288 kb |
Host | smart-207113c9-d8f6-4351-aa5f-4c1a4f2e151a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1699826725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1699826725 |
Directory | /workspace/19.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1997049343 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 1237426776 ps |
CPU time | 7.66 seconds |
Started | Jul 29 07:35:37 PM PDT 24 |
Finished | Jul 29 07:35:44 PM PDT 24 |
Peak memory | 208604 kb |
Host | smart-8422078c-1e34-4fe9-8132-0d516a1aacc6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1997049343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1997049343 |
Directory | /workspace/19.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/19.keymgr_kmac_rsp_err.133483909 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 185658953 ps |
CPU time | 2.84 seconds |
Started | Jul 29 07:35:22 PM PDT 24 |
Finished | Jul 29 07:35:25 PM PDT 24 |
Peak memory | 214504 kb |
Host | smart-56327710-4fa5-4156-a3fa-014eaed1d6ad |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=133483909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.133483909 |
Directory | /workspace/19.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/19.keymgr_random.2898222658 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 310322704 ps |
CPU time | 8.84 seconds |
Started | Jul 29 07:35:21 PM PDT 24 |
Finished | Jul 29 07:35:30 PM PDT 24 |
Peak memory | 218320 kb |
Host | smart-91f6d754-406b-4ff0-902c-bedf4319496e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2898222658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2898222658 |
Directory | /workspace/19.keymgr_random/latest |
Test location | /workspace/coverage/default/19.keymgr_sideload.402547423 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 463569695 ps |
CPU time | 10.11 seconds |
Started | Jul 29 07:35:12 PM PDT 24 |
Finished | Jul 29 07:35:22 PM PDT 24 |
Peak memory | 208340 kb |
Host | smart-bc3cb267-a641-4acd-b0b5-0c8483683b63 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=402547423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.402547423 |
Directory | /workspace/19.keymgr_sideload/latest |
Test location | /workspace/coverage/default/19.keymgr_sideload_aes.1022190286 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 538466788 ps |
CPU time | 7.75 seconds |
Started | Jul 29 07:35:20 PM PDT 24 |
Finished | Jul 29 07:35:28 PM PDT 24 |
Peak memory | 208440 kb |
Host | smart-7bb171be-dc18-47be-9fa7-0c3b1a56cea4 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022190286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1022190286 |
Directory | /workspace/19.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/19.keymgr_sideload_kmac.1265216824 |
Short name | T784 |
Test name | |
Test status | |
Simulation time | 2180499797 ps |
CPU time | 38.1 seconds |
Started | Jul 29 07:35:21 PM PDT 24 |
Finished | Jul 29 07:35:59 PM PDT 24 |
Peak memory | 209052 kb |
Host | smart-67f91022-b42e-4b28-93f3-395b16e04ccc |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265216824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1265216824 |
Directory | /workspace/19.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/19.keymgr_sideload_otbn.2119489122 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 132510714 ps |
CPU time | 3.32 seconds |
Started | Jul 29 07:35:15 PM PDT 24 |
Finished | Jul 29 07:35:18 PM PDT 24 |
Peak memory | 208652 kb |
Host | smart-1fb07603-a9c9-4255-b623-bc837aaee90f |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119489122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2119489122 |
Directory | /workspace/19.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/19.keymgr_sideload_protect.553557085 |
Short name | T745 |
Test name | |
Test status | |
Simulation time | 220532190 ps |
CPU time | 3.57 seconds |
Started | Jul 29 07:35:18 PM PDT 24 |
Finished | Jul 29 07:35:22 PM PDT 24 |
Peak memory | 215864 kb |
Host | smart-3736f122-8082-490d-a789-1ac441c01095 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=553557085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.553557085 |
Directory | /workspace/19.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/19.keymgr_smoke.1920006112 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 544476351 ps |
CPU time | 3.78 seconds |
Started | Jul 29 07:35:12 PM PDT 24 |
Finished | Jul 29 07:35:16 PM PDT 24 |
Peak memory | 208488 kb |
Host | smart-3cb0ffcd-85b4-4916-894b-b04aa5070745 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1920006112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1920006112 |
Directory | /workspace/19.keymgr_smoke/latest |
Test location | /workspace/coverage/default/19.keymgr_sw_invalid_input.3739491151 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 1201199804 ps |
CPU time | 13.62 seconds |
Started | Jul 29 07:35:19 PM PDT 24 |
Finished | Jul 29 07:35:33 PM PDT 24 |
Peak memory | 214248 kb |
Host | smart-dc603f3f-6a61-4e31-8a13-675fd58b1d54 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3739491151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3739491151 |
Directory | /workspace/19.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/19.keymgr_sync_async_fault_cross.775969669 |
Short name | T742 |
Test name | |
Test status | |
Simulation time | 59644079 ps |
CPU time | 1.28 seconds |
Started | Jul 29 07:35:28 PM PDT 24 |
Finished | Jul 29 07:35:29 PM PDT 24 |
Peak memory | 210024 kb |
Host | smart-d3bbf2e0-46ef-4ef8-98f4-5497491f281e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=775969669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.775969669 |
Directory | /workspace/19.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/2.keymgr_alert_test.480695622 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 21012150 ps |
CPU time | 0.75 seconds |
Started | Jul 29 07:34:38 PM PDT 24 |
Finished | Jul 29 07:34:39 PM PDT 24 |
Peak memory | 205968 kb |
Host | smart-8de4da23-7214-4482-9289-d4e47fc801d9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480695622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.480695622 |
Directory | /workspace/2.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/2.keymgr_cfg_regwen.2553371120 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 142109822 ps |
CPU time | 2.9 seconds |
Started | Jul 29 07:34:37 PM PDT 24 |
Finished | Jul 29 07:34:40 PM PDT 24 |
Peak memory | 214376 kb |
Host | smart-d11d0249-7351-4709-a48d-5a0e8fc49b5d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2553371120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2553371120 |
Directory | /workspace/2.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/2.keymgr_direct_to_disabled.612533896 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 3993745627 ps |
CPU time | 33.61 seconds |
Started | Jul 29 07:34:41 PM PDT 24 |
Finished | Jul 29 07:35:15 PM PDT 24 |
Peak memory | 209032 kb |
Host | smart-81c9a0bc-4aaa-4f58-9d30-df8727694c83 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=612533896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.612533896 |
Directory | /workspace/2.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/2.keymgr_hwsw_invalid_input.4065828629 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 60002157 ps |
CPU time | 2.03 seconds |
Started | Jul 29 07:34:34 PM PDT 24 |
Finished | Jul 29 07:34:37 PM PDT 24 |
Peak memory | 214436 kb |
Host | smart-8848a255-d906-41c1-9039-89bc66957541 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4065828629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.4065828629 |
Directory | /workspace/2.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/2.keymgr_kmac_rsp_err.3236464915 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 81074054 ps |
CPU time | 1.84 seconds |
Started | Jul 29 07:34:36 PM PDT 24 |
Finished | Jul 29 07:34:38 PM PDT 24 |
Peak memory | 214272 kb |
Host | smart-3f665aac-15cb-48a5-a1b4-775dc4993e33 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3236464915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3236464915 |
Directory | /workspace/2.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/2.keymgr_lc_disable.4174468284 |
Short name | T799 |
Test name | |
Test status | |
Simulation time | 287202171 ps |
CPU time | 7.32 seconds |
Started | Jul 29 07:34:40 PM PDT 24 |
Finished | Jul 29 07:34:47 PM PDT 24 |
Peak memory | 219528 kb |
Host | smart-0486ceb3-fe84-4a28-939e-1cc0f97b323f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4174468284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.4174468284 |
Directory | /workspace/2.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/2.keymgr_random.2053544463 |
Short name | T762 |
Test name | |
Test status | |
Simulation time | 323018183 ps |
CPU time | 3.46 seconds |
Started | Jul 29 07:34:42 PM PDT 24 |
Finished | Jul 29 07:34:45 PM PDT 24 |
Peak memory | 208608 kb |
Host | smart-b81a60de-4d2a-43c5-9160-bcf2cfa2601e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2053544463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2053544463 |
Directory | /workspace/2.keymgr_random/latest |
Test location | /workspace/coverage/default/2.keymgr_sec_cm.381216314 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 639174755 ps |
CPU time | 5.06 seconds |
Started | Jul 29 07:34:39 PM PDT 24 |
Finished | Jul 29 07:34:44 PM PDT 24 |
Peak memory | 233480 kb |
Host | smart-484bd4c2-8b6a-468a-8f6d-6f06158f45f2 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381216314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.381216314 |
Directory | /workspace/2.keymgr_sec_cm/latest |
Test location | /workspace/coverage/default/2.keymgr_sideload.3588840328 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 34158825 ps |
CPU time | 2.33 seconds |
Started | Jul 29 07:34:33 PM PDT 24 |
Finished | Jul 29 07:34:35 PM PDT 24 |
Peak memory | 206976 kb |
Host | smart-b41171fb-b18f-4e07-be9a-b27cee9c6d1c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3588840328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3588840328 |
Directory | /workspace/2.keymgr_sideload/latest |
Test location | /workspace/coverage/default/2.keymgr_sideload_aes.3976100968 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 370369687 ps |
CPU time | 4.36 seconds |
Started | Jul 29 07:34:39 PM PDT 24 |
Finished | Jul 29 07:34:44 PM PDT 24 |
Peak memory | 208548 kb |
Host | smart-144594b1-fdff-4882-96d5-19340294ae4d |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976100968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3976100968 |
Directory | /workspace/2.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/2.keymgr_sideload_kmac.2742780451 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 309239169 ps |
CPU time | 4.39 seconds |
Started | Jul 29 07:34:39 PM PDT 24 |
Finished | Jul 29 07:34:44 PM PDT 24 |
Peak memory | 207824 kb |
Host | smart-944bb652-0835-43dd-82a6-4c0e3ef5fe39 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742780451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2742780451 |
Directory | /workspace/2.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/2.keymgr_sideload_otbn.830529730 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 23469774 ps |
CPU time | 1.88 seconds |
Started | Jul 29 07:34:43 PM PDT 24 |
Finished | Jul 29 07:34:45 PM PDT 24 |
Peak memory | 206876 kb |
Host | smart-d9cce942-4a63-4405-8df2-7c5cdcb5ba60 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830529730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.830529730 |
Directory | /workspace/2.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/2.keymgr_sideload_protect.63754416 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 355637709 ps |
CPU time | 2.94 seconds |
Started | Jul 29 07:34:37 PM PDT 24 |
Finished | Jul 29 07:34:40 PM PDT 24 |
Peak memory | 215976 kb |
Host | smart-d577db83-6b51-46e4-ac8f-1d15002381a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=63754416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.63754416 |
Directory | /workspace/2.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/2.keymgr_smoke.111703852 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 827851458 ps |
CPU time | 12.41 seconds |
Started | Jul 29 07:34:33 PM PDT 24 |
Finished | Jul 29 07:34:45 PM PDT 24 |
Peak memory | 207740 kb |
Host | smart-d4113118-237b-43bc-b252-2bd93861b667 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=111703852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.111703852 |
Directory | /workspace/2.keymgr_smoke/latest |
Test location | /workspace/coverage/default/2.keymgr_sw_invalid_input.687835435 |
Short name | T875 |
Test name | |
Test status | |
Simulation time | 198581273 ps |
CPU time | 5.6 seconds |
Started | Jul 29 07:34:43 PM PDT 24 |
Finished | Jul 29 07:34:48 PM PDT 24 |
Peak memory | 209076 kb |
Host | smart-ae867c56-6953-4660-9589-2b18e7913bb0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=687835435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.687835435 |
Directory | /workspace/2.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2854900336 |
Short name | T647 |
Test name | |
Test status | |
Simulation time | 34035596 ps |
CPU time | 1.83 seconds |
Started | Jul 29 07:34:33 PM PDT 24 |
Finished | Jul 29 07:34:35 PM PDT 24 |
Peak memory | 209776 kb |
Host | smart-f63fc2ed-ffa6-4090-803c-53f20029ba65 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2854900336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2854900336 |
Directory | /workspace/2.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/20.keymgr_alert_test.3678147976 |
Short name | T657 |
Test name | |
Test status | |
Simulation time | 13401127 ps |
CPU time | 0.91 seconds |
Started | Jul 29 07:35:30 PM PDT 24 |
Finished | Jul 29 07:35:31 PM PDT 24 |
Peak memory | 205952 kb |
Host | smart-f4a31272-97bd-433c-afc3-ee771e48d687 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678147976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3678147976 |
Directory | /workspace/20.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/20.keymgr_cfg_regwen.3282718274 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 59083148 ps |
CPU time | 3.53 seconds |
Started | Jul 29 07:35:21 PM PDT 24 |
Finished | Jul 29 07:35:25 PM PDT 24 |
Peak memory | 214252 kb |
Host | smart-7562782b-467b-48c3-930a-cf8fc77fbd8e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3282718274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3282718274 |
Directory | /workspace/20.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/20.keymgr_custom_cm.3697977488 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 160893160 ps |
CPU time | 3.62 seconds |
Started | Jul 29 07:35:18 PM PDT 24 |
Finished | Jul 29 07:35:21 PM PDT 24 |
Peak memory | 210420 kb |
Host | smart-dff2e77a-a3a9-4740-9793-9645976afe59 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3697977488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3697977488 |
Directory | /workspace/20.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/20.keymgr_direct_to_disabled.151629953 |
Short name | T701 |
Test name | |
Test status | |
Simulation time | 55790849 ps |
CPU time | 1.56 seconds |
Started | Jul 29 07:35:28 PM PDT 24 |
Finished | Jul 29 07:35:30 PM PDT 24 |
Peak memory | 207204 kb |
Host | smart-04ceea15-e86d-409e-9ab5-821b1c9f56de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=151629953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.151629953 |
Directory | /workspace/20.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2116020892 |
Short name | T846 |
Test name | |
Test status | |
Simulation time | 126196139 ps |
CPU time | 2.19 seconds |
Started | Jul 29 07:35:22 PM PDT 24 |
Finished | Jul 29 07:35:24 PM PDT 24 |
Peak memory | 214308 kb |
Host | smart-a73f78f1-b7ba-4ba5-a4ed-4fca250dd9bc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2116020892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2116020892 |
Directory | /workspace/20.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/20.keymgr_kmac_rsp_err.2387665475 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 249048056 ps |
CPU time | 2.23 seconds |
Started | Jul 29 07:35:32 PM PDT 24 |
Finished | Jul 29 07:35:34 PM PDT 24 |
Peak memory | 220508 kb |
Host | smart-c09a5fa0-2a72-404e-bca2-f8fd85b252fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2387665475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2387665475 |
Directory | /workspace/20.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/20.keymgr_lc_disable.633561658 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 216659782 ps |
CPU time | 3.34 seconds |
Started | Jul 29 07:35:24 PM PDT 24 |
Finished | Jul 29 07:35:27 PM PDT 24 |
Peak memory | 208048 kb |
Host | smart-f455efee-db99-4b64-b1c0-155f168eb23d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=633561658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.633561658 |
Directory | /workspace/20.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/20.keymgr_random.357013354 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 543960744 ps |
CPU time | 8.39 seconds |
Started | Jul 29 07:35:32 PM PDT 24 |
Finished | Jul 29 07:35:40 PM PDT 24 |
Peak memory | 209844 kb |
Host | smart-4f1f0232-57d6-4b04-8dd7-6fb799b468de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=357013354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.357013354 |
Directory | /workspace/20.keymgr_random/latest |
Test location | /workspace/coverage/default/20.keymgr_sideload.2856098630 |
Short name | T707 |
Test name | |
Test status | |
Simulation time | 5682817474 ps |
CPU time | 55.63 seconds |
Started | Jul 29 07:35:36 PM PDT 24 |
Finished | Jul 29 07:36:32 PM PDT 24 |
Peak memory | 208988 kb |
Host | smart-fefaf5f8-5471-47a5-b459-8ef5b051f5da |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2856098630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2856098630 |
Directory | /workspace/20.keymgr_sideload/latest |
Test location | /workspace/coverage/default/20.keymgr_sideload_aes.1187803054 |
Short name | T769 |
Test name | |
Test status | |
Simulation time | 222795487 ps |
CPU time | 5.19 seconds |
Started | Jul 29 07:35:19 PM PDT 24 |
Finished | Jul 29 07:35:24 PM PDT 24 |
Peak memory | 208732 kb |
Host | smart-042a3239-40c9-498b-9581-382fa3e87b62 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187803054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1187803054 |
Directory | /workspace/20.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/20.keymgr_sideload_kmac.3555489803 |
Short name | T632 |
Test name | |
Test status | |
Simulation time | 862868135 ps |
CPU time | 5.27 seconds |
Started | Jul 29 07:35:17 PM PDT 24 |
Finished | Jul 29 07:35:22 PM PDT 24 |
Peak memory | 208620 kb |
Host | smart-4c679a67-ff07-4a33-a1be-eda6179896ad |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555489803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3555489803 |
Directory | /workspace/20.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/20.keymgr_sideload_otbn.2908050635 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 558387996 ps |
CPU time | 4.67 seconds |
Started | Jul 29 07:35:18 PM PDT 24 |
Finished | Jul 29 07:35:22 PM PDT 24 |
Peak memory | 208892 kb |
Host | smart-7c8b44e8-9012-4fcc-b0c2-fbe9e0a57fcb |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908050635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2908050635 |
Directory | /workspace/20.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/20.keymgr_sideload_protect.3503107690 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 23356727 ps |
CPU time | 1.86 seconds |
Started | Jul 29 07:35:26 PM PDT 24 |
Finished | Jul 29 07:35:28 PM PDT 24 |
Peak memory | 208748 kb |
Host | smart-8fd67567-f98b-4ba9-bad1-3f0f294050eb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3503107690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3503107690 |
Directory | /workspace/20.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/20.keymgr_smoke.417852442 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 39837755 ps |
CPU time | 2.09 seconds |
Started | Jul 29 07:35:19 PM PDT 24 |
Finished | Jul 29 07:35:21 PM PDT 24 |
Peak memory | 206736 kb |
Host | smart-3474ee23-0272-4da2-9f94-e1998a678e76 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=417852442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.417852442 |
Directory | /workspace/20.keymgr_smoke/latest |
Test location | /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.982806272 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 273487868 ps |
CPU time | 9.45 seconds |
Started | Jul 29 07:35:18 PM PDT 24 |
Finished | Jul 29 07:35:28 PM PDT 24 |
Peak memory | 222172 kb |
Host | smart-4c8a9584-7023-43b9-9417-982fef7dbafc |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982806272 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.982806272 |
Directory | /workspace/20.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/20.keymgr_sw_invalid_input.3423030363 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 310520127 ps |
CPU time | 8.25 seconds |
Started | Jul 29 07:35:24 PM PDT 24 |
Finished | Jul 29 07:35:33 PM PDT 24 |
Peak memory | 209920 kb |
Host | smart-3553c765-2152-4c5f-abb3-14dd2bedc454 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3423030363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3423030363 |
Directory | /workspace/20.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3761732515 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 112187523 ps |
CPU time | 1.9 seconds |
Started | Jul 29 07:35:22 PM PDT 24 |
Finished | Jul 29 07:35:24 PM PDT 24 |
Peak memory | 210132 kb |
Host | smart-e3d159c8-b4d4-452b-a5ab-7b2b2a2d366b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3761732515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3761732515 |
Directory | /workspace/20.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/21.keymgr_alert_test.3784854598 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 18004036 ps |
CPU time | 0.76 seconds |
Started | Jul 29 07:35:22 PM PDT 24 |
Finished | Jul 29 07:35:23 PM PDT 24 |
Peak memory | 205960 kb |
Host | smart-d7c219f0-8413-4edb-b1eb-c5f41d1f6255 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784854598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3784854598 |
Directory | /workspace/21.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/21.keymgr_direct_to_disabled.1069707372 |
Short name | T625 |
Test name | |
Test status | |
Simulation time | 22971937 ps |
CPU time | 1.87 seconds |
Started | Jul 29 07:35:32 PM PDT 24 |
Finished | Jul 29 07:35:34 PM PDT 24 |
Peak memory | 209924 kb |
Host | smart-0941b403-250e-4f41-8d61-85fed61bea4d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1069707372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1069707372 |
Directory | /workspace/21.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1575330641 |
Short name | T792 |
Test name | |
Test status | |
Simulation time | 1326050247 ps |
CPU time | 7.23 seconds |
Started | Jul 29 07:35:24 PM PDT 24 |
Finished | Jul 29 07:35:31 PM PDT 24 |
Peak memory | 214184 kb |
Host | smart-1fb739df-99a0-4aec-86d4-d55930756884 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1575330641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1575330641 |
Directory | /workspace/21.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/21.keymgr_kmac_rsp_err.829493303 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 33622892 ps |
CPU time | 2.35 seconds |
Started | Jul 29 07:35:19 PM PDT 24 |
Finished | Jul 29 07:35:22 PM PDT 24 |
Peak memory | 211420 kb |
Host | smart-00701385-d9df-4070-b16d-c2f96cbcea3e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=829493303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.829493303 |
Directory | /workspace/21.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/21.keymgr_lc_disable.113272201 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 228951448 ps |
CPU time | 3.87 seconds |
Started | Jul 29 07:35:18 PM PDT 24 |
Finished | Jul 29 07:35:22 PM PDT 24 |
Peak memory | 222404 kb |
Host | smart-8e15bc4f-5a47-48c6-a3f9-2535944adf34 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113272201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.113272201 |
Directory | /workspace/21.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/21.keymgr_random.894865680 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 194617119 ps |
CPU time | 3.62 seconds |
Started | Jul 29 07:35:24 PM PDT 24 |
Finished | Jul 29 07:35:27 PM PDT 24 |
Peak memory | 218304 kb |
Host | smart-77b91adc-2d04-4efb-ba3c-7c1a6e556367 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=894865680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.894865680 |
Directory | /workspace/21.keymgr_random/latest |
Test location | /workspace/coverage/default/21.keymgr_sideload.766403321 |
Short name | T688 |
Test name | |
Test status | |
Simulation time | 427900933 ps |
CPU time | 3.56 seconds |
Started | Jul 29 07:35:28 PM PDT 24 |
Finished | Jul 29 07:35:32 PM PDT 24 |
Peak memory | 206920 kb |
Host | smart-7db95689-00ae-4f30-ad60-f8cafaba4081 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=766403321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.766403321 |
Directory | /workspace/21.keymgr_sideload/latest |
Test location | /workspace/coverage/default/21.keymgr_sideload_aes.1168647541 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 236783605 ps |
CPU time | 2.55 seconds |
Started | Jul 29 07:35:31 PM PDT 24 |
Finished | Jul 29 07:35:33 PM PDT 24 |
Peak memory | 207436 kb |
Host | smart-d3008aad-00ba-4554-b67e-02102d2b6f82 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168647541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1168647541 |
Directory | /workspace/21.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/21.keymgr_sideload_kmac.528344324 |
Short name | T741 |
Test name | |
Test status | |
Simulation time | 61775888 ps |
CPU time | 2.13 seconds |
Started | Jul 29 07:35:30 PM PDT 24 |
Finished | Jul 29 07:35:33 PM PDT 24 |
Peak memory | 206916 kb |
Host | smart-50aa295c-33ac-49c6-bfc6-04cb1eae3333 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528344324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.528344324 |
Directory | /workspace/21.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/21.keymgr_sideload_otbn.1303955150 |
Short name | T761 |
Test name | |
Test status | |
Simulation time | 213968167 ps |
CPU time | 5.64 seconds |
Started | Jul 29 07:35:17 PM PDT 24 |
Finished | Jul 29 07:35:23 PM PDT 24 |
Peak memory | 208636 kb |
Host | smart-aa658d53-da8a-4198-8f0e-2868ac6181b5 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303955150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1303955150 |
Directory | /workspace/21.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/21.keymgr_sideload_protect.4168400611 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 151440027 ps |
CPU time | 1.98 seconds |
Started | Jul 29 07:35:42 PM PDT 24 |
Finished | Jul 29 07:35:44 PM PDT 24 |
Peak memory | 208852 kb |
Host | smart-378dc0e1-9acf-4756-879e-36d486a653ea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4168400611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.4168400611 |
Directory | /workspace/21.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/21.keymgr_smoke.683569263 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 86284363 ps |
CPU time | 2.22 seconds |
Started | Jul 29 07:35:31 PM PDT 24 |
Finished | Jul 29 07:35:33 PM PDT 24 |
Peak memory | 207132 kb |
Host | smart-baa94b04-37ef-4295-a5e7-32662cce0294 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=683569263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.683569263 |
Directory | /workspace/21.keymgr_smoke/latest |
Test location | /workspace/coverage/default/21.keymgr_stress_all.2786499061 |
Short name | T705 |
Test name | |
Test status | |
Simulation time | 7334828065 ps |
CPU time | 57.59 seconds |
Started | Jul 29 07:35:22 PM PDT 24 |
Finished | Jul 29 07:36:20 PM PDT 24 |
Peak memory | 222476 kb |
Host | smart-dab23748-798f-4c28-b110-c0ed2c299dae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786499061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2786499061 |
Directory | /workspace/21.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/21.keymgr_sw_invalid_input.178663218 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 208485405 ps |
CPU time | 3.8 seconds |
Started | Jul 29 07:35:23 PM PDT 24 |
Finished | Jul 29 07:35:27 PM PDT 24 |
Peak memory | 208312 kb |
Host | smart-40832d34-abd8-4868-91df-f5b717d14cf7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=178663218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.178663218 |
Directory | /workspace/21.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3373278192 |
Short name | T845 |
Test name | |
Test status | |
Simulation time | 74606519 ps |
CPU time | 2.55 seconds |
Started | Jul 29 07:35:22 PM PDT 24 |
Finished | Jul 29 07:35:24 PM PDT 24 |
Peak memory | 210324 kb |
Host | smart-b8c8c9cb-5fe2-43fd-9ff9-0d19b196e4ff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3373278192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3373278192 |
Directory | /workspace/21.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/22.keymgr_alert_test.1590772574 |
Short name | T644 |
Test name | |
Test status | |
Simulation time | 40338016 ps |
CPU time | 0.84 seconds |
Started | Jul 29 07:35:44 PM PDT 24 |
Finished | Jul 29 07:35:45 PM PDT 24 |
Peak memory | 205972 kb |
Host | smart-24b03fac-6b6f-42d5-aa25-e7c375a282e6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590772574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1590772574 |
Directory | /workspace/22.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/22.keymgr_cfg_regwen.4156518462 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 34053104 ps |
CPU time | 2.54 seconds |
Started | Jul 29 07:35:20 PM PDT 24 |
Finished | Jul 29 07:35:23 PM PDT 24 |
Peak memory | 215464 kb |
Host | smart-da7cfd3f-8720-4361-ab0a-8ccfd6b1836f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4156518462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.4156518462 |
Directory | /workspace/22.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/22.keymgr_custom_cm.164863271 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 133246028 ps |
CPU time | 3.67 seconds |
Started | Jul 29 07:35:41 PM PDT 24 |
Finished | Jul 29 07:35:45 PM PDT 24 |
Peak memory | 219328 kb |
Host | smart-1fc93bb0-9ff1-4963-95dc-bd8e8ad665c9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=164863271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.164863271 |
Directory | /workspace/22.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/22.keymgr_direct_to_disabled.85797861 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 119192962 ps |
CPU time | 3.35 seconds |
Started | Jul 29 07:35:27 PM PDT 24 |
Finished | Jul 29 07:35:30 PM PDT 24 |
Peak memory | 207384 kb |
Host | smart-3ec22382-cc68-4837-8759-5ab841f42821 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=85797861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.85797861 |
Directory | /workspace/22.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/22.keymgr_hwsw_invalid_input.514788597 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 5744679116 ps |
CPU time | 27.83 seconds |
Started | Jul 29 07:35:35 PM PDT 24 |
Finished | Jul 29 07:36:04 PM PDT 24 |
Peak memory | 222548 kb |
Host | smart-50bc9e07-6aa6-4b08-927a-3d60e185d38c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=514788597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.514788597 |
Directory | /workspace/22.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/22.keymgr_kmac_rsp_err.1527182099 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 158013228 ps |
CPU time | 3.1 seconds |
Started | Jul 29 07:35:20 PM PDT 24 |
Finished | Jul 29 07:35:23 PM PDT 24 |
Peak memory | 222332 kb |
Host | smart-af8a2198-d606-40c1-8004-e7084a8ad413 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1527182099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1527182099 |
Directory | /workspace/22.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/22.keymgr_lc_disable.2164095699 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 317717176 ps |
CPU time | 2.1 seconds |
Started | Jul 29 07:35:41 PM PDT 24 |
Finished | Jul 29 07:35:43 PM PDT 24 |
Peak memory | 219408 kb |
Host | smart-a84a0d78-350d-41f7-9835-1ff16bed5b7f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2164095699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2164095699 |
Directory | /workspace/22.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/22.keymgr_random.2110573550 |
Short name | T899 |
Test name | |
Test status | |
Simulation time | 1134522645 ps |
CPU time | 29.72 seconds |
Started | Jul 29 07:35:39 PM PDT 24 |
Finished | Jul 29 07:36:09 PM PDT 24 |
Peak memory | 214356 kb |
Host | smart-e8f01864-aaf9-4afe-8f9d-b1b541730a58 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2110573550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2110573550 |
Directory | /workspace/22.keymgr_random/latest |
Test location | /workspace/coverage/default/22.keymgr_sideload.66496047 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 52000335 ps |
CPU time | 2.87 seconds |
Started | Jul 29 07:35:32 PM PDT 24 |
Finished | Jul 29 07:35:35 PM PDT 24 |
Peak memory | 208784 kb |
Host | smart-bcc5365c-29eb-464b-b3bd-02cbb61f9c3d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66496047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.66496047 |
Directory | /workspace/22.keymgr_sideload/latest |
Test location | /workspace/coverage/default/22.keymgr_sideload_aes.2167713169 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 83450498 ps |
CPU time | 3.95 seconds |
Started | Jul 29 07:35:19 PM PDT 24 |
Finished | Jul 29 07:35:23 PM PDT 24 |
Peak memory | 208776 kb |
Host | smart-1d77b91f-3b59-47c6-8df2-35fa3c39ac90 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167713169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2167713169 |
Directory | /workspace/22.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/22.keymgr_sideload_kmac.162317634 |
Short name | T872 |
Test name | |
Test status | |
Simulation time | 212393228 ps |
CPU time | 3.64 seconds |
Started | Jul 29 07:35:22 PM PDT 24 |
Finished | Jul 29 07:35:26 PM PDT 24 |
Peak memory | 206964 kb |
Host | smart-4ac6f3b3-33b1-4562-b3be-5321cbaf82d1 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162317634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.162317634 |
Directory | /workspace/22.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/22.keymgr_sideload_otbn.4001389059 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 220889466 ps |
CPU time | 2.53 seconds |
Started | Jul 29 07:35:20 PM PDT 24 |
Finished | Jul 29 07:35:23 PM PDT 24 |
Peak memory | 208328 kb |
Host | smart-c29e96d6-9490-437b-b0ef-2bcd1df9e29e |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001389059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.4001389059 |
Directory | /workspace/22.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/22.keymgr_sideload_protect.3792098396 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 41575514 ps |
CPU time | 2.51 seconds |
Started | Jul 29 07:35:19 PM PDT 24 |
Finished | Jul 29 07:35:22 PM PDT 24 |
Peak memory | 210080 kb |
Host | smart-75067012-572d-464c-8bdc-58b2083dae03 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3792098396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3792098396 |
Directory | /workspace/22.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/22.keymgr_smoke.297083001 |
Short name | T820 |
Test name | |
Test status | |
Simulation time | 69874811 ps |
CPU time | 2.83 seconds |
Started | Jul 29 07:35:36 PM PDT 24 |
Finished | Jul 29 07:35:39 PM PDT 24 |
Peak memory | 208592 kb |
Host | smart-314cf924-a227-4616-84ae-b8221d73580f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=297083001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.297083001 |
Directory | /workspace/22.keymgr_smoke/latest |
Test location | /workspace/coverage/default/22.keymgr_stress_all.3373604781 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 926789652 ps |
CPU time | 31.55 seconds |
Started | Jul 29 07:35:31 PM PDT 24 |
Finished | Jul 29 07:36:02 PM PDT 24 |
Peak memory | 222416 kb |
Host | smart-2117bca8-66f8-47c9-b375-aa3b15180865 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373604781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3373604781 |
Directory | /workspace/22.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/22.keymgr_sw_invalid_input.3146387571 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 182479521 ps |
CPU time | 4.98 seconds |
Started | Jul 29 07:35:23 PM PDT 24 |
Finished | Jul 29 07:35:28 PM PDT 24 |
Peak memory | 207956 kb |
Host | smart-5242b705-0388-4676-9c54-c1e2ab80269c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3146387571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3146387571 |
Directory | /workspace/22.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3431733814 |
Short name | T682 |
Test name | |
Test status | |
Simulation time | 45745520 ps |
CPU time | 2.62 seconds |
Started | Jul 29 07:35:22 PM PDT 24 |
Finished | Jul 29 07:35:25 PM PDT 24 |
Peak memory | 209752 kb |
Host | smart-80e32aa4-c93c-4f33-9149-933e720ee497 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3431733814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3431733814 |
Directory | /workspace/22.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/23.keymgr_alert_test.1368547553 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 20689241 ps |
CPU time | 0.8 seconds |
Started | Jul 29 07:35:52 PM PDT 24 |
Finished | Jul 29 07:35:53 PM PDT 24 |
Peak memory | 205980 kb |
Host | smart-9e98ffa0-c3e2-4cfd-bebd-71cfa92ea3da |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368547553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1368547553 |
Directory | /workspace/23.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/23.keymgr_direct_to_disabled.3434658795 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 115856684 ps |
CPU time | 2.21 seconds |
Started | Jul 29 07:35:39 PM PDT 24 |
Finished | Jul 29 07:35:42 PM PDT 24 |
Peak memory | 207632 kb |
Host | smart-25d1f5f0-c1b9-4334-8aa0-908f54ab6264 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3434658795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3434658795 |
Directory | /workspace/23.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2209104819 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 259432169 ps |
CPU time | 2.41 seconds |
Started | Jul 29 07:35:39 PM PDT 24 |
Finished | Jul 29 07:35:42 PM PDT 24 |
Peak memory | 214268 kb |
Host | smart-9bf569b8-1148-4440-aad2-56f3df081215 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2209104819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2209104819 |
Directory | /workspace/23.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/23.keymgr_kmac_rsp_err.1497569640 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 178873555 ps |
CPU time | 3.52 seconds |
Started | Jul 29 07:35:38 PM PDT 24 |
Finished | Jul 29 07:35:42 PM PDT 24 |
Peak memory | 219524 kb |
Host | smart-ab1358a4-0770-4480-be3a-9b99a5d3e62a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1497569640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1497569640 |
Directory | /workspace/23.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/23.keymgr_lc_disable.3240219333 |
Short name | T851 |
Test name | |
Test status | |
Simulation time | 75830731 ps |
CPU time | 2.39 seconds |
Started | Jul 29 07:35:41 PM PDT 24 |
Finished | Jul 29 07:35:43 PM PDT 24 |
Peak memory | 206104 kb |
Host | smart-8a02d982-3885-4e60-990f-261df33d4fbe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3240219333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3240219333 |
Directory | /workspace/23.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/23.keymgr_random.312539032 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 152873135 ps |
CPU time | 6.24 seconds |
Started | Jul 29 07:35:39 PM PDT 24 |
Finished | Jul 29 07:35:46 PM PDT 24 |
Peak memory | 210408 kb |
Host | smart-59d93189-2f6a-457c-a6f3-adb167c1a0bb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=312539032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.312539032 |
Directory | /workspace/23.keymgr_random/latest |
Test location | /workspace/coverage/default/23.keymgr_sideload.242670898 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 100677928 ps |
CPU time | 4.26 seconds |
Started | Jul 29 07:35:25 PM PDT 24 |
Finished | Jul 29 07:35:29 PM PDT 24 |
Peak memory | 208888 kb |
Host | smart-98c57ce9-f7b7-422e-89d9-b8ca4dd760a8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=242670898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.242670898 |
Directory | /workspace/23.keymgr_sideload/latest |
Test location | /workspace/coverage/default/23.keymgr_sideload_aes.3876879167 |
Short name | T722 |
Test name | |
Test status | |
Simulation time | 726316461 ps |
CPU time | 9.28 seconds |
Started | Jul 29 07:35:21 PM PDT 24 |
Finished | Jul 29 07:35:30 PM PDT 24 |
Peak memory | 207964 kb |
Host | smart-0c61ded5-ea52-41a3-86d3-f2f2ed62e025 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876879167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3876879167 |
Directory | /workspace/23.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/23.keymgr_sideload_kmac.3491771839 |
Short name | T638 |
Test name | |
Test status | |
Simulation time | 711389899 ps |
CPU time | 8.39 seconds |
Started | Jul 29 07:35:25 PM PDT 24 |
Finished | Jul 29 07:35:33 PM PDT 24 |
Peak memory | 208780 kb |
Host | smart-81558a8a-a89c-4a0c-9a84-939c9f857b05 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491771839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3491771839 |
Directory | /workspace/23.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/23.keymgr_sideload_otbn.78002621 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 372700695 ps |
CPU time | 4.11 seconds |
Started | Jul 29 07:35:45 PM PDT 24 |
Finished | Jul 29 07:35:49 PM PDT 24 |
Peak memory | 208484 kb |
Host | smart-ada13895-13aa-48ee-aa46-ff3e31b53be9 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78002621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.78002621 |
Directory | /workspace/23.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/23.keymgr_sideload_protect.792800448 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 143152450 ps |
CPU time | 2.53 seconds |
Started | Jul 29 07:35:46 PM PDT 24 |
Finished | Jul 29 07:35:49 PM PDT 24 |
Peak memory | 210232 kb |
Host | smart-2661d6ae-38fe-43b6-a8a2-947cca04a510 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=792800448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.792800448 |
Directory | /workspace/23.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/23.keymgr_smoke.3212657860 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 183043922 ps |
CPU time | 2.59 seconds |
Started | Jul 29 07:35:25 PM PDT 24 |
Finished | Jul 29 07:35:28 PM PDT 24 |
Peak memory | 206068 kb |
Host | smart-01fd1269-5077-4314-a8ca-cd1e786a4287 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3212657860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3212657860 |
Directory | /workspace/23.keymgr_smoke/latest |
Test location | /workspace/coverage/default/23.keymgr_stress_all.326633357 |
Short name | T816 |
Test name | |
Test status | |
Simulation time | 1492145435 ps |
CPU time | 13.31 seconds |
Started | Jul 29 07:35:58 PM PDT 24 |
Finished | Jul 29 07:36:12 PM PDT 24 |
Peak memory | 222552 kb |
Host | smart-51fba25e-fc51-4c14-b983-a0b1d69b4d99 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326633357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.326633357 |
Directory | /workspace/23.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/23.keymgr_sw_invalid_input.3106869599 |
Short name | T883 |
Test name | |
Test status | |
Simulation time | 603693494 ps |
CPU time | 5.49 seconds |
Started | Jul 29 07:35:25 PM PDT 24 |
Finished | Jul 29 07:35:30 PM PDT 24 |
Peak memory | 214312 kb |
Host | smart-41d834da-0c75-4908-84ed-785bc5f71b4c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3106869599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3106869599 |
Directory | /workspace/23.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3721343471 |
Short name | T773 |
Test name | |
Test status | |
Simulation time | 75113224 ps |
CPU time | 1.87 seconds |
Started | Jul 29 07:35:42 PM PDT 24 |
Finished | Jul 29 07:35:44 PM PDT 24 |
Peak memory | 209664 kb |
Host | smart-7fb8777e-f0d1-426e-921f-75e5966d5182 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3721343471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3721343471 |
Directory | /workspace/23.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/24.keymgr_alert_test.175569343 |
Short name | T876 |
Test name | |
Test status | |
Simulation time | 38480724 ps |
CPU time | 0.75 seconds |
Started | Jul 29 07:35:55 PM PDT 24 |
Finished | Jul 29 07:35:56 PM PDT 24 |
Peak memory | 205940 kb |
Host | smart-442ac16b-6d66-4693-abfe-d774e0bdecf2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175569343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.175569343 |
Directory | /workspace/24.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/24.keymgr_cfg_regwen.2614227676 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 203623310 ps |
CPU time | 3.92 seconds |
Started | Jul 29 07:35:50 PM PDT 24 |
Finished | Jul 29 07:35:54 PM PDT 24 |
Peak memory | 215388 kb |
Host | smart-a1cf0929-3ae8-473b-ba90-31eb4207d7ea |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2614227676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2614227676 |
Directory | /workspace/24.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/24.keymgr_custom_cm.3152805048 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 497381458 ps |
CPU time | 3.91 seconds |
Started | Jul 29 07:35:38 PM PDT 24 |
Finished | Jul 29 07:35:42 PM PDT 24 |
Peak memory | 218908 kb |
Host | smart-fff71e82-cb9e-456e-8e2e-82fd51c1ff33 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3152805048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3152805048 |
Directory | /workspace/24.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/24.keymgr_direct_to_disabled.3159039640 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 23981131 ps |
CPU time | 2.04 seconds |
Started | Jul 29 07:35:40 PM PDT 24 |
Finished | Jul 29 07:35:42 PM PDT 24 |
Peak memory | 207956 kb |
Host | smart-2676f8f8-c8ec-4c6c-ab1e-33e9b534c192 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3159039640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3159039640 |
Directory | /workspace/24.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2536192648 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 388781135 ps |
CPU time | 5.21 seconds |
Started | Jul 29 07:35:48 PM PDT 24 |
Finished | Jul 29 07:35:53 PM PDT 24 |
Peak memory | 220320 kb |
Host | smart-e5797764-d104-4161-b21f-7a2396630491 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2536192648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2536192648 |
Directory | /workspace/24.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/24.keymgr_kmac_rsp_err.978017940 |
Short name | T887 |
Test name | |
Test status | |
Simulation time | 104925878 ps |
CPU time | 4.56 seconds |
Started | Jul 29 07:35:56 PM PDT 24 |
Finished | Jul 29 07:36:01 PM PDT 24 |
Peak memory | 214288 kb |
Host | smart-4f74f983-46e1-446f-a420-3c3c0dfb2efd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=978017940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.978017940 |
Directory | /workspace/24.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/24.keymgr_random.535060613 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 439506185 ps |
CPU time | 3.56 seconds |
Started | Jul 29 07:35:55 PM PDT 24 |
Finished | Jul 29 07:35:59 PM PDT 24 |
Peak memory | 207708 kb |
Host | smart-5e25f390-7992-4236-ad7b-962d4aaa9935 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=535060613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.535060613 |
Directory | /workspace/24.keymgr_random/latest |
Test location | /workspace/coverage/default/24.keymgr_sideload.2506505009 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 69950958 ps |
CPU time | 1.76 seconds |
Started | Jul 29 07:35:40 PM PDT 24 |
Finished | Jul 29 07:35:42 PM PDT 24 |
Peak memory | 206996 kb |
Host | smart-faf9fca0-9517-44b6-8c68-118d1a868880 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2506505009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2506505009 |
Directory | /workspace/24.keymgr_sideload/latest |
Test location | /workspace/coverage/default/24.keymgr_sideload_aes.1476406211 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 1301465491 ps |
CPU time | 36.42 seconds |
Started | Jul 29 07:35:51 PM PDT 24 |
Finished | Jul 29 07:36:28 PM PDT 24 |
Peak memory | 209012 kb |
Host | smart-c61164aa-0455-4709-89bd-dab38be83b60 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476406211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1476406211 |
Directory | /workspace/24.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/24.keymgr_sideload_kmac.3473647120 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 193349473 ps |
CPU time | 5.28 seconds |
Started | Jul 29 07:35:40 PM PDT 24 |
Finished | Jul 29 07:35:45 PM PDT 24 |
Peak memory | 207984 kb |
Host | smart-65df520e-d3ab-44ae-afac-e7df67bfb076 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473647120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3473647120 |
Directory | /workspace/24.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/24.keymgr_sideload_otbn.3409327836 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 20455435 ps |
CPU time | 1.74 seconds |
Started | Jul 29 07:35:52 PM PDT 24 |
Finished | Jul 29 07:35:54 PM PDT 24 |
Peak memory | 206980 kb |
Host | smart-02f4f11e-cbdd-43f1-8695-6cdaea9aa482 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409327836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3409327836 |
Directory | /workspace/24.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/24.keymgr_sideload_protect.1412371310 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 105801254 ps |
CPU time | 3 seconds |
Started | Jul 29 07:35:40 PM PDT 24 |
Finished | Jul 29 07:35:44 PM PDT 24 |
Peak memory | 214316 kb |
Host | smart-3ed0e9d6-9226-493e-b4db-2e8f592cfdbc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1412371310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1412371310 |
Directory | /workspace/24.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/24.keymgr_smoke.3661024545 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 152224626 ps |
CPU time | 2.4 seconds |
Started | Jul 29 07:35:55 PM PDT 24 |
Finished | Jul 29 07:35:57 PM PDT 24 |
Peak memory | 208468 kb |
Host | smart-e15e816b-9503-48fa-8a7d-6b7e3010cfa3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3661024545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3661024545 |
Directory | /workspace/24.keymgr_smoke/latest |
Test location | /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.984401789 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 214769433 ps |
CPU time | 7.45 seconds |
Started | Jul 29 07:35:58 PM PDT 24 |
Finished | Jul 29 07:36:06 PM PDT 24 |
Peak memory | 222592 kb |
Host | smart-8826c939-c79b-464d-821b-dab9897837ef |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984401789 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.984401789 |
Directory | /workspace/24.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/24.keymgr_sw_invalid_input.1038647856 |
Short name | T873 |
Test name | |
Test status | |
Simulation time | 320714748 ps |
CPU time | 3.62 seconds |
Started | Jul 29 07:35:49 PM PDT 24 |
Finished | Jul 29 07:35:53 PM PDT 24 |
Peak memory | 207776 kb |
Host | smart-a2ac491e-6304-4e66-b8f8-f4b425abbf3c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1038647856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1038647856 |
Directory | /workspace/24.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3203363993 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 46827829 ps |
CPU time | 2.4 seconds |
Started | Jul 29 07:35:54 PM PDT 24 |
Finished | Jul 29 07:35:57 PM PDT 24 |
Peak memory | 210096 kb |
Host | smart-7473e29e-a7ab-4cf2-bb81-d5fde247b31f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3203363993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3203363993 |
Directory | /workspace/24.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/25.keymgr_alert_test.2265986918 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 32720010 ps |
CPU time | 0.71 seconds |
Started | Jul 29 07:35:46 PM PDT 24 |
Finished | Jul 29 07:35:47 PM PDT 24 |
Peak memory | 205980 kb |
Host | smart-d99dbf4d-fc2b-46f4-af88-b76135362ccb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265986918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2265986918 |
Directory | /workspace/25.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/25.keymgr_custom_cm.3550049392 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 457340561 ps |
CPU time | 4.68 seconds |
Started | Jul 29 07:35:46 PM PDT 24 |
Finished | Jul 29 07:35:51 PM PDT 24 |
Peak memory | 209704 kb |
Host | smart-ade892b4-c757-4474-b46c-54b12f2e7c26 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550049392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3550049392 |
Directory | /workspace/25.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/25.keymgr_direct_to_disabled.3895145952 |
Short name | T847 |
Test name | |
Test status | |
Simulation time | 627340886 ps |
CPU time | 7.7 seconds |
Started | Jul 29 07:35:37 PM PDT 24 |
Finished | Jul 29 07:35:45 PM PDT 24 |
Peak memory | 208336 kb |
Host | smart-64b45ade-64c4-479a-8ed2-3d9f8a238612 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3895145952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3895145952 |
Directory | /workspace/25.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/25.keymgr_hwsw_invalid_input.3178856226 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 373859730 ps |
CPU time | 4.44 seconds |
Started | Jul 29 07:35:42 PM PDT 24 |
Finished | Jul 29 07:35:46 PM PDT 24 |
Peak memory | 214356 kb |
Host | smart-0210d12b-af80-4ec5-9ed0-f415840346b6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3178856226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3178856226 |
Directory | /workspace/25.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/25.keymgr_kmac_rsp_err.3236666351 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 1775646498 ps |
CPU time | 6.76 seconds |
Started | Jul 29 07:35:42 PM PDT 24 |
Finished | Jul 29 07:35:49 PM PDT 24 |
Peak memory | 220520 kb |
Host | smart-46d886d2-6e59-4e72-aaff-7ccecedfe91d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3236666351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3236666351 |
Directory | /workspace/25.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/25.keymgr_lc_disable.2075467062 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 53955957 ps |
CPU time | 2.18 seconds |
Started | Jul 29 07:35:46 PM PDT 24 |
Finished | Jul 29 07:35:48 PM PDT 24 |
Peak memory | 214260 kb |
Host | smart-b845fb11-6936-4fe2-91e8-073a208e8699 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2075467062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2075467062 |
Directory | /workspace/25.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/25.keymgr_random.2049327928 |
Short name | T844 |
Test name | |
Test status | |
Simulation time | 2973817922 ps |
CPU time | 7.62 seconds |
Started | Jul 29 07:35:44 PM PDT 24 |
Finished | Jul 29 07:35:52 PM PDT 24 |
Peak memory | 214364 kb |
Host | smart-a9dbbfe9-a02a-4545-b611-2fc320c0dac8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2049327928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2049327928 |
Directory | /workspace/25.keymgr_random/latest |
Test location | /workspace/coverage/default/25.keymgr_sideload.1788427243 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 346058332 ps |
CPU time | 7.36 seconds |
Started | Jul 29 07:35:55 PM PDT 24 |
Finished | Jul 29 07:36:02 PM PDT 24 |
Peak memory | 208000 kb |
Host | smart-1ea72a4c-f20b-4c8a-b44f-99469ca2ef65 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1788427243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1788427243 |
Directory | /workspace/25.keymgr_sideload/latest |
Test location | /workspace/coverage/default/25.keymgr_sideload_aes.3052732169 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 583290055 ps |
CPU time | 4.29 seconds |
Started | Jul 29 07:35:55 PM PDT 24 |
Finished | Jul 29 07:35:59 PM PDT 24 |
Peak memory | 209100 kb |
Host | smart-e9ccd8dd-6a54-4a3e-b4cf-5fa050fc6d0c |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052732169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3052732169 |
Directory | /workspace/25.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/25.keymgr_sideload_kmac.4188755740 |
Short name | T717 |
Test name | |
Test status | |
Simulation time | 149294118 ps |
CPU time | 2.22 seconds |
Started | Jul 29 07:35:52 PM PDT 24 |
Finished | Jul 29 07:35:54 PM PDT 24 |
Peak memory | 207000 kb |
Host | smart-cbd2b8dc-cc02-4de4-ac78-707a650c4f59 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188755740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.4188755740 |
Directory | /workspace/25.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/25.keymgr_sideload_otbn.3606741728 |
Short name | T789 |
Test name | |
Test status | |
Simulation time | 340012363 ps |
CPU time | 5.62 seconds |
Started | Jul 29 07:35:50 PM PDT 24 |
Finished | Jul 29 07:35:56 PM PDT 24 |
Peak memory | 207984 kb |
Host | smart-574e7ab3-0c01-4efc-a70b-506790a828ce |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606741728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3606741728 |
Directory | /workspace/25.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/25.keymgr_sideload_protect.3665383722 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 53351416 ps |
CPU time | 2.53 seconds |
Started | Jul 29 07:35:50 PM PDT 24 |
Finished | Jul 29 07:35:52 PM PDT 24 |
Peak memory | 209416 kb |
Host | smart-055b5760-b39d-49a8-9acf-cda61b8627ef |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3665383722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3665383722 |
Directory | /workspace/25.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/25.keymgr_smoke.3605400460 |
Short name | T621 |
Test name | |
Test status | |
Simulation time | 285769512 ps |
CPU time | 2.18 seconds |
Started | Jul 29 07:35:38 PM PDT 24 |
Finished | Jul 29 07:35:41 PM PDT 24 |
Peak memory | 206792 kb |
Host | smart-16e320d9-0723-4437-a694-0d061e59d7b1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3605400460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3605400460 |
Directory | /workspace/25.keymgr_smoke/latest |
Test location | /workspace/coverage/default/25.keymgr_sw_invalid_input.2872900996 |
Short name | T912 |
Test name | |
Test status | |
Simulation time | 34612420 ps |
CPU time | 2.19 seconds |
Started | Jul 29 07:35:54 PM PDT 24 |
Finished | Jul 29 07:35:57 PM PDT 24 |
Peak memory | 209448 kb |
Host | smart-29391a45-d4c7-49c1-9790-44eb9cc69359 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2872900996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2872900996 |
Directory | /workspace/25.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/26.keymgr_alert_test.3198433720 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 40419841 ps |
CPU time | 0.84 seconds |
Started | Jul 29 07:35:44 PM PDT 24 |
Finished | Jul 29 07:35:45 PM PDT 24 |
Peak memory | 205940 kb |
Host | smart-2ef3f28f-3610-42ce-b89b-1c96360115ae |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198433720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3198433720 |
Directory | /workspace/26.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/26.keymgr_cfg_regwen.1127399131 |
Short name | T806 |
Test name | |
Test status | |
Simulation time | 6959861994 ps |
CPU time | 25.8 seconds |
Started | Jul 29 07:35:51 PM PDT 24 |
Finished | Jul 29 07:36:17 PM PDT 24 |
Peak memory | 214788 kb |
Host | smart-3cc38c48-4139-40e8-a6f4-e61264fa05b0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1127399131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.1127399131 |
Directory | /workspace/26.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/26.keymgr_custom_cm.2560219951 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 137842875 ps |
CPU time | 6.58 seconds |
Started | Jul 29 07:35:51 PM PDT 24 |
Finished | Jul 29 07:35:57 PM PDT 24 |
Peak memory | 214516 kb |
Host | smart-437ced75-e18d-484a-8423-8972bd7c6355 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2560219951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2560219951 |
Directory | /workspace/26.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/26.keymgr_direct_to_disabled.2194172162 |
Short name | T748 |
Test name | |
Test status | |
Simulation time | 120176761 ps |
CPU time | 3.11 seconds |
Started | Jul 29 07:35:54 PM PDT 24 |
Finished | Jul 29 07:35:57 PM PDT 24 |
Peak memory | 218332 kb |
Host | smart-e74b4733-f6ab-47db-bf75-bcb43e10e7e2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2194172162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2194172162 |
Directory | /workspace/26.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2793841402 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 1732700748 ps |
CPU time | 5.26 seconds |
Started | Jul 29 07:35:48 PM PDT 24 |
Finished | Jul 29 07:35:53 PM PDT 24 |
Peak memory | 214332 kb |
Host | smart-612f6665-d291-441f-a5d3-49677ac00d6f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2793841402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2793841402 |
Directory | /workspace/26.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/26.keymgr_lc_disable.1571912818 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 88038709 ps |
CPU time | 2.69 seconds |
Started | Jul 29 07:35:44 PM PDT 24 |
Finished | Jul 29 07:35:46 PM PDT 24 |
Peak memory | 206132 kb |
Host | smart-f872890c-1703-49bc-b414-32ff672f8f99 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1571912818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1571912818 |
Directory | /workspace/26.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/26.keymgr_random.2772523251 |
Short name | T878 |
Test name | |
Test status | |
Simulation time | 188488675 ps |
CPU time | 5.66 seconds |
Started | Jul 29 07:35:53 PM PDT 24 |
Finished | Jul 29 07:35:59 PM PDT 24 |
Peak memory | 219784 kb |
Host | smart-723ddffa-1634-439c-8efd-073db0aa1a3b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2772523251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2772523251 |
Directory | /workspace/26.keymgr_random/latest |
Test location | /workspace/coverage/default/26.keymgr_sideload.1239553055 |
Short name | T889 |
Test name | |
Test status | |
Simulation time | 123109134 ps |
CPU time | 2.36 seconds |
Started | Jul 29 07:35:50 PM PDT 24 |
Finished | Jul 29 07:35:53 PM PDT 24 |
Peak memory | 206052 kb |
Host | smart-1a0441b1-aa59-4d5b-8eb8-04ac901b7044 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1239553055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1239553055 |
Directory | /workspace/26.keymgr_sideload/latest |
Test location | /workspace/coverage/default/26.keymgr_sideload_aes.3178915350 |
Short name | T837 |
Test name | |
Test status | |
Simulation time | 301755743 ps |
CPU time | 5.04 seconds |
Started | Jul 29 07:35:39 PM PDT 24 |
Finished | Jul 29 07:35:45 PM PDT 24 |
Peak memory | 208008 kb |
Host | smart-dad7e4c9-8c93-4f2b-96dd-5886ef3b46d6 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178915350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3178915350 |
Directory | /workspace/26.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/26.keymgr_sideload_kmac.2957724566 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 128619627 ps |
CPU time | 2.42 seconds |
Started | Jul 29 07:35:39 PM PDT 24 |
Finished | Jul 29 07:35:42 PM PDT 24 |
Peak memory | 206964 kb |
Host | smart-6643914f-ace5-494a-b75b-59fa8e47fab8 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957724566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2957724566 |
Directory | /workspace/26.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/26.keymgr_sideload_otbn.1007356608 |
Short name | T640 |
Test name | |
Test status | |
Simulation time | 21717444 ps |
CPU time | 1.65 seconds |
Started | Jul 29 07:35:42 PM PDT 24 |
Finished | Jul 29 07:35:44 PM PDT 24 |
Peak memory | 206784 kb |
Host | smart-4fc76741-5caa-44b1-9b43-9069995619a5 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007356608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1007356608 |
Directory | /workspace/26.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/26.keymgr_sideload_protect.1925794017 |
Short name | T896 |
Test name | |
Test status | |
Simulation time | 291860016 ps |
CPU time | 2.5 seconds |
Started | Jul 29 07:35:41 PM PDT 24 |
Finished | Jul 29 07:35:44 PM PDT 24 |
Peak memory | 208416 kb |
Host | smart-3e4dda05-b187-4a07-8d0e-b8c46a4c2548 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1925794017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1925794017 |
Directory | /workspace/26.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/26.keymgr_smoke.3856997779 |
Short name | T819 |
Test name | |
Test status | |
Simulation time | 1588787023 ps |
CPU time | 16.89 seconds |
Started | Jul 29 07:35:52 PM PDT 24 |
Finished | Jul 29 07:36:09 PM PDT 24 |
Peak memory | 207924 kb |
Host | smart-09d37927-e0be-4f7a-ace8-ef233f0f63bf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3856997779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3856997779 |
Directory | /workspace/26.keymgr_smoke/latest |
Test location | /workspace/coverage/default/26.keymgr_stress_all.937994105 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 254199587 ps |
CPU time | 3.92 seconds |
Started | Jul 29 07:35:58 PM PDT 24 |
Finished | Jul 29 07:36:02 PM PDT 24 |
Peak memory | 214340 kb |
Host | smart-e5a46585-964c-439f-b929-518f956b1169 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937994105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.937994105 |
Directory | /workspace/26.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/26.keymgr_sw_invalid_input.826024894 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 122136191 ps |
CPU time | 5.43 seconds |
Started | Jul 29 07:35:52 PM PDT 24 |
Finished | Jul 29 07:35:57 PM PDT 24 |
Peak memory | 214320 kb |
Host | smart-beaffa3b-01bd-4f3f-9f87-e501f9d23822 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=826024894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.826024894 |
Directory | /workspace/26.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/26.keymgr_sync_async_fault_cross.92684468 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 100261522 ps |
CPU time | 2.98 seconds |
Started | Jul 29 07:35:40 PM PDT 24 |
Finished | Jul 29 07:35:48 PM PDT 24 |
Peak memory | 210040 kb |
Host | smart-6a6094c7-b5b8-433b-a0ea-4ae132aa4ea4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=92684468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.92684468 |
Directory | /workspace/26.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/27.keymgr_alert_test.631297603 |
Short name | T687 |
Test name | |
Test status | |
Simulation time | 59738893 ps |
CPU time | 0.97 seconds |
Started | Jul 29 07:35:52 PM PDT 24 |
Finished | Jul 29 07:35:53 PM PDT 24 |
Peak memory | 206132 kb |
Host | smart-19e1a518-ddff-4d72-bca7-6a9bf7bb7474 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631297603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.631297603 |
Directory | /workspace/27.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/27.keymgr_cfg_regwen.572483733 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 54098668 ps |
CPU time | 4.02 seconds |
Started | Jul 29 07:35:40 PM PDT 24 |
Finished | Jul 29 07:35:44 PM PDT 24 |
Peak memory | 215708 kb |
Host | smart-4595c1f1-1500-4142-b451-21aeb11f77f7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=572483733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.572483733 |
Directory | /workspace/27.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/27.keymgr_custom_cm.38748121 |
Short name | T768 |
Test name | |
Test status | |
Simulation time | 3819236621 ps |
CPU time | 48.02 seconds |
Started | Jul 29 07:36:06 PM PDT 24 |
Finished | Jul 29 07:36:54 PM PDT 24 |
Peak memory | 214660 kb |
Host | smart-45e58605-ccc1-4a8b-bcb0-e5f88489061f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=38748121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.38748121 |
Directory | /workspace/27.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/27.keymgr_direct_to_disabled.3532061840 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 72945620 ps |
CPU time | 2.37 seconds |
Started | Jul 29 07:35:39 PM PDT 24 |
Finished | Jul 29 07:35:41 PM PDT 24 |
Peak memory | 207876 kb |
Host | smart-9a583166-32db-4cf4-9b11-9c6818d17e4a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3532061840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3532061840 |
Directory | /workspace/27.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1726066888 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 690439487 ps |
CPU time | 5.7 seconds |
Started | Jul 29 07:35:56 PM PDT 24 |
Finished | Jul 29 07:36:02 PM PDT 24 |
Peak memory | 222448 kb |
Host | smart-083fe481-b99f-4cc4-8a56-9c98907bad6d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1726066888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1726066888 |
Directory | /workspace/27.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/27.keymgr_kmac_rsp_err.392725441 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 270045335 ps |
CPU time | 3.31 seconds |
Started | Jul 29 07:35:49 PM PDT 24 |
Finished | Jul 29 07:35:53 PM PDT 24 |
Peak memory | 222352 kb |
Host | smart-ff1728a4-e7fd-4cce-9b85-a699a1e1a71d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=392725441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.392725441 |
Directory | /workspace/27.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/27.keymgr_lc_disable.3803207202 |
Short name | T832 |
Test name | |
Test status | |
Simulation time | 261191471 ps |
CPU time | 3.39 seconds |
Started | Jul 29 07:35:45 PM PDT 24 |
Finished | Jul 29 07:35:48 PM PDT 24 |
Peak memory | 214296 kb |
Host | smart-a6f5ca04-1733-4795-8c4b-e67c3f2f4b0c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3803207202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3803207202 |
Directory | /workspace/27.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/27.keymgr_random.2004451115 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 119099978 ps |
CPU time | 2.51 seconds |
Started | Jul 29 07:36:03 PM PDT 24 |
Finished | Jul 29 07:36:06 PM PDT 24 |
Peak memory | 214288 kb |
Host | smart-36d7c60f-8e8b-434b-8a1e-96525f00ae6b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2004451115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2004451115 |
Directory | /workspace/27.keymgr_random/latest |
Test location | /workspace/coverage/default/27.keymgr_sideload.4255229095 |
Short name | T711 |
Test name | |
Test status | |
Simulation time | 310503062 ps |
CPU time | 2.66 seconds |
Started | Jul 29 07:35:41 PM PDT 24 |
Finished | Jul 29 07:35:44 PM PDT 24 |
Peak memory | 206904 kb |
Host | smart-76a8a149-e695-46ad-bb9f-6f3b762fdef2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4255229095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.4255229095 |
Directory | /workspace/27.keymgr_sideload/latest |
Test location | /workspace/coverage/default/27.keymgr_sideload_aes.1065352569 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 2284061369 ps |
CPU time | 43.57 seconds |
Started | Jul 29 07:35:44 PM PDT 24 |
Finished | Jul 29 07:36:27 PM PDT 24 |
Peak memory | 208560 kb |
Host | smart-93583cbe-ef76-45ec-97ee-2204df1fe68d |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065352569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1065352569 |
Directory | /workspace/27.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/27.keymgr_sideload_kmac.2690857880 |
Short name | T885 |
Test name | |
Test status | |
Simulation time | 4815468211 ps |
CPU time | 45.6 seconds |
Started | Jul 29 07:35:39 PM PDT 24 |
Finished | Jul 29 07:36:25 PM PDT 24 |
Peak memory | 209284 kb |
Host | smart-860f2c6c-446d-48eb-897b-04e604184dc5 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690857880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2690857880 |
Directory | /workspace/27.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/27.keymgr_sideload_otbn.2614455146 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 42169157 ps |
CPU time | 2.53 seconds |
Started | Jul 29 07:35:47 PM PDT 24 |
Finished | Jul 29 07:35:50 PM PDT 24 |
Peak memory | 207404 kb |
Host | smart-53706a6f-ca6d-4935-ad7e-8ecd3cd008a4 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614455146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2614455146 |
Directory | /workspace/27.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/27.keymgr_sideload_protect.3084262873 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 95857753 ps |
CPU time | 3.17 seconds |
Started | Jul 29 07:35:51 PM PDT 24 |
Finished | Jul 29 07:35:55 PM PDT 24 |
Peak memory | 215736 kb |
Host | smart-dd7450be-5d6c-4121-8661-0560b92d4574 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3084262873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3084262873 |
Directory | /workspace/27.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/27.keymgr_smoke.2934411432 |
Short name | T811 |
Test name | |
Test status | |
Simulation time | 53128464 ps |
CPU time | 2.47 seconds |
Started | Jul 29 07:35:40 PM PDT 24 |
Finished | Jul 29 07:35:43 PM PDT 24 |
Peak memory | 208724 kb |
Host | smart-815b8aac-8663-42e2-8d20-de9dd15eb3ea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2934411432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2934411432 |
Directory | /workspace/27.keymgr_smoke/latest |
Test location | /workspace/coverage/default/27.keymgr_stress_all.1698774729 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 276605256 ps |
CPU time | 7.28 seconds |
Started | Jul 29 07:35:52 PM PDT 24 |
Finished | Jul 29 07:36:00 PM PDT 24 |
Peak memory | 215808 kb |
Host | smart-d5ca0d2e-db2a-494e-8427-5337ceb737a8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698774729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1698774729 |
Directory | /workspace/27.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.2179782047 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 207693467 ps |
CPU time | 7.49 seconds |
Started | Jul 29 07:36:00 PM PDT 24 |
Finished | Jul 29 07:36:07 PM PDT 24 |
Peak memory | 222524 kb |
Host | smart-0d6f3f26-6fed-442d-a667-926ba68afa41 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179782047 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.2179782047 |
Directory | /workspace/27.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/27.keymgr_sw_invalid_input.1408947189 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 765170283 ps |
CPU time | 3.38 seconds |
Started | Jul 29 07:35:50 PM PDT 24 |
Finished | Jul 29 07:35:54 PM PDT 24 |
Peak memory | 207316 kb |
Host | smart-bd19b01f-d876-4e5c-b368-dd556890fdda |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1408947189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1408947189 |
Directory | /workspace/27.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1623732899 |
Short name | T776 |
Test name | |
Test status | |
Simulation time | 114859872 ps |
CPU time | 2.28 seconds |
Started | Jul 29 07:35:52 PM PDT 24 |
Finished | Jul 29 07:35:55 PM PDT 24 |
Peak memory | 210000 kb |
Host | smart-fd40b45c-94fe-4763-b7a6-68d3d337413f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1623732899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1623732899 |
Directory | /workspace/27.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/28.keymgr_alert_test.2204340687 |
Short name | T637 |
Test name | |
Test status | |
Simulation time | 38881969 ps |
CPU time | 0.83 seconds |
Started | Jul 29 07:35:50 PM PDT 24 |
Finished | Jul 29 07:35:51 PM PDT 24 |
Peak memory | 205932 kb |
Host | smart-730b1d81-d9b9-4a34-85a6-fcd25e4ab6a4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204340687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2204340687 |
Directory | /workspace/28.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/28.keymgr_custom_cm.2641619235 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 542271929 ps |
CPU time | 2.34 seconds |
Started | Jul 29 07:35:56 PM PDT 24 |
Finished | Jul 29 07:35:59 PM PDT 24 |
Peak memory | 218372 kb |
Host | smart-0c790a39-06a9-4417-8256-b1d5b86f4647 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2641619235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2641619235 |
Directory | /workspace/28.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/28.keymgr_direct_to_disabled.2521762234 |
Short name | T804 |
Test name | |
Test status | |
Simulation time | 82124444 ps |
CPU time | 1.75 seconds |
Started | Jul 29 07:36:05 PM PDT 24 |
Finished | Jul 29 07:36:07 PM PDT 24 |
Peak memory | 208772 kb |
Host | smart-6a8e873d-a394-4d0d-b5ef-0489ad1d9544 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2521762234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2521762234 |
Directory | /workspace/28.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1702240325 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 227088756 ps |
CPU time | 3.21 seconds |
Started | Jul 29 07:35:53 PM PDT 24 |
Finished | Jul 29 07:35:57 PM PDT 24 |
Peak memory | 214368 kb |
Host | smart-8d6b44c2-d90e-4e35-b64f-b18e36ab0820 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1702240325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1702240325 |
Directory | /workspace/28.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/28.keymgr_lc_disable.3633766257 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 129889774 ps |
CPU time | 4.37 seconds |
Started | Jul 29 07:35:53 PM PDT 24 |
Finished | Jul 29 07:35:58 PM PDT 24 |
Peak memory | 217772 kb |
Host | smart-dbe3085f-1968-4d39-adf0-32753ec4c2be |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3633766257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3633766257 |
Directory | /workspace/28.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/28.keymgr_random.1187327068 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 162622103 ps |
CPU time | 5.59 seconds |
Started | Jul 29 07:35:59 PM PDT 24 |
Finished | Jul 29 07:36:04 PM PDT 24 |
Peak memory | 210456 kb |
Host | smart-19dfd120-50d3-47b7-9bd9-4544491536de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1187327068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1187327068 |
Directory | /workspace/28.keymgr_random/latest |
Test location | /workspace/coverage/default/28.keymgr_sideload.3926425974 |
Short name | T697 |
Test name | |
Test status | |
Simulation time | 853000592 ps |
CPU time | 3.12 seconds |
Started | Jul 29 07:36:02 PM PDT 24 |
Finished | Jul 29 07:36:05 PM PDT 24 |
Peak memory | 208372 kb |
Host | smart-669dea8a-d4be-48f2-a80d-c002017f8e79 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3926425974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3926425974 |
Directory | /workspace/28.keymgr_sideload/latest |
Test location | /workspace/coverage/default/28.keymgr_sideload_aes.1907125877 |
Short name | T737 |
Test name | |
Test status | |
Simulation time | 80407477 ps |
CPU time | 2.52 seconds |
Started | Jul 29 07:35:57 PM PDT 24 |
Finished | Jul 29 07:36:00 PM PDT 24 |
Peak memory | 206928 kb |
Host | smart-690e4288-6469-44ce-83e8-aba39b8c33a6 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907125877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1907125877 |
Directory | /workspace/28.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/28.keymgr_sideload_kmac.2363487214 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 5775741998 ps |
CPU time | 39.79 seconds |
Started | Jul 29 07:35:58 PM PDT 24 |
Finished | Jul 29 07:36:38 PM PDT 24 |
Peak memory | 208800 kb |
Host | smart-4661ad29-9317-4725-b3ba-1e7a8955bd35 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363487214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2363487214 |
Directory | /workspace/28.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/28.keymgr_sideload_otbn.3824879845 |
Short name | T893 |
Test name | |
Test status | |
Simulation time | 302846473 ps |
CPU time | 3.47 seconds |
Started | Jul 29 07:35:56 PM PDT 24 |
Finished | Jul 29 07:36:00 PM PDT 24 |
Peak memory | 208804 kb |
Host | smart-447868c3-d011-40a2-a2d5-9c41babe7d79 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824879845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3824879845 |
Directory | /workspace/28.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/28.keymgr_sideload_protect.1054409070 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 347577370 ps |
CPU time | 3.84 seconds |
Started | Jul 29 07:35:53 PM PDT 24 |
Finished | Jul 29 07:35:57 PM PDT 24 |
Peak memory | 214340 kb |
Host | smart-1493f21a-f8be-4cfd-ad05-7faade76b2c9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1054409070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1054409070 |
Directory | /workspace/28.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/28.keymgr_smoke.1550923330 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 183774819 ps |
CPU time | 5.73 seconds |
Started | Jul 29 07:35:56 PM PDT 24 |
Finished | Jul 29 07:36:02 PM PDT 24 |
Peak memory | 206816 kb |
Host | smart-49247646-d163-4a59-9ed0-4cd9b4b977e9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1550923330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1550923330 |
Directory | /workspace/28.keymgr_smoke/latest |
Test location | /workspace/coverage/default/28.keymgr_sw_invalid_input.3239459918 |
Short name | T879 |
Test name | |
Test status | |
Simulation time | 144743545 ps |
CPU time | 6.67 seconds |
Started | Jul 29 07:35:51 PM PDT 24 |
Finished | Jul 29 07:35:58 PM PDT 24 |
Peak memory | 210008 kb |
Host | smart-c0f662b5-49f1-4606-8bdc-7118c20df87f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3239459918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3239459918 |
Directory | /workspace/28.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/29.keymgr_alert_test.364188155 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 40794513 ps |
CPU time | 0.75 seconds |
Started | Jul 29 07:35:52 PM PDT 24 |
Finished | Jul 29 07:35:53 PM PDT 24 |
Peak memory | 205988 kb |
Host | smart-125dd337-7fd8-4e4d-87ed-3024f8ab4b34 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364188155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.364188155 |
Directory | /workspace/29.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/29.keymgr_cfg_regwen.4013273097 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 1025058393 ps |
CPU time | 13.85 seconds |
Started | Jul 29 07:35:55 PM PDT 24 |
Finished | Jul 29 07:36:09 PM PDT 24 |
Peak memory | 214640 kb |
Host | smart-18dcbf1b-6682-41e9-8077-95caab7040c7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4013273097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.4013273097 |
Directory | /workspace/29.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/29.keymgr_custom_cm.1266156490 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 1205747712 ps |
CPU time | 5.5 seconds |
Started | Jul 29 07:35:52 PM PDT 24 |
Finished | Jul 29 07:35:58 PM PDT 24 |
Peak memory | 222596 kb |
Host | smart-50e7c32f-6230-49bb-a2cb-61e2074e0d89 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1266156490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1266156490 |
Directory | /workspace/29.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/29.keymgr_direct_to_disabled.701172143 |
Short name | T839 |
Test name | |
Test status | |
Simulation time | 138554759 ps |
CPU time | 1.64 seconds |
Started | Jul 29 07:35:59 PM PDT 24 |
Finished | Jul 29 07:36:01 PM PDT 24 |
Peak memory | 214380 kb |
Host | smart-fc74bf6a-1714-49bf-96f4-3fdd32a5ffcc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=701172143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.701172143 |
Directory | /workspace/29.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/29.keymgr_hwsw_invalid_input.955692236 |
Short name | T904 |
Test name | |
Test status | |
Simulation time | 2649882415 ps |
CPU time | 25.64 seconds |
Started | Jul 29 07:35:51 PM PDT 24 |
Finished | Jul 29 07:36:17 PM PDT 24 |
Peak memory | 214332 kb |
Host | smart-4207dc41-14c9-4a49-8658-03de2e18800b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=955692236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.955692236 |
Directory | /workspace/29.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/29.keymgr_kmac_rsp_err.3109657002 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 140689926 ps |
CPU time | 2.81 seconds |
Started | Jul 29 07:35:48 PM PDT 24 |
Finished | Jul 29 07:35:51 PM PDT 24 |
Peak memory | 214260 kb |
Host | smart-d78163a8-df3d-4a8d-9893-bb5dd781b126 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3109657002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3109657002 |
Directory | /workspace/29.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/29.keymgr_lc_disable.325649651 |
Short name | T763 |
Test name | |
Test status | |
Simulation time | 224737260 ps |
CPU time | 3.69 seconds |
Started | Jul 29 07:35:56 PM PDT 24 |
Finished | Jul 29 07:36:00 PM PDT 24 |
Peak memory | 218572 kb |
Host | smart-d5421d2c-3fd2-4afa-96bf-29903ca87b25 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=325649651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.325649651 |
Directory | /workspace/29.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/29.keymgr_random.3803937731 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 81519183 ps |
CPU time | 3.9 seconds |
Started | Jul 29 07:35:56 PM PDT 24 |
Finished | Jul 29 07:36:00 PM PDT 24 |
Peak memory | 208392 kb |
Host | smart-c259862d-b24d-49ff-8485-f4ca4ff0d583 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3803937731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3803937731 |
Directory | /workspace/29.keymgr_random/latest |
Test location | /workspace/coverage/default/29.keymgr_sideload.3468670262 |
Short name | T782 |
Test name | |
Test status | |
Simulation time | 40215739 ps |
CPU time | 2.5 seconds |
Started | Jul 29 07:35:50 PM PDT 24 |
Finished | Jul 29 07:35:53 PM PDT 24 |
Peak memory | 208460 kb |
Host | smart-dc850611-57b6-4ca7-8cc3-473409733823 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3468670262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3468670262 |
Directory | /workspace/29.keymgr_sideload/latest |
Test location | /workspace/coverage/default/29.keymgr_sideload_aes.2765903272 |
Short name | T770 |
Test name | |
Test status | |
Simulation time | 6908152837 ps |
CPU time | 55.55 seconds |
Started | Jul 29 07:35:53 PM PDT 24 |
Finished | Jul 29 07:36:49 PM PDT 24 |
Peak memory | 208204 kb |
Host | smart-bb212225-308e-403c-938c-a35a7e981d72 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765903272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2765903272 |
Directory | /workspace/29.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/29.keymgr_sideload_kmac.3772452093 |
Short name | T908 |
Test name | |
Test status | |
Simulation time | 341117393 ps |
CPU time | 3.6 seconds |
Started | Jul 29 07:35:51 PM PDT 24 |
Finished | Jul 29 07:35:55 PM PDT 24 |
Peak memory | 208604 kb |
Host | smart-4a404303-a92d-40b6-8f99-29f44e79a0f6 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772452093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3772452093 |
Directory | /workspace/29.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/29.keymgr_sideload_protect.1577734793 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 1433431064 ps |
CPU time | 11.83 seconds |
Started | Jul 29 07:35:49 PM PDT 24 |
Finished | Jul 29 07:36:01 PM PDT 24 |
Peak memory | 209772 kb |
Host | smart-a0a142f0-6b62-475c-9f00-b155b719f233 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1577734793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1577734793 |
Directory | /workspace/29.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/29.keymgr_smoke.3127374622 |
Short name | T785 |
Test name | |
Test status | |
Simulation time | 132954164 ps |
CPU time | 2.75 seconds |
Started | Jul 29 07:35:54 PM PDT 24 |
Finished | Jul 29 07:35:57 PM PDT 24 |
Peak memory | 208108 kb |
Host | smart-685d5530-3e8f-41f6-b1eb-9069889127f2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3127374622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3127374622 |
Directory | /workspace/29.keymgr_smoke/latest |
Test location | /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.2528073196 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 183181478 ps |
CPU time | 3.79 seconds |
Started | Jul 29 07:35:52 PM PDT 24 |
Finished | Jul 29 07:35:56 PM PDT 24 |
Peak memory | 218480 kb |
Host | smart-bc3ea97b-7530-4ae2-aeca-bcb1179f446e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528073196 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.2528073196 |
Directory | /workspace/29.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/29.keymgr_sw_invalid_input.479023824 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 184191410 ps |
CPU time | 4.18 seconds |
Started | Jul 29 07:35:48 PM PDT 24 |
Finished | Jul 29 07:35:53 PM PDT 24 |
Peak memory | 208432 kb |
Host | smart-254322b5-82f4-4c63-9e2f-e2c56f876146 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=479023824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.479023824 |
Directory | /workspace/29.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/29.keymgr_sync_async_fault_cross.17845885 |
Short name | T813 |
Test name | |
Test status | |
Simulation time | 2010197176 ps |
CPU time | 6.77 seconds |
Started | Jul 29 07:35:57 PM PDT 24 |
Finished | Jul 29 07:36:03 PM PDT 24 |
Peak memory | 210980 kb |
Host | smart-9475014c-70ba-4877-8248-87b764ae7a43 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=17845885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.17845885 |
Directory | /workspace/29.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/3.keymgr_alert_test.486498014 |
Short name | T713 |
Test name | |
Test status | |
Simulation time | 16293070 ps |
CPU time | 0.74 seconds |
Started | Jul 29 07:34:44 PM PDT 24 |
Finished | Jul 29 07:34:45 PM PDT 24 |
Peak memory | 206028 kb |
Host | smart-006bde2a-aea1-4123-a8a3-f5d008944240 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486498014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.486498014 |
Directory | /workspace/3.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/3.keymgr_direct_to_disabled.1652430013 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 168706040 ps |
CPU time | 2.74 seconds |
Started | Jul 29 07:34:42 PM PDT 24 |
Finished | Jul 29 07:34:44 PM PDT 24 |
Peak memory | 209980 kb |
Host | smart-99933689-fd04-4ac8-b25c-8489210d08d5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1652430013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1652430013 |
Directory | /workspace/3.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3728498213 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 78340038 ps |
CPU time | 2.71 seconds |
Started | Jul 29 07:34:43 PM PDT 24 |
Finished | Jul 29 07:34:46 PM PDT 24 |
Peak memory | 208632 kb |
Host | smart-eb654c54-6e4c-4c83-995f-f1c8666df805 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3728498213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3728498213 |
Directory | /workspace/3.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/3.keymgr_kmac_rsp_err.1373937430 |
Short name | T772 |
Test name | |
Test status | |
Simulation time | 55228841 ps |
CPU time | 2.88 seconds |
Started | Jul 29 07:34:46 PM PDT 24 |
Finished | Jul 29 07:34:49 PM PDT 24 |
Peak memory | 222408 kb |
Host | smart-2bac2d15-d187-4ce2-b437-1b582d4a0c9e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1373937430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1373937430 |
Directory | /workspace/3.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/3.keymgr_random.2386125521 |
Short name | T650 |
Test name | |
Test status | |
Simulation time | 205390946 ps |
CPU time | 3.63 seconds |
Started | Jul 29 07:34:40 PM PDT 24 |
Finished | Jul 29 07:34:44 PM PDT 24 |
Peak memory | 210752 kb |
Host | smart-75824db9-9f63-428a-abbc-8cf5a5ab4de2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2386125521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2386125521 |
Directory | /workspace/3.keymgr_random/latest |
Test location | /workspace/coverage/default/3.keymgr_sec_cm.2482969598 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 1764276117 ps |
CPU time | 12.49 seconds |
Started | Jul 29 07:34:45 PM PDT 24 |
Finished | Jul 29 07:34:58 PM PDT 24 |
Peak memory | 229436 kb |
Host | smart-7bbf8e9f-cc65-417a-8e14-efda5146dec5 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482969598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2482969598 |
Directory | /workspace/3.keymgr_sec_cm/latest |
Test location | /workspace/coverage/default/3.keymgr_sideload.2443701976 |
Short name | T672 |
Test name | |
Test status | |
Simulation time | 99832809 ps |
CPU time | 2.25 seconds |
Started | Jul 29 07:34:37 PM PDT 24 |
Finished | Jul 29 07:34:40 PM PDT 24 |
Peak memory | 206920 kb |
Host | smart-714e7192-eeb4-4bcd-85f1-47c58d4fabff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2443701976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.2443701976 |
Directory | /workspace/3.keymgr_sideload/latest |
Test location | /workspace/coverage/default/3.keymgr_sideload_aes.2413435387 |
Short name | T771 |
Test name | |
Test status | |
Simulation time | 1366631404 ps |
CPU time | 7 seconds |
Started | Jul 29 07:34:39 PM PDT 24 |
Finished | Jul 29 07:34:47 PM PDT 24 |
Peak memory | 208668 kb |
Host | smart-2cf00109-09c0-4af0-8e5a-8a0b402522d5 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413435387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2413435387 |
Directory | /workspace/3.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/3.keymgr_sideload_kmac.2570218787 |
Short name | T824 |
Test name | |
Test status | |
Simulation time | 974102380 ps |
CPU time | 21.87 seconds |
Started | Jul 29 07:34:37 PM PDT 24 |
Finished | Jul 29 07:34:59 PM PDT 24 |
Peak memory | 209108 kb |
Host | smart-28ceff20-aca6-4ef1-bc0b-6207adbd635c |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570218787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2570218787 |
Directory | /workspace/3.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/3.keymgr_sideload_otbn.2808662156 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 116764680 ps |
CPU time | 2.3 seconds |
Started | Jul 29 07:34:45 PM PDT 24 |
Finished | Jul 29 07:34:48 PM PDT 24 |
Peak memory | 206808 kb |
Host | smart-90cdaf33-9648-492d-9271-775b0ae21fd8 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808662156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2808662156 |
Directory | /workspace/3.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/3.keymgr_sideload_protect.2635076798 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 57408438 ps |
CPU time | 2.57 seconds |
Started | Jul 29 07:34:46 PM PDT 24 |
Finished | Jul 29 07:34:48 PM PDT 24 |
Peak memory | 214348 kb |
Host | smart-3bbd9e80-fc6b-4e53-8fbe-b4f63b44a5cc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2635076798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2635076798 |
Directory | /workspace/3.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/3.keymgr_smoke.3327310512 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 185148095 ps |
CPU time | 2.36 seconds |
Started | Jul 29 07:34:36 PM PDT 24 |
Finished | Jul 29 07:34:39 PM PDT 24 |
Peak memory | 206948 kb |
Host | smart-26d04c74-470c-4c22-8b2f-0ee5db717069 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3327310512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3327310512 |
Directory | /workspace/3.keymgr_smoke/latest |
Test location | /workspace/coverage/default/3.keymgr_stress_all.107334896 |
Short name | T857 |
Test name | |
Test status | |
Simulation time | 790292041 ps |
CPU time | 20.81 seconds |
Started | Jul 29 07:34:49 PM PDT 24 |
Finished | Jul 29 07:35:10 PM PDT 24 |
Peak memory | 215384 kb |
Host | smart-7bab5500-76d1-4b0e-9be4-8ddf6505e3ae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107334896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.107334896 |
Directory | /workspace/3.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/3.keymgr_sw_invalid_input.3494093642 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 54477613 ps |
CPU time | 3.14 seconds |
Started | Jul 29 07:34:44 PM PDT 24 |
Finished | Jul 29 07:34:47 PM PDT 24 |
Peak memory | 218440 kb |
Host | smart-139d0d1a-81d6-4cbb-a6dd-5fd55b76f25d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3494093642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3494093642 |
Directory | /workspace/3.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1346691688 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 133548598 ps |
CPU time | 1.99 seconds |
Started | Jul 29 07:34:45 PM PDT 24 |
Finished | Jul 29 07:34:47 PM PDT 24 |
Peak memory | 209916 kb |
Host | smart-cbdbd422-ef7d-4b40-ad84-0e7bc6fec349 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1346691688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1346691688 |
Directory | /workspace/3.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/30.keymgr_alert_test.2588758293 |
Short name | T868 |
Test name | |
Test status | |
Simulation time | 50284494 ps |
CPU time | 0.85 seconds |
Started | Jul 29 07:35:57 PM PDT 24 |
Finished | Jul 29 07:35:58 PM PDT 24 |
Peak memory | 205992 kb |
Host | smart-a04ed8bb-1ce3-4ea3-9580-2af9c84b708a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588758293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2588758293 |
Directory | /workspace/30.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/30.keymgr_cfg_regwen.1141882198 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 115312596 ps |
CPU time | 2.33 seconds |
Started | Jul 29 07:35:55 PM PDT 24 |
Finished | Jul 29 07:35:58 PM PDT 24 |
Peak memory | 215272 kb |
Host | smart-fb8b03c3-16e3-4cdb-a34c-4477f1f1677b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1141882198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1141882198 |
Directory | /workspace/30.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/30.keymgr_custom_cm.1796166810 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 62122573 ps |
CPU time | 1.83 seconds |
Started | Jul 29 07:35:56 PM PDT 24 |
Finished | Jul 29 07:35:58 PM PDT 24 |
Peak memory | 208732 kb |
Host | smart-b6836e2a-029c-4ce0-9d35-ca7513d8fd1d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1796166810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1796166810 |
Directory | /workspace/30.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/30.keymgr_direct_to_disabled.399228187 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 363494673 ps |
CPU time | 2.7 seconds |
Started | Jul 29 07:35:52 PM PDT 24 |
Finished | Jul 29 07:35:55 PM PDT 24 |
Peak memory | 208788 kb |
Host | smart-b868ff9c-aaf9-4eea-866d-c3e1ef930864 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=399228187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.399228187 |
Directory | /workspace/30.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/30.keymgr_hwsw_invalid_input.838679405 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 196059128 ps |
CPU time | 4.42 seconds |
Started | Jul 29 07:35:53 PM PDT 24 |
Finished | Jul 29 07:35:58 PM PDT 24 |
Peak memory | 220924 kb |
Host | smart-cb2f55b8-69f7-469b-8c06-e8285e05039a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=838679405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.838679405 |
Directory | /workspace/30.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/30.keymgr_kmac_rsp_err.343593389 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 607586910 ps |
CPU time | 6.11 seconds |
Started | Jul 29 07:35:55 PM PDT 24 |
Finished | Jul 29 07:36:01 PM PDT 24 |
Peak memory | 221484 kb |
Host | smart-3ed9ae65-db94-4c03-a10f-ae71b4b38dfb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=343593389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.343593389 |
Directory | /workspace/30.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/30.keymgr_lc_disable.2824362834 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 542499755 ps |
CPU time | 3.46 seconds |
Started | Jul 29 07:35:49 PM PDT 24 |
Finished | Jul 29 07:35:52 PM PDT 24 |
Peak memory | 207644 kb |
Host | smart-f202ecee-b00e-4d7a-aee4-5dcb10a92268 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2824362834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2824362834 |
Directory | /workspace/30.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/30.keymgr_random.3442283553 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 773542208 ps |
CPU time | 5.55 seconds |
Started | Jul 29 07:36:05 PM PDT 24 |
Finished | Jul 29 07:36:11 PM PDT 24 |
Peak memory | 208288 kb |
Host | smart-b5365c3b-7507-47f0-9849-5b39833991fd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3442283553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3442283553 |
Directory | /workspace/30.keymgr_random/latest |
Test location | /workspace/coverage/default/30.keymgr_sideload.2557211988 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 500763724 ps |
CPU time | 4.12 seconds |
Started | Jul 29 07:35:50 PM PDT 24 |
Finished | Jul 29 07:35:54 PM PDT 24 |
Peak memory | 208544 kb |
Host | smart-c9481602-9597-430b-8b7c-b41cdf918ae2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2557211988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2557211988 |
Directory | /workspace/30.keymgr_sideload/latest |
Test location | /workspace/coverage/default/30.keymgr_sideload_aes.741912361 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 1611022357 ps |
CPU time | 20.52 seconds |
Started | Jul 29 07:35:55 PM PDT 24 |
Finished | Jul 29 07:36:16 PM PDT 24 |
Peak memory | 208380 kb |
Host | smart-deb74dda-f85a-48cf-b2e0-264b21d6b41f |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741912361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.741912361 |
Directory | /workspace/30.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/30.keymgr_sideload_kmac.3467341455 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 153060231 ps |
CPU time | 3.51 seconds |
Started | Jul 29 07:36:02 PM PDT 24 |
Finished | Jul 29 07:36:05 PM PDT 24 |
Peak memory | 208648 kb |
Host | smart-4db24082-6ad4-442a-96d6-b7b737e21b44 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467341455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3467341455 |
Directory | /workspace/30.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/30.keymgr_sideload_otbn.4220998527 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 318043234 ps |
CPU time | 6.75 seconds |
Started | Jul 29 07:35:51 PM PDT 24 |
Finished | Jul 29 07:35:58 PM PDT 24 |
Peak memory | 208576 kb |
Host | smart-1c7e3f91-d04f-4666-8a91-6e69ec05dc97 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220998527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.4220998527 |
Directory | /workspace/30.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/30.keymgr_sideload_protect.3109112166 |
Short name | T690 |
Test name | |
Test status | |
Simulation time | 105968400 ps |
CPU time | 2.98 seconds |
Started | Jul 29 07:35:57 PM PDT 24 |
Finished | Jul 29 07:36:01 PM PDT 24 |
Peak memory | 209216 kb |
Host | smart-bc484b9f-8f92-47da-bcfb-97324a4f8d38 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3109112166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3109112166 |
Directory | /workspace/30.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/30.keymgr_smoke.690287794 |
Short name | T888 |
Test name | |
Test status | |
Simulation time | 78243212 ps |
CPU time | 2.53 seconds |
Started | Jul 29 07:35:47 PM PDT 24 |
Finished | Jul 29 07:35:50 PM PDT 24 |
Peak memory | 206688 kb |
Host | smart-1604fbb3-c0fc-486f-8660-7c8fc51d64c4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=690287794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.690287794 |
Directory | /workspace/30.keymgr_smoke/latest |
Test location | /workspace/coverage/default/30.keymgr_stress_all.2586582281 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 6216584728 ps |
CPU time | 41.9 seconds |
Started | Jul 29 07:35:51 PM PDT 24 |
Finished | Jul 29 07:36:33 PM PDT 24 |
Peak memory | 216520 kb |
Host | smart-917526c2-5f93-4053-979e-c502c3b1cfb8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586582281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2586582281 |
Directory | /workspace/30.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2380455773 |
Short name | T829 |
Test name | |
Test status | |
Simulation time | 1630354702 ps |
CPU time | 18.08 seconds |
Started | Jul 29 07:36:02 PM PDT 24 |
Finished | Jul 29 07:36:21 PM PDT 24 |
Peak memory | 222568 kb |
Host | smart-786d28cf-45c8-4211-b980-76a401887f9c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380455773 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2380455773 |
Directory | /workspace/30.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/30.keymgr_sw_invalid_input.4242763567 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 55507535 ps |
CPU time | 2.85 seconds |
Started | Jul 29 07:35:53 PM PDT 24 |
Finished | Jul 29 07:35:57 PM PDT 24 |
Peak memory | 207208 kb |
Host | smart-f6cb4d5a-1711-4e21-9843-8f0c4b1efc7a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4242763567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.4242763567 |
Directory | /workspace/30.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1245140429 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 1392721417 ps |
CPU time | 11.8 seconds |
Started | Jul 29 07:35:54 PM PDT 24 |
Finished | Jul 29 07:36:06 PM PDT 24 |
Peak memory | 211020 kb |
Host | smart-fa54cf49-34af-4a7e-8f38-697043d4a024 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1245140429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1245140429 |
Directory | /workspace/30.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/31.keymgr_alert_test.284844627 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 23372503 ps |
CPU time | 0.71 seconds |
Started | Jul 29 07:35:54 PM PDT 24 |
Finished | Jul 29 07:35:55 PM PDT 24 |
Peak memory | 205900 kb |
Host | smart-588b73a2-4924-4b75-94c4-f3161add8c28 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284844627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.284844627 |
Directory | /workspace/31.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/31.keymgr_custom_cm.2348117362 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 111020875 ps |
CPU time | 3.73 seconds |
Started | Jul 29 07:36:00 PM PDT 24 |
Finished | Jul 29 07:36:04 PM PDT 24 |
Peak memory | 222616 kb |
Host | smart-2c220af0-d11b-4fcd-83a1-a6625245817b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2348117362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2348117362 |
Directory | /workspace/31.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/31.keymgr_direct_to_disabled.2517644598 |
Short name | T709 |
Test name | |
Test status | |
Simulation time | 95725814 ps |
CPU time | 1.68 seconds |
Started | Jul 29 07:36:10 PM PDT 24 |
Finished | Jul 29 07:36:12 PM PDT 24 |
Peak memory | 208080 kb |
Host | smart-57be7dd2-daa2-4ec5-bb50-d7db304b2ee7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2517644598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2517644598 |
Directory | /workspace/31.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2426623862 |
Short name | T833 |
Test name | |
Test status | |
Simulation time | 668455916 ps |
CPU time | 10.3 seconds |
Started | Jul 29 07:36:03 PM PDT 24 |
Finished | Jul 29 07:36:13 PM PDT 24 |
Peak memory | 222504 kb |
Host | smart-7c8de8f8-11ed-4517-8090-261c2693cff4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2426623862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2426623862 |
Directory | /workspace/31.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/31.keymgr_lc_disable.3352057455 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 110369469 ps |
CPU time | 4.57 seconds |
Started | Jul 29 07:36:00 PM PDT 24 |
Finished | Jul 29 07:36:05 PM PDT 24 |
Peak memory | 222568 kb |
Host | smart-b78b20d6-8c0a-4139-b970-63bccd45e118 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3352057455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3352057455 |
Directory | /workspace/31.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/31.keymgr_random.2889783903 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 96634671 ps |
CPU time | 4.21 seconds |
Started | Jul 29 07:35:54 PM PDT 24 |
Finished | Jul 29 07:35:59 PM PDT 24 |
Peak memory | 209400 kb |
Host | smart-cdf3ff33-4a36-473d-810b-727e3d928d9e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2889783903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2889783903 |
Directory | /workspace/31.keymgr_random/latest |
Test location | /workspace/coverage/default/31.keymgr_sideload.320469774 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 322506292 ps |
CPU time | 4.19 seconds |
Started | Jul 29 07:35:54 PM PDT 24 |
Finished | Jul 29 07:35:59 PM PDT 24 |
Peak memory | 208744 kb |
Host | smart-b70aea76-3e80-4d3a-9c3d-9816728663de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=320469774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.320469774 |
Directory | /workspace/31.keymgr_sideload/latest |
Test location | /workspace/coverage/default/31.keymgr_sideload_aes.2835146285 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 67350051 ps |
CPU time | 2.32 seconds |
Started | Jul 29 07:36:05 PM PDT 24 |
Finished | Jul 29 07:36:07 PM PDT 24 |
Peak memory | 207044 kb |
Host | smart-dbc00d56-2cb4-4c18-8228-8a13457a98f0 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835146285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2835146285 |
Directory | /workspace/31.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/31.keymgr_sideload_kmac.4002018270 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 108086943 ps |
CPU time | 2.88 seconds |
Started | Jul 29 07:35:55 PM PDT 24 |
Finished | Jul 29 07:35:58 PM PDT 24 |
Peak memory | 208196 kb |
Host | smart-958ecff3-cdfa-438b-8138-48d7f1fe2c86 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002018270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.4002018270 |
Directory | /workspace/31.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/31.keymgr_sideload_otbn.739771171 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 39259273 ps |
CPU time | 2.58 seconds |
Started | Jul 29 07:35:55 PM PDT 24 |
Finished | Jul 29 07:35:58 PM PDT 24 |
Peak memory | 208616 kb |
Host | smart-ec3c5557-4e00-4860-b82e-70af29ef1db9 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739771171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.739771171 |
Directory | /workspace/31.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/31.keymgr_sideload_protect.951535349 |
Short name | T744 |
Test name | |
Test status | |
Simulation time | 659828440 ps |
CPU time | 4.49 seconds |
Started | Jul 29 07:35:51 PM PDT 24 |
Finished | Jul 29 07:35:56 PM PDT 24 |
Peak memory | 214300 kb |
Host | smart-9d9458dd-fb5c-4e62-bdab-918b7caa43f3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=951535349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.951535349 |
Directory | /workspace/31.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/31.keymgr_smoke.861591498 |
Short name | T754 |
Test name | |
Test status | |
Simulation time | 4538758942 ps |
CPU time | 24.49 seconds |
Started | Jul 29 07:36:02 PM PDT 24 |
Finished | Jul 29 07:36:26 PM PDT 24 |
Peak memory | 209032 kb |
Host | smart-b2895901-f1bc-4c4e-8e20-24b45103e5ab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=861591498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.861591498 |
Directory | /workspace/31.keymgr_smoke/latest |
Test location | /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.1629262748 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 387607122 ps |
CPU time | 16.9 seconds |
Started | Jul 29 07:35:58 PM PDT 24 |
Finished | Jul 29 07:36:15 PM PDT 24 |
Peak memory | 222456 kb |
Host | smart-04e3fda9-360c-4f4b-921b-17f7661e5dd2 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629262748 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.1629262748 |
Directory | /workspace/31.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/31.keymgr_sw_invalid_input.3708609814 |
Short name | T765 |
Test name | |
Test status | |
Simulation time | 335976966 ps |
CPU time | 5.41 seconds |
Started | Jul 29 07:35:55 PM PDT 24 |
Finished | Jul 29 07:36:01 PM PDT 24 |
Peak memory | 209712 kb |
Host | smart-8dca143c-1780-495f-8ca0-39af57612b33 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3708609814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3708609814 |
Directory | /workspace/31.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/31.keymgr_sync_async_fault_cross.353475827 |
Short name | T767 |
Test name | |
Test status | |
Simulation time | 74747923 ps |
CPU time | 1.61 seconds |
Started | Jul 29 07:35:56 PM PDT 24 |
Finished | Jul 29 07:35:58 PM PDT 24 |
Peak memory | 210080 kb |
Host | smart-0ff857fc-9ae5-4dbb-b34c-8a81e52752d5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=353475827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.353475827 |
Directory | /workspace/31.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/32.keymgr_alert_test.170526397 |
Short name | T861 |
Test name | |
Test status | |
Simulation time | 27710739 ps |
CPU time | 0.72 seconds |
Started | Jul 29 07:35:59 PM PDT 24 |
Finished | Jul 29 07:36:00 PM PDT 24 |
Peak memory | 205968 kb |
Host | smart-92a19f15-9780-41f9-85e7-24af74f0b0da |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170526397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.170526397 |
Directory | /workspace/32.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/32.keymgr_direct_to_disabled.3462536628 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 61194787 ps |
CPU time | 2.83 seconds |
Started | Jul 29 07:36:02 PM PDT 24 |
Finished | Jul 29 07:36:05 PM PDT 24 |
Peak memory | 214156 kb |
Host | smart-86f0bb00-e90a-4910-ac54-aa39b1f6e55c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3462536628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3462536628 |
Directory | /workspace/32.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/32.keymgr_kmac_rsp_err.3276087197 |
Short name | T751 |
Test name | |
Test status | |
Simulation time | 328233039 ps |
CPU time | 4.18 seconds |
Started | Jul 29 07:36:03 PM PDT 24 |
Finished | Jul 29 07:36:07 PM PDT 24 |
Peak memory | 215200 kb |
Host | smart-78effb77-8c81-40fa-b063-b241a5cc018f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3276087197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3276087197 |
Directory | /workspace/32.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/32.keymgr_lc_disable.3468673279 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 203307630 ps |
CPU time | 2.59 seconds |
Started | Jul 29 07:35:51 PM PDT 24 |
Finished | Jul 29 07:35:54 PM PDT 24 |
Peak memory | 208376 kb |
Host | smart-b17fd784-dc8b-42f7-ba12-0914897e4ee8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3468673279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3468673279 |
Directory | /workspace/32.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/32.keymgr_random.3333473683 |
Short name | T903 |
Test name | |
Test status | |
Simulation time | 162758678 ps |
CPU time | 5.92 seconds |
Started | Jul 29 07:36:06 PM PDT 24 |
Finished | Jul 29 07:36:12 PM PDT 24 |
Peak memory | 207536 kb |
Host | smart-50e19703-464b-4e7f-bec8-3ce45e396277 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3333473683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3333473683 |
Directory | /workspace/32.keymgr_random/latest |
Test location | /workspace/coverage/default/32.keymgr_sideload.2692957574 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 181121280 ps |
CPU time | 6.26 seconds |
Started | Jul 29 07:35:48 PM PDT 24 |
Finished | Jul 29 07:35:54 PM PDT 24 |
Peak memory | 208188 kb |
Host | smart-75b7a8d4-499d-4ddf-9d92-2a81bd3987c0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2692957574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2692957574 |
Directory | /workspace/32.keymgr_sideload/latest |
Test location | /workspace/coverage/default/32.keymgr_sideload_aes.3861521359 |
Short name | T642 |
Test name | |
Test status | |
Simulation time | 237781874 ps |
CPU time | 6.39 seconds |
Started | Jul 29 07:35:53 PM PDT 24 |
Finished | Jul 29 07:35:59 PM PDT 24 |
Peak memory | 208076 kb |
Host | smart-2db2e7a9-8c85-4653-941f-90e78621ee48 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861521359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3861521359 |
Directory | /workspace/32.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/32.keymgr_sideload_kmac.3748303372 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 103042609 ps |
CPU time | 2.29 seconds |
Started | Jul 29 07:35:57 PM PDT 24 |
Finished | Jul 29 07:35:59 PM PDT 24 |
Peak memory | 209000 kb |
Host | smart-10883302-2065-481f-aeb5-e91910344204 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748303372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3748303372 |
Directory | /workspace/32.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/32.keymgr_sideload_otbn.2294547886 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 4100309907 ps |
CPU time | 22.57 seconds |
Started | Jul 29 07:35:53 PM PDT 24 |
Finished | Jul 29 07:36:16 PM PDT 24 |
Peak memory | 208712 kb |
Host | smart-ad6945d9-2de8-4dc0-b3ba-65933a18ff7a |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294547886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2294547886 |
Directory | /workspace/32.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/32.keymgr_sideload_protect.4235241477 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 135470734 ps |
CPU time | 2.65 seconds |
Started | Jul 29 07:35:58 PM PDT 24 |
Finished | Jul 29 07:36:01 PM PDT 24 |
Peak memory | 218408 kb |
Host | smart-8409a2df-12eb-4e15-951b-fe58f211fea5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4235241477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.4235241477 |
Directory | /workspace/32.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/32.keymgr_smoke.2662234477 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 2011317735 ps |
CPU time | 11.73 seconds |
Started | Jul 29 07:35:54 PM PDT 24 |
Finished | Jul 29 07:36:06 PM PDT 24 |
Peak memory | 207860 kb |
Host | smart-88d65f30-c2a0-44ad-bfe2-a01097b59470 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2662234477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2662234477 |
Directory | /workspace/32.keymgr_smoke/latest |
Test location | /workspace/coverage/default/32.keymgr_stress_all.326214810 |
Short name | T747 |
Test name | |
Test status | |
Simulation time | 1247264343 ps |
CPU time | 44.39 seconds |
Started | Jul 29 07:35:52 PM PDT 24 |
Finished | Jul 29 07:36:37 PM PDT 24 |
Peak memory | 216756 kb |
Host | smart-e154c4a7-c064-4ccd-9c93-f472404261d6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326214810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.326214810 |
Directory | /workspace/32.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/32.keymgr_sw_invalid_input.4013748851 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 137784739 ps |
CPU time | 5.77 seconds |
Started | Jul 29 07:36:08 PM PDT 24 |
Finished | Jul 29 07:36:14 PM PDT 24 |
Peak memory | 209456 kb |
Host | smart-28ff6b42-4e8d-4235-a42b-57498d64cec3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4013748851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.4013748851 |
Directory | /workspace/32.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2978505679 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 70939069 ps |
CPU time | 1.71 seconds |
Started | Jul 29 07:36:00 PM PDT 24 |
Finished | Jul 29 07:36:02 PM PDT 24 |
Peak memory | 210280 kb |
Host | smart-f00c9e21-8928-4b61-9cc4-21aea024e25d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2978505679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2978505679 |
Directory | /workspace/32.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/33.keymgr_alert_test.727711824 |
Short name | T743 |
Test name | |
Test status | |
Simulation time | 17550083 ps |
CPU time | 0.68 seconds |
Started | Jul 29 07:36:04 PM PDT 24 |
Finished | Jul 29 07:36:05 PM PDT 24 |
Peak memory | 205976 kb |
Host | smart-cf66e7a3-351d-4825-aca0-c110df8cdfb4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727711824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.727711824 |
Directory | /workspace/33.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/33.keymgr_cfg_regwen.1100658361 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 109798138 ps |
CPU time | 2.59 seconds |
Started | Jul 29 07:35:55 PM PDT 24 |
Finished | Jul 29 07:35:58 PM PDT 24 |
Peak memory | 214308 kb |
Host | smart-c57b9b53-8d68-4ed0-a3a0-be26c4223311 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1100658361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1100658361 |
Directory | /workspace/33.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/33.keymgr_custom_cm.2102094010 |
Short name | T810 |
Test name | |
Test status | |
Simulation time | 145496031 ps |
CPU time | 3.91 seconds |
Started | Jul 29 07:35:58 PM PDT 24 |
Finished | Jul 29 07:36:03 PM PDT 24 |
Peak memory | 209264 kb |
Host | smart-be4f5980-3d41-47a1-8a19-3f91dd86d770 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2102094010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2102094010 |
Directory | /workspace/33.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/33.keymgr_direct_to_disabled.4194622806 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 2146745829 ps |
CPU time | 12.98 seconds |
Started | Jul 29 07:36:08 PM PDT 24 |
Finished | Jul 29 07:36:21 PM PDT 24 |
Peak memory | 209656 kb |
Host | smart-a094cb13-f955-47ea-bf9a-676e09491682 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4194622806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.4194622806 |
Directory | /workspace/33.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1090489242 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 741203003 ps |
CPU time | 10.11 seconds |
Started | Jul 29 07:36:01 PM PDT 24 |
Finished | Jul 29 07:36:11 PM PDT 24 |
Peak memory | 219132 kb |
Host | smart-9e7b248d-cb66-4d00-9ce4-e70708087d7b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1090489242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1090489242 |
Directory | /workspace/33.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/33.keymgr_kmac_rsp_err.1423002877 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 204620856 ps |
CPU time | 4.88 seconds |
Started | Jul 29 07:36:10 PM PDT 24 |
Finished | Jul 29 07:36:15 PM PDT 24 |
Peak memory | 222448 kb |
Host | smart-3f5f2ddb-51d4-493b-b463-9270bb89df49 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1423002877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1423002877 |
Directory | /workspace/33.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/33.keymgr_lc_disable.2179534191 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 278064909 ps |
CPU time | 4.67 seconds |
Started | Jul 29 07:35:58 PM PDT 24 |
Finished | Jul 29 07:36:03 PM PDT 24 |
Peak memory | 217744 kb |
Host | smart-e774e3f5-0b88-482e-b6c9-69a2e426f353 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2179534191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2179534191 |
Directory | /workspace/33.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/33.keymgr_random.3616707090 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 105324184 ps |
CPU time | 2.36 seconds |
Started | Jul 29 07:35:54 PM PDT 24 |
Finished | Jul 29 07:35:57 PM PDT 24 |
Peak memory | 208316 kb |
Host | smart-0ef61b9b-f0d3-4a6f-aa23-a5f02bbd65a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3616707090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3616707090 |
Directory | /workspace/33.keymgr_random/latest |
Test location | /workspace/coverage/default/33.keymgr_sideload.3575729174 |
Short name | T852 |
Test name | |
Test status | |
Simulation time | 24765823 ps |
CPU time | 1.89 seconds |
Started | Jul 29 07:36:10 PM PDT 24 |
Finished | Jul 29 07:36:12 PM PDT 24 |
Peak memory | 208640 kb |
Host | smart-1216930f-8a4a-4c12-9122-65ef1d30d03f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3575729174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3575729174 |
Directory | /workspace/33.keymgr_sideload/latest |
Test location | /workspace/coverage/default/33.keymgr_sideload_aes.3685835540 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 40227061 ps |
CPU time | 2.36 seconds |
Started | Jul 29 07:36:00 PM PDT 24 |
Finished | Jul 29 07:36:03 PM PDT 24 |
Peak memory | 207128 kb |
Host | smart-858f5b70-aee6-4695-a219-5aa0652902c1 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685835540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3685835540 |
Directory | /workspace/33.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/33.keymgr_sideload_kmac.935094114 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 43227085 ps |
CPU time | 1.86 seconds |
Started | Jul 29 07:35:53 PM PDT 24 |
Finished | Jul 29 07:35:55 PM PDT 24 |
Peak memory | 206988 kb |
Host | smart-2d99b133-3afd-4919-bd8a-bc746fbeabc6 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935094114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.935094114 |
Directory | /workspace/33.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/33.keymgr_sideload_otbn.1396584248 |
Short name | T831 |
Test name | |
Test status | |
Simulation time | 1028312494 ps |
CPU time | 24.93 seconds |
Started | Jul 29 07:36:06 PM PDT 24 |
Finished | Jul 29 07:36:31 PM PDT 24 |
Peak memory | 208824 kb |
Host | smart-7f7c9e12-7599-4a4b-8c33-526ff2058e91 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396584248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1396584248 |
Directory | /workspace/33.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/33.keymgr_sideload_protect.35185260 |
Short name | T780 |
Test name | |
Test status | |
Simulation time | 78434886 ps |
CPU time | 1.94 seconds |
Started | Jul 29 07:35:59 PM PDT 24 |
Finished | Jul 29 07:36:01 PM PDT 24 |
Peak memory | 208436 kb |
Host | smart-8e40a0a8-eb51-4cb8-973e-3ab0d7cb89c8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=35185260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.35185260 |
Directory | /workspace/33.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/33.keymgr_smoke.4169396322 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 197922450 ps |
CPU time | 4.57 seconds |
Started | Jul 29 07:36:10 PM PDT 24 |
Finished | Jul 29 07:36:15 PM PDT 24 |
Peak memory | 206940 kb |
Host | smart-d58c9401-6678-4250-a869-f7406c90d5a7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4169396322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.4169396322 |
Directory | /workspace/33.keymgr_smoke/latest |
Test location | /workspace/coverage/default/33.keymgr_stress_all.2245724207 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 385817435 ps |
CPU time | 3.63 seconds |
Started | Jul 29 07:35:57 PM PDT 24 |
Finished | Jul 29 07:36:01 PM PDT 24 |
Peak memory | 214320 kb |
Host | smart-142854e1-74ef-4bad-ab2f-d28fffd40aa5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245724207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2245724207 |
Directory | /workspace/33.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/33.keymgr_sw_invalid_input.4187429186 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 1737988763 ps |
CPU time | 8.93 seconds |
Started | Jul 29 07:35:58 PM PDT 24 |
Finished | Jul 29 07:36:07 PM PDT 24 |
Peak memory | 214256 kb |
Host | smart-da3b5e04-4809-4e4d-af3c-8cc0405f3e4c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4187429186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.4187429186 |
Directory | /workspace/33.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/33.keymgr_sync_async_fault_cross.61150511 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 283935661 ps |
CPU time | 2.16 seconds |
Started | Jul 29 07:35:57 PM PDT 24 |
Finished | Jul 29 07:36:00 PM PDT 24 |
Peak memory | 210084 kb |
Host | smart-28ed40d7-0760-4578-9d8f-a7f71827c134 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=61150511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.61150511 |
Directory | /workspace/33.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/34.keymgr_alert_test.3219544568 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 13981993 ps |
CPU time | 0.76 seconds |
Started | Jul 29 07:36:08 PM PDT 24 |
Finished | Jul 29 07:36:09 PM PDT 24 |
Peak memory | 205992 kb |
Host | smart-c515be3f-e0fb-4b76-a0ee-8fb2ad6ccacc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219544568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3219544568 |
Directory | /workspace/34.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/34.keymgr_direct_to_disabled.3813536215 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 190165292 ps |
CPU time | 2.85 seconds |
Started | Jul 29 07:36:05 PM PDT 24 |
Finished | Jul 29 07:36:08 PM PDT 24 |
Peak memory | 208216 kb |
Host | smart-b7f23bdf-1563-4f8c-b715-461148d7e50d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3813536215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3813536215 |
Directory | /workspace/34.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/34.keymgr_hwsw_invalid_input.415193208 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 22516167 ps |
CPU time | 1.56 seconds |
Started | Jul 29 07:36:01 PM PDT 24 |
Finished | Jul 29 07:36:02 PM PDT 24 |
Peak memory | 214392 kb |
Host | smart-30c609ce-ae42-4204-bad9-e50f863885a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=415193208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.415193208 |
Directory | /workspace/34.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/34.keymgr_kmac_rsp_err.3733424098 |
Short name | T801 |
Test name | |
Test status | |
Simulation time | 217850060 ps |
CPU time | 3.58 seconds |
Started | Jul 29 07:36:03 PM PDT 24 |
Finished | Jul 29 07:36:06 PM PDT 24 |
Peak memory | 214412 kb |
Host | smart-3438491c-42c0-419a-b316-843ffad1593d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3733424098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3733424098 |
Directory | /workspace/34.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/34.keymgr_lc_disable.3599597185 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 244453445 ps |
CPU time | 5.76 seconds |
Started | Jul 29 07:36:02 PM PDT 24 |
Finished | Jul 29 07:36:07 PM PDT 24 |
Peak memory | 210832 kb |
Host | smart-7c9f7cd9-0fc2-455b-b50a-d1dd121e969c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3599597185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3599597185 |
Directory | /workspace/34.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/34.keymgr_random.1837676219 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 73928198 ps |
CPU time | 2.57 seconds |
Started | Jul 29 07:36:05 PM PDT 24 |
Finished | Jul 29 07:36:08 PM PDT 24 |
Peak memory | 214304 kb |
Host | smart-6b83426c-c54a-4ba0-b00c-c17ed95dd2c8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1837676219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1837676219 |
Directory | /workspace/34.keymgr_random/latest |
Test location | /workspace/coverage/default/34.keymgr_sideload.3710434727 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 85862151 ps |
CPU time | 3.96 seconds |
Started | Jul 29 07:35:58 PM PDT 24 |
Finished | Jul 29 07:36:02 PM PDT 24 |
Peak memory | 208420 kb |
Host | smart-327abd9e-1594-4bd8-bc7d-7ee6ccd7cc6d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3710434727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3710434727 |
Directory | /workspace/34.keymgr_sideload/latest |
Test location | /workspace/coverage/default/34.keymgr_sideload_aes.352163029 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 125193986 ps |
CPU time | 3.17 seconds |
Started | Jul 29 07:36:02 PM PDT 24 |
Finished | Jul 29 07:36:05 PM PDT 24 |
Peak memory | 206952 kb |
Host | smart-7ddb7aa8-19e3-4014-b8ad-95d97ee63014 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352163029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.352163029 |
Directory | /workspace/34.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/34.keymgr_sideload_kmac.3233187380 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 3333158876 ps |
CPU time | 22.72 seconds |
Started | Jul 29 07:35:59 PM PDT 24 |
Finished | Jul 29 07:36:22 PM PDT 24 |
Peak memory | 208288 kb |
Host | smart-18f61652-c7f1-4217-81ef-efb0a0dd4f72 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233187380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3233187380 |
Directory | /workspace/34.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/34.keymgr_sideload_otbn.1805383321 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 1167877059 ps |
CPU time | 4.37 seconds |
Started | Jul 29 07:36:05 PM PDT 24 |
Finished | Jul 29 07:36:10 PM PDT 24 |
Peak memory | 209068 kb |
Host | smart-63996fe1-d070-40a5-9d09-eaa917efcfb7 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805383321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1805383321 |
Directory | /workspace/34.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/34.keymgr_sideload_protect.43341100 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 494380982 ps |
CPU time | 3.35 seconds |
Started | Jul 29 07:36:01 PM PDT 24 |
Finished | Jul 29 07:36:05 PM PDT 24 |
Peak memory | 218280 kb |
Host | smart-66b668b0-dfa1-496d-b4a0-8f4ef95c9020 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=43341100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.43341100 |
Directory | /workspace/34.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/34.keymgr_smoke.705994692 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 45838251 ps |
CPU time | 2.39 seconds |
Started | Jul 29 07:36:06 PM PDT 24 |
Finished | Jul 29 07:36:09 PM PDT 24 |
Peak memory | 208520 kb |
Host | smart-90debd71-f03a-4d8a-afc9-0e92063779e4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=705994692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.705994692 |
Directory | /workspace/34.keymgr_smoke/latest |
Test location | /workspace/coverage/default/34.keymgr_stress_all.2593470010 |
Short name | T777 |
Test name | |
Test status | |
Simulation time | 724659600 ps |
CPU time | 34.27 seconds |
Started | Jul 29 07:35:56 PM PDT 24 |
Finished | Jul 29 07:36:30 PM PDT 24 |
Peak memory | 215124 kb |
Host | smart-8458ab7e-6812-4b3f-8a7f-8770cae63b34 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593470010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2593470010 |
Directory | /workspace/34.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/34.keymgr_sw_invalid_input.1570745951 |
Short name | T673 |
Test name | |
Test status | |
Simulation time | 127066447 ps |
CPU time | 4.79 seconds |
Started | Jul 29 07:35:59 PM PDT 24 |
Finished | Jul 29 07:36:04 PM PDT 24 |
Peak memory | 214452 kb |
Host | smart-c0cfd8f7-795c-4c9c-bcde-4977f941f3c7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1570745951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1570745951 |
Directory | /workspace/34.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2834450913 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 227786287 ps |
CPU time | 2.03 seconds |
Started | Jul 29 07:36:04 PM PDT 24 |
Finished | Jul 29 07:36:06 PM PDT 24 |
Peak memory | 210352 kb |
Host | smart-322a4612-6fa6-4881-85de-d7743026b03e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2834450913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2834450913 |
Directory | /workspace/34.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/35.keymgr_alert_test.3364519107 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 63261822 ps |
CPU time | 0.82 seconds |
Started | Jul 29 07:36:04 PM PDT 24 |
Finished | Jul 29 07:36:05 PM PDT 24 |
Peak memory | 205976 kb |
Host | smart-3be76c7c-9b35-43a9-b559-81bf778f014b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364519107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3364519107 |
Directory | /workspace/35.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/35.keymgr_cfg_regwen.2198977907 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 601497665 ps |
CPU time | 7.87 seconds |
Started | Jul 29 07:36:09 PM PDT 24 |
Finished | Jul 29 07:36:17 PM PDT 24 |
Peak memory | 222428 kb |
Host | smart-2894ed91-0bab-4e74-a15b-2154195884d7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2198977907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2198977907 |
Directory | /workspace/35.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/35.keymgr_custom_cm.2541345030 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 380164197 ps |
CPU time | 2.12 seconds |
Started | Jul 29 07:36:06 PM PDT 24 |
Finished | Jul 29 07:36:08 PM PDT 24 |
Peak memory | 209748 kb |
Host | smart-2cf8cbd9-09e7-4a4f-9d5d-c0e900c535da |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2541345030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2541345030 |
Directory | /workspace/35.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/35.keymgr_direct_to_disabled.1464014693 |
Short name | T882 |
Test name | |
Test status | |
Simulation time | 118865700 ps |
CPU time | 3.31 seconds |
Started | Jul 29 07:35:58 PM PDT 24 |
Finished | Jul 29 07:36:02 PM PDT 24 |
Peak memory | 214280 kb |
Host | smart-99bef24f-2188-423f-aa56-14fddc074345 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1464014693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1464014693 |
Directory | /workspace/35.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/35.keymgr_hwsw_invalid_input.196244392 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 226869081 ps |
CPU time | 3.04 seconds |
Started | Jul 29 07:36:05 PM PDT 24 |
Finished | Jul 29 07:36:08 PM PDT 24 |
Peak memory | 209572 kb |
Host | smart-8e7915b9-dfa5-4d14-8e28-0c925402a4f9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=196244392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.196244392 |
Directory | /workspace/35.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/35.keymgr_kmac_rsp_err.885646230 |
Short name | T708 |
Test name | |
Test status | |
Simulation time | 154601020 ps |
CPU time | 2.1 seconds |
Started | Jul 29 07:36:10 PM PDT 24 |
Finished | Jul 29 07:36:12 PM PDT 24 |
Peak memory | 211548 kb |
Host | smart-42df7793-15bf-441f-9c5c-75a37724f63b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=885646230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.885646230 |
Directory | /workspace/35.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/35.keymgr_lc_disable.2753955936 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 87643275 ps |
CPU time | 3.22 seconds |
Started | Jul 29 07:35:55 PM PDT 24 |
Finished | Jul 29 07:35:59 PM PDT 24 |
Peak memory | 220360 kb |
Host | smart-57f060ff-f220-434a-bbe1-8c40c1b7602a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2753955936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2753955936 |
Directory | /workspace/35.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/35.keymgr_random.731985337 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 3339571560 ps |
CPU time | 31.64 seconds |
Started | Jul 29 07:36:01 PM PDT 24 |
Finished | Jul 29 07:36:33 PM PDT 24 |
Peak memory | 208132 kb |
Host | smart-873e54a1-06cb-42cd-8c75-81b54a8596fd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=731985337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.731985337 |
Directory | /workspace/35.keymgr_random/latest |
Test location | /workspace/coverage/default/35.keymgr_sideload.2290852766 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 262043803 ps |
CPU time | 6.55 seconds |
Started | Jul 29 07:35:58 PM PDT 24 |
Finished | Jul 29 07:36:05 PM PDT 24 |
Peak memory | 208460 kb |
Host | smart-048cc74d-40e5-41f4-8ef2-d61cecdeb861 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2290852766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2290852766 |
Directory | /workspace/35.keymgr_sideload/latest |
Test location | /workspace/coverage/default/35.keymgr_sideload_aes.2980092494 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 342427692 ps |
CPU time | 3.31 seconds |
Started | Jul 29 07:36:04 PM PDT 24 |
Finished | Jul 29 07:36:08 PM PDT 24 |
Peak memory | 208768 kb |
Host | smart-f6dcf346-ba07-4f8f-8c4d-5f0558b2da40 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980092494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2980092494 |
Directory | /workspace/35.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/35.keymgr_sideload_kmac.979096670 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 233615799 ps |
CPU time | 6.42 seconds |
Started | Jul 29 07:36:07 PM PDT 24 |
Finished | Jul 29 07:36:13 PM PDT 24 |
Peak memory | 208944 kb |
Host | smart-4c8930cd-3064-4eaf-a884-db6d8170eca1 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979096670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.979096670 |
Directory | /workspace/35.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/35.keymgr_sideload_otbn.2762839916 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 226058482 ps |
CPU time | 2.67 seconds |
Started | Jul 29 07:35:59 PM PDT 24 |
Finished | Jul 29 07:36:02 PM PDT 24 |
Peak memory | 208876 kb |
Host | smart-09ed71ab-38d5-4fe4-8c4f-6e5c93176069 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762839916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2762839916 |
Directory | /workspace/35.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/35.keymgr_sideload_protect.652621796 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 98653419 ps |
CPU time | 2.66 seconds |
Started | Jul 29 07:35:54 PM PDT 24 |
Finished | Jul 29 07:35:56 PM PDT 24 |
Peak memory | 214296 kb |
Host | smart-74851460-496c-4e4c-adc6-7f3aa440f22b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=652621796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.652621796 |
Directory | /workspace/35.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/35.keymgr_smoke.3629954943 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 205654102 ps |
CPU time | 2.52 seconds |
Started | Jul 29 07:35:59 PM PDT 24 |
Finished | Jul 29 07:36:02 PM PDT 24 |
Peak memory | 206728 kb |
Host | smart-60ce2d3b-a737-47ac-adc9-27d3c89cbb7b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3629954943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3629954943 |
Directory | /workspace/35.keymgr_smoke/latest |
Test location | /workspace/coverage/default/35.keymgr_sw_invalid_input.4056056521 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 805864109 ps |
CPU time | 5.24 seconds |
Started | Jul 29 07:36:05 PM PDT 24 |
Finished | Jul 29 07:36:11 PM PDT 24 |
Peak memory | 210500 kb |
Host | smart-131f5b50-7981-4cde-8669-98c5d799d3a5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4056056521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.4056056521 |
Directory | /workspace/35.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/35.keymgr_sync_async_fault_cross.667318060 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 97819406 ps |
CPU time | 1.67 seconds |
Started | Jul 29 07:36:01 PM PDT 24 |
Finished | Jul 29 07:36:08 PM PDT 24 |
Peak memory | 210812 kb |
Host | smart-b5189053-96d3-4f9e-94e3-df5352d4df81 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=667318060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.667318060 |
Directory | /workspace/35.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/36.keymgr_alert_test.2568788573 |
Short name | T817 |
Test name | |
Test status | |
Simulation time | 39835389 ps |
CPU time | 0.72 seconds |
Started | Jul 29 07:36:07 PM PDT 24 |
Finished | Jul 29 07:36:08 PM PDT 24 |
Peak memory | 205964 kb |
Host | smart-969e5430-2e8c-4b42-bbfc-1c210540c8ab |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568788573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2568788573 |
Directory | /workspace/36.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/36.keymgr_cfg_regwen.804392469 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 155396761 ps |
CPU time | 8.31 seconds |
Started | Jul 29 07:36:09 PM PDT 24 |
Finished | Jul 29 07:36:17 PM PDT 24 |
Peak memory | 214484 kb |
Host | smart-d27c32f9-ea36-4d64-bf5e-3559faad5bf2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=804392469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.804392469 |
Directory | /workspace/36.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/36.keymgr_custom_cm.2735145241 |
Short name | T774 |
Test name | |
Test status | |
Simulation time | 267961757 ps |
CPU time | 7.05 seconds |
Started | Jul 29 07:36:03 PM PDT 24 |
Finished | Jul 29 07:36:10 PM PDT 24 |
Peak memory | 221700 kb |
Host | smart-8d5dd187-70aa-4ad6-9de6-863d2d6ef5c9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2735145241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2735145241 |
Directory | /workspace/36.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/36.keymgr_direct_to_disabled.2003653706 |
Short name | T669 |
Test name | |
Test status | |
Simulation time | 185549328 ps |
CPU time | 2.38 seconds |
Started | Jul 29 07:36:08 PM PDT 24 |
Finished | Jul 29 07:36:11 PM PDT 24 |
Peak memory | 214260 kb |
Host | smart-cc39c782-1cbe-46a5-a418-01b1a75aa44d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2003653706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2003653706 |
Directory | /workspace/36.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/36.keymgr_kmac_rsp_err.105067829 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 119275881 ps |
CPU time | 3.8 seconds |
Started | Jul 29 07:36:09 PM PDT 24 |
Finished | Jul 29 07:36:13 PM PDT 24 |
Peak memory | 214392 kb |
Host | smart-c96fa86b-5b60-4f01-8f20-d2fcd579c0c2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=105067829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.105067829 |
Directory | /workspace/36.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/36.keymgr_lc_disable.2361754766 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 166441464 ps |
CPU time | 2.51 seconds |
Started | Jul 29 07:36:03 PM PDT 24 |
Finished | Jul 29 07:36:05 PM PDT 24 |
Peak memory | 219020 kb |
Host | smart-571f8862-9562-4078-9e74-682fffdc1dcb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2361754766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2361754766 |
Directory | /workspace/36.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/36.keymgr_random.2827549123 |
Short name | T822 |
Test name | |
Test status | |
Simulation time | 183390263 ps |
CPU time | 4.6 seconds |
Started | Jul 29 07:36:09 PM PDT 24 |
Finished | Jul 29 07:36:14 PM PDT 24 |
Peak memory | 209864 kb |
Host | smart-f616f7ca-9a55-41a4-b963-574e41671fe2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2827549123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2827549123 |
Directory | /workspace/36.keymgr_random/latest |
Test location | /workspace/coverage/default/36.keymgr_sideload.4134410193 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 223116291 ps |
CPU time | 2.06 seconds |
Started | Jul 29 07:35:59 PM PDT 24 |
Finished | Jul 29 07:36:02 PM PDT 24 |
Peak memory | 208576 kb |
Host | smart-ce5ba46d-9aea-4fed-88ba-346ba2eacd02 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4134410193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.4134410193 |
Directory | /workspace/36.keymgr_sideload/latest |
Test location | /workspace/coverage/default/36.keymgr_sideload_aes.1934201974 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 171265937 ps |
CPU time | 4.97 seconds |
Started | Jul 29 07:36:04 PM PDT 24 |
Finished | Jul 29 07:36:09 PM PDT 24 |
Peak memory | 207984 kb |
Host | smart-55f364a0-6885-4f8a-b42d-ef8321caae67 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934201974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1934201974 |
Directory | /workspace/36.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/36.keymgr_sideload_kmac.3915953400 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 189830152 ps |
CPU time | 4.39 seconds |
Started | Jul 29 07:35:53 PM PDT 24 |
Finished | Jul 29 07:35:58 PM PDT 24 |
Peak memory | 208512 kb |
Host | smart-103ec974-63c3-4cc3-84b0-4382ed9ddbfc |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915953400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3915953400 |
Directory | /workspace/36.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/36.keymgr_sideload_otbn.817104899 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 196098241 ps |
CPU time | 2.86 seconds |
Started | Jul 29 07:36:09 PM PDT 24 |
Finished | Jul 29 07:36:12 PM PDT 24 |
Peak memory | 206876 kb |
Host | smart-59e4d324-30c9-4304-9092-69aef9f1045c |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817104899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.817104899 |
Directory | /workspace/36.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/36.keymgr_sideload_protect.91123174 |
Short name | T646 |
Test name | |
Test status | |
Simulation time | 116172082 ps |
CPU time | 2.93 seconds |
Started | Jul 29 07:36:01 PM PDT 24 |
Finished | Jul 29 07:36:04 PM PDT 24 |
Peak memory | 215648 kb |
Host | smart-45a583c9-0b76-4ccd-8e14-e07efeb3355d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=91123174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.91123174 |
Directory | /workspace/36.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/36.keymgr_smoke.528406080 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 77929800 ps |
CPU time | 3.17 seconds |
Started | Jul 29 07:35:59 PM PDT 24 |
Finished | Jul 29 07:36:02 PM PDT 24 |
Peak memory | 209008 kb |
Host | smart-6bb1a0dc-4c69-4a24-97a6-f08c7b8080da |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=528406080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.528406080 |
Directory | /workspace/36.keymgr_smoke/latest |
Test location | /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.1352556235 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 147237785 ps |
CPU time | 6.22 seconds |
Started | Jul 29 07:36:09 PM PDT 24 |
Finished | Jul 29 07:36:15 PM PDT 24 |
Peak memory | 222480 kb |
Host | smart-806e80bd-6297-44e6-aac0-13da35d7fb18 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352556235 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.1352556235 |
Directory | /workspace/36.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/36.keymgr_sw_invalid_input.3176963589 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 407582392 ps |
CPU time | 5.37 seconds |
Started | Jul 29 07:36:12 PM PDT 24 |
Finished | Jul 29 07:36:17 PM PDT 24 |
Peak memory | 208624 kb |
Host | smart-80e4ca02-6480-4051-9341-cd11f97aa487 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3176963589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3176963589 |
Directory | /workspace/36.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/36.keymgr_sync_async_fault_cross.4097668866 |
Short name | T681 |
Test name | |
Test status | |
Simulation time | 398428269 ps |
CPU time | 9.2 seconds |
Started | Jul 29 07:35:58 PM PDT 24 |
Finished | Jul 29 07:36:08 PM PDT 24 |
Peak memory | 210248 kb |
Host | smart-9716ff8e-2715-42b5-9dbb-d80c642f09f4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4097668866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.4097668866 |
Directory | /workspace/36.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/37.keymgr_alert_test.3891648963 |
Short name | T911 |
Test name | |
Test status | |
Simulation time | 20894747 ps |
CPU time | 0.78 seconds |
Started | Jul 29 07:36:04 PM PDT 24 |
Finished | Jul 29 07:36:04 PM PDT 24 |
Peak memory | 205960 kb |
Host | smart-61c66fc3-3a04-407a-8ecb-4a16899f6423 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891648963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3891648963 |
Directory | /workspace/37.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/37.keymgr_cfg_regwen.1149815210 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 58388799 ps |
CPU time | 3.99 seconds |
Started | Jul 29 07:35:56 PM PDT 24 |
Finished | Jul 29 07:36:00 PM PDT 24 |
Peak memory | 215420 kb |
Host | smart-ea473e94-59cd-4d6d-9970-654a0bcd487e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1149815210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1149815210 |
Directory | /workspace/37.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/37.keymgr_custom_cm.3872560393 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 203075417 ps |
CPU time | 4.21 seconds |
Started | Jul 29 07:36:09 PM PDT 24 |
Finished | Jul 29 07:36:14 PM PDT 24 |
Peak memory | 209776 kb |
Host | smart-8f3e6492-fc0a-40ea-ba7b-df525339cdf9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3872560393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3872560393 |
Directory | /workspace/37.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/37.keymgr_direct_to_disabled.4017993802 |
Short name | T654 |
Test name | |
Test status | |
Simulation time | 142578713 ps |
CPU time | 3.4 seconds |
Started | Jul 29 07:36:10 PM PDT 24 |
Finished | Jul 29 07:36:14 PM PDT 24 |
Peak memory | 218468 kb |
Host | smart-76f2847e-9891-4be9-b2b0-03305c889c83 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4017993802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.4017993802 |
Directory | /workspace/37.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3739138364 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 246565134 ps |
CPU time | 4.05 seconds |
Started | Jul 29 07:36:06 PM PDT 24 |
Finished | Jul 29 07:36:11 PM PDT 24 |
Peak memory | 214316 kb |
Host | smart-89e9b2a7-a32a-47fa-832e-ae2e7001d1ca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3739138364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3739138364 |
Directory | /workspace/37.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/37.keymgr_kmac_rsp_err.3852684902 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 236577167 ps |
CPU time | 2.84 seconds |
Started | Jul 29 07:36:06 PM PDT 24 |
Finished | Jul 29 07:36:09 PM PDT 24 |
Peak memory | 220484 kb |
Host | smart-3d662835-8d60-492c-9339-5bdf15d6ce10 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3852684902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3852684902 |
Directory | /workspace/37.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/37.keymgr_lc_disable.2431508568 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 51807781 ps |
CPU time | 2.65 seconds |
Started | Jul 29 07:36:04 PM PDT 24 |
Finished | Jul 29 07:36:07 PM PDT 24 |
Peak memory | 208940 kb |
Host | smart-90996996-0055-4085-a164-0dff4e22be12 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2431508568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2431508568 |
Directory | /workspace/37.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/37.keymgr_random.1466507352 |
Short name | T834 |
Test name | |
Test status | |
Simulation time | 279353983 ps |
CPU time | 3.55 seconds |
Started | Jul 29 07:36:05 PM PDT 24 |
Finished | Jul 29 07:36:08 PM PDT 24 |
Peak memory | 214408 kb |
Host | smart-b61512d4-6283-4a6a-ac68-6f55f683d51a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1466507352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1466507352 |
Directory | /workspace/37.keymgr_random/latest |
Test location | /workspace/coverage/default/37.keymgr_sideload.1363612693 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 795159621 ps |
CPU time | 23.15 seconds |
Started | Jul 29 07:36:11 PM PDT 24 |
Finished | Jul 29 07:36:34 PM PDT 24 |
Peak memory | 208076 kb |
Host | smart-24cc0f41-6497-4c15-9234-7e99156f80f7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1363612693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1363612693 |
Directory | /workspace/37.keymgr_sideload/latest |
Test location | /workspace/coverage/default/37.keymgr_sideload_aes.3345147954 |
Short name | T781 |
Test name | |
Test status | |
Simulation time | 595011567 ps |
CPU time | 7.16 seconds |
Started | Jul 29 07:36:06 PM PDT 24 |
Finished | Jul 29 07:36:13 PM PDT 24 |
Peak memory | 208588 kb |
Host | smart-ab8a7336-5f33-4a46-8886-9cb307faf4a5 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345147954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3345147954 |
Directory | /workspace/37.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/37.keymgr_sideload_kmac.3680113723 |
Short name | T680 |
Test name | |
Test status | |
Simulation time | 198628162 ps |
CPU time | 5.55 seconds |
Started | Jul 29 07:36:07 PM PDT 24 |
Finished | Jul 29 07:36:13 PM PDT 24 |
Peak memory | 207876 kb |
Host | smart-ab8c0059-5229-425f-9436-80a3ae65c573 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680113723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3680113723 |
Directory | /workspace/37.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/37.keymgr_sideload_otbn.1201735524 |
Short name | T733 |
Test name | |
Test status | |
Simulation time | 101124403 ps |
CPU time | 3.51 seconds |
Started | Jul 29 07:36:08 PM PDT 24 |
Finished | Jul 29 07:36:12 PM PDT 24 |
Peak memory | 208904 kb |
Host | smart-3b82d3a1-32e5-44be-b5f4-4e38aea52e6d |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201735524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1201735524 |
Directory | /workspace/37.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/37.keymgr_sideload_protect.3452417773 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 124605654 ps |
CPU time | 3.39 seconds |
Started | Jul 29 07:35:59 PM PDT 24 |
Finished | Jul 29 07:36:03 PM PDT 24 |
Peak memory | 214312 kb |
Host | smart-c5da500e-1c78-4582-8b21-92b05f1e5d96 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3452417773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3452417773 |
Directory | /workspace/37.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/37.keymgr_smoke.2252136933 |
Short name | T866 |
Test name | |
Test status | |
Simulation time | 429937493 ps |
CPU time | 11.29 seconds |
Started | Jul 29 07:36:08 PM PDT 24 |
Finished | Jul 29 07:36:19 PM PDT 24 |
Peak memory | 208236 kb |
Host | smart-ba84f988-ac7d-4402-89fb-41ac48053e3d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2252136933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2252136933 |
Directory | /workspace/37.keymgr_smoke/latest |
Test location | /workspace/coverage/default/37.keymgr_stress_all.672514417 |
Short name | T855 |
Test name | |
Test status | |
Simulation time | 8774698759 ps |
CPU time | 15.77 seconds |
Started | Jul 29 07:36:05 PM PDT 24 |
Finished | Jul 29 07:36:21 PM PDT 24 |
Peak memory | 219820 kb |
Host | smart-f8e10a45-3198-4298-9f6f-5a2580598f17 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672514417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.672514417 |
Directory | /workspace/37.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/37.keymgr_sw_invalid_input.2215641647 |
Short name | T838 |
Test name | |
Test status | |
Simulation time | 462332838 ps |
CPU time | 9.87 seconds |
Started | Jul 29 07:36:06 PM PDT 24 |
Finished | Jul 29 07:36:16 PM PDT 24 |
Peak memory | 218448 kb |
Host | smart-92842f4f-465d-459e-843d-7e902c2241f4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2215641647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2215641647 |
Directory | /workspace/37.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2899212593 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 963941182 ps |
CPU time | 8.91 seconds |
Started | Jul 29 07:35:56 PM PDT 24 |
Finished | Jul 29 07:36:05 PM PDT 24 |
Peak memory | 211068 kb |
Host | smart-1047ac90-cba4-46ff-9feb-1a97321fe1ba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2899212593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2899212593 |
Directory | /workspace/37.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/38.keymgr_alert_test.834800700 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 46385446 ps |
CPU time | 0.76 seconds |
Started | Jul 29 07:36:03 PM PDT 24 |
Finished | Jul 29 07:36:04 PM PDT 24 |
Peak memory | 205956 kb |
Host | smart-840302f2-deb3-4d86-8db9-0745dd8fb5fc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834800700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.834800700 |
Directory | /workspace/38.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/38.keymgr_cfg_regwen.1596296668 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 57648837 ps |
CPU time | 4.05 seconds |
Started | Jul 29 07:36:02 PM PDT 24 |
Finished | Jul 29 07:36:06 PM PDT 24 |
Peak memory | 214324 kb |
Host | smart-22f8279d-2cf0-43a0-bbac-e0f0415e32e4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1596296668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1596296668 |
Directory | /workspace/38.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/38.keymgr_custom_cm.475665955 |
Short name | T659 |
Test name | |
Test status | |
Simulation time | 39437871 ps |
CPU time | 2.61 seconds |
Started | Jul 29 07:35:57 PM PDT 24 |
Finished | Jul 29 07:36:00 PM PDT 24 |
Peak memory | 220072 kb |
Host | smart-2e20845b-dd6c-4e9c-bc12-334d59e43606 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=475665955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.475665955 |
Directory | /workspace/38.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/38.keymgr_direct_to_disabled.1582917885 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 156393545 ps |
CPU time | 2.22 seconds |
Started | Jul 29 07:36:07 PM PDT 24 |
Finished | Jul 29 07:36:10 PM PDT 24 |
Peak memory | 208052 kb |
Host | smart-870ec509-12ae-4b67-ae23-80e898c4dd64 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1582917885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1582917885 |
Directory | /workspace/38.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/38.keymgr_kmac_rsp_err.1733604304 |
Short name | T909 |
Test name | |
Test status | |
Simulation time | 926319145 ps |
CPU time | 4.21 seconds |
Started | Jul 29 07:36:04 PM PDT 24 |
Finished | Jul 29 07:36:09 PM PDT 24 |
Peak memory | 222364 kb |
Host | smart-934931af-146b-412c-8a0b-26e6d79df0e6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1733604304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1733604304 |
Directory | /workspace/38.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/38.keymgr_lc_disable.3585381234 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 112982880 ps |
CPU time | 3.83 seconds |
Started | Jul 29 07:36:06 PM PDT 24 |
Finished | Jul 29 07:36:10 PM PDT 24 |
Peak memory | 216356 kb |
Host | smart-e4064cc5-a959-4585-a443-1edb7821bbf6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3585381234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3585381234 |
Directory | /workspace/38.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/38.keymgr_random.237375322 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 782877148 ps |
CPU time | 9.37 seconds |
Started | Jul 29 07:36:06 PM PDT 24 |
Finished | Jul 29 07:36:16 PM PDT 24 |
Peak memory | 218080 kb |
Host | smart-68182b8a-b842-478d-939d-8c8c2a70b063 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=237375322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.237375322 |
Directory | /workspace/38.keymgr_random/latest |
Test location | /workspace/coverage/default/38.keymgr_sideload.1096101404 |
Short name | T807 |
Test name | |
Test status | |
Simulation time | 423340045 ps |
CPU time | 3.22 seconds |
Started | Jul 29 07:36:01 PM PDT 24 |
Finished | Jul 29 07:36:04 PM PDT 24 |
Peak memory | 208460 kb |
Host | smart-19a49bca-3b60-42a8-996e-c6f76d9e651a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1096101404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1096101404 |
Directory | /workspace/38.keymgr_sideload/latest |
Test location | /workspace/coverage/default/38.keymgr_sideload_aes.3984069269 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 22645446 ps |
CPU time | 1.82 seconds |
Started | Jul 29 07:36:04 PM PDT 24 |
Finished | Jul 29 07:36:06 PM PDT 24 |
Peak memory | 206676 kb |
Host | smart-50aa35ea-0e02-40d3-ae32-1ce4539c7f77 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984069269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3984069269 |
Directory | /workspace/38.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/38.keymgr_sideload_kmac.2690806762 |
Short name | T639 |
Test name | |
Test status | |
Simulation time | 24616103 ps |
CPU time | 2 seconds |
Started | Jul 29 07:36:08 PM PDT 24 |
Finished | Jul 29 07:36:10 PM PDT 24 |
Peak memory | 208680 kb |
Host | smart-1b109fee-2090-4f61-9c8c-89a27cd429f2 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690806762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2690806762 |
Directory | /workspace/38.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/38.keymgr_sideload_otbn.1669782962 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 233621904 ps |
CPU time | 3.21 seconds |
Started | Jul 29 07:36:03 PM PDT 24 |
Finished | Jul 29 07:36:07 PM PDT 24 |
Peak memory | 208880 kb |
Host | smart-fa669b55-5ac7-4980-bec1-a4aad1ccd4aa |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669782962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1669782962 |
Directory | /workspace/38.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/38.keymgr_sideload_protect.861118832 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 256746540 ps |
CPU time | 5.37 seconds |
Started | Jul 29 07:36:03 PM PDT 24 |
Finished | Jul 29 07:36:08 PM PDT 24 |
Peak memory | 208984 kb |
Host | smart-8b39cf35-ad13-4934-bcd9-3a43867e842d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=861118832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.861118832 |
Directory | /workspace/38.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/38.keymgr_smoke.2923199826 |
Short name | T622 |
Test name | |
Test status | |
Simulation time | 74510310 ps |
CPU time | 2.08 seconds |
Started | Jul 29 07:36:05 PM PDT 24 |
Finished | Jul 29 07:36:08 PM PDT 24 |
Peak memory | 206984 kb |
Host | smart-5a13a687-960b-4139-a832-4b40a3726220 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2923199826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2923199826 |
Directory | /workspace/38.keymgr_smoke/latest |
Test location | /workspace/coverage/default/38.keymgr_stress_all.2185171582 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 1590285119 ps |
CPU time | 33.76 seconds |
Started | Jul 29 07:35:56 PM PDT 24 |
Finished | Jul 29 07:36:30 PM PDT 24 |
Peak memory | 216760 kb |
Host | smart-b3c4f93d-548c-4ec8-848d-b4a4cf0beada |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185171582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2185171582 |
Directory | /workspace/38.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.2430682774 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 1041119170 ps |
CPU time | 20.02 seconds |
Started | Jul 29 07:36:05 PM PDT 24 |
Finished | Jul 29 07:36:25 PM PDT 24 |
Peak memory | 222500 kb |
Host | smart-07b75bb7-fabb-4fc4-b08f-5686e26b0275 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430682774 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.2430682774 |
Directory | /workspace/38.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/38.keymgr_sw_invalid_input.3762937448 |
Short name | T869 |
Test name | |
Test status | |
Simulation time | 278149146 ps |
CPU time | 8.16 seconds |
Started | Jul 29 07:35:59 PM PDT 24 |
Finished | Jul 29 07:36:13 PM PDT 24 |
Peak memory | 208048 kb |
Host | smart-1cc6588d-b8a4-4113-8a52-0f5ae6318735 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3762937448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3762937448 |
Directory | /workspace/38.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/39.keymgr_alert_test.1143627093 |
Short name | T803 |
Test name | |
Test status | |
Simulation time | 22370034 ps |
CPU time | 0.82 seconds |
Started | Jul 29 07:36:12 PM PDT 24 |
Finished | Jul 29 07:36:18 PM PDT 24 |
Peak memory | 205936 kb |
Host | smart-0da88304-4b04-4c85-8c95-c819169364ef |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143627093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1143627093 |
Directory | /workspace/39.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/39.keymgr_cfg_regwen.2905508989 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 4508955548 ps |
CPU time | 62.96 seconds |
Started | Jul 29 07:36:11 PM PDT 24 |
Finished | Jul 29 07:37:14 PM PDT 24 |
Peak memory | 222504 kb |
Host | smart-67319ccb-5465-44f3-b2dc-0f2ced2fb688 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2905508989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2905508989 |
Directory | /workspace/39.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/39.keymgr_direct_to_disabled.2834681036 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 524272420 ps |
CPU time | 8.39 seconds |
Started | Jul 29 07:36:17 PM PDT 24 |
Finished | Jul 29 07:36:26 PM PDT 24 |
Peak memory | 209736 kb |
Host | smart-d4f843e3-4810-4c21-8d1d-ec1cefbe9bf8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2834681036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2834681036 |
Directory | /workspace/39.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2150890890 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 35853894 ps |
CPU time | 1.79 seconds |
Started | Jul 29 07:36:22 PM PDT 24 |
Finished | Jul 29 07:36:23 PM PDT 24 |
Peak memory | 214324 kb |
Host | smart-d01e63d1-6df0-48d9-96bd-c529d904822c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2150890890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2150890890 |
Directory | /workspace/39.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/39.keymgr_kmac_rsp_err.1894874058 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 171716514 ps |
CPU time | 3.4 seconds |
Started | Jul 29 07:36:11 PM PDT 24 |
Finished | Jul 29 07:36:15 PM PDT 24 |
Peak memory | 222440 kb |
Host | smart-13199b0e-b71e-4acc-90f1-eb6c18177e38 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1894874058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.1894874058 |
Directory | /workspace/39.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/39.keymgr_lc_disable.916598556 |
Short name | T818 |
Test name | |
Test status | |
Simulation time | 255766355 ps |
CPU time | 3.21 seconds |
Started | Jul 29 07:36:12 PM PDT 24 |
Finished | Jul 29 07:36:15 PM PDT 24 |
Peak memory | 219180 kb |
Host | smart-6dc02d4d-62e0-46c8-98ef-e92c39e8ae75 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=916598556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.916598556 |
Directory | /workspace/39.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/39.keymgr_random.2306938810 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 555304532 ps |
CPU time | 3.34 seconds |
Started | Jul 29 07:36:18 PM PDT 24 |
Finished | Jul 29 07:36:21 PM PDT 24 |
Peak memory | 208312 kb |
Host | smart-8ec363a9-ea2d-410f-ac37-bc05da381fbf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2306938810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2306938810 |
Directory | /workspace/39.keymgr_random/latest |
Test location | /workspace/coverage/default/39.keymgr_sideload.817467179 |
Short name | T798 |
Test name | |
Test status | |
Simulation time | 78434907 ps |
CPU time | 3.21 seconds |
Started | Jul 29 07:36:09 PM PDT 24 |
Finished | Jul 29 07:36:13 PM PDT 24 |
Peak memory | 208492 kb |
Host | smart-ae6400c8-c53a-4408-bf79-1c656ac7e66c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=817467179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.817467179 |
Directory | /workspace/39.keymgr_sideload/latest |
Test location | /workspace/coverage/default/39.keymgr_sideload_aes.476068664 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 300513494 ps |
CPU time | 3.16 seconds |
Started | Jul 29 07:36:22 PM PDT 24 |
Finished | Jul 29 07:36:25 PM PDT 24 |
Peak memory | 206896 kb |
Host | smart-12fa6cef-e703-4c2d-8643-c5d89cf8edc3 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476068664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.476068664 |
Directory | /workspace/39.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/39.keymgr_sideload_kmac.2116715487 |
Short name | T719 |
Test name | |
Test status | |
Simulation time | 842894341 ps |
CPU time | 16.13 seconds |
Started | Jul 29 07:36:09 PM PDT 24 |
Finished | Jul 29 07:36:26 PM PDT 24 |
Peak memory | 207900 kb |
Host | smart-ab8c8743-7747-484a-bb04-ea0f542f8e2a |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116715487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2116715487 |
Directory | /workspace/39.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/39.keymgr_sideload_otbn.3273934868 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 1860928020 ps |
CPU time | 4.7 seconds |
Started | Jul 29 07:36:11 PM PDT 24 |
Finished | Jul 29 07:36:16 PM PDT 24 |
Peak memory | 208812 kb |
Host | smart-267dac56-95ba-4d59-b37d-d62b8fbe98d8 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273934868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3273934868 |
Directory | /workspace/39.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/39.keymgr_sideload_protect.91983048 |
Short name | T738 |
Test name | |
Test status | |
Simulation time | 364741579 ps |
CPU time | 1.9 seconds |
Started | Jul 29 07:36:12 PM PDT 24 |
Finished | Jul 29 07:36:14 PM PDT 24 |
Peak memory | 215512 kb |
Host | smart-6ee3a435-58a2-4385-b85b-72b3cd16d727 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=91983048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.91983048 |
Directory | /workspace/39.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/39.keymgr_smoke.1270179711 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 87540382 ps |
CPU time | 2.86 seconds |
Started | Jul 29 07:36:11 PM PDT 24 |
Finished | Jul 29 07:36:14 PM PDT 24 |
Peak memory | 206972 kb |
Host | smart-516723c6-db9f-4b7d-aee7-18b0209adf77 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1270179711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1270179711 |
Directory | /workspace/39.keymgr_smoke/latest |
Test location | /workspace/coverage/default/39.keymgr_sw_invalid_input.2819489064 |
Short name | T667 |
Test name | |
Test status | |
Simulation time | 107810215 ps |
CPU time | 2.21 seconds |
Started | Jul 29 07:36:11 PM PDT 24 |
Finished | Jul 29 07:36:13 PM PDT 24 |
Peak memory | 207936 kb |
Host | smart-def46d39-88b0-48d2-bed0-5c2d1802bc21 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2819489064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2819489064 |
Directory | /workspace/39.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/39.keymgr_sync_async_fault_cross.1674923818 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 63444521 ps |
CPU time | 2.72 seconds |
Started | Jul 29 07:36:22 PM PDT 24 |
Finished | Jul 29 07:36:25 PM PDT 24 |
Peak memory | 210040 kb |
Host | smart-417fa937-d0b8-4644-b5d0-3473ae8bbda9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1674923818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.1674923818 |
Directory | /workspace/39.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/4.keymgr_alert_test.2747641622 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 16996233 ps |
CPU time | 0.8 seconds |
Started | Jul 29 07:34:44 PM PDT 24 |
Finished | Jul 29 07:34:45 PM PDT 24 |
Peak memory | 205948 kb |
Host | smart-f67ac8f5-a276-4715-b3c3-9b817ea25d95 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747641622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2747641622 |
Directory | /workspace/4.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/4.keymgr_cfg_regwen.264516260 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 186225117 ps |
CPU time | 3.82 seconds |
Started | Jul 29 07:34:41 PM PDT 24 |
Finished | Jul 29 07:34:45 PM PDT 24 |
Peak memory | 215368 kb |
Host | smart-6358871f-16c0-469f-8b15-7a5df8921956 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=264516260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.264516260 |
Directory | /workspace/4.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/4.keymgr_direct_to_disabled.933956432 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 44204605 ps |
CPU time | 2.24 seconds |
Started | Jul 29 07:34:40 PM PDT 24 |
Finished | Jul 29 07:34:43 PM PDT 24 |
Peak memory | 208256 kb |
Host | smart-962bdadb-6952-4c72-967d-b9636be22d45 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=933956432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.933956432 |
Directory | /workspace/4.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/4.keymgr_hwsw_invalid_input.668444841 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 64093595 ps |
CPU time | 2.63 seconds |
Started | Jul 29 07:34:48 PM PDT 24 |
Finished | Jul 29 07:34:51 PM PDT 24 |
Peak memory | 214376 kb |
Host | smart-1bdbbe4f-ada2-4dd3-8f5e-ddc70d565949 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=668444841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.668444841 |
Directory | /workspace/4.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/4.keymgr_lc_disable.677433196 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 194652860 ps |
CPU time | 3.46 seconds |
Started | Jul 29 07:34:39 PM PDT 24 |
Finished | Jul 29 07:34:42 PM PDT 24 |
Peak memory | 209548 kb |
Host | smart-4301e48a-cde5-48f9-9c26-6caabb70ea3d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=677433196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.677433196 |
Directory | /workspace/4.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/4.keymgr_random.859107679 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 1015472336 ps |
CPU time | 3.84 seconds |
Started | Jul 29 07:34:49 PM PDT 24 |
Finished | Jul 29 07:34:53 PM PDT 24 |
Peak memory | 208476 kb |
Host | smart-11908827-cc09-450e-a266-353b9d1fb907 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=859107679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.859107679 |
Directory | /workspace/4.keymgr_random/latest |
Test location | /workspace/coverage/default/4.keymgr_sec_cm.3850827019 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 1068906027 ps |
CPU time | 15.87 seconds |
Started | Jul 29 07:34:48 PM PDT 24 |
Finished | Jul 29 07:35:04 PM PDT 24 |
Peak memory | 231712 kb |
Host | smart-aa698140-bbb0-44a7-b08d-6e2ed8b27c5c |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850827019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3850827019 |
Directory | /workspace/4.keymgr_sec_cm/latest |
Test location | /workspace/coverage/default/4.keymgr_sideload.472318423 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 82848884 ps |
CPU time | 1.87 seconds |
Started | Jul 29 07:34:42 PM PDT 24 |
Finished | Jul 29 07:34:44 PM PDT 24 |
Peak memory | 206816 kb |
Host | smart-9e4b22ad-2f45-4622-81d5-a72bb5d7fd9e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=472318423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.472318423 |
Directory | /workspace/4.keymgr_sideload/latest |
Test location | /workspace/coverage/default/4.keymgr_sideload_aes.2232586145 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 67318832 ps |
CPU time | 3.06 seconds |
Started | Jul 29 07:34:39 PM PDT 24 |
Finished | Jul 29 07:34:43 PM PDT 24 |
Peak memory | 208084 kb |
Host | smart-5e4b0e7c-7667-48ab-ab47-d215f9cfe2fa |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232586145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2232586145 |
Directory | /workspace/4.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/4.keymgr_sideload_kmac.3791065099 |
Short name | T627 |
Test name | |
Test status | |
Simulation time | 38705885 ps |
CPU time | 2.38 seconds |
Started | Jul 29 07:34:46 PM PDT 24 |
Finished | Jul 29 07:34:49 PM PDT 24 |
Peak memory | 206936 kb |
Host | smart-ba46497a-8399-4cca-b43f-812dcbf8d3f3 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791065099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3791065099 |
Directory | /workspace/4.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/4.keymgr_sideload_otbn.3486368202 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 99531050 ps |
CPU time | 4.04 seconds |
Started | Jul 29 07:34:48 PM PDT 24 |
Finished | Jul 29 07:34:52 PM PDT 24 |
Peak memory | 208908 kb |
Host | smart-e3f05b0d-8538-4b6c-8cd3-264445cb732a |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486368202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3486368202 |
Directory | /workspace/4.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/4.keymgr_sideload_protect.3298334473 |
Short name | T626 |
Test name | |
Test status | |
Simulation time | 43374402 ps |
CPU time | 1.75 seconds |
Started | Jul 29 07:34:48 PM PDT 24 |
Finished | Jul 29 07:34:50 PM PDT 24 |
Peak memory | 206932 kb |
Host | smart-ae28624e-cc48-445d-8353-2168de43b740 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3298334473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3298334473 |
Directory | /workspace/4.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/4.keymgr_smoke.1829133979 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 66829357 ps |
CPU time | 2.96 seconds |
Started | Jul 29 07:34:44 PM PDT 24 |
Finished | Jul 29 07:34:47 PM PDT 24 |
Peak memory | 208004 kb |
Host | smart-efea91d4-82a6-4e3f-92b4-965ec33f8974 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1829133979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1829133979 |
Directory | /workspace/4.keymgr_smoke/latest |
Test location | /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.1363188871 |
Short name | T790 |
Test name | |
Test status | |
Simulation time | 655377324 ps |
CPU time | 25.55 seconds |
Started | Jul 29 07:34:48 PM PDT 24 |
Finished | Jul 29 07:35:13 PM PDT 24 |
Peak memory | 222532 kb |
Host | smart-f25e8152-eaf3-4c00-b473-143e813dc56b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363188871 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.1363188871 |
Directory | /workspace/4.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/4.keymgr_sw_invalid_input.2429089511 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 359598951 ps |
CPU time | 4.53 seconds |
Started | Jul 29 07:34:41 PM PDT 24 |
Finished | Jul 29 07:34:46 PM PDT 24 |
Peak memory | 218408 kb |
Host | smart-39f88cc3-42fb-45bc-883b-aa24e052e2f2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2429089511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2429089511 |
Directory | /workspace/4.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/4.keymgr_sync_async_fault_cross.795839306 |
Short name | T674 |
Test name | |
Test status | |
Simulation time | 299854475 ps |
CPU time | 7.65 seconds |
Started | Jul 29 07:34:49 PM PDT 24 |
Finished | Jul 29 07:34:56 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-c07555c5-e30a-40f4-8f0f-39db52d0c8d4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=795839306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.795839306 |
Directory | /workspace/4.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/40.keymgr_alert_test.640651352 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 10528236 ps |
CPU time | 0.89 seconds |
Started | Jul 29 07:36:20 PM PDT 24 |
Finished | Jul 29 07:36:21 PM PDT 24 |
Peak memory | 205948 kb |
Host | smart-d1bd7c62-2f3f-458f-8d70-c9361af252db |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640651352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.640651352 |
Directory | /workspace/40.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/40.keymgr_cfg_regwen.3607341476 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 415917550 ps |
CPU time | 11.29 seconds |
Started | Jul 29 07:36:11 PM PDT 24 |
Finished | Jul 29 07:36:22 PM PDT 24 |
Peak memory | 214504 kb |
Host | smart-c1966a6e-9954-43f1-923d-76692f975cbf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3607341476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3607341476 |
Directory | /workspace/40.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/40.keymgr_custom_cm.806549865 |
Short name | T732 |
Test name | |
Test status | |
Simulation time | 567006152 ps |
CPU time | 2.76 seconds |
Started | Jul 29 07:36:17 PM PDT 24 |
Finished | Jul 29 07:36:20 PM PDT 24 |
Peak memory | 209188 kb |
Host | smart-89159c1f-ca05-4d1d-a518-eeaa9f5182b4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=806549865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.806549865 |
Directory | /workspace/40.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/40.keymgr_direct_to_disabled.3673961420 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 39443916 ps |
CPU time | 2.11 seconds |
Started | Jul 29 07:36:12 PM PDT 24 |
Finished | Jul 29 07:36:14 PM PDT 24 |
Peak memory | 214320 kb |
Host | smart-52d5d0b5-dc17-4494-9a0d-8f91ea8a24ea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3673961420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3673961420 |
Directory | /workspace/40.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/40.keymgr_hwsw_invalid_input.4083889978 |
Short name | T884 |
Test name | |
Test status | |
Simulation time | 249316180 ps |
CPU time | 3.21 seconds |
Started | Jul 29 07:36:12 PM PDT 24 |
Finished | Jul 29 07:36:15 PM PDT 24 |
Peak memory | 209208 kb |
Host | smart-b95393a4-d3e0-49ed-b6e8-42c81a258590 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4083889978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.4083889978 |
Directory | /workspace/40.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/40.keymgr_lc_disable.4065451206 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 407040919 ps |
CPU time | 2.82 seconds |
Started | Jul 29 07:36:12 PM PDT 24 |
Finished | Jul 29 07:36:15 PM PDT 24 |
Peak memory | 214296 kb |
Host | smart-b04ab51f-02ea-4e06-ba68-c30a92ccbbc8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4065451206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.4065451206 |
Directory | /workspace/40.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/40.keymgr_random.1321513723 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 14066280895 ps |
CPU time | 26.62 seconds |
Started | Jul 29 07:36:12 PM PDT 24 |
Finished | Jul 29 07:36:39 PM PDT 24 |
Peak memory | 208680 kb |
Host | smart-400d1074-821a-491d-b4bd-0f8dcfacf86f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1321513723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1321513723 |
Directory | /workspace/40.keymgr_random/latest |
Test location | /workspace/coverage/default/40.keymgr_sideload.1464260221 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 261020323 ps |
CPU time | 3.16 seconds |
Started | Jul 29 07:36:12 PM PDT 24 |
Finished | Jul 29 07:36:20 PM PDT 24 |
Peak memory | 208816 kb |
Host | smart-df6b3bdc-5419-4924-97de-86665a29a0b1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1464260221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1464260221 |
Directory | /workspace/40.keymgr_sideload/latest |
Test location | /workspace/coverage/default/40.keymgr_sideload_aes.3910103466 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 116424585 ps |
CPU time | 4.12 seconds |
Started | Jul 29 07:36:10 PM PDT 24 |
Finished | Jul 29 07:36:15 PM PDT 24 |
Peak memory | 206936 kb |
Host | smart-7dd5008b-a730-4b04-8e55-bf80834c02b0 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910103466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3910103466 |
Directory | /workspace/40.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/40.keymgr_sideload_kmac.3320389257 |
Short name | T692 |
Test name | |
Test status | |
Simulation time | 211453866 ps |
CPU time | 7.94 seconds |
Started | Jul 29 07:36:22 PM PDT 24 |
Finished | Jul 29 07:36:30 PM PDT 24 |
Peak memory | 208640 kb |
Host | smart-973dc545-db93-428c-be89-09ef1aa0ca95 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320389257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3320389257 |
Directory | /workspace/40.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/40.keymgr_sideload_otbn.93102287 |
Short name | T628 |
Test name | |
Test status | |
Simulation time | 351064742 ps |
CPU time | 3.67 seconds |
Started | Jul 29 07:36:11 PM PDT 24 |
Finished | Jul 29 07:36:15 PM PDT 24 |
Peak memory | 208720 kb |
Host | smart-f850248c-39ec-4065-9353-98ea4891b13e |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93102287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.93102287 |
Directory | /workspace/40.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/40.keymgr_sideload_protect.1959083499 |
Short name | T710 |
Test name | |
Test status | |
Simulation time | 348500681 ps |
CPU time | 10.64 seconds |
Started | Jul 29 07:36:17 PM PDT 24 |
Finished | Jul 29 07:36:27 PM PDT 24 |
Peak memory | 209444 kb |
Host | smart-beae2dfc-93d7-4b89-95ea-2d2d07dce47e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1959083499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1959083499 |
Directory | /workspace/40.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/40.keymgr_smoke.1860017374 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 3280964342 ps |
CPU time | 15.93 seconds |
Started | Jul 29 07:36:14 PM PDT 24 |
Finished | Jul 29 07:36:30 PM PDT 24 |
Peak memory | 207940 kb |
Host | smart-2175a869-34af-48cc-88a8-12092e420ae3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1860017374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1860017374 |
Directory | /workspace/40.keymgr_smoke/latest |
Test location | /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.1776005667 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 797898903 ps |
CPU time | 31.06 seconds |
Started | Jul 29 07:36:06 PM PDT 24 |
Finished | Jul 29 07:36:37 PM PDT 24 |
Peak memory | 222428 kb |
Host | smart-aee21d4b-141e-4710-8515-77151699e217 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776005667 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.1776005667 |
Directory | /workspace/40.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/40.keymgr_sw_invalid_input.1489245411 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 139131564 ps |
CPU time | 4.66 seconds |
Started | Jul 29 07:36:11 PM PDT 24 |
Finished | Jul 29 07:36:16 PM PDT 24 |
Peak memory | 207368 kb |
Host | smart-70169f33-3b88-4068-a8b7-c32acccbc0aa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1489245411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1489245411 |
Directory | /workspace/40.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/40.keymgr_sync_async_fault_cross.722204513 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 44076351 ps |
CPU time | 1.64 seconds |
Started | Jul 29 07:36:10 PM PDT 24 |
Finished | Jul 29 07:36:12 PM PDT 24 |
Peak memory | 208552 kb |
Host | smart-921fa3db-18ff-4e97-88ae-0c18dc7283cc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=722204513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.722204513 |
Directory | /workspace/40.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/41.keymgr_alert_test.2501823038 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 34370413 ps |
CPU time | 0.72 seconds |
Started | Jul 29 07:36:34 PM PDT 24 |
Finished | Jul 29 07:36:35 PM PDT 24 |
Peak memory | 205940 kb |
Host | smart-9d252b68-68ac-4874-93a7-1c6a79cd5e5e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501823038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2501823038 |
Directory | /workspace/41.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/41.keymgr_cfg_regwen.812918511 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 620340123 ps |
CPU time | 14.77 seconds |
Started | Jul 29 07:36:17 PM PDT 24 |
Finished | Jul 29 07:36:32 PM PDT 24 |
Peak memory | 214344 kb |
Host | smart-8d6d3d55-4f76-4f3a-b9e7-1b810f7c465a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=812918511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.812918511 |
Directory | /workspace/41.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/41.keymgr_custom_cm.30851614 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 103715610 ps |
CPU time | 2.52 seconds |
Started | Jul 29 07:36:15 PM PDT 24 |
Finished | Jul 29 07:36:17 PM PDT 24 |
Peak memory | 222608 kb |
Host | smart-bbbe9bba-1e57-4202-9fdf-2999700305fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30851614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.30851614 |
Directory | /workspace/41.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/41.keymgr_direct_to_disabled.3424956182 |
Short name | T752 |
Test name | |
Test status | |
Simulation time | 75178779 ps |
CPU time | 2.5 seconds |
Started | Jul 29 07:36:14 PM PDT 24 |
Finished | Jul 29 07:36:16 PM PDT 24 |
Peak memory | 214360 kb |
Host | smart-fca01491-fbf1-4c0d-8554-b5ce6142f6b1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3424956182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3424956182 |
Directory | /workspace/41.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/41.keymgr_kmac_rsp_err.562098367 |
Short name | T700 |
Test name | |
Test status | |
Simulation time | 33331750 ps |
CPU time | 1.37 seconds |
Started | Jul 29 07:36:24 PM PDT 24 |
Finished | Jul 29 07:36:25 PM PDT 24 |
Peak memory | 214280 kb |
Host | smart-1122e466-7675-4ac4-a20f-b8a690e06774 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=562098367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.562098367 |
Directory | /workspace/41.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/41.keymgr_lc_disable.4045120775 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 257484187 ps |
CPU time | 4.15 seconds |
Started | Jul 29 07:36:24 PM PDT 24 |
Finished | Jul 29 07:36:28 PM PDT 24 |
Peak memory | 222452 kb |
Host | smart-2a54fe58-0f13-457a-a57d-059952b1aaed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4045120775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.4045120775 |
Directory | /workspace/41.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/41.keymgr_random.1760816904 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 147588343 ps |
CPU time | 2.82 seconds |
Started | Jul 29 07:36:21 PM PDT 24 |
Finished | Jul 29 07:36:24 PM PDT 24 |
Peak memory | 214312 kb |
Host | smart-3d3c83c8-f584-4571-a463-d22f41862857 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1760816904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1760816904 |
Directory | /workspace/41.keymgr_random/latest |
Test location | /workspace/coverage/default/41.keymgr_sideload.3680546783 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 64268450 ps |
CPU time | 3.08 seconds |
Started | Jul 29 07:36:10 PM PDT 24 |
Finished | Jul 29 07:36:13 PM PDT 24 |
Peak memory | 206948 kb |
Host | smart-7a5dad09-07a3-4ed1-a123-fc03d6f3d141 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3680546783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3680546783 |
Directory | /workspace/41.keymgr_sideload/latest |
Test location | /workspace/coverage/default/41.keymgr_sideload_aes.2493138990 |
Short name | T877 |
Test name | |
Test status | |
Simulation time | 213779098 ps |
CPU time | 2.94 seconds |
Started | Jul 29 07:36:06 PM PDT 24 |
Finished | Jul 29 07:36:09 PM PDT 24 |
Peak memory | 206944 kb |
Host | smart-3333bac2-6b71-4561-ab1c-061462fc4650 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493138990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2493138990 |
Directory | /workspace/41.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/41.keymgr_sideload_kmac.3065670739 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 390064902 ps |
CPU time | 3.25 seconds |
Started | Jul 29 07:36:12 PM PDT 24 |
Finished | Jul 29 07:36:15 PM PDT 24 |
Peak memory | 208536 kb |
Host | smart-155ad823-6498-4ee9-bf9c-7377bdb2cbab |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065670739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3065670739 |
Directory | /workspace/41.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/41.keymgr_sideload_otbn.3813198203 |
Short name | T907 |
Test name | |
Test status | |
Simulation time | 568726981 ps |
CPU time | 2.84 seconds |
Started | Jul 29 07:36:11 PM PDT 24 |
Finished | Jul 29 07:36:14 PM PDT 24 |
Peak memory | 207108 kb |
Host | smart-e1d0fc85-e44a-40d6-bc58-83120dda7ec3 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813198203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3813198203 |
Directory | /workspace/41.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/41.keymgr_sideload_protect.2390222479 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 196077623 ps |
CPU time | 2.7 seconds |
Started | Jul 29 07:36:23 PM PDT 24 |
Finished | Jul 29 07:36:26 PM PDT 24 |
Peak memory | 209800 kb |
Host | smart-410005d3-cc45-4802-bd86-2ea5091c2ccf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2390222479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2390222479 |
Directory | /workspace/41.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/41.keymgr_smoke.1899375815 |
Short name | T760 |
Test name | |
Test status | |
Simulation time | 77237541 ps |
CPU time | 2.12 seconds |
Started | Jul 29 07:36:30 PM PDT 24 |
Finished | Jul 29 07:36:33 PM PDT 24 |
Peak memory | 208868 kb |
Host | smart-7e642fc3-2fe4-42bb-b286-586eee42a534 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1899375815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1899375815 |
Directory | /workspace/41.keymgr_smoke/latest |
Test location | /workspace/coverage/default/41.keymgr_sw_invalid_input.3653471950 |
Short name | T827 |
Test name | |
Test status | |
Simulation time | 513539156 ps |
CPU time | 2.69 seconds |
Started | Jul 29 07:36:18 PM PDT 24 |
Finished | Jul 29 07:36:20 PM PDT 24 |
Peak memory | 207780 kb |
Host | smart-91b0b9fc-044d-4527-b1ca-c1ca85d4ca85 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3653471950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3653471950 |
Directory | /workspace/41.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3775639513 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 206423642 ps |
CPU time | 3.52 seconds |
Started | Jul 29 07:36:25 PM PDT 24 |
Finished | Jul 29 07:36:28 PM PDT 24 |
Peak memory | 210352 kb |
Host | smart-3e9a6086-ac0f-4061-8776-4ed4bf3960f1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3775639513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3775639513 |
Directory | /workspace/41.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/42.keymgr_alert_test.2572173077 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 25827616 ps |
CPU time | 0.88 seconds |
Started | Jul 29 07:36:37 PM PDT 24 |
Finished | Jul 29 07:36:38 PM PDT 24 |
Peak memory | 205968 kb |
Host | smart-384b6a98-f3cf-4528-bb48-c13e899cc12e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572173077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2572173077 |
Directory | /workspace/42.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/42.keymgr_cfg_regwen.3997071895 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 52434718 ps |
CPU time | 3.87 seconds |
Started | Jul 29 07:36:12 PM PDT 24 |
Finished | Jul 29 07:36:16 PM PDT 24 |
Peak memory | 214300 kb |
Host | smart-ebedf9dc-6344-4ca3-9202-7d7021e3e611 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3997071895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3997071895 |
Directory | /workspace/42.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/42.keymgr_custom_cm.3659660791 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 167156908 ps |
CPU time | 2.4 seconds |
Started | Jul 29 07:36:28 PM PDT 24 |
Finished | Jul 29 07:36:31 PM PDT 24 |
Peak memory | 214588 kb |
Host | smart-7f44a3b0-04c4-449d-ae95-29682899820d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3659660791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3659660791 |
Directory | /workspace/42.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/42.keymgr_direct_to_disabled.3188598313 |
Short name | T892 |
Test name | |
Test status | |
Simulation time | 27401081 ps |
CPU time | 1.89 seconds |
Started | Jul 29 07:36:23 PM PDT 24 |
Finished | Jul 29 07:36:25 PM PDT 24 |
Peak memory | 218352 kb |
Host | smart-8c54452c-360d-4248-86c3-a0d95af698b7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3188598313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3188598313 |
Directory | /workspace/42.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/42.keymgr_hwsw_invalid_input.561106119 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 8420432588 ps |
CPU time | 81.08 seconds |
Started | Jul 29 07:36:21 PM PDT 24 |
Finished | Jul 29 07:37:42 PM PDT 24 |
Peak memory | 214316 kb |
Host | smart-09b69b5d-9962-42e7-813c-6267f90c94da |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=561106119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.561106119 |
Directory | /workspace/42.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/42.keymgr_kmac_rsp_err.2027362476 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 56325729 ps |
CPU time | 2.05 seconds |
Started | Jul 29 07:36:19 PM PDT 24 |
Finished | Jul 29 07:36:21 PM PDT 24 |
Peak memory | 214264 kb |
Host | smart-cedb5665-18a3-47e1-bdc6-018fa7f783f4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027362476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2027362476 |
Directory | /workspace/42.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/42.keymgr_lc_disable.3465748058 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 332626734 ps |
CPU time | 2.85 seconds |
Started | Jul 29 07:36:31 PM PDT 24 |
Finished | Jul 29 07:36:35 PM PDT 24 |
Peak memory | 218200 kb |
Host | smart-d1d4b435-a277-4d2c-b51b-b85070f935d7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3465748058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3465748058 |
Directory | /workspace/42.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/42.keymgr_random.669216145 |
Short name | T791 |
Test name | |
Test status | |
Simulation time | 192960516 ps |
CPU time | 4.88 seconds |
Started | Jul 29 07:36:23 PM PDT 24 |
Finished | Jul 29 07:36:28 PM PDT 24 |
Peak memory | 219884 kb |
Host | smart-2ce81ea8-b4e6-485c-ad76-6b62bab46a70 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=669216145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.669216145 |
Directory | /workspace/42.keymgr_random/latest |
Test location | /workspace/coverage/default/42.keymgr_sideload.2174416583 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 767337115 ps |
CPU time | 2.61 seconds |
Started | Jul 29 07:36:11 PM PDT 24 |
Finished | Jul 29 07:36:14 PM PDT 24 |
Peak memory | 208272 kb |
Host | smart-39d8717f-019f-4dfc-9906-c29a4dc67260 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2174416583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2174416583 |
Directory | /workspace/42.keymgr_sideload/latest |
Test location | /workspace/coverage/default/42.keymgr_sideload_aes.12550535 |
Short name | T702 |
Test name | |
Test status | |
Simulation time | 54556875 ps |
CPU time | 3.07 seconds |
Started | Jul 29 07:36:09 PM PDT 24 |
Finished | Jul 29 07:36:13 PM PDT 24 |
Peak memory | 208812 kb |
Host | smart-e73a7eb8-a71e-49b7-8d5d-311170b80c46 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12550535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.12550535 |
Directory | /workspace/42.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/42.keymgr_sideload_kmac.3877067649 |
Short name | T630 |
Test name | |
Test status | |
Simulation time | 79842186 ps |
CPU time | 3.08 seconds |
Started | Jul 29 07:36:18 PM PDT 24 |
Finished | Jul 29 07:36:21 PM PDT 24 |
Peak memory | 208512 kb |
Host | smart-55bda98c-3590-4b82-91f3-d5d8ad624c6a |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877067649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3877067649 |
Directory | /workspace/42.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/42.keymgr_sideload_otbn.1101446778 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 411849560 ps |
CPU time | 10.26 seconds |
Started | Jul 29 07:36:14 PM PDT 24 |
Finished | Jul 29 07:36:25 PM PDT 24 |
Peak memory | 208636 kb |
Host | smart-dcf5ae52-a9de-4106-8fce-b31330b2bdb7 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101446778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1101446778 |
Directory | /workspace/42.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/42.keymgr_sideload_protect.1053702967 |
Short name | T895 |
Test name | |
Test status | |
Simulation time | 5288762773 ps |
CPU time | 18.41 seconds |
Started | Jul 29 07:36:14 PM PDT 24 |
Finished | Jul 29 07:36:32 PM PDT 24 |
Peak memory | 208052 kb |
Host | smart-a6ac46e3-272f-4d45-be7d-358225352df7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1053702967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1053702967 |
Directory | /workspace/42.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/42.keymgr_smoke.729707475 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 116073569 ps |
CPU time | 2.81 seconds |
Started | Jul 29 07:36:18 PM PDT 24 |
Finished | Jul 29 07:36:20 PM PDT 24 |
Peak memory | 206860 kb |
Host | smart-b9333700-c95d-4ec5-8322-1ee9972ca4a8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=729707475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.729707475 |
Directory | /workspace/42.keymgr_smoke/latest |
Test location | /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.1497361234 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 675292680 ps |
CPU time | 7.04 seconds |
Started | Jul 29 07:36:39 PM PDT 24 |
Finished | Jul 29 07:36:46 PM PDT 24 |
Peak memory | 222524 kb |
Host | smart-bddab2db-37de-4fc0-9507-fbbf68518255 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497361234 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.1497361234 |
Directory | /workspace/42.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/42.keymgr_sw_invalid_input.2354281861 |
Short name | T828 |
Test name | |
Test status | |
Simulation time | 128377058 ps |
CPU time | 4.11 seconds |
Started | Jul 29 07:36:20 PM PDT 24 |
Finished | Jul 29 07:36:24 PM PDT 24 |
Peak memory | 214320 kb |
Host | smart-1344c5d4-2431-4674-8cfc-c14448b2ff25 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2354281861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2354281861 |
Directory | /workspace/42.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2594121636 |
Short name | T735 |
Test name | |
Test status | |
Simulation time | 2390100913 ps |
CPU time | 13.93 seconds |
Started | Jul 29 07:36:32 PM PDT 24 |
Finished | Jul 29 07:36:46 PM PDT 24 |
Peak memory | 211152 kb |
Host | smart-7e53b443-f9be-4fa7-b02f-fa3b998e671d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2594121636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2594121636 |
Directory | /workspace/42.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/43.keymgr_alert_test.3316180355 |
Short name | T643 |
Test name | |
Test status | |
Simulation time | 54877405 ps |
CPU time | 0.74 seconds |
Started | Jul 29 07:36:32 PM PDT 24 |
Finished | Jul 29 07:36:33 PM PDT 24 |
Peak memory | 205952 kb |
Host | smart-f3df56de-71b3-4d50-8a50-6fcb6d84a6da |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316180355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3316180355 |
Directory | /workspace/43.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/43.keymgr_custom_cm.3042539267 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 148751714 ps |
CPU time | 8.02 seconds |
Started | Jul 29 07:36:22 PM PDT 24 |
Finished | Jul 29 07:36:30 PM PDT 24 |
Peak memory | 222692 kb |
Host | smart-3ff76d83-146b-418e-b52b-708d3aef0abb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3042539267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3042539267 |
Directory | /workspace/43.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/43.keymgr_direct_to_disabled.1492472503 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 180397346 ps |
CPU time | 1.85 seconds |
Started | Jul 29 07:36:38 PM PDT 24 |
Finished | Jul 29 07:36:40 PM PDT 24 |
Peak memory | 208404 kb |
Host | smart-43fafcfb-99d9-4c02-84b9-cdf28fea66b8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1492472503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1492472503 |
Directory | /workspace/43.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/43.keymgr_kmac_rsp_err.2564646992 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 409831283 ps |
CPU time | 11.01 seconds |
Started | Jul 29 07:36:35 PM PDT 24 |
Finished | Jul 29 07:36:46 PM PDT 24 |
Peak memory | 211456 kb |
Host | smart-ed55b098-9631-4e75-b683-5ab368d60cf3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2564646992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2564646992 |
Directory | /workspace/43.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/43.keymgr_lc_disable.1646254033 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 35506118 ps |
CPU time | 2.5 seconds |
Started | Jul 29 07:36:24 PM PDT 24 |
Finished | Jul 29 07:36:31 PM PDT 24 |
Peak memory | 220432 kb |
Host | smart-e16687e5-9e42-44f2-bc41-e3214e367d34 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1646254033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1646254033 |
Directory | /workspace/43.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/43.keymgr_random.3632540448 |
Short name | T629 |
Test name | |
Test status | |
Simulation time | 393431806 ps |
CPU time | 4.74 seconds |
Started | Jul 29 07:36:37 PM PDT 24 |
Finished | Jul 29 07:36:42 PM PDT 24 |
Peak memory | 207136 kb |
Host | smart-d40bd2c4-11d3-43f1-a4a5-9374692a4430 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3632540448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3632540448 |
Directory | /workspace/43.keymgr_random/latest |
Test location | /workspace/coverage/default/43.keymgr_sideload.2020614740 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 192394408 ps |
CPU time | 6.25 seconds |
Started | Jul 29 07:36:29 PM PDT 24 |
Finished | Jul 29 07:36:35 PM PDT 24 |
Peak memory | 208620 kb |
Host | smart-71b1a776-bb73-4581-b711-80e428388e8a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2020614740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2020614740 |
Directory | /workspace/43.keymgr_sideload/latest |
Test location | /workspace/coverage/default/43.keymgr_sideload_aes.998873246 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 1831581218 ps |
CPU time | 36.44 seconds |
Started | Jul 29 07:36:26 PM PDT 24 |
Finished | Jul 29 07:37:02 PM PDT 24 |
Peak memory | 208104 kb |
Host | smart-6dfd5e3e-cdc0-4209-b446-2e3a15701dd5 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998873246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.998873246 |
Directory | /workspace/43.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/43.keymgr_sideload_kmac.1202408276 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 154613116 ps |
CPU time | 5.04 seconds |
Started | Jul 29 07:36:26 PM PDT 24 |
Finished | Jul 29 07:36:31 PM PDT 24 |
Peak memory | 208080 kb |
Host | smart-8189fabf-fa7b-4c6f-9296-759423bd5466 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202408276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1202408276 |
Directory | /workspace/43.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/43.keymgr_sideload_otbn.3780176713 |
Short name | T734 |
Test name | |
Test status | |
Simulation time | 808071145 ps |
CPU time | 5.91 seconds |
Started | Jul 29 07:36:21 PM PDT 24 |
Finished | Jul 29 07:36:27 PM PDT 24 |
Peak memory | 208700 kb |
Host | smart-8d177957-d622-4e8f-992e-c3072ce4a38d |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780176713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3780176713 |
Directory | /workspace/43.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/43.keymgr_sideload_protect.2728898381 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 75535807 ps |
CPU time | 2.58 seconds |
Started | Jul 29 07:36:20 PM PDT 24 |
Finished | Jul 29 07:36:23 PM PDT 24 |
Peak memory | 215792 kb |
Host | smart-9a85778d-5efa-4bb8-ab78-ff58ec972221 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2728898381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2728898381 |
Directory | /workspace/43.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/43.keymgr_smoke.907378605 |
Short name | T794 |
Test name | |
Test status | |
Simulation time | 112295685 ps |
CPU time | 3.85 seconds |
Started | Jul 29 07:36:34 PM PDT 24 |
Finished | Jul 29 07:36:38 PM PDT 24 |
Peak memory | 208788 kb |
Host | smart-3c8666d8-4da5-4325-a0ca-4a78f4ca717e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=907378605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.907378605 |
Directory | /workspace/43.keymgr_smoke/latest |
Test location | /workspace/coverage/default/43.keymgr_stress_all.3214612425 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 2543385678 ps |
CPU time | 19.63 seconds |
Started | Jul 29 07:36:34 PM PDT 24 |
Finished | Jul 29 07:36:53 PM PDT 24 |
Peak memory | 216588 kb |
Host | smart-2e0f29cf-6419-44cb-96d4-de9a5ec5be12 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214612425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3214612425 |
Directory | /workspace/43.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.385376842 |
Short name | T830 |
Test name | |
Test status | |
Simulation time | 748794860 ps |
CPU time | 8.17 seconds |
Started | Jul 29 07:36:22 PM PDT 24 |
Finished | Jul 29 07:36:30 PM PDT 24 |
Peak memory | 219500 kb |
Host | smart-658ee5d5-1f53-421e-a68f-aef147457979 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385376842 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.385376842 |
Directory | /workspace/43.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/43.keymgr_sw_invalid_input.514996174 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 697318588 ps |
CPU time | 9.8 seconds |
Started | Jul 29 07:36:19 PM PDT 24 |
Finished | Jul 29 07:36:29 PM PDT 24 |
Peak memory | 210312 kb |
Host | smart-207acaca-6c85-4614-8637-47ae5026d23f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=514996174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.514996174 |
Directory | /workspace/43.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/43.keymgr_sync_async_fault_cross.300900962 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 103731658 ps |
CPU time | 1.98 seconds |
Started | Jul 29 07:36:20 PM PDT 24 |
Finished | Jul 29 07:36:22 PM PDT 24 |
Peak memory | 210192 kb |
Host | smart-073ba4c9-2c65-48d1-b9c5-8a75ea496ef0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=300900962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.300900962 |
Directory | /workspace/43.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/44.keymgr_alert_test.1541906162 |
Short name | T668 |
Test name | |
Test status | |
Simulation time | 25921950 ps |
CPU time | 0.74 seconds |
Started | Jul 29 07:36:53 PM PDT 24 |
Finished | Jul 29 07:36:54 PM PDT 24 |
Peak memory | 205892 kb |
Host | smart-c3bdf42a-42c7-4ee7-9a70-9fdd5a52ff3a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541906162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1541906162 |
Directory | /workspace/44.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/44.keymgr_cfg_regwen.1617009925 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 121460497 ps |
CPU time | 2.44 seconds |
Started | Jul 29 07:36:29 PM PDT 24 |
Finished | Jul 29 07:36:32 PM PDT 24 |
Peak memory | 214552 kb |
Host | smart-cf4d3ba6-ced5-4c8b-b27d-0b098ebae495 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1617009925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1617009925 |
Directory | /workspace/44.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/44.keymgr_direct_to_disabled.1910903286 |
Short name | T651 |
Test name | |
Test status | |
Simulation time | 48480268 ps |
CPU time | 2.38 seconds |
Started | Jul 29 07:36:33 PM PDT 24 |
Finished | Jul 29 07:36:35 PM PDT 24 |
Peak memory | 207688 kb |
Host | smart-78577646-73ae-4501-ab11-14b1985ecf43 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1910903286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1910903286 |
Directory | /workspace/44.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/44.keymgr_hwsw_invalid_input.104488925 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 168962066 ps |
CPU time | 2.81 seconds |
Started | Jul 29 07:36:21 PM PDT 24 |
Finished | Jul 29 07:36:24 PM PDT 24 |
Peak memory | 214324 kb |
Host | smart-6453d08c-418b-4835-865a-e1e039d34e72 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=104488925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.104488925 |
Directory | /workspace/44.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/44.keymgr_kmac_rsp_err.3130741563 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 1035235594 ps |
CPU time | 5.35 seconds |
Started | Jul 29 07:36:40 PM PDT 24 |
Finished | Jul 29 07:36:46 PM PDT 24 |
Peak memory | 214272 kb |
Host | smart-9b64fc4b-a63d-4bf0-b0f7-373578227aa1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3130741563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3130741563 |
Directory | /workspace/44.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/44.keymgr_lc_disable.1490549078 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 103868631 ps |
CPU time | 3.88 seconds |
Started | Jul 29 07:36:36 PM PDT 24 |
Finished | Jul 29 07:36:40 PM PDT 24 |
Peak memory | 214356 kb |
Host | smart-c41d5bfc-af4e-42b1-b791-b1d61163c5d8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1490549078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1490549078 |
Directory | /workspace/44.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/44.keymgr_random.3074324833 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 82525424 ps |
CPU time | 3.67 seconds |
Started | Jul 29 07:36:42 PM PDT 24 |
Finished | Jul 29 07:36:46 PM PDT 24 |
Peak memory | 209788 kb |
Host | smart-02ff1986-fa36-4fcf-bd6f-f5c81ea553a0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3074324833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3074324833 |
Directory | /workspace/44.keymgr_random/latest |
Test location | /workspace/coverage/default/44.keymgr_sideload.3860220709 |
Short name | T730 |
Test name | |
Test status | |
Simulation time | 558104049 ps |
CPU time | 2.64 seconds |
Started | Jul 29 07:36:23 PM PDT 24 |
Finished | Jul 29 07:36:26 PM PDT 24 |
Peak memory | 206936 kb |
Host | smart-362db20b-393f-4bca-b4c5-c26d43483087 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3860220709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3860220709 |
Directory | /workspace/44.keymgr_sideload/latest |
Test location | /workspace/coverage/default/44.keymgr_sideload_aes.3358647846 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 1074590606 ps |
CPU time | 25.94 seconds |
Started | Jul 29 07:36:23 PM PDT 24 |
Finished | Jul 29 07:36:49 PM PDT 24 |
Peak memory | 208996 kb |
Host | smart-75567225-bf79-4c7f-abc3-28165901ab96 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358647846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3358647846 |
Directory | /workspace/44.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/44.keymgr_sideload_kmac.442347630 |
Short name | T641 |
Test name | |
Test status | |
Simulation time | 219504569 ps |
CPU time | 2.91 seconds |
Started | Jul 29 07:36:26 PM PDT 24 |
Finished | Jul 29 07:36:29 PM PDT 24 |
Peak memory | 208592 kb |
Host | smart-bfdb09d5-4389-40ac-a595-517b58362438 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442347630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.442347630 |
Directory | /workspace/44.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/44.keymgr_sideload_otbn.1654397303 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 42971131 ps |
CPU time | 2.29 seconds |
Started | Jul 29 07:36:33 PM PDT 24 |
Finished | Jul 29 07:36:36 PM PDT 24 |
Peak memory | 206900 kb |
Host | smart-582fbbc5-b626-4be0-9cb1-1cffbeeb2661 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654397303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1654397303 |
Directory | /workspace/44.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/44.keymgr_sideload_protect.1638282067 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 84998232 ps |
CPU time | 1.75 seconds |
Started | Jul 29 07:36:42 PM PDT 24 |
Finished | Jul 29 07:36:44 PM PDT 24 |
Peak memory | 209360 kb |
Host | smart-97f1225f-5f28-444b-8f20-a9bb7ab6bdd2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1638282067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1638282067 |
Directory | /workspace/44.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/44.keymgr_smoke.2550043681 |
Short name | T775 |
Test name | |
Test status | |
Simulation time | 94879043 ps |
CPU time | 3.72 seconds |
Started | Jul 29 07:36:21 PM PDT 24 |
Finished | Jul 29 07:36:25 PM PDT 24 |
Peak memory | 208536 kb |
Host | smart-d9bf3d2f-5d47-4f8f-bf12-370537e4a974 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2550043681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2550043681 |
Directory | /workspace/44.keymgr_smoke/latest |
Test location | /workspace/coverage/default/44.keymgr_stress_all.317150394 |
Short name | T766 |
Test name | |
Test status | |
Simulation time | 15879253508 ps |
CPU time | 449.03 seconds |
Started | Jul 29 07:36:33 PM PDT 24 |
Finished | Jul 29 07:44:02 PM PDT 24 |
Peak memory | 222440 kb |
Host | smart-df584731-7e00-4a98-99ed-fae70e2d30c2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317150394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.317150394 |
Directory | /workspace/44.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/44.keymgr_sw_invalid_input.2050477564 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 76506518 ps |
CPU time | 4.35 seconds |
Started | Jul 29 07:36:27 PM PDT 24 |
Finished | Jul 29 07:36:31 PM PDT 24 |
Peak memory | 218584 kb |
Host | smart-255910e5-c100-4c74-9423-2075f15397a2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2050477564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2050477564 |
Directory | /workspace/44.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3174272664 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 610856731 ps |
CPU time | 4.97 seconds |
Started | Jul 29 07:36:40 PM PDT 24 |
Finished | Jul 29 07:36:45 PM PDT 24 |
Peak memory | 211064 kb |
Host | smart-94d2447b-5e6a-4c45-9929-1dc10f30fcc6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3174272664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3174272664 |
Directory | /workspace/44.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/45.keymgr_alert_test.2828902598 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 56040328 ps |
CPU time | 0.74 seconds |
Started | Jul 29 07:36:38 PM PDT 24 |
Finished | Jul 29 07:36:39 PM PDT 24 |
Peak memory | 205932 kb |
Host | smart-50e0c8b6-4c9b-4c08-9bae-516d44581319 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828902598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2828902598 |
Directory | /workspace/45.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/45.keymgr_cfg_regwen.3957558122 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 59157391 ps |
CPU time | 3.83 seconds |
Started | Jul 29 07:36:29 PM PDT 24 |
Finished | Jul 29 07:36:33 PM PDT 24 |
Peak memory | 215756 kb |
Host | smart-c3cf79c7-b6f9-4b2a-aeb3-dae669a59687 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3957558122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3957558122 |
Directory | /workspace/45.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/45.keymgr_direct_to_disabled.4119058141 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 197922860 ps |
CPU time | 2.77 seconds |
Started | Jul 29 07:36:45 PM PDT 24 |
Finished | Jul 29 07:36:48 PM PDT 24 |
Peak memory | 207972 kb |
Host | smart-0ebb4036-aaf2-4482-887f-adc51c4fb77f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4119058141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.4119058141 |
Directory | /workspace/45.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/45.keymgr_hwsw_invalid_input.3348214092 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 143529109 ps |
CPU time | 5.58 seconds |
Started | Jul 29 07:36:45 PM PDT 24 |
Finished | Jul 29 07:36:50 PM PDT 24 |
Peak memory | 220952 kb |
Host | smart-27715d28-2c48-4d7a-9b9b-bf9502a0d3fc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3348214092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3348214092 |
Directory | /workspace/45.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/45.keymgr_kmac_rsp_err.2304680542 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 115643260 ps |
CPU time | 3.37 seconds |
Started | Jul 29 07:36:27 PM PDT 24 |
Finished | Jul 29 07:36:31 PM PDT 24 |
Peak memory | 214340 kb |
Host | smart-1ca94541-f351-4837-995e-5af5fa3271b1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2304680542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2304680542 |
Directory | /workspace/45.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/45.keymgr_lc_disable.3047238586 |
Short name | T901 |
Test name | |
Test status | |
Simulation time | 716231334 ps |
CPU time | 3.19 seconds |
Started | Jul 29 07:36:27 PM PDT 24 |
Finished | Jul 29 07:36:30 PM PDT 24 |
Peak memory | 206120 kb |
Host | smart-199b62a4-33b1-47b3-9386-85fcf7f0bc9b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3047238586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3047238586 |
Directory | /workspace/45.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/45.keymgr_random.1698276482 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 360015440 ps |
CPU time | 5.24 seconds |
Started | Jul 29 07:36:28 PM PDT 24 |
Finished | Jul 29 07:36:34 PM PDT 24 |
Peak memory | 214292 kb |
Host | smart-2cbdb71e-9031-44f0-9da5-9f36d3898ea6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1698276482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1698276482 |
Directory | /workspace/45.keymgr_random/latest |
Test location | /workspace/coverage/default/45.keymgr_sideload.2284614435 |
Short name | T891 |
Test name | |
Test status | |
Simulation time | 2087388466 ps |
CPU time | 33.3 seconds |
Started | Jul 29 07:36:31 PM PDT 24 |
Finished | Jul 29 07:37:04 PM PDT 24 |
Peak memory | 208504 kb |
Host | smart-004e7942-13fd-42bf-a756-6dfcf1b45ddd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2284614435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2284614435 |
Directory | /workspace/45.keymgr_sideload/latest |
Test location | /workspace/coverage/default/45.keymgr_sideload_aes.1008452506 |
Short name | T679 |
Test name | |
Test status | |
Simulation time | 497259548 ps |
CPU time | 11.56 seconds |
Started | Jul 29 07:36:46 PM PDT 24 |
Finished | Jul 29 07:36:58 PM PDT 24 |
Peak memory | 208352 kb |
Host | smart-eea0ca7c-d64a-47de-959f-4f42daacda78 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008452506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1008452506 |
Directory | /workspace/45.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/45.keymgr_sideload_kmac.145123369 |
Short name | T706 |
Test name | |
Test status | |
Simulation time | 119514037 ps |
CPU time | 3.64 seconds |
Started | Jul 29 07:36:29 PM PDT 24 |
Finished | Jul 29 07:36:32 PM PDT 24 |
Peak memory | 208548 kb |
Host | smart-40b8284e-86ec-4284-8e58-a45383921009 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145123369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.145123369 |
Directory | /workspace/45.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/45.keymgr_sideload_otbn.1797959766 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 493151639 ps |
CPU time | 6.98 seconds |
Started | Jul 29 07:36:44 PM PDT 24 |
Finished | Jul 29 07:36:51 PM PDT 24 |
Peak memory | 207996 kb |
Host | smart-d8711d9b-fec0-4e6f-8057-e5c93fea7d9d |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797959766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1797959766 |
Directory | /workspace/45.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/45.keymgr_sideload_protect.1651165369 |
Short name | T664 |
Test name | |
Test status | |
Simulation time | 141956213 ps |
CPU time | 3.62 seconds |
Started | Jul 29 07:36:30 PM PDT 24 |
Finished | Jul 29 07:36:34 PM PDT 24 |
Peak memory | 208760 kb |
Host | smart-96fdb571-7e7f-4049-ab93-713112dcb235 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1651165369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1651165369 |
Directory | /workspace/45.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/45.keymgr_smoke.1077829794 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 98802232 ps |
CPU time | 2.74 seconds |
Started | Jul 29 07:36:42 PM PDT 24 |
Finished | Jul 29 07:36:45 PM PDT 24 |
Peak memory | 206804 kb |
Host | smart-7bbcbd4f-540c-452a-9f38-14f6e3dc943b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1077829794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1077829794 |
Directory | /workspace/45.keymgr_smoke/latest |
Test location | /workspace/coverage/default/45.keymgr_stress_all.2937800712 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 11782617570 ps |
CPU time | 296.6 seconds |
Started | Jul 29 07:36:44 PM PDT 24 |
Finished | Jul 29 07:41:41 PM PDT 24 |
Peak memory | 218976 kb |
Host | smart-01829806-d18d-4c0d-bcb0-c436208ac59c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937800712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2937800712 |
Directory | /workspace/45.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.4258052236 |
Short name | T800 |
Test name | |
Test status | |
Simulation time | 431280654 ps |
CPU time | 15.67 seconds |
Started | Jul 29 07:36:37 PM PDT 24 |
Finished | Jul 29 07:36:53 PM PDT 24 |
Peak memory | 222528 kb |
Host | smart-95896541-7a3e-4dfe-8694-4e5dd3a86e28 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258052236 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.4258052236 |
Directory | /workspace/45.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/45.keymgr_sw_invalid_input.52325434 |
Short name | T652 |
Test name | |
Test status | |
Simulation time | 270885069 ps |
CPU time | 5.51 seconds |
Started | Jul 29 07:36:45 PM PDT 24 |
Finished | Jul 29 07:36:51 PM PDT 24 |
Peak memory | 208900 kb |
Host | smart-a7d455fd-0b47-4dc5-902f-a0801e298cee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=52325434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.52325434 |
Directory | /workspace/45.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1116282286 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 33594010 ps |
CPU time | 1.37 seconds |
Started | Jul 29 07:36:26 PM PDT 24 |
Finished | Jul 29 07:36:28 PM PDT 24 |
Peak memory | 210400 kb |
Host | smart-2864a2e6-04c3-4941-82fb-222434f249fc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1116282286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1116282286 |
Directory | /workspace/45.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/46.keymgr_alert_test.2800828876 |
Short name | T778 |
Test name | |
Test status | |
Simulation time | 10033784 ps |
CPU time | 0.82 seconds |
Started | Jul 29 07:36:42 PM PDT 24 |
Finished | Jul 29 07:36:43 PM PDT 24 |
Peak memory | 205960 kb |
Host | smart-1f69f189-1048-4d8d-b274-ac192ea5c447 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800828876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2800828876 |
Directory | /workspace/46.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/46.keymgr_cfg_regwen.1510581652 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 332460203 ps |
CPU time | 2.89 seconds |
Started | Jul 29 07:36:33 PM PDT 24 |
Finished | Jul 29 07:36:36 PM PDT 24 |
Peak memory | 222592 kb |
Host | smart-84a1a689-9415-4b90-8a0f-ef2df32c1428 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1510581652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1510581652 |
Directory | /workspace/46.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/46.keymgr_custom_cm.816531721 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 79542047 ps |
CPU time | 2.27 seconds |
Started | Jul 29 07:36:43 PM PDT 24 |
Finished | Jul 29 07:36:45 PM PDT 24 |
Peak memory | 222568 kb |
Host | smart-67da9e79-24df-43e0-93af-358aff0d9fed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=816531721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.816531721 |
Directory | /workspace/46.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/46.keymgr_direct_to_disabled.2311796574 |
Short name | T736 |
Test name | |
Test status | |
Simulation time | 193812009 ps |
CPU time | 2.06 seconds |
Started | Jul 29 07:36:42 PM PDT 24 |
Finished | Jul 29 07:36:44 PM PDT 24 |
Peak memory | 207116 kb |
Host | smart-e6fcebcc-7c0c-443c-812e-f84ca7eadb55 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2311796574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2311796574 |
Directory | /workspace/46.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3901187487 |
Short name | T853 |
Test name | |
Test status | |
Simulation time | 354042774 ps |
CPU time | 8.62 seconds |
Started | Jul 29 07:36:44 PM PDT 24 |
Finished | Jul 29 07:36:52 PM PDT 24 |
Peak memory | 214300 kb |
Host | smart-6a60b178-c3b4-428f-81b4-e347293d4d0b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3901187487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3901187487 |
Directory | /workspace/46.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/46.keymgr_kmac_rsp_err.3347314410 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 49638036 ps |
CPU time | 2.48 seconds |
Started | Jul 29 07:36:30 PM PDT 24 |
Finished | Jul 29 07:36:32 PM PDT 24 |
Peak memory | 211820 kb |
Host | smart-60b06d62-3c0f-45ad-be4f-8c615d79f6f2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3347314410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3347314410 |
Directory | /workspace/46.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/46.keymgr_lc_disable.1057865325 |
Short name | T805 |
Test name | |
Test status | |
Simulation time | 623434575 ps |
CPU time | 5.04 seconds |
Started | Jul 29 07:36:36 PM PDT 24 |
Finished | Jul 29 07:36:41 PM PDT 24 |
Peak memory | 214308 kb |
Host | smart-47414242-b72b-40c4-818a-fd75080873c1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1057865325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1057865325 |
Directory | /workspace/46.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/46.keymgr_random.255904064 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 128802797 ps |
CPU time | 5.14 seconds |
Started | Jul 29 07:36:41 PM PDT 24 |
Finished | Jul 29 07:36:46 PM PDT 24 |
Peak memory | 214248 kb |
Host | smart-65024ae1-c876-434e-a77b-34ec4151f50d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=255904064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.255904064 |
Directory | /workspace/46.keymgr_random/latest |
Test location | /workspace/coverage/default/46.keymgr_sideload.1281832746 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 1532824328 ps |
CPU time | 47.91 seconds |
Started | Jul 29 07:36:41 PM PDT 24 |
Finished | Jul 29 07:37:29 PM PDT 24 |
Peak memory | 209008 kb |
Host | smart-42e84f50-15a7-4cff-b71c-2347c5ff53ee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1281832746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1281832746 |
Directory | /workspace/46.keymgr_sideload/latest |
Test location | /workspace/coverage/default/46.keymgr_sideload_aes.2646393040 |
Short name | T671 |
Test name | |
Test status | |
Simulation time | 269825653 ps |
CPU time | 3.09 seconds |
Started | Jul 29 07:36:29 PM PDT 24 |
Finished | Jul 29 07:36:32 PM PDT 24 |
Peak memory | 206912 kb |
Host | smart-41ec4d23-c0fd-42a9-84f9-f24cef568499 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646393040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2646393040 |
Directory | /workspace/46.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/46.keymgr_sideload_kmac.982707534 |
Short name | T779 |
Test name | |
Test status | |
Simulation time | 79271903 ps |
CPU time | 3.43 seconds |
Started | Jul 29 07:36:30 PM PDT 24 |
Finished | Jul 29 07:36:33 PM PDT 24 |
Peak memory | 208500 kb |
Host | smart-7de8ab0a-f87d-4631-852e-a162722d559e |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982707534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.982707534 |
Directory | /workspace/46.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/46.keymgr_sideload_otbn.2252894670 |
Short name | T786 |
Test name | |
Test status | |
Simulation time | 159504970 ps |
CPU time | 4.05 seconds |
Started | Jul 29 07:36:45 PM PDT 24 |
Finished | Jul 29 07:36:50 PM PDT 24 |
Peak memory | 207812 kb |
Host | smart-2f1354d1-169d-4510-b60a-c9c4f03ba477 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252894670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2252894670 |
Directory | /workspace/46.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/46.keymgr_sideload_protect.4017600040 |
Short name | T897 |
Test name | |
Test status | |
Simulation time | 1033264548 ps |
CPU time | 6.29 seconds |
Started | Jul 29 07:36:50 PM PDT 24 |
Finished | Jul 29 07:36:56 PM PDT 24 |
Peak memory | 208560 kb |
Host | smart-f5292cb2-58e9-4d0e-a307-50f827b6ecc8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4017600040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.4017600040 |
Directory | /workspace/46.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/46.keymgr_smoke.4262997382 |
Short name | T746 |
Test name | |
Test status | |
Simulation time | 168899738 ps |
CPU time | 4.71 seconds |
Started | Jul 29 07:36:37 PM PDT 24 |
Finished | Jul 29 07:36:42 PM PDT 24 |
Peak memory | 206676 kb |
Host | smart-8f3782b0-b1e3-4704-a84e-6c0f7027f50c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4262997382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.4262997382 |
Directory | /workspace/46.keymgr_smoke/latest |
Test location | /workspace/coverage/default/46.keymgr_stress_all.451127673 |
Short name | T648 |
Test name | |
Test status | |
Simulation time | 734657688 ps |
CPU time | 29.23 seconds |
Started | Jul 29 07:36:35 PM PDT 24 |
Finished | Jul 29 07:37:05 PM PDT 24 |
Peak memory | 220108 kb |
Host | smart-8c39b5b8-88f4-4061-91bd-899a637519c4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451127673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.451127673 |
Directory | /workspace/46.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.792380908 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 163853811 ps |
CPU time | 6.39 seconds |
Started | Jul 29 07:36:44 PM PDT 24 |
Finished | Jul 29 07:36:50 PM PDT 24 |
Peak memory | 222492 kb |
Host | smart-2a4e7035-318c-44d6-8075-acba4bd5ab6b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792380908 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.792380908 |
Directory | /workspace/46.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/46.keymgr_sw_invalid_input.975382967 |
Short name | T653 |
Test name | |
Test status | |
Simulation time | 236606419 ps |
CPU time | 3.15 seconds |
Started | Jul 29 07:36:42 PM PDT 24 |
Finished | Jul 29 07:36:45 PM PDT 24 |
Peak memory | 208232 kb |
Host | smart-5b3745ac-7015-4882-b023-60f549ae7ea5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=975382967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.975382967 |
Directory | /workspace/46.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/46.keymgr_sync_async_fault_cross.795853646 |
Short name | T740 |
Test name | |
Test status | |
Simulation time | 78469360 ps |
CPU time | 2.46 seconds |
Started | Jul 29 07:36:43 PM PDT 24 |
Finished | Jul 29 07:36:46 PM PDT 24 |
Peak memory | 210464 kb |
Host | smart-b155feb0-8cde-40f5-bb3a-4a3fc1bb98ec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=795853646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.795853646 |
Directory | /workspace/46.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/47.keymgr_alert_test.2504074766 |
Short name | T660 |
Test name | |
Test status | |
Simulation time | 11160257 ps |
CPU time | 0.7 seconds |
Started | Jul 29 07:36:58 PM PDT 24 |
Finished | Jul 29 07:36:59 PM PDT 24 |
Peak memory | 205944 kb |
Host | smart-c5503efc-8f24-4510-9d29-2db54699e4dd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504074766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2504074766 |
Directory | /workspace/47.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/47.keymgr_cfg_regwen.3031488087 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 278231326 ps |
CPU time | 4.08 seconds |
Started | Jul 29 07:36:48 PM PDT 24 |
Finished | Jul 29 07:36:53 PM PDT 24 |
Peak memory | 214320 kb |
Host | smart-c8926def-03cc-490a-ba5e-b31d7edfaa47 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3031488087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3031488087 |
Directory | /workspace/47.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/47.keymgr_custom_cm.1330813288 |
Short name | T663 |
Test name | |
Test status | |
Simulation time | 565007782 ps |
CPU time | 4.17 seconds |
Started | Jul 29 07:36:50 PM PDT 24 |
Finished | Jul 29 07:36:55 PM PDT 24 |
Peak memory | 209844 kb |
Host | smart-bea74203-6e90-44e7-9f80-bd0cf3e258ee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1330813288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1330813288 |
Directory | /workspace/47.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/47.keymgr_direct_to_disabled.3722533114 |
Short name | T699 |
Test name | |
Test status | |
Simulation time | 97334317 ps |
CPU time | 2.45 seconds |
Started | Jul 29 07:36:47 PM PDT 24 |
Finished | Jul 29 07:36:50 PM PDT 24 |
Peak memory | 208072 kb |
Host | smart-f87f7f61-e845-4341-819b-a49f7db71558 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3722533114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3722533114 |
Directory | /workspace/47.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/47.keymgr_hwsw_invalid_input.4001766832 |
Short name | T808 |
Test name | |
Test status | |
Simulation time | 30286000 ps |
CPU time | 1.93 seconds |
Started | Jul 29 07:36:46 PM PDT 24 |
Finished | Jul 29 07:36:48 PM PDT 24 |
Peak memory | 214280 kb |
Host | smart-7273ced4-72fe-48dc-a149-e0e26043b8fa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4001766832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.4001766832 |
Directory | /workspace/47.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/47.keymgr_kmac_rsp_err.3223650843 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 99496350 ps |
CPU time | 2.09 seconds |
Started | Jul 29 07:36:48 PM PDT 24 |
Finished | Jul 29 07:36:50 PM PDT 24 |
Peak memory | 222384 kb |
Host | smart-a7021c6c-adcc-49ab-80b3-7f377c9263b0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3223650843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3223650843 |
Directory | /workspace/47.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/47.keymgr_lc_disable.2606609009 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 154758621 ps |
CPU time | 4.17 seconds |
Started | Jul 29 07:36:39 PM PDT 24 |
Finished | Jul 29 07:36:43 PM PDT 24 |
Peak memory | 222568 kb |
Host | smart-ff72fed6-9546-4863-8fd3-31a65f950ac7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2606609009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2606609009 |
Directory | /workspace/47.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/47.keymgr_random.614874747 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 1082042266 ps |
CPU time | 12.62 seconds |
Started | Jul 29 07:36:31 PM PDT 24 |
Finished | Jul 29 07:36:44 PM PDT 24 |
Peak memory | 209524 kb |
Host | smart-3e3cd568-ab02-48b4-b1f6-18d28213da76 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=614874747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.614874747 |
Directory | /workspace/47.keymgr_random/latest |
Test location | /workspace/coverage/default/47.keymgr_sideload.2237743813 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 63425238 ps |
CPU time | 3.1 seconds |
Started | Jul 29 07:36:48 PM PDT 24 |
Finished | Jul 29 07:36:59 PM PDT 24 |
Peak memory | 208720 kb |
Host | smart-803c9e4f-07f6-4140-bf9c-bf41789e5909 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2237743813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2237743813 |
Directory | /workspace/47.keymgr_sideload/latest |
Test location | /workspace/coverage/default/47.keymgr_sideload_aes.3715644751 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 139381992 ps |
CPU time | 2.5 seconds |
Started | Jul 29 07:36:45 PM PDT 24 |
Finished | Jul 29 07:36:47 PM PDT 24 |
Peak memory | 206936 kb |
Host | smart-36c76a9e-cb87-4d98-8aa1-c5a18ad791fd |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715644751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3715644751 |
Directory | /workspace/47.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/47.keymgr_sideload_kmac.1053790670 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 559677876 ps |
CPU time | 4.08 seconds |
Started | Jul 29 07:36:30 PM PDT 24 |
Finished | Jul 29 07:36:34 PM PDT 24 |
Peak memory | 208600 kb |
Host | smart-131e72f3-17b8-4885-a0dd-ab977613231e |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053790670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1053790670 |
Directory | /workspace/47.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/47.keymgr_sideload_otbn.255115022 |
Short name | T726 |
Test name | |
Test status | |
Simulation time | 32353329 ps |
CPU time | 2.1 seconds |
Started | Jul 29 07:36:46 PM PDT 24 |
Finished | Jul 29 07:36:49 PM PDT 24 |
Peak memory | 208588 kb |
Host | smart-00104689-343d-4718-a224-57c21002e7e6 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255115022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.255115022 |
Directory | /workspace/47.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/47.keymgr_sideload_protect.3499059624 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 1135451868 ps |
CPU time | 6.58 seconds |
Started | Jul 29 07:36:50 PM PDT 24 |
Finished | Jul 29 07:36:56 PM PDT 24 |
Peak memory | 214292 kb |
Host | smart-517bae18-00fb-40a6-ab63-9023ae739ae6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3499059624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3499059624 |
Directory | /workspace/47.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/47.keymgr_smoke.649718594 |
Short name | T843 |
Test name | |
Test status | |
Simulation time | 635886542 ps |
CPU time | 2.79 seconds |
Started | Jul 29 07:36:28 PM PDT 24 |
Finished | Jul 29 07:36:36 PM PDT 24 |
Peak memory | 208920 kb |
Host | smart-45338963-8ddd-4747-a729-c2cbaecf689a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=649718594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.649718594 |
Directory | /workspace/47.keymgr_smoke/latest |
Test location | /workspace/coverage/default/47.keymgr_stress_all.1183940912 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 2437787876 ps |
CPU time | 13.95 seconds |
Started | Jul 29 07:36:49 PM PDT 24 |
Finished | Jul 29 07:37:03 PM PDT 24 |
Peak memory | 219736 kb |
Host | smart-bbbc41fa-eb9c-4dc7-a54c-4e364e82795b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183940912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1183940912 |
Directory | /workspace/47.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.2763421600 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 86356185 ps |
CPU time | 5.85 seconds |
Started | Jul 29 07:37:02 PM PDT 24 |
Finished | Jul 29 07:37:09 PM PDT 24 |
Peak memory | 222536 kb |
Host | smart-dc0446db-4427-46b1-8a61-89c30c1a146e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763421600 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.2763421600 |
Directory | /workspace/47.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/47.keymgr_sw_invalid_input.976367505 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 1826635611 ps |
CPU time | 10.87 seconds |
Started | Jul 29 07:36:43 PM PDT 24 |
Finished | Jul 29 07:36:54 PM PDT 24 |
Peak memory | 208428 kb |
Host | smart-f55c4d87-cb3b-4022-85cb-cadf25af5152 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=976367505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.976367505 |
Directory | /workspace/47.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1427610775 |
Short name | T880 |
Test name | |
Test status | |
Simulation time | 41791304 ps |
CPU time | 1.52 seconds |
Started | Jul 29 07:36:44 PM PDT 24 |
Finished | Jul 29 07:36:46 PM PDT 24 |
Peak memory | 209628 kb |
Host | smart-41ecf0bc-20cd-4b5b-85d2-486dca02fa2e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1427610775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1427610775 |
Directory | /workspace/47.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/48.keymgr_alert_test.3936026488 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 9362076 ps |
CPU time | 0.72 seconds |
Started | Jul 29 07:36:53 PM PDT 24 |
Finished | Jul 29 07:36:54 PM PDT 24 |
Peak memory | 205952 kb |
Host | smart-3c557f2b-bef5-4345-856e-e6b9bedc8f41 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936026488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3936026488 |
Directory | /workspace/48.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/48.keymgr_cfg_regwen.703066395 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 142936142 ps |
CPU time | 2.42 seconds |
Started | Jul 29 07:36:58 PM PDT 24 |
Finished | Jul 29 07:37:01 PM PDT 24 |
Peak memory | 214344 kb |
Host | smart-bce782c2-e9b1-4bfa-a284-d3f875c5e22f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=703066395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.703066395 |
Directory | /workspace/48.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/48.keymgr_custom_cm.3550175275 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 295853094 ps |
CPU time | 4.05 seconds |
Started | Jul 29 07:36:57 PM PDT 24 |
Finished | Jul 29 07:37:01 PM PDT 24 |
Peak memory | 222688 kb |
Host | smart-2fe7b9b8-2090-496e-a6a4-82ef67d6584d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550175275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3550175275 |
Directory | /workspace/48.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/48.keymgr_direct_to_disabled.4028654199 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 64340809 ps |
CPU time | 1.79 seconds |
Started | Jul 29 07:36:45 PM PDT 24 |
Finished | Jul 29 07:36:47 PM PDT 24 |
Peak memory | 207428 kb |
Host | smart-5bec20f8-9bd0-47ff-a12c-f02acfc1cc34 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4028654199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.4028654199 |
Directory | /workspace/48.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/48.keymgr_hwsw_invalid_input.71708232 |
Short name | T678 |
Test name | |
Test status | |
Simulation time | 588211540 ps |
CPU time | 7.87 seconds |
Started | Jul 29 07:36:46 PM PDT 24 |
Finished | Jul 29 07:36:54 PM PDT 24 |
Peak memory | 214520 kb |
Host | smart-33d1abbd-1fc9-4d3a-98c8-137d896220f3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=71708232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.71708232 |
Directory | /workspace/48.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/48.keymgr_kmac_rsp_err.655990127 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 105855606 ps |
CPU time | 4.39 seconds |
Started | Jul 29 07:36:44 PM PDT 24 |
Finished | Jul 29 07:36:48 PM PDT 24 |
Peak memory | 214248 kb |
Host | smart-03d5c99e-07e9-4076-8c96-8554b1c7651c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=655990127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.655990127 |
Directory | /workspace/48.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/48.keymgr_lc_disable.271853087 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 173312512 ps |
CPU time | 3.09 seconds |
Started | Jul 29 07:36:49 PM PDT 24 |
Finished | Jul 29 07:36:53 PM PDT 24 |
Peak memory | 208492 kb |
Host | smart-981bca3d-d8ec-4087-9f66-83b13baa9888 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=271853087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.271853087 |
Directory | /workspace/48.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/48.keymgr_random.913968511 |
Short name | T867 |
Test name | |
Test status | |
Simulation time | 406997846 ps |
CPU time | 8.98 seconds |
Started | Jul 29 07:36:59 PM PDT 24 |
Finished | Jul 29 07:37:08 PM PDT 24 |
Peak memory | 217984 kb |
Host | smart-18957a68-e69b-4876-9b6c-e258d3de6ca2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=913968511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.913968511 |
Directory | /workspace/48.keymgr_random/latest |
Test location | /workspace/coverage/default/48.keymgr_sideload.366848021 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 77575344 ps |
CPU time | 3.91 seconds |
Started | Jul 29 07:36:52 PM PDT 24 |
Finished | Jul 29 07:36:56 PM PDT 24 |
Peak memory | 207516 kb |
Host | smart-9043e0e9-7a2b-46e2-b529-538d844e14e7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=366848021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.366848021 |
Directory | /workspace/48.keymgr_sideload/latest |
Test location | /workspace/coverage/default/48.keymgr_sideload_aes.600221285 |
Short name | T856 |
Test name | |
Test status | |
Simulation time | 106366852 ps |
CPU time | 4.31 seconds |
Started | Jul 29 07:36:48 PM PDT 24 |
Finished | Jul 29 07:36:53 PM PDT 24 |
Peak memory | 208532 kb |
Host | smart-698d72a6-179e-479e-a3c7-9558198c6f77 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600221285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.600221285 |
Directory | /workspace/48.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/48.keymgr_sideload_kmac.1407907731 |
Short name | T645 |
Test name | |
Test status | |
Simulation time | 26633336335 ps |
CPU time | 64.7 seconds |
Started | Jul 29 07:36:49 PM PDT 24 |
Finished | Jul 29 07:37:54 PM PDT 24 |
Peak memory | 208720 kb |
Host | smart-e072e6c9-ac3d-4f5b-a2ef-76e178363516 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407907731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1407907731 |
Directory | /workspace/48.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/48.keymgr_sideload_otbn.3472567329 |
Short name | T661 |
Test name | |
Test status | |
Simulation time | 874874900 ps |
CPU time | 3.42 seconds |
Started | Jul 29 07:36:59 PM PDT 24 |
Finished | Jul 29 07:37:03 PM PDT 24 |
Peak memory | 208728 kb |
Host | smart-51badeb5-83a8-42c4-ae40-6ca4f39b0f85 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472567329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3472567329 |
Directory | /workspace/48.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/48.keymgr_sideload_protect.1879246706 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 65092530 ps |
CPU time | 2.69 seconds |
Started | Jul 29 07:36:56 PM PDT 24 |
Finished | Jul 29 07:36:58 PM PDT 24 |
Peak memory | 210020 kb |
Host | smart-71aede51-7e0e-498e-8ac4-2518435672c9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1879246706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1879246706 |
Directory | /workspace/48.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/48.keymgr_smoke.378498050 |
Short name | T821 |
Test name | |
Test status | |
Simulation time | 280360866 ps |
CPU time | 4.54 seconds |
Started | Jul 29 07:36:42 PM PDT 24 |
Finished | Jul 29 07:36:47 PM PDT 24 |
Peak memory | 207952 kb |
Host | smart-cf38b0ee-8c18-4e6c-8046-9d438277991f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=378498050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.378498050 |
Directory | /workspace/48.keymgr_smoke/latest |
Test location | /workspace/coverage/default/48.keymgr_stress_all.2455208866 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 5017841928 ps |
CPU time | 30.46 seconds |
Started | Jul 29 07:36:59 PM PDT 24 |
Finished | Jul 29 07:37:30 PM PDT 24 |
Peak memory | 222556 kb |
Host | smart-4f82b7bf-0418-4a8f-8940-0b71e52ebe4f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455208866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2455208866 |
Directory | /workspace/48.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3305542870 |
Short name | T758 |
Test name | |
Test status | |
Simulation time | 284076401 ps |
CPU time | 17.83 seconds |
Started | Jul 29 07:36:55 PM PDT 24 |
Finished | Jul 29 07:37:13 PM PDT 24 |
Peak memory | 222488 kb |
Host | smart-8b33e40d-ef37-4ac8-b110-e00459e28396 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305542870 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3305542870 |
Directory | /workspace/48.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/48.keymgr_sw_invalid_input.568773602 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 146637959 ps |
CPU time | 2.83 seconds |
Started | Jul 29 07:36:45 PM PDT 24 |
Finished | Jul 29 07:36:48 PM PDT 24 |
Peak memory | 214376 kb |
Host | smart-9c7f37a3-33fd-4763-8f53-ff62d7cc60a8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=568773602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.568773602 |
Directory | /workspace/48.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/48.keymgr_sync_async_fault_cross.733309270 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 212204950 ps |
CPU time | 1.85 seconds |
Started | Jul 29 07:36:58 PM PDT 24 |
Finished | Jul 29 07:37:00 PM PDT 24 |
Peak memory | 209972 kb |
Host | smart-006cbacd-792c-4b9c-b208-9025c744b7db |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=733309270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.733309270 |
Directory | /workspace/48.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/49.keymgr_alert_test.2041914932 |
Short name | T731 |
Test name | |
Test status | |
Simulation time | 13679848 ps |
CPU time | 0.86 seconds |
Started | Jul 29 07:36:46 PM PDT 24 |
Finished | Jul 29 07:36:47 PM PDT 24 |
Peak memory | 205952 kb |
Host | smart-f3af6def-673c-42b8-8ecf-bdf08e23cd81 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041914932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2041914932 |
Directory | /workspace/49.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/49.keymgr_custom_cm.4261607700 |
Short name | T634 |
Test name | |
Test status | |
Simulation time | 93282919 ps |
CPU time | 3.93 seconds |
Started | Jul 29 07:36:43 PM PDT 24 |
Finished | Jul 29 07:36:47 PM PDT 24 |
Peak memory | 218232 kb |
Host | smart-df73536e-76a2-4295-a901-d44201f70539 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4261607700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.4261607700 |
Directory | /workspace/49.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/49.keymgr_direct_to_disabled.399686664 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 965824603 ps |
CPU time | 6.35 seconds |
Started | Jul 29 07:36:46 PM PDT 24 |
Finished | Jul 29 07:36:53 PM PDT 24 |
Peak memory | 214396 kb |
Host | smart-1fe295f5-6dc4-4270-a810-6767595de641 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=399686664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.399686664 |
Directory | /workspace/49.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3059580223 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 7849181505 ps |
CPU time | 16 seconds |
Started | Jul 29 07:36:54 PM PDT 24 |
Finished | Jul 29 07:37:10 PM PDT 24 |
Peak memory | 222492 kb |
Host | smart-646026b5-b016-49b2-9391-d71a753e214a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3059580223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3059580223 |
Directory | /workspace/49.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/49.keymgr_kmac_rsp_err.3158997961 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 1035570120 ps |
CPU time | 3.73 seconds |
Started | Jul 29 07:36:48 PM PDT 24 |
Finished | Jul 29 07:36:52 PM PDT 24 |
Peak memory | 214220 kb |
Host | smart-b918fb85-3f91-4625-a871-44e5d60e2525 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3158997961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3158997961 |
Directory | /workspace/49.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/49.keymgr_lc_disable.489796667 |
Short name | T809 |
Test name | |
Test status | |
Simulation time | 177729317 ps |
CPU time | 3.82 seconds |
Started | Jul 29 07:36:54 PM PDT 24 |
Finished | Jul 29 07:36:58 PM PDT 24 |
Peak memory | 220480 kb |
Host | smart-3146291a-214c-488f-a313-372fc1a52ebe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=489796667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.489796667 |
Directory | /workspace/49.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/49.keymgr_random.3841230259 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 69926312 ps |
CPU time | 3.7 seconds |
Started | Jul 29 07:36:45 PM PDT 24 |
Finished | Jul 29 07:36:49 PM PDT 24 |
Peak memory | 208092 kb |
Host | smart-bcc22c2b-dca9-4a88-bd83-7fb10d01d524 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3841230259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3841230259 |
Directory | /workspace/49.keymgr_random/latest |
Test location | /workspace/coverage/default/49.keymgr_sideload.2842560153 |
Short name | T662 |
Test name | |
Test status | |
Simulation time | 1426964091 ps |
CPU time | 20.65 seconds |
Started | Jul 29 07:36:52 PM PDT 24 |
Finished | Jul 29 07:37:13 PM PDT 24 |
Peak memory | 208588 kb |
Host | smart-1866781e-29a3-4fb9-8801-f1df6a447bec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2842560153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2842560153 |
Directory | /workspace/49.keymgr_sideload/latest |
Test location | /workspace/coverage/default/49.keymgr_sideload_aes.3705465854 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 667935749 ps |
CPU time | 2.93 seconds |
Started | Jul 29 07:36:57 PM PDT 24 |
Finished | Jul 29 07:37:00 PM PDT 24 |
Peak memory | 206804 kb |
Host | smart-8cdd679a-0730-4914-9911-1a6b42277a70 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705465854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3705465854 |
Directory | /workspace/49.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/49.keymgr_sideload_kmac.47906782 |
Short name | T870 |
Test name | |
Test status | |
Simulation time | 225188788 ps |
CPU time | 3.55 seconds |
Started | Jul 29 07:36:56 PM PDT 24 |
Finished | Jul 29 07:36:59 PM PDT 24 |
Peak memory | 206928 kb |
Host | smart-25070af0-18a6-4d95-b734-5fa99a34d9c2 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47906782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.47906782 |
Directory | /workspace/49.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/49.keymgr_sideload_otbn.1659385272 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 2964207422 ps |
CPU time | 14.6 seconds |
Started | Jul 29 07:36:49 PM PDT 24 |
Finished | Jul 29 07:37:06 PM PDT 24 |
Peak memory | 208964 kb |
Host | smart-50888f3f-01f7-4bcc-b48c-58bf863daf99 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659385272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1659385272 |
Directory | /workspace/49.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/49.keymgr_sideload_protect.1521183954 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 137697915 ps |
CPU time | 4.53 seconds |
Started | Jul 29 07:36:44 PM PDT 24 |
Finished | Jul 29 07:36:49 PM PDT 24 |
Peak memory | 208328 kb |
Host | smart-4e2fd632-f9b1-45fd-bab5-e25652ba720b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1521183954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1521183954 |
Directory | /workspace/49.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/49.keymgr_smoke.891651400 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 40691576 ps |
CPU time | 2.19 seconds |
Started | Jul 29 07:36:49 PM PDT 24 |
Finished | Jul 29 07:36:53 PM PDT 24 |
Peak memory | 208532 kb |
Host | smart-615497c5-ad45-4515-a785-7303bc17b2cc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=891651400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.891651400 |
Directory | /workspace/49.keymgr_smoke/latest |
Test location | /workspace/coverage/default/49.keymgr_stress_all.1647718388 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 1794039440 ps |
CPU time | 18.24 seconds |
Started | Jul 29 07:36:51 PM PDT 24 |
Finished | Jul 29 07:37:09 PM PDT 24 |
Peak memory | 215516 kb |
Host | smart-fec7588d-ff9f-471d-a1f2-a3c44018c392 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647718388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1647718388 |
Directory | /workspace/49.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/49.keymgr_sw_invalid_input.1709598781 |
Short name | T793 |
Test name | |
Test status | |
Simulation time | 362241638 ps |
CPU time | 5.77 seconds |
Started | Jul 29 07:36:47 PM PDT 24 |
Finished | Jul 29 07:36:53 PM PDT 24 |
Peak memory | 207480 kb |
Host | smart-1a37636a-ee46-45bb-8fce-769a3c592967 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1709598781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1709598781 |
Directory | /workspace/49.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2463030726 |
Short name | T890 |
Test name | |
Test status | |
Simulation time | 93599084 ps |
CPU time | 2.11 seconds |
Started | Jul 29 07:36:50 PM PDT 24 |
Finished | Jul 29 07:36:52 PM PDT 24 |
Peak memory | 210172 kb |
Host | smart-67a0fa78-3053-4291-9b9f-aa882d3f7ede |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2463030726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2463030726 |
Directory | /workspace/49.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/5.keymgr_alert_test.3244342792 |
Short name | T906 |
Test name | |
Test status | |
Simulation time | 35275753 ps |
CPU time | 0.73 seconds |
Started | Jul 29 07:34:45 PM PDT 24 |
Finished | Jul 29 07:34:46 PM PDT 24 |
Peak memory | 205904 kb |
Host | smart-5e1886a8-6212-47b7-a363-c373418cb828 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244342792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3244342792 |
Directory | /workspace/5.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/5.keymgr_direct_to_disabled.3202852033 |
Short name | T905 |
Test name | |
Test status | |
Simulation time | 50930492 ps |
CPU time | 2.54 seconds |
Started | Jul 29 07:34:48 PM PDT 24 |
Finished | Jul 29 07:34:51 PM PDT 24 |
Peak memory | 210392 kb |
Host | smart-736106a8-786d-4ced-b954-1afc02d61bd6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3202852033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3202852033 |
Directory | /workspace/5.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/5.keymgr_lc_disable.2865073403 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 273029304 ps |
CPU time | 3.97 seconds |
Started | Jul 29 07:34:49 PM PDT 24 |
Finished | Jul 29 07:34:53 PM PDT 24 |
Peak memory | 209692 kb |
Host | smart-01418fc4-a433-4443-a573-060461292e9c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2865073403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2865073403 |
Directory | /workspace/5.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/5.keymgr_random.2230514080 |
Short name | T863 |
Test name | |
Test status | |
Simulation time | 114368569 ps |
CPU time | 3.88 seconds |
Started | Jul 29 07:34:47 PM PDT 24 |
Finished | Jul 29 07:34:51 PM PDT 24 |
Peak memory | 208928 kb |
Host | smart-ddfc78fb-c4d3-48e3-9450-21eaf9e2b3e3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2230514080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2230514080 |
Directory | /workspace/5.keymgr_random/latest |
Test location | /workspace/coverage/default/5.keymgr_sideload.1609869779 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 40625094 ps |
CPU time | 2.74 seconds |
Started | Jul 29 07:34:41 PM PDT 24 |
Finished | Jul 29 07:34:44 PM PDT 24 |
Peak memory | 209016 kb |
Host | smart-1a99cb96-d6f8-42fd-90c6-6047b8fb846f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1609869779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1609869779 |
Directory | /workspace/5.keymgr_sideload/latest |
Test location | /workspace/coverage/default/5.keymgr_sideload_aes.165502701 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 120054364 ps |
CPU time | 3.17 seconds |
Started | Jul 29 07:34:39 PM PDT 24 |
Finished | Jul 29 07:34:42 PM PDT 24 |
Peak memory | 208092 kb |
Host | smart-2a9d6ce2-1fd3-47f2-a438-02c5fe2d0f03 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165502701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.165502701 |
Directory | /workspace/5.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/5.keymgr_sideload_kmac.2735936247 |
Short name | T676 |
Test name | |
Test status | |
Simulation time | 6045133361 ps |
CPU time | 44.6 seconds |
Started | Jul 29 07:34:48 PM PDT 24 |
Finished | Jul 29 07:35:33 PM PDT 24 |
Peak memory | 209328 kb |
Host | smart-e72f2def-e247-4e86-850f-96d54f40ca81 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735936247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2735936247 |
Directory | /workspace/5.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/5.keymgr_sideload_otbn.2620738881 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 380350898 ps |
CPU time | 2.99 seconds |
Started | Jul 29 07:34:49 PM PDT 24 |
Finished | Jul 29 07:34:52 PM PDT 24 |
Peak memory | 208664 kb |
Host | smart-11be8634-98a7-4a68-a500-06d9d2d7d8d3 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620738881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2620738881 |
Directory | /workspace/5.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/5.keymgr_sideload_protect.3430711546 |
Short name | T666 |
Test name | |
Test status | |
Simulation time | 100751316 ps |
CPU time | 2.89 seconds |
Started | Jul 29 07:34:49 PM PDT 24 |
Finished | Jul 29 07:34:52 PM PDT 24 |
Peak memory | 209180 kb |
Host | smart-b9cdcc87-133a-44ee-b617-bc8f8ce0310c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3430711546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3430711546 |
Directory | /workspace/5.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/5.keymgr_smoke.1117996328 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 421119566 ps |
CPU time | 2.44 seconds |
Started | Jul 29 07:34:48 PM PDT 24 |
Finished | Jul 29 07:34:51 PM PDT 24 |
Peak memory | 208576 kb |
Host | smart-2199b8cb-c343-4c9e-bc68-49670340b056 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1117996328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1117996328 |
Directory | /workspace/5.keymgr_smoke/latest |
Test location | /workspace/coverage/default/5.keymgr_sw_invalid_input.3417781989 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 5228952463 ps |
CPU time | 11.78 seconds |
Started | Jul 29 07:34:41 PM PDT 24 |
Finished | Jul 29 07:34:53 PM PDT 24 |
Peak memory | 208920 kb |
Host | smart-810dccb9-79a8-4e3d-b951-92d9d533ea61 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3417781989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3417781989 |
Directory | /workspace/5.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3423497490 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 373248842 ps |
CPU time | 2.83 seconds |
Started | Jul 29 07:34:46 PM PDT 24 |
Finished | Jul 29 07:34:49 PM PDT 24 |
Peak memory | 210200 kb |
Host | smart-91a20ff1-e72b-402f-b9f3-633a36586cb3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3423497490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3423497490 |
Directory | /workspace/5.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/6.keymgr_alert_test.1283164058 |
Short name | T849 |
Test name | |
Test status | |
Simulation time | 14164271 ps |
CPU time | 0.75 seconds |
Started | Jul 29 07:34:54 PM PDT 24 |
Finished | Jul 29 07:34:55 PM PDT 24 |
Peak memory | 206104 kb |
Host | smart-a41b6cc2-bedf-484e-981d-9a346737601e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283164058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1283164058 |
Directory | /workspace/6.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/6.keymgr_cfg_regwen.3423030035 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 182048287 ps |
CPU time | 3.63 seconds |
Started | Jul 29 07:34:47 PM PDT 24 |
Finished | Jul 29 07:34:51 PM PDT 24 |
Peak memory | 214400 kb |
Host | smart-bb0388c2-b369-4c0c-a390-5168a05b6abd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3423030035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3423030035 |
Directory | /workspace/6.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/6.keymgr_custom_cm.736754243 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 292270232 ps |
CPU time | 2.27 seconds |
Started | Jul 29 07:34:50 PM PDT 24 |
Finished | Jul 29 07:34:52 PM PDT 24 |
Peak memory | 214444 kb |
Host | smart-d2f70c47-9334-4919-b07b-06f677984835 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=736754243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.736754243 |
Directory | /workspace/6.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/6.keymgr_direct_to_disabled.811091250 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 66156385 ps |
CPU time | 1.99 seconds |
Started | Jul 29 07:34:47 PM PDT 24 |
Finished | Jul 29 07:34:49 PM PDT 24 |
Peak memory | 206972 kb |
Host | smart-ac5d6434-ee45-457a-8f46-82b1f8fcdcf2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=811091250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.811091250 |
Directory | /workspace/6.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/6.keymgr_hwsw_invalid_input.237743201 |
Short name | T725 |
Test name | |
Test status | |
Simulation time | 146446249 ps |
CPU time | 3.33 seconds |
Started | Jul 29 07:34:59 PM PDT 24 |
Finished | Jul 29 07:35:02 PM PDT 24 |
Peak memory | 220708 kb |
Host | smart-58b53ed8-8ad3-47ea-a689-7d6c17f579e9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=237743201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.237743201 |
Directory | /workspace/6.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/6.keymgr_kmac_rsp_err.2948786848 |
Short name | T750 |
Test name | |
Test status | |
Simulation time | 98803116 ps |
CPU time | 2.43 seconds |
Started | Jul 29 07:34:59 PM PDT 24 |
Finished | Jul 29 07:35:01 PM PDT 24 |
Peak memory | 216680 kb |
Host | smart-a86ea3ff-93a8-419d-9e76-509ec74c8dfe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2948786848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2948786848 |
Directory | /workspace/6.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/6.keymgr_lc_disable.1610101100 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 130150035 ps |
CPU time | 2.79 seconds |
Started | Jul 29 07:34:56 PM PDT 24 |
Finished | Jul 29 07:34:59 PM PDT 24 |
Peak memory | 216632 kb |
Host | smart-719eb857-e978-47b3-a82a-c117bab1fb27 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1610101100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1610101100 |
Directory | /workspace/6.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/6.keymgr_random.2121935802 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 56982588 ps |
CPU time | 2.32 seconds |
Started | Jul 29 07:34:56 PM PDT 24 |
Finished | Jul 29 07:34:59 PM PDT 24 |
Peak memory | 207364 kb |
Host | smart-62c58337-b487-433f-bbdb-e409d67cae21 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2121935802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2121935802 |
Directory | /workspace/6.keymgr_random/latest |
Test location | /workspace/coverage/default/6.keymgr_sideload.3135365631 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 267555360 ps |
CPU time | 3.37 seconds |
Started | Jul 29 07:34:45 PM PDT 24 |
Finished | Jul 29 07:34:49 PM PDT 24 |
Peak memory | 208552 kb |
Host | smart-5a130916-6c9e-4111-9845-9b0ffb159799 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3135365631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3135365631 |
Directory | /workspace/6.keymgr_sideload/latest |
Test location | /workspace/coverage/default/6.keymgr_sideload_aes.2422377384 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 166416662 ps |
CPU time | 5.58 seconds |
Started | Jul 29 07:34:54 PM PDT 24 |
Finished | Jul 29 07:35:00 PM PDT 24 |
Peak memory | 208604 kb |
Host | smart-9bc8034b-c2db-4d77-9cde-4b1ce726a995 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422377384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2422377384 |
Directory | /workspace/6.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/6.keymgr_sideload_kmac.882399690 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 270596498 ps |
CPU time | 4.4 seconds |
Started | Jul 29 07:34:54 PM PDT 24 |
Finished | Jul 29 07:34:59 PM PDT 24 |
Peak memory | 208788 kb |
Host | smart-dc7bc59c-b32f-408c-865b-9220f9299833 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882399690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.882399690 |
Directory | /workspace/6.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/6.keymgr_sideload_otbn.999471115 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 65345232 ps |
CPU time | 3.13 seconds |
Started | Jul 29 07:34:48 PM PDT 24 |
Finished | Jul 29 07:34:51 PM PDT 24 |
Peak memory | 208188 kb |
Host | smart-2ad9b991-f9a9-462c-ba8c-4198ee2377c6 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999471115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.999471115 |
Directory | /workspace/6.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/6.keymgr_sideload_protect.2969799022 |
Short name | T860 |
Test name | |
Test status | |
Simulation time | 158968320 ps |
CPU time | 3.94 seconds |
Started | Jul 29 07:34:46 PM PDT 24 |
Finished | Jul 29 07:34:50 PM PDT 24 |
Peak memory | 218480 kb |
Host | smart-e770ec4f-80e8-4bcf-8c9c-39da52a06c7a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2969799022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2969799022 |
Directory | /workspace/6.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/6.keymgr_smoke.2305076420 |
Short name | T721 |
Test name | |
Test status | |
Simulation time | 311584328 ps |
CPU time | 3.32 seconds |
Started | Jul 29 07:34:54 PM PDT 24 |
Finished | Jul 29 07:34:58 PM PDT 24 |
Peak memory | 207016 kb |
Host | smart-afc62036-d205-4f64-a996-b3c0f87451f1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2305076420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2305076420 |
Directory | /workspace/6.keymgr_smoke/latest |
Test location | /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.936330368 |
Short name | T902 |
Test name | |
Test status | |
Simulation time | 1187027264 ps |
CPU time | 13.93 seconds |
Started | Jul 29 07:34:54 PM PDT 24 |
Finished | Jul 29 07:35:08 PM PDT 24 |
Peak memory | 222420 kb |
Host | smart-628fff1f-44c7-429e-b421-28d92bee0c50 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936330368 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.936330368 |
Directory | /workspace/6.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/6.keymgr_sw_invalid_input.3448764630 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 109313296 ps |
CPU time | 4.41 seconds |
Started | Jul 29 07:34:59 PM PDT 24 |
Finished | Jul 29 07:35:03 PM PDT 24 |
Peak memory | 207716 kb |
Host | smart-2246af35-5251-4dbc-9063-6d8c8d2099be |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3448764630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3448764630 |
Directory | /workspace/6.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/6.keymgr_sync_async_fault_cross.309531892 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 489687609 ps |
CPU time | 2.29 seconds |
Started | Jul 29 07:34:59 PM PDT 24 |
Finished | Jul 29 07:35:01 PM PDT 24 |
Peak memory | 209408 kb |
Host | smart-fe14f348-b74e-460b-8abd-5bff6b3e2737 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=309531892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.309531892 |
Directory | /workspace/6.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/7.keymgr_alert_test.506639581 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 126691918 ps |
CPU time | 0.86 seconds |
Started | Jul 29 07:34:55 PM PDT 24 |
Finished | Jul 29 07:34:56 PM PDT 24 |
Peak memory | 205912 kb |
Host | smart-d094fa0d-4f59-4858-b71f-3ec32c3effb8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506639581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.506639581 |
Directory | /workspace/7.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/7.keymgr_custom_cm.1304308478 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 19159136 ps |
CPU time | 1.2 seconds |
Started | Jul 29 07:34:47 PM PDT 24 |
Finished | Jul 29 07:34:49 PM PDT 24 |
Peak memory | 207108 kb |
Host | smart-a3180f88-991c-42a8-a6db-d7af3293b92d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1304308478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1304308478 |
Directory | /workspace/7.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/7.keymgr_direct_to_disabled.2682495524 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 49602497 ps |
CPU time | 2.35 seconds |
Started | Jul 29 07:34:56 PM PDT 24 |
Finished | Jul 29 07:34:58 PM PDT 24 |
Peak memory | 209100 kb |
Host | smart-b8bee4ca-2375-45fc-91cb-cff7e48b0988 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2682495524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2682495524 |
Directory | /workspace/7.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/7.keymgr_hwsw_invalid_input.330600514 |
Short name | T787 |
Test name | |
Test status | |
Simulation time | 55604225 ps |
CPU time | 3.14 seconds |
Started | Jul 29 07:34:56 PM PDT 24 |
Finished | Jul 29 07:34:59 PM PDT 24 |
Peak memory | 214312 kb |
Host | smart-59677348-3b68-408b-ab11-ff86f2e1735c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=330600514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.330600514 |
Directory | /workspace/7.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/7.keymgr_kmac_rsp_err.2095592029 |
Short name | T723 |
Test name | |
Test status | |
Simulation time | 251880801 ps |
CPU time | 3.64 seconds |
Started | Jul 29 07:34:48 PM PDT 24 |
Finished | Jul 29 07:34:52 PM PDT 24 |
Peak memory | 221244 kb |
Host | smart-7a6ee700-bf8d-4a83-8ac7-23d3779197bb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2095592029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2095592029 |
Directory | /workspace/7.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/7.keymgr_lc_disable.2920742651 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 43917341 ps |
CPU time | 2.23 seconds |
Started | Jul 29 07:34:46 PM PDT 24 |
Finished | Jul 29 07:34:49 PM PDT 24 |
Peak memory | 222444 kb |
Host | smart-b0fb8746-2bfe-41b1-bbfc-d60fdfa4f783 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2920742651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2920742651 |
Directory | /workspace/7.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/7.keymgr_random.345650199 |
Short name | T686 |
Test name | |
Test status | |
Simulation time | 84466234 ps |
CPU time | 4.17 seconds |
Started | Jul 29 07:34:55 PM PDT 24 |
Finished | Jul 29 07:34:59 PM PDT 24 |
Peak memory | 214412 kb |
Host | smart-1a2ad185-4540-4d41-b084-dddda30c5ab1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=345650199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.345650199 |
Directory | /workspace/7.keymgr_random/latest |
Test location | /workspace/coverage/default/7.keymgr_sideload.248970064 |
Short name | T812 |
Test name | |
Test status | |
Simulation time | 580149902 ps |
CPU time | 4.18 seconds |
Started | Jul 29 07:34:47 PM PDT 24 |
Finished | Jul 29 07:34:51 PM PDT 24 |
Peak memory | 208900 kb |
Host | smart-a3100789-56c4-4126-b668-570e6aae098a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=248970064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.248970064 |
Directory | /workspace/7.keymgr_sideload/latest |
Test location | /workspace/coverage/default/7.keymgr_sideload_aes.2387723 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 63842073 ps |
CPU time | 2.71 seconds |
Started | Jul 29 07:34:55 PM PDT 24 |
Finished | Jul 29 07:34:58 PM PDT 24 |
Peak memory | 207032 kb |
Host | smart-5fe77aa3-7ab6-4799-8d06-5bd2b3e3c26e |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2387723 |
Directory | /workspace/7.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/7.keymgr_sideload_kmac.4150436219 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 100532668 ps |
CPU time | 2.41 seconds |
Started | Jul 29 07:34:50 PM PDT 24 |
Finished | Jul 29 07:34:52 PM PDT 24 |
Peak memory | 208440 kb |
Host | smart-79c6b084-f74e-45c3-b831-b2de2e6e2286 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150436219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.4150436219 |
Directory | /workspace/7.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/7.keymgr_sideload_protect.3738467166 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 421618643 ps |
CPU time | 2.66 seconds |
Started | Jul 29 07:34:56 PM PDT 24 |
Finished | Jul 29 07:34:59 PM PDT 24 |
Peak memory | 214312 kb |
Host | smart-d6d393b4-38a1-4fac-9ab1-c920e787a4f4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3738467166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3738467166 |
Directory | /workspace/7.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/7.keymgr_smoke.2002643793 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 1747015088 ps |
CPU time | 23.12 seconds |
Started | Jul 29 07:34:47 PM PDT 24 |
Finished | Jul 29 07:35:10 PM PDT 24 |
Peak memory | 208880 kb |
Host | smart-523edaba-f8e8-466e-ab3b-84a65ae32dc4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2002643793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2002643793 |
Directory | /workspace/7.keymgr_smoke/latest |
Test location | /workspace/coverage/default/7.keymgr_stress_all.2274224539 |
Short name | T900 |
Test name | |
Test status | |
Simulation time | 8690646942 ps |
CPU time | 26.72 seconds |
Started | Jul 29 07:34:56 PM PDT 24 |
Finished | Jul 29 07:35:23 PM PDT 24 |
Peak memory | 218792 kb |
Host | smart-bb8fb587-d11c-4eaa-af84-47ae335fbc8c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274224539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2274224539 |
Directory | /workspace/7.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.3903115613 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 1063904345 ps |
CPU time | 19.15 seconds |
Started | Jul 29 07:34:56 PM PDT 24 |
Finished | Jul 29 07:35:16 PM PDT 24 |
Peak memory | 222536 kb |
Host | smart-d2fafef3-8b43-4b6e-b669-1030c736bc2a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903115613 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.3903115613 |
Directory | /workspace/7.keymgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/7.keymgr_sw_invalid_input.3669694701 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 148655507 ps |
CPU time | 5.84 seconds |
Started | Jul 29 07:34:45 PM PDT 24 |
Finished | Jul 29 07:34:51 PM PDT 24 |
Peak memory | 214308 kb |
Host | smart-2df804f1-c956-4441-b6fe-10ec893cc193 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3669694701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3669694701 |
Directory | /workspace/7.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/8.keymgr_alert_test.2643937817 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 59513137 ps |
CPU time | 0.72 seconds |
Started | Jul 29 07:34:52 PM PDT 24 |
Finished | Jul 29 07:34:53 PM PDT 24 |
Peak memory | 205968 kb |
Host | smart-6f226a63-8f80-47c0-96c5-df96d9c7f9e0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643937817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2643937817 |
Directory | /workspace/8.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/8.keymgr_cfg_regwen.4283293735 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 57351586 ps |
CPU time | 2.69 seconds |
Started | Jul 29 07:34:55 PM PDT 24 |
Finished | Jul 29 07:34:58 PM PDT 24 |
Peak memory | 214740 kb |
Host | smart-54c4cbf9-d64b-4e8e-bbbe-b5ef47c02ae4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4283293735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.4283293735 |
Directory | /workspace/8.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/8.keymgr_custom_cm.3734937942 |
Short name | T862 |
Test name | |
Test status | |
Simulation time | 183649898 ps |
CPU time | 5.86 seconds |
Started | Jul 29 07:34:54 PM PDT 24 |
Finished | Jul 29 07:35:00 PM PDT 24 |
Peak memory | 210484 kb |
Host | smart-97af1180-dbb4-4394-ac21-6b021c4df746 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3734937942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3734937942 |
Directory | /workspace/8.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/8.keymgr_direct_to_disabled.2799196669 |
Short name | T635 |
Test name | |
Test status | |
Simulation time | 111205841 ps |
CPU time | 2.09 seconds |
Started | Jul 29 07:34:49 PM PDT 24 |
Finished | Jul 29 07:34:52 PM PDT 24 |
Peak memory | 207364 kb |
Host | smart-628cfb10-c108-4764-96f4-830af1737ae2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2799196669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2799196669 |
Directory | /workspace/8.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/8.keymgr_hwsw_invalid_input.3603736574 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 119207064 ps |
CPU time | 2.45 seconds |
Started | Jul 29 07:34:54 PM PDT 24 |
Finished | Jul 29 07:34:57 PM PDT 24 |
Peak memory | 214464 kb |
Host | smart-da8a19fb-c5d7-4fae-a29a-1fab6b25cb40 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3603736574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3603736574 |
Directory | /workspace/8.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/8.keymgr_kmac_rsp_err.1518168603 |
Short name | T714 |
Test name | |
Test status | |
Simulation time | 60223409 ps |
CPU time | 2.57 seconds |
Started | Jul 29 07:34:50 PM PDT 24 |
Finished | Jul 29 07:34:52 PM PDT 24 |
Peak memory | 214200 kb |
Host | smart-5059182a-abb9-43ee-b369-8d36b2736b99 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1518168603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1518168603 |
Directory | /workspace/8.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/8.keymgr_lc_disable.805971828 |
Short name | T753 |
Test name | |
Test status | |
Simulation time | 97217538 ps |
CPU time | 3.63 seconds |
Started | Jul 29 07:34:50 PM PDT 24 |
Finished | Jul 29 07:34:53 PM PDT 24 |
Peak memory | 209072 kb |
Host | smart-43b4e6fd-2f40-41a1-88e2-73e29c1d54c7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=805971828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.805971828 |
Directory | /workspace/8.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/8.keymgr_random.907829158 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 71754284 ps |
CPU time | 3.57 seconds |
Started | Jul 29 07:34:55 PM PDT 24 |
Finished | Jul 29 07:34:59 PM PDT 24 |
Peak memory | 207172 kb |
Host | smart-5f296aae-5b6c-4061-b8e9-e0266661858b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=907829158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.907829158 |
Directory | /workspace/8.keymgr_random/latest |
Test location | /workspace/coverage/default/8.keymgr_sideload.3036655284 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 4012069931 ps |
CPU time | 31.81 seconds |
Started | Jul 29 07:34:50 PM PDT 24 |
Finished | Jul 29 07:35:22 PM PDT 24 |
Peak memory | 208384 kb |
Host | smart-4b956661-e133-4287-b58d-f96110e7b077 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3036655284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3036655284 |
Directory | /workspace/8.keymgr_sideload/latest |
Test location | /workspace/coverage/default/8.keymgr_sideload_aes.1529406407 |
Short name | T698 |
Test name | |
Test status | |
Simulation time | 1115858520 ps |
CPU time | 3 seconds |
Started | Jul 29 07:34:56 PM PDT 24 |
Finished | Jul 29 07:34:59 PM PDT 24 |
Peak memory | 208564 kb |
Host | smart-927dc537-6cf5-402e-991b-713142020483 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529406407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1529406407 |
Directory | /workspace/8.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/8.keymgr_sideload_kmac.1142337504 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 609537207 ps |
CPU time | 4.32 seconds |
Started | Jul 29 07:34:46 PM PDT 24 |
Finished | Jul 29 07:34:51 PM PDT 24 |
Peak memory | 207584 kb |
Host | smart-e525f890-ecd0-43ec-8b92-f2805f93837f |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142337504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1142337504 |
Directory | /workspace/8.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/8.keymgr_sideload_otbn.3838407768 |
Short name | T684 |
Test name | |
Test status | |
Simulation time | 817395944 ps |
CPU time | 25.85 seconds |
Started | Jul 29 07:34:52 PM PDT 24 |
Finished | Jul 29 07:35:18 PM PDT 24 |
Peak memory | 208808 kb |
Host | smart-8e77ffd6-f793-42aa-b9a1-b39902905282 |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838407768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3838407768 |
Directory | /workspace/8.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/8.keymgr_sideload_protect.1737824276 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 202580625 ps |
CPU time | 2.01 seconds |
Started | Jul 29 07:34:47 PM PDT 24 |
Finished | Jul 29 07:34:50 PM PDT 24 |
Peak memory | 207484 kb |
Host | smart-d25d0168-fb8f-4b85-b91c-b07a94c926c0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1737824276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1737824276 |
Directory | /workspace/8.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/8.keymgr_smoke.3953017670 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 40814165 ps |
CPU time | 2 seconds |
Started | Jul 29 07:34:50 PM PDT 24 |
Finished | Jul 29 07:34:52 PM PDT 24 |
Peak memory | 208356 kb |
Host | smart-5170dd68-9c13-48fa-9a03-a660acf4a792 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3953017670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3953017670 |
Directory | /workspace/8.keymgr_smoke/latest |
Test location | /workspace/coverage/default/8.keymgr_stress_all.385121049 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 1106036007 ps |
CPU time | 24.92 seconds |
Started | Jul 29 07:34:47 PM PDT 24 |
Finished | Jul 29 07:35:12 PM PDT 24 |
Peak memory | 216188 kb |
Host | smart-cf5fd73b-13af-42e3-a60f-6f65cf399044 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385121049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.385121049 |
Directory | /workspace/8.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/8.keymgr_sw_invalid_input.1195274646 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 581341495 ps |
CPU time | 4.93 seconds |
Started | Jul 29 07:34:55 PM PDT 24 |
Finished | Jul 29 07:35:00 PM PDT 24 |
Peak memory | 218312 kb |
Host | smart-6e1efbe9-ecb9-4677-8ac5-4cb5b866d1ab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1195274646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1195274646 |
Directory | /workspace/8.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1460676335 |
Short name | T842 |
Test name | |
Test status | |
Simulation time | 183517946 ps |
CPU time | 3.55 seconds |
Started | Jul 29 07:34:57 PM PDT 24 |
Finished | Jul 29 07:35:00 PM PDT 24 |
Peak memory | 209988 kb |
Host | smart-576c9538-2112-47bb-9a0f-975cf1f8e708 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1460676335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1460676335 |
Directory | /workspace/8.keymgr_sync_async_fault_cross/latest |
Test location | /workspace/coverage/default/9.keymgr_alert_test.103137063 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 12136589 ps |
CPU time | 0.76 seconds |
Started | Jul 29 07:34:58 PM PDT 24 |
Finished | Jul 29 07:34:59 PM PDT 24 |
Peak memory | 205936 kb |
Host | smart-d83d5a50-044f-4251-8822-5b8831e7d45a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103137063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.103137063 |
Directory | /workspace/9.keymgr_alert_test/latest |
Test location | /workspace/coverage/default/9.keymgr_cfg_regwen.1801440885 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 3168305137 ps |
CPU time | 10.08 seconds |
Started | Jul 29 07:34:52 PM PDT 24 |
Finished | Jul 29 07:35:03 PM PDT 24 |
Peak memory | 214384 kb |
Host | smart-16b8bce9-ef63-4faa-92b4-14760c0e1c4c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1801440885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1801440885 |
Directory | /workspace/9.keymgr_cfg_regwen/latest |
Test location | /workspace/coverage/default/9.keymgr_custom_cm.2492591543 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 60613806 ps |
CPU time | 3.88 seconds |
Started | Jul 29 07:35:01 PM PDT 24 |
Finished | Jul 29 07:35:05 PM PDT 24 |
Peak memory | 217696 kb |
Host | smart-0de23fff-1429-48e7-8a53-e14f2b9290ab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2492591543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2492591543 |
Directory | /workspace/9.keymgr_custom_cm/latest |
Test location | /workspace/coverage/default/9.keymgr_direct_to_disabled.2799506271 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 377892453 ps |
CPU time | 3.15 seconds |
Started | Jul 29 07:34:53 PM PDT 24 |
Finished | Jul 29 07:34:56 PM PDT 24 |
Peak memory | 208048 kb |
Host | smart-d3d65da6-7dfc-436a-a4a4-e323a82d7ce1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2799506271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2799506271 |
Directory | /workspace/9.keymgr_direct_to_disabled/latest |
Test location | /workspace/coverage/default/9.keymgr_hwsw_invalid_input.491548226 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 66623092 ps |
CPU time | 2.43 seconds |
Started | Jul 29 07:35:00 PM PDT 24 |
Finished | Jul 29 07:35:02 PM PDT 24 |
Peak memory | 214140 kb |
Host | smart-74ccd72e-088f-43be-ba93-f441cde3c525 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=491548226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.491548226 |
Directory | /workspace/9.keymgr_hwsw_invalid_input/latest |
Test location | /workspace/coverage/default/9.keymgr_kmac_rsp_err.3954339384 |
Short name | T656 |
Test name | |
Test status | |
Simulation time | 85831436 ps |
CPU time | 3.92 seconds |
Started | Jul 29 07:35:03 PM PDT 24 |
Finished | Jul 29 07:35:07 PM PDT 24 |
Peak memory | 215316 kb |
Host | smart-01afa44c-9624-4cc4-891f-ebe75ce4c812 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3954339384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.3954339384 |
Directory | /workspace/9.keymgr_kmac_rsp_err/latest |
Test location | /workspace/coverage/default/9.keymgr_lc_disable.526453686 |
Short name | T788 |
Test name | |
Test status | |
Simulation time | 191419344 ps |
CPU time | 2.79 seconds |
Started | Jul 29 07:34:55 PM PDT 24 |
Finished | Jul 29 07:34:58 PM PDT 24 |
Peak memory | 214364 kb |
Host | smart-5adef5fc-5a81-4720-b449-a445940d657d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=526453686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.526453686 |
Directory | /workspace/9.keymgr_lc_disable/latest |
Test location | /workspace/coverage/default/9.keymgr_random.71027837 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 90239427 ps |
CPU time | 4.38 seconds |
Started | Jul 29 07:34:53 PM PDT 24 |
Finished | Jul 29 07:34:58 PM PDT 24 |
Peak memory | 218436 kb |
Host | smart-df250216-e1f9-4473-9bec-0f186cdbc707 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=71027837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.71027837 |
Directory | /workspace/9.keymgr_random/latest |
Test location | /workspace/coverage/default/9.keymgr_sideload.1348467694 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 128036672 ps |
CPU time | 2.41 seconds |
Started | Jul 29 07:34:56 PM PDT 24 |
Finished | Jul 29 07:34:58 PM PDT 24 |
Peak memory | 206824 kb |
Host | smart-88a4cfab-7ad5-4ebe-a5fc-3469f381a855 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1348467694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1348467694 |
Directory | /workspace/9.keymgr_sideload/latest |
Test location | /workspace/coverage/default/9.keymgr_sideload_aes.2825632699 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 130162961 ps |
CPU time | 5.2 seconds |
Started | Jul 29 07:35:01 PM PDT 24 |
Finished | Jul 29 07:35:06 PM PDT 24 |
Peak memory | 208428 kb |
Host | smart-cd2a2fee-e6bb-49ff-916a-bee9bf7d78e2 |
User | root |
Command | /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825632699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2825632699 |
Directory | /workspace/9.keymgr_sideload_aes/latest |
Test location | /workspace/coverage/default/9.keymgr_sideload_kmac.2856318798 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 746198132 ps |
CPU time | 23.25 seconds |
Started | Jul 29 07:34:57 PM PDT 24 |
Finished | Jul 29 07:35:20 PM PDT 24 |
Peak memory | 208712 kb |
Host | smart-86b5b2ce-f868-4c62-97d1-513d4d1d1b41 |
User | root |
Command | /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856318798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2856318798 |
Directory | /workspace/9.keymgr_sideload_kmac/latest |
Test location | /workspace/coverage/default/9.keymgr_sideload_otbn.800906922 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 36565258 ps |
CPU time | 1.98 seconds |
Started | Jul 29 07:34:56 PM PDT 24 |
Finished | Jul 29 07:34:59 PM PDT 24 |
Peak memory | 208764 kb |
Host | smart-346549c8-a5be-48e5-aa31-19965662a83a |
User | root |
Command | /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800906922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.800906922 |
Directory | /workspace/9.keymgr_sideload_otbn/latest |
Test location | /workspace/coverage/default/9.keymgr_sideload_protect.3553724527 |
Short name | T755 |
Test name | |
Test status | |
Simulation time | 235933816 ps |
CPU time | 3.82 seconds |
Started | Jul 29 07:34:58 PM PDT 24 |
Finished | Jul 29 07:35:02 PM PDT 24 |
Peak memory | 209092 kb |
Host | smart-d3087675-8a53-41e2-ba53-f0dd5ff4079c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3553724527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3553724527 |
Directory | /workspace/9.keymgr_sideload_protect/latest |
Test location | /workspace/coverage/default/9.keymgr_smoke.1439582687 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 839728278 ps |
CPU time | 17.31 seconds |
Started | Jul 29 07:34:47 PM PDT 24 |
Finished | Jul 29 07:35:04 PM PDT 24 |
Peak memory | 207908 kb |
Host | smart-7a6a2ca6-50d5-4ad9-9b4c-7a322d24894d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1439582687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1439582687 |
Directory | /workspace/9.keymgr_smoke/latest |
Test location | /workspace/coverage/default/9.keymgr_stress_all.1083402372 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 2902834662 ps |
CPU time | 38.06 seconds |
Started | Jul 29 07:35:00 PM PDT 24 |
Finished | Jul 29 07:35:38 PM PDT 24 |
Peak memory | 215640 kb |
Host | smart-368253a2-0bf8-4b92-85e4-f80708c0b149 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083402372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1083402372 |
Directory | /workspace/9.keymgr_stress_all/latest |
Test location | /workspace/coverage/default/9.keymgr_sw_invalid_input.1249016174 |
Short name | T624 |
Test name | |
Test status | |
Simulation time | 3507231239 ps |
CPU time | 20.84 seconds |
Started | Jul 29 07:35:06 PM PDT 24 |
Finished | Jul 29 07:35:27 PM PDT 24 |
Peak memory | 208940 kb |
Host | smart-ce0222e7-4a03-4b6d-ad8c-8e130ed10d6e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1249016174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1249016174 |
Directory | /workspace/9.keymgr_sw_invalid_input/latest |
Test location | /workspace/coverage/default/9.keymgr_sync_async_fault_cross.150231030 |
Short name | T865 |
Test name | |
Test status | |
Simulation time | 129109296 ps |
CPU time | 2.24 seconds |
Started | Jul 29 07:34:57 PM PDT 24 |
Finished | Jul 29 07:34:59 PM PDT 24 |
Peak memory | 210412 kb |
Host | smart-aac3b0f2-4e46-476a-a6b4-b732fb11ed21 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=150231030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.150231030 |
Directory | /workspace/9.keymgr_sync_async_fault_cross/latest |
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