Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11617

1

T1

6

T2

8

T3

15

auto[Attestation]

8031

1

T1

7

T2

1

T3

7

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2933	1			T2	3		T3	3		T4	4
auto[Aes]	3580	1			T1	13		T2	1		T3	6
auto[Kmac]	3440	1			T2	1		T3	4		T4	5
auto[Otbn]	3528	1			T3	4		T4	3		T12	4

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7930	1			T1	8		T2	8		T3	8
auto[OpGenId]	6167	1			T2	4		T3	5		T4	4
auto[OpGenSwOut]	6292	1			T2	2		T3	7		T4	7
auto[OpGenHwOut]	7189	1			T1	13		T2	3		T3	10
auto[OpDisable]	137	1			T16	2		T44	1		T45	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10989

1

T1

8

T2

8

T3

9

auto[OpDoneFail]

16726

1

T1

13

T2

9

T3

21

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6635	1			T1	6		T2	2		T3	10
auto[StInit]	3866	1			T1	2		T2	2		T3	3
auto[StCreatorRootKey]	3255	1			T1	2		T2	2		T3	2
auto[StOwnerIntKey]	2890	1			T1	2		T2	2		T3	3
auto[StOwnerKey]	2624	1			T1	2		T2	2		T3	2
auto[StDisabled]	8445	1			T1	7		T2	7		T3	10

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	356	1			T2	1		T3	1		T13	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	103	1			T16	1		T85	1		T130	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	72	1			T16	1		T141	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	73	1			T44	1		T43	2		T199	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	64	1			T13	1		T117	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	267	1			T4	1		T13	1		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	338	1			T3	1		T14	2		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	96	1			T16	1		T36	1		T37	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	75	1			T13	1		T16	1		T116	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	71	1			T13	1		T16	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	58	1			T12	1		T13	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	240	1			T4	1		T12	1		T16	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	327	1			T14	1		T16	3		T141	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	105	1			T3	1		T33	1		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	81	1			T16	1		T85	1		T130	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	61	1			T16	1		T85	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	55	1			T16	2		T143	1		T200	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	241	1			T2	1		T3	1		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	351	1			T13	1		T14	2		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	103	1			T16	2		T44	2		T62	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	88	1			T14	1		T16	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	85	1			T16	2		T33	1		T136	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	67	1			T12	1		T14	1		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	253	1			T13	1		T16	6		T85	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	70	1			T16	4		T44	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	116	1			T14	1		T138	1		T140	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	88	1			T14	1		T16	2		T116	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	77	1			T12	1		T16	3		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	62	1			T5	2		T201	1		T200	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	227	1			T4	1		T16	2		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	84	1			T16	3		T56	2		T77	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	119	1			T3	1		T4	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	96	1			T3	1		T12	1		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	75	1			T16	1		T33	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	75	1			T12	1		T16	4		T43	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	251	1			T4	1		T14	2		T16	5
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	88	1			T16	4		T44	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	120	1			T4	1		T16	2		T37	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	80	1			T16	1		T17	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	74	1			T16	4		T90	1		T43	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	72	1			T14	1		T44	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	234	1			T4	1		T12	1		T14	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	91	1			T16	3		T44	1		T5	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	103	1			T16	1		T85	1		T117	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	99	1			T130	1		T5	1		T100	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	72	1			T16	1		T141	2		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	56	1			T3	1		T135	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	233	1			T12	1		T16	4		T116	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	292	1			T3	1		T13	2		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	107	1			T2	1		T16	2		T5	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	74	1			T13	1		T16	1		T141	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	64	1			T85	1		T44	1		T130	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	71	1			T33	1		T44	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	205	1			T4	1		T16	1		T116	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	474	1			T1	5		T3	1		T13	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	115	1			T16	1		T143	1		T200	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	109	1			T13	1		T14	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	118	1			T13	1		T16	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	92	1			T16	2		T5	1		T143	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	309	1			T1	1		T2	1		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	438	1			T3	2		T14	1		T16	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	111	1			T12	1		T16	1		T117	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	112	1			T16	2		T37	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	100	1			T16	3		T139	1		T141	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	98	1			T131	1		T45	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	293	1			T17	1		T85	1		T117	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	462	1			T3	1		T16	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	121	1			T4	1		T14	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	116	1			T16	2		T44	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	101	1			T44	2		T130	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	87	1			T33	1		T44	1		T62	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	295	1			T3	2		T14	1		T16	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	56	1			T44	1		T43	1		T77	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	97	1			T14	1		T16	2		T116	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	75	1			T12	1		T117	1		T5	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	70	1			T2	1		T3	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	51	1			T44	1		T137	1		T100	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	196	1			T4	1		T12	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	65	1			T16	1		T44	1		T43	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	122	1			T1	1		T37	1		T130	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	105	1			T1	1		T13	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	105	1			T1	1		T3	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	83	1			T1	1		T16	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	305	1			T1	3		T3	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	60	1			T16	2		T44	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	123	1			T4	1		T85	1		T139	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	103	1			T13	1		T138	1		T139	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	87	1			T4	1		T12	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	92	1			T139	1		T44	2		T100	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	285	1			T4	1		T16	4		T85	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	49	1			T16	3		T44	2		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	111	1			T116	1		T44	2		T135	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	108	1			T16	1		T141	1		T44	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	102	1			T4	1		T13	1		T16	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	101	1			T12	1		T16	2		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	274	1			T4	1		T12	1		T16	3

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	189	1			T13	1		T16	1		T117	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	746	1			T2	1		T3	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	189	1			T12	1		T13	3		T16	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	689	1			T3	1		T4	1		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	181	1			T16	4		T85	2		T130	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	689	1			T2	1		T3	2		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	218	1			T12	1		T14	1		T16	5
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	729	1			T13	2		T14	3		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	203	1			T12	1		T14	1		T16	5
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	437	1			T4	1		T14	1		T16	6
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	235	1			T3	1		T12	2		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	465	1			T3	1		T4	2		T14	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	214	1			T14	1		T16	5		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	454	1			T4	2		T12	1		T14	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	203	1			T3	1		T141	1		T130	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	451	1			T12	1		T16	9		T85	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	187	1			T13	1		T16	1		T85	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	626	1			T2	1		T3	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	303	1			T13	2		T16	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	914	1			T1	6		T2	1		T3	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	291	1			T16	5		T139	1		T141	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	861	1			T3	2		T12	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	289	1			T16	1		T33	1		T44	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	893	1			T3	3		T4	1		T14	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	176	1			T2	1		T3	1		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	369	1			T4	1		T12	1		T14	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	274	1			T1	3		T3	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	511	1			T1	4		T3	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	266	1			T12	1		T13	2		T16	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	484	1			T4	3		T16	6		T85	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	288	1			T4	1		T12	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	457	1			T4	1		T12	1		T16	7