Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33980

1

T1

25

T2

20

T3

33

auto[1]

259

1

T85

6

T116

3

T117

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33986	1			T1	25		T2	20		T3	33
auto[134217728:268435455]	6	1			T117	1		T279	1		T398	1
auto[268435456:402653183]	6	1			T117	1		T138	1		T248	1
auto[402653184:536870911]	7	1			T136	1		T276	1		T303	1
auto[536870912:671088639]	10	1			T136	1		T324	1		T243	1
auto[671088640:805306367]	6	1			T117	1		T399	3		T400	1
auto[805306368:939524095]	13	1			T138	1		T136	1		T251	1
auto[939524096:1073741823]	6	1			T138	1		T251	1		T369	1
auto[1073741824:1207959551]	5	1			T85	1		T243	2		T291	1
auto[1207959552:1342177279]	5	1			T235	1		T276	1		T401	1
auto[1342177280:1476395007]	11	1			T143	1		T250	1		T251	1
auto[1476395008:1610612735]	8	1			T85	1		T136	1		T243	1
auto[1610612736:1744830463]	7	1			T324	1		T243	1		T369	1
auto[1744830464:1879048191]	8	1			T85	1		T250	1		T399	1
auto[1879048192:2013265919]	6	1			T402	1		T398	2		T403	1
auto[2013265920:2147483647]	11	1			T117	1		T250	1		T251	1
auto[2147483648:2281701375]	10	1			T276	1		T251	1		T243	1
auto[2281701376:2415919103]	10	1			T85	1		T276	1		T402	2
auto[2415919104:2550136831]	7	1			T117	1		T251	1		T402	1
auto[2550136832:2684354559]	8	1			T243	1		T387	1		T303	1
auto[2684354560:2818572287]	8	1			T250	1		T276	1		T243	1
auto[2818572288:2952790015]	7	1			T251	1		T248	1		T291	1
auto[2952790016:3087007743]	9	1			T138	1		T136	1		T232	1
auto[3087007744:3221225471]	10	1			T138	1		T276	1		T251	2
auto[3221225472:3355443199]	8	1			T138	1		T251	1		T387	1
auto[3355443200:3489660927]	6	1			T243	1		T387	1		T303	1
auto[3489660928:3623878655]	11	1			T117	1		T136	1		T310	1
auto[3623878656:3758096383]	5	1			T235	1		T291	1		T404	1
auto[3758096384:3892314111]	10	1			T85	1		T138	1		T136	1
auto[3892314112:4026531839]	8	1			T116	1		T117	1		T405	1
auto[4026531840:4160749567]	13	1			T116	2		T276	1		T243	1
auto[4160749568:4294967295]	8	1			T251	1		T398	1		T303	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33980	1			T1	25		T2	20		T3	33
auto[0:134217727]	auto[1]	6	1			T85	1		T190	1		T248	1
auto[134217728:268435455]	auto[1]	6	1			T117	1		T279	1		T398	1
auto[268435456:402653183]	auto[1]	6	1			T117	1		T138	1		T248	1
auto[402653184:536870911]	auto[1]	7	1			T136	1		T276	1		T303	1
auto[536870912:671088639]	auto[1]	10	1			T136	1		T324	1		T243	1
auto[671088640:805306367]	auto[1]	6	1			T117	1		T399	3		T400	1
auto[805306368:939524095]	auto[1]	13	1			T138	1		T136	1		T251	1
auto[939524096:1073741823]	auto[1]	6	1			T138	1		T251	1		T369	1
auto[1073741824:1207959551]	auto[1]	5	1			T85	1		T243	2		T291	1
auto[1207959552:1342177279]	auto[1]	5	1			T235	1		T276	1		T401	1
auto[1342177280:1476395007]	auto[1]	11	1			T143	1		T250	1		T251	1
auto[1476395008:1610612735]	auto[1]	8	1			T85	1		T136	1		T243	1
auto[1610612736:1744830463]	auto[1]	7	1			T324	1		T243	1		T369	1
auto[1744830464:1879048191]	auto[1]	8	1			T85	1		T250	1		T399	1
auto[1879048192:2013265919]	auto[1]	6	1			T402	1		T398	2		T403	1
auto[2013265920:2147483647]	auto[1]	11	1			T117	1		T250	1		T251	1
auto[2147483648:2281701375]	auto[1]	10	1			T276	1		T251	1		T243	1
auto[2281701376:2415919103]	auto[1]	10	1			T85	1		T276	1		T402	2
auto[2415919104:2550136831]	auto[1]	7	1			T117	1		T251	1		T402	1
auto[2550136832:2684354559]	auto[1]	8	1			T243	1		T387	1		T303	1
auto[2684354560:2818572287]	auto[1]	8	1			T250	1		T276	1		T243	1
auto[2818572288:2952790015]	auto[1]	7	1			T251	1		T248	1		T291	1
auto[2952790016:3087007743]	auto[1]	9	1			T138	1		T136	1		T232	1
auto[3087007744:3221225471]	auto[1]	10	1			T138	1		T276	1		T251	2
auto[3221225472:3355443199]	auto[1]	8	1			T138	1		T251	1		T387	1
auto[3355443200:3489660927]	auto[1]	6	1			T243	1		T387	1		T303	1
auto[3489660928:3623878655]	auto[1]	11	1			T117	1		T136	1		T310	1
auto[3623878656:3758096383]	auto[1]	5	1			T235	1		T291	1		T404	1
auto[3758096384:3892314111]	auto[1]	10	1			T85	1		T138	1		T136	1
auto[3892314112:4026531839]	auto[1]	8	1			T116	1		T117	1		T405	1
auto[4026531840:4160749567]	auto[1]	13	1			T116	2		T276	1		T243	1
auto[4160749568:4294967295]	auto[1]	8	1			T251	1		T398	1		T303	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1709

1

T3

2

T4

4

T12

2

auto[1]

1766

1

T3

5

T4

2

T13

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	119	1			T16	1		T138	1		T44	1
auto[134217728:268435455]	101	1			T3	1		T13	1		T138	1
auto[268435456:402653183]	90	1			T17	1		T85	1		T46	1
auto[402653184:536870911]	106	1			T14	1		T85	1		T44	1
auto[536870912:671088639]	99	1			T16	1		T116	1		T34	1
auto[671088640:805306367]	123	1			T13	1		T16	4		T17	2
auto[805306368:939524095]	104	1			T3	1		T14	1		T16	2
auto[939524096:1073741823]	139	1			T14	1		T16	2		T85	1
auto[1073741824:1207959551]	88	1			T16	2		T117	1		T141	1
auto[1207959552:1342177279]	107	1			T4	1		T16	2		T44	1
auto[1342177280:1476395007]	114	1			T3	1		T4	1		T16	2
auto[1476395008:1610612735]	103	1			T16	1		T141	1		T5	1
auto[1610612736:1744830463]	114	1			T14	1		T16	3		T132	1
auto[1744830464:1879048191]	108	1			T3	1		T4	1		T16	1
auto[1879048192:2013265919]	115	1			T3	2		T13	1		T14	1
auto[2013265920:2147483647]	121	1			T13	1		T16	2		T17	1
auto[2147483648:2281701375]	107	1			T14	1		T16	4		T44	2
auto[2281701376:2415919103]	129	1			T13	1		T16	1		T116	2
auto[2415919104:2550136831]	101	1			T14	1		T16	1		T85	1
auto[2550136832:2684354559]	101	1			T12	1		T16	2		T17	2
auto[2684354560:2818572287]	118	1			T4	1		T16	3		T116	1
auto[2818572288:2952790015]	119	1			T3	1		T4	1		T16	1
auto[2952790016:3087007743]	95	1			T12	1		T16	1		T44	2
auto[3087007744:3221225471]	105	1			T14	1		T116	1		T35	1
auto[3221225472:3355443199]	93	1			T17	1		T117	1		T44	3
auto[3355443200:3489660927]	97	1			T16	2		T116	1		T138	1
auto[3489660928:3623878655]	134	1			T13	1		T14	1		T16	1
auto[3623878656:3758096383]	116	1			T16	2		T44	1		T5	2
auto[3758096384:3892314111]	94	1			T16	3		T44	1		T136	2
auto[3892314112:4026531839]	105	1			T4	1		T13	1		T16	2
auto[4026531840:4160749567]	113	1			T16	1		T35	1		T44	1
auto[4160749568:4294967295]	97	1			T16	2		T141	1		T34	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	57	1			T138	1		T44	1		T5	1
auto[0:134217727]	auto[1]	62	1			T16	1		T22	1		T199	1
auto[134217728:268435455]	auto[0]	40	1			T3	1		T13	1		T44	1
auto[134217728:268435455]	auto[1]	61	1			T138	1		T50	1		T110	1
auto[268435456:402653183]	auto[0]	42	1			T17	1		T85	1		T46	1
auto[268435456:402653183]	auto[1]	48	1			T5	2		T201	1		T143	1
auto[402653184:536870911]	auto[0]	47	1			T14	1		T19	1		T43	1
auto[402653184:536870911]	auto[1]	59	1			T85	1		T44	1		T42	1
auto[536870912:671088639]	auto[0]	50	1			T16	1		T235	1		T81	1
auto[536870912:671088639]	auto[1]	49	1			T116	1		T34	1		T18	1
auto[671088640:805306367]	auto[0]	68	1			T13	1		T16	1		T17	1
auto[671088640:805306367]	auto[1]	55	1			T16	3		T17	1		T5	1
auto[805306368:939524095]	auto[0]	58	1			T14	1		T16	1		T5	1
auto[805306368:939524095]	auto[1]	46	1			T3	1		T16	1		T20	1
auto[939524096:1073741823]	auto[0]	68	1			T85	1		T18	1		T100	1
auto[939524096:1073741823]	auto[1]	71	1			T14	1		T16	2		T44	1
auto[1073741824:1207959551]	auto[0]	41	1			T16	1		T44	1		T43	1
auto[1073741824:1207959551]	auto[1]	47	1			T16	1		T117	1		T141	1
auto[1207959552:1342177279]	auto[0]	53	1			T5	3		T47	1		T50	1
auto[1207959552:1342177279]	auto[1]	54	1			T4	1		T16	2		T44	1
auto[1342177280:1476395007]	auto[0]	58	1			T4	1		T16	1		T35	1
auto[1342177280:1476395007]	auto[1]	56	1			T3	1		T16	1		T85	1
auto[1476395008:1610612735]	auto[0]	53	1			T16	1		T5	1		T19	1
auto[1476395008:1610612735]	auto[1]	50	1			T141	1		T47	1		T200	1
auto[1610612736:1744830463]	auto[0]	60	1			T16	1		T132	1		T5	1
auto[1610612736:1744830463]	auto[1]	54	1			T14	1		T16	2		T5	2
auto[1744830464:1879048191]	auto[0]	51	1			T4	1		T16	1		T46	2
auto[1744830464:1879048191]	auto[1]	57	1			T3	1		T17	1		T44	1
auto[1879048192:2013265919]	auto[0]	54	1			T3	1		T14	1		T16	1
auto[1879048192:2013265919]	auto[1]	61	1			T3	1		T13	1		T37	1
auto[2013265920:2147483647]	auto[0]	61	1			T16	2		T17	1		T50	1
auto[2013265920:2147483647]	auto[1]	60	1			T13	1		T44	1		T86	1
auto[2147483648:2281701375]	auto[0]	53	1			T14	1		T16	2		T44	1
auto[2147483648:2281701375]	auto[1]	54	1			T16	2		T44	1		T5	2
auto[2281701376:2415919103]	auto[0]	61	1			T44	1		T45	1		T5	1
auto[2281701376:2415919103]	auto[1]	68	1			T13	1		T16	1		T116	2
auto[2415919104:2550136831]	auto[0]	57	1			T14	1		T16	1		T130	1
auto[2415919104:2550136831]	auto[1]	44	1			T85	1		T44	1		T45	1
auto[2550136832:2684354559]	auto[0]	63	1			T12	1		T16	2		T17	1
auto[2550136832:2684354559]	auto[1]	38	1			T17	1		T44	1		T130	1
auto[2684354560:2818572287]	auto[0]	63	1			T16	2		T116	1		T141	1
auto[2684354560:2818572287]	auto[1]	55	1			T4	1		T16	1		T44	1
auto[2818572288:2952790015]	auto[0]	49	1			T4	1		T5	1		T62	1
auto[2818572288:2952790015]	auto[1]	70	1			T3	1		T16	1		T138	1
auto[2952790016:3087007743]	auto[0]	47	1			T12	1		T44	2		T46	1
auto[2952790016:3087007743]	auto[1]	48	1			T16	1		T46	1		T5	1
auto[3087007744:3221225471]	auto[0]	47	1			T35	1		T5	1		T43	1
auto[3087007744:3221225471]	auto[1]	58	1			T14	1		T116	1		T5	1
auto[3221225472:3355443199]	auto[0]	43	1			T44	2		T47	1		T66	1
auto[3221225472:3355443199]	auto[1]	50	1			T17	1		T117	1		T44	1
auto[3355443200:3489660927]	auto[0]	44	1			T16	1		T5	1		T352	1
auto[3355443200:3489660927]	auto[1]	53	1			T16	1		T116	1		T138	1
auto[3489660928:3623878655]	auto[0]	67	1			T13	1		T14	1		T44	2
auto[3489660928:3623878655]	auto[1]	67	1			T16	1		T5	2		T62	1
auto[3623878656:3758096383]	auto[0]	61	1			T16	1		T352	1		T240	1
auto[3623878656:3758096383]	auto[1]	55	1			T16	1		T44	1		T5	2
auto[3758096384:3892314111]	auto[0]	37	1			T16	1		T56	1		T53	1
auto[3758096384:3892314111]	auto[1]	57	1			T16	2		T44	1		T136	2
auto[3892314112:4026531839]	auto[0]	58	1			T4	1		T46	1		T5	2
auto[3892314112:4026531839]	auto[1]	47	1			T13	1		T16	2		T44	1
auto[4026531840:4160749567]	auto[0]	53	1			T35	1		T200	1		T77	1
auto[4026531840:4160749567]	auto[1]	60	1			T16	1		T44	1		T5	3
auto[4160749568:4294967295]	auto[0]	45	1			T16	2		T141	1		T5	1
auto[4160749568:4294967295]	auto[1]	52	1			T34	1		T44	1		T5	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1681

1

T3

3

T4

3

T12

1

auto[1]

1794

1

T3

4

T4

3

T12

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T16	3		T85	1		T44	1
auto[134217728:268435455]	105	1			T12	1		T13	1		T117	1
auto[268435456:402653183]	98	1			T4	1		T13	1		T14	1
auto[402653184:536870911]	103	1			T14	1		T16	5		T17	2
auto[536870912:671088639]	124	1			T16	3		T5	1		T49	1
auto[671088640:805306367]	141	1			T13	1		T14	1		T16	2
auto[805306368:939524095]	105	1			T14	1		T16	1		T116	1
auto[939524096:1073741823]	100	1			T3	1		T14	1		T85	1
auto[1073741824:1207959551]	121	1			T3	1		T4	1		T16	1
auto[1207959552:1342177279]	118	1			T3	1		T16	1		T85	1
auto[1342177280:1476395007]	97	1			T3	1		T14	1		T16	3
auto[1476395008:1610612735]	99	1			T16	4		T17	1		T141	1
auto[1610612736:1744830463]	86	1			T138	1		T44	4		T42	2
auto[1744830464:1879048191]	101	1			T16	1		T116	1		T141	1
auto[1879048192:2013265919]	102	1			T4	1		T16	2		T138	1
auto[2013265920:2147483647]	120	1			T4	1		T14	1		T16	1
auto[2147483648:2281701375]	109	1			T16	4		T44	2		T45	1
auto[2281701376:2415919103]	131	1			T16	2		T17	1		T85	1
auto[2415919104:2550136831]	98	1			T4	1		T16	2		T35	1
auto[2550136832:2684354559]	95	1			T34	1		T44	2		T200	1
auto[2684354560:2818572287]	95	1			T12	1		T16	2		T116	1
auto[2818572288:2952790015]	94	1			T4	1		T85	1		T5	1
auto[2952790016:3087007743]	112	1			T16	1		T17	1		T44	2
auto[3087007744:3221225471]	123	1			T16	2		T116	1		T117	1
auto[3221225472:3355443199]	112	1			T3	1		T16	1		T35	1
auto[3355443200:3489660927]	112	1			T13	3		T16	1		T34	1
auto[3489660928:3623878655]	117	1			T3	1		T16	1		T44	2
auto[3623878656:3758096383]	109	1			T16	1		T85	1		T46	1
auto[3758096384:3892314111]	114	1			T13	1		T14	1		T16	2
auto[3892314112:4026531839]	104	1			T14	1		T16	2		T138	1
auto[4026531840:4160749567]	128	1			T16	1		T17	1		T141	1
auto[4160749568:4294967295]	97	1			T3	1		T16	1		T130	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	44	1			T16	2		T44	1		T42	1
auto[0:134217727]	auto[1]	61	1			T16	1		T85	1		T45	1
auto[134217728:268435455]	auto[0]	47	1			T12	1		T44	1		T46	1
auto[134217728:268435455]	auto[1]	58	1			T13	1		T117	1		T44	1
auto[268435456:402653183]	auto[0]	53	1			T4	1		T14	1		T277	1
auto[268435456:402653183]	auto[1]	45	1			T13	1		T5	2		T143	1
auto[402653184:536870911]	auto[0]	51	1			T14	1		T16	1		T46	1
auto[402653184:536870911]	auto[1]	52	1			T16	4		T17	2		T116	1
auto[536870912:671088639]	auto[0]	60	1			T16	1		T5	1		T49	1
auto[536870912:671088639]	auto[1]	64	1			T16	2		T143	1		T63	1
auto[671088640:805306367]	auto[0]	73	1			T13	1		T14	1		T16	1
auto[671088640:805306367]	auto[1]	68	1			T16	1		T17	1		T5	2
auto[805306368:939524095]	auto[0]	44	1			T44	1		T45	1		T5	2
auto[805306368:939524095]	auto[1]	61	1			T14	1		T16	1		T116	1
auto[939524096:1073741823]	auto[0]	47	1			T14	1		T85	1		T35	1
auto[939524096:1073741823]	auto[1]	53	1			T3	1		T5	1		T43	1
auto[1073741824:1207959551]	auto[0]	55	1			T16	1		T85	1		T44	1
auto[1073741824:1207959551]	auto[1]	66	1			T3	1		T4	1		T44	3
auto[1207959552:1342177279]	auto[0]	56	1			T16	1		T130	1		T5	1
auto[1207959552:1342177279]	auto[1]	62	1			T3	1		T85	1		T5	2
auto[1342177280:1476395007]	auto[0]	55	1			T3	1		T14	1		T16	2
auto[1342177280:1476395007]	auto[1]	42	1			T16	1		T44	1		T5	1
auto[1476395008:1610612735]	auto[0]	49	1			T16	2		T17	1		T44	1
auto[1476395008:1610612735]	auto[1]	50	1			T16	2		T141	1		T44	1
auto[1610612736:1744830463]	auto[0]	40	1			T47	1		T250	1		T213	1
auto[1610612736:1744830463]	auto[1]	46	1			T138	1		T44	4		T42	2
auto[1744830464:1879048191]	auto[0]	45	1			T141	1		T5	1		T43	1
auto[1744830464:1879048191]	auto[1]	56	1			T16	1		T116	1		T44	1
auto[1879048192:2013265919]	auto[0]	52	1			T43	1		T240	1		T56	1
auto[1879048192:2013265919]	auto[1]	50	1			T4	1		T16	2		T138	1
auto[2013265920:2147483647]	auto[0]	59	1			T4	1		T14	1		T5	1
auto[2013265920:2147483647]	auto[1]	61	1			T16	1		T138	1		T5	2
auto[2147483648:2281701375]	auto[0]	60	1			T16	2		T100	1		T84	1
auto[2147483648:2281701375]	auto[1]	49	1			T16	2		T44	2		T45	1
auto[2281701376:2415919103]	auto[0]	54	1			T16	1		T44	1		T132	1
auto[2281701376:2415919103]	auto[1]	77	1			T16	1		T17	1		T85	1
auto[2415919104:2550136831]	auto[0]	59	1			T16	1		T35	1		T5	2
auto[2415919104:2550136831]	auto[1]	39	1			T4	1		T16	1		T44	1
auto[2550136832:2684354559]	auto[0]	45	1			T44	2		T250	1		T81	1
auto[2550136832:2684354559]	auto[1]	50	1			T34	1		T200	1		T62	1
auto[2684354560:2818572287]	auto[0]	30	1			T16	1		T47	1		T62	1
auto[2684354560:2818572287]	auto[1]	65	1			T12	1		T16	1		T116	1
auto[2818572288:2952790015]	auto[0]	53	1			T4	1		T66	1		T127	1
auto[2818572288:2952790015]	auto[1]	41	1			T85	1		T5	1		T100	1
auto[2952790016:3087007743]	auto[0]	52	1			T16	1		T17	1		T130	1
auto[2952790016:3087007743]	auto[1]	60	1			T44	2		T5	2		T43	2
auto[3087007744:3221225471]	auto[0]	60	1			T16	2		T5	2		T47	1
auto[3087007744:3221225471]	auto[1]	63	1			T116	1		T117	1		T44	1
auto[3221225472:3355443199]	auto[0]	60	1			T3	1		T35	1		T44	1
auto[3221225472:3355443199]	auto[1]	52	1			T16	1		T352	1		T43	1
auto[3355443200:3489660927]	auto[0]	50	1			T13	1		T44	1		T45	1
auto[3355443200:3489660927]	auto[1]	62	1			T13	2		T16	1		T34	1
auto[3489660928:3623878655]	auto[0]	57	1			T5	2		T352	1		T19	1
auto[3489660928:3623878655]	auto[1]	60	1			T3	1		T16	1		T44	2
auto[3623878656:3758096383]	auto[0]	52	1			T85	1		T46	1		T136	1
auto[3623878656:3758096383]	auto[1]	57	1			T16	1		T132	1		T5	2
auto[3758096384:3892314111]	auto[0]	59	1			T13	1		T16	1		T18	1
auto[3758096384:3892314111]	auto[1]	55	1			T14	1		T16	1		T116	1
auto[3892314112:4026531839]	auto[0]	48	1			T14	1		T16	1		T22	1
auto[3892314112:4026531839]	auto[1]	56	1			T16	1		T138	1		T55	2
auto[4026531840:4160749567]	auto[0]	70	1			T16	1		T17	1		T141	1
auto[4026531840:4160749567]	auto[1]	58	1			T22	1		T110	1		T56	1
auto[4160749568:4294967295]	auto[0]	42	1			T3	1		T5	2		T47	1
auto[4160749568:4294967295]	auto[1]	55	1			T16	1		T130	1		T63	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1719

1

T3

3

T4

3

T13

2

auto[1]

1757

1

T3

4

T4

3

T12

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	112	1			T13	1		T16	2		T85	1
auto[134217728:268435455]	92	1			T16	1		T85	1		T44	1
auto[268435456:402653183]	109	1			T3	2		T14	1		T16	2
auto[402653184:536870911]	114	1			T3	1		T16	4		T132	1
auto[536870912:671088639]	121	1			T14	2		T16	1		T44	1
auto[671088640:805306367]	91	1			T16	3		T117	1		T138	1
auto[805306368:939524095]	99	1			T14	1		T16	1		T116	1
auto[939524096:1073741823]	103	1			T14	1		T16	1		T17	1
auto[1073741824:1207959551]	115	1			T13	1		T16	1		T138	1
auto[1207959552:1342177279]	109	1			T14	1		T16	2		T44	1
auto[1342177280:1476395007]	113	1			T16	5		T17	1		T117	1
auto[1476395008:1610612735]	100	1			T4	1		T16	2		T116	1
auto[1610612736:1744830463]	117	1			T13	1		T16	1		T44	1
auto[1744830464:1879048191]	105	1			T4	1		T14	1		T16	2
auto[1879048192:2013265919]	100	1			T141	1		T34	1		T44	1
auto[2013265920:2147483647]	111	1			T16	2		T141	1		T18	1
auto[2147483648:2281701375]	123	1			T4	2		T16	2		T141	1
auto[2281701376:2415919103]	111	1			T3	2		T14	1		T138	1
auto[2415919104:2550136831]	117	1			T13	1		T14	1		T16	2
auto[2550136832:2684354559]	118	1			T16	3		T17	1		T37	1
auto[2684354560:2818572287]	110	1			T4	1		T16	1		T17	1
auto[2818572288:2952790015]	105	1			T12	1		T16	2		T44	1
auto[2952790016:3087007743]	93	1			T3	1		T13	1		T85	1
auto[3087007744:3221225471]	117	1			T4	1		T12	1		T16	1
auto[3221225472:3355443199]	133	1			T13	1		T16	1		T85	1
auto[3355443200:3489660927]	125	1			T16	1		T17	1		T116	1
auto[3489660928:3623878655]	91	1			T16	2		T17	1		T44	1
auto[3623878656:3758096383]	88	1			T13	1		T16	1		T116	1
auto[3758096384:3892314111]	106	1			T16	1		T35	1		T45	1
auto[3892314112:4026531839]	105	1			T16	1		T17	1		T44	2
auto[4026531840:4160749567]	121	1			T16	1		T44	2		T5	2
auto[4160749568:4294967295]	102	1			T3	1		T16	1		T141	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	55	1			T85	1		T43	1		T235	1
auto[0:134217727]	auto[1]	57	1			T13	1		T16	2		T34	1
auto[134217728:268435455]	auto[0]	45	1			T16	1		T44	1		T5	1
auto[134217728:268435455]	auto[1]	47	1			T85	1		T43	1		T110	1
auto[268435456:402653183]	auto[0]	59	1			T3	1		T14	1		T16	1
auto[268435456:402653183]	auto[1]	50	1			T3	1		T16	1		T44	1
auto[402653184:536870911]	auto[0]	56	1			T16	3		T62	1		T43	1
auto[402653184:536870911]	auto[1]	58	1			T3	1		T16	1		T132	1
auto[536870912:671088639]	auto[0]	61	1			T14	1		T46	2		T5	2
auto[536870912:671088639]	auto[1]	60	1			T14	1		T16	1		T44	1
auto[671088640:805306367]	auto[0]	46	1			T16	1		T56	1		T79	1
auto[671088640:805306367]	auto[1]	45	1			T16	2		T117	1		T138	1
auto[805306368:939524095]	auto[0]	51	1			T16	1		T44	2		T5	1
auto[805306368:939524095]	auto[1]	48	1			T14	1		T116	1		T136	1
auto[939524096:1073741823]	auto[0]	51	1			T14	1		T138	1		T46	2
auto[939524096:1073741823]	auto[1]	52	1			T16	1		T17	1		T44	1
auto[1073741824:1207959551]	auto[0]	59	1			T13	1		T16	1		T51	1
auto[1073741824:1207959551]	auto[1]	56	1			T138	1		T34	1		T44	1
auto[1207959552:1342177279]	auto[0]	57	1			T16	2		T45	1		T250	1
auto[1207959552:1342177279]	auto[1]	52	1			T14	1		T44	1		T56	1
auto[1342177280:1476395007]	auto[0]	50	1			T16	1		T44	1		T5	1
auto[1342177280:1476395007]	auto[1]	63	1			T16	4		T17	1		T117	1
auto[1476395008:1610612735]	auto[0]	45	1			T5	1		T136	1		T62	1
auto[1476395008:1610612735]	auto[1]	55	1			T4	1		T16	2		T116	1
auto[1610612736:1744830463]	auto[0]	53	1			T44	1		T5	2		T43	1
auto[1610612736:1744830463]	auto[1]	64	1			T13	1		T16	1		T42	1
auto[1744830464:1879048191]	auto[0]	56	1			T4	1		T14	1		T46	1
auto[1744830464:1879048191]	auto[1]	49	1			T16	2		T44	1		T43	1
auto[1879048192:2013265919]	auto[0]	49	1			T141	1		T44	1		T5	1
auto[1879048192:2013265919]	auto[1]	51	1			T34	1		T42	1		T5	2
auto[2013265920:2147483647]	auto[0]	48	1			T16	1		T141	1		T19	1
auto[2013265920:2147483647]	auto[1]	63	1			T16	1		T18	1		T200	1
auto[2147483648:2281701375]	auto[0]	60	1			T4	1		T16	1		T44	1
auto[2147483648:2281701375]	auto[1]	63	1			T4	1		T16	1		T141	1
auto[2281701376:2415919103]	auto[0]	55	1			T14	1		T138	1		T5	1
auto[2281701376:2415919103]	auto[1]	56	1			T3	2		T44	1		T45	1
auto[2415919104:2550136831]	auto[0]	58	1			T13	1		T14	1		T16	2
auto[2415919104:2550136831]	auto[1]	59	1			T85	2		T44	1		T136	1
auto[2550136832:2684354559]	auto[0]	55	1			T16	3		T352	1		T79	1
auto[2550136832:2684354559]	auto[1]	63	1			T17	1		T37	1		T44	2
auto[2684354560:2818572287]	auto[0]	46	1			T16	1		T18	1		T56	1
auto[2684354560:2818572287]	auto[1]	64	1			T4	1		T17	1		T44	2
auto[2818572288:2952790015]	auto[0]	55	1			T5	1		T50	2		T56	3
auto[2818572288:2952790015]	auto[1]	50	1			T12	1		T16	2		T44	1
auto[2952790016:3087007743]	auto[0]	47	1			T3	1		T44	2		T49	1
auto[2952790016:3087007743]	auto[1]	46	1			T13	1		T85	1		T116	1
auto[3087007744:3221225471]	auto[0]	47	1			T4	1		T46	1		T352	1
auto[3087007744:3221225471]	auto[1]	70	1			T12	1		T16	1		T138	1
auto[3221225472:3355443199]	auto[0]	68	1			T16	1		T85	1		T5	2
auto[3221225472:3355443199]	auto[1]	65	1			T13	1		T116	1		T5	1
auto[3355443200:3489660927]	auto[0]	61	1			T16	1		T17	1		T130	1
auto[3355443200:3489660927]	auto[1]	64	1			T116	1		T5	3		T100	1
auto[3489660928:3623878655]	auto[0]	56	1			T44	1		T5	1		T49	2
auto[3489660928:3623878655]	auto[1]	35	1			T16	2		T17	1		T43	2
auto[3623878656:3758096383]	auto[0]	41	1			T16	1		T116	1		T5	1
auto[3623878656:3758096383]	auto[1]	47	1			T13	1		T5	2		T22	1
auto[3758096384:3892314111]	auto[0]	52	1			T35	1		T45	1		T5	1
auto[3758096384:3892314111]	auto[1]	54	1			T16	1		T90	1		T200	1
auto[3892314112:4026531839]	auto[0]	55	1			T17	1		T44	2		T130	1
auto[3892314112:4026531839]	auto[1]	50	1			T16	1		T130	1		T5	1
auto[4026531840:4160749567]	auto[0]	63	1			T47	1		T352	1		T277	1
auto[4026531840:4160749567]	auto[1]	58	1			T16	1		T44	2		T5	2
auto[4160749568:4294967295]	auto[0]	59	1			T3	1		T16	1		T141	1
auto[4160749568:4294967295]	auto[1]	43	1			T42	1		T5	1		T66	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1691

1

T3

2

T4

5

T12

2

auto[1]

1784

1

T3

5

T4

1

T13

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	117	1			T116	1		T117	1		T44	1
auto[134217728:268435455]	109	1			T16	1		T85	1		T141	1
auto[268435456:402653183]	108	1			T4	1		T16	4		T18	1
auto[402653184:536870911]	111	1			T3	1		T44	2		T45	1
auto[536870912:671088639]	106	1			T16	1		T138	1		T44	2
auto[671088640:805306367]	100	1			T16	3		T85	1		T5	2
auto[805306368:939524095]	113	1			T3	1		T4	1		T16	1
auto[939524096:1073741823]	122	1			T14	1		T16	1		T85	1
auto[1073741824:1207959551]	119	1			T12	1		T16	3		T17	1
auto[1207959552:1342177279]	101	1			T4	1		T13	2		T16	1
auto[1342177280:1476395007]	95	1			T4	1		T13	1		T16	2
auto[1476395008:1610612735]	102	1			T16	1		T44	1		T100	1
auto[1610612736:1744830463]	116	1			T3	1		T16	2		T17	1
auto[1744830464:1879048191]	123	1			T3	1		T4	1		T16	2
auto[1879048192:2013265919]	106	1			T16	1		T35	1		T44	1
auto[2013265920:2147483647]	114	1			T3	1		T13	1		T16	2
auto[2147483648:2281701375]	93	1			T3	1		T13	1		T14	1
auto[2281701376:2415919103]	103	1			T14	1		T16	1		T17	1
auto[2415919104:2550136831]	118	1			T16	2		T44	1		T45	1
auto[2550136832:2684354559]	112	1			T14	2		T16	2		T85	1
auto[2684354560:2818572287]	112	1			T14	2		T16	3		T5	2
auto[2818572288:2952790015]	109	1			T12	1		T14	1		T16	2
auto[2952790016:3087007743]	100	1			T16	1		T44	2		T5	1
auto[3087007744:3221225471]	119	1			T13	2		T17	2		T85	1
auto[3221225472:3355443199]	105	1			T44	2		T45	1		T5	2
auto[3355443200:3489660927]	98	1			T16	2		T42	1		T45	1
auto[3489660928:3623878655]	119	1			T16	1		T35	1		T44	2
auto[3623878656:3758096383]	101	1			T14	1		T16	2		T138	1
auto[3758096384:3892314111]	109	1			T3	1		T16	1		T44	2
auto[3892314112:4026531839]	104	1			T4	1		T16	1		T44	1
auto[4026531840:4160749567]	120	1			T16	5		T44	1		T5	2
auto[4160749568:4294967295]	91	1			T16	1		T141	1		T44	1