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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4748 1 T4 10 T12 2 T13 12
auto[1] 2202 1 T3 14 T4 2 T12 2



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 214 1 T16 4 T116 2 T138 2
auto[134217728:268435455] 238 1 T17 2 T141 2 T34 2
auto[268435456:402653183] 218 1 T16 8 T44 4 T5 2
auto[402653184:536870911] 240 1 T13 4 T16 6 T85 2
auto[536870912:671088639] 218 1 T16 2 T141 2 T35 2
auto[671088640:805306367] 212 1 T14 2 T16 2 T44 2
auto[805306368:939524095] 214 1 T138 2 T141 2 T44 2
auto[939524096:1073741823] 214 1 T16 2 T44 6 T5 6
auto[1073741824:1207959551] 222 1 T16 6 T138 2 T44 2
auto[1207959552:1342177279] 220 1 T3 2 T13 2 T16 2
auto[1342177280:1476395007] 178 1 T5 4 T136 2 T62 2
auto[1476395008:1610612735] 192 1 T13 2 T14 4 T16 4
auto[1610612736:1744830463] 198 1 T3 2 T12 2 T14 2
auto[1744830464:1879048191] 208 1 T5 4 T100 2 T19 2
auto[1879048192:2013265919] 212 1 T12 2 T16 6 T85 2
auto[2013265920:2147483647] 234 1 T16 2 T85 2 T138 2
auto[2147483648:2281701375] 232 1 T3 2 T16 6 T17 2
auto[2281701376:2415919103] 202 1 T13 2 T35 2 T46 2
auto[2415919104:2550136831] 202 1 T3 2 T14 2 T16 2
auto[2550136832:2684354559] 232 1 T16 2 T85 2 T5 6
auto[2684354560:2818572287] 212 1 T16 4 T17 2 T116 4
auto[2818572288:2952790015] 208 1 T4 4 T14 2 T16 2
auto[2952790016:3087007743] 198 1 T3 2 T14 2 T16 2
auto[3087007744:3221225471] 212 1 T16 4 T17 2 T116 2
auto[3221225472:3355443199] 260 1 T14 2 T16 6 T5 6
auto[3355443200:3489660927] 248 1 T13 2 T14 2 T16 2
auto[3489660928:3623878655] 222 1 T3 4 T4 2 T16 2
auto[3623878656:3758096383] 206 1 T16 2 T17 2 T132 2
auto[3758096384:3892314111] 218 1 T16 2 T44 2 T42 2
auto[3892314112:4026531839] 216 1 T16 4 T44 2 T45 2
auto[4026531840:4160749567] 230 1 T4 2 T13 2 T16 4
auto[4160749568:4294967295] 220 1 T4 4 T16 6 T5 4



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 158 1 T16 4 T116 2 T44 2
auto[0:134217727] auto[1] 56 1 T138 2 T49 2 T274 2
auto[134217728:268435455] auto[0] 180 1 T17 2 T141 2 T45 2
auto[134217728:268435455] auto[1] 58 1 T34 2 T44 4 T352 2
auto[268435456:402653183] auto[0] 146 1 T16 6 T44 4 T5 2
auto[268435456:402653183] auto[1] 72 1 T16 2 T136 2 T43 4
auto[402653184:536870911] auto[0] 162 1 T13 2 T16 6 T85 2
auto[402653184:536870911] auto[1] 78 1 T13 2 T116 2 T201 2
auto[536870912:671088639] auto[0] 150 1 T16 2 T34 2 T44 4
auto[536870912:671088639] auto[1] 68 1 T141 2 T35 2 T90 2
auto[671088640:805306367] auto[0] 116 1 T14 2 T16 2 T5 2
auto[671088640:805306367] auto[1] 96 1 T44 2 T130 2 T5 4
auto[805306368:939524095] auto[0] 136 1 T138 2 T44 2 T42 2
auto[805306368:939524095] auto[1] 78 1 T141 2 T130 2 T5 2
auto[939524096:1073741823] auto[0] 156 1 T16 2 T44 4 T5 6
auto[939524096:1073741823] auto[1] 58 1 T44 2 T136 2 T51 2
auto[1073741824:1207959551] auto[0] 156 1 T16 6 T138 2 T46 2
auto[1073741824:1207959551] auto[1] 66 1 T44 2 T46 4 T199 2
auto[1207959552:1342177279] auto[0] 156 1 T13 2 T16 2 T44 4
auto[1207959552:1342177279] auto[1] 64 1 T3 2 T44 2 T100 2
auto[1342177280:1476395007] auto[0] 100 1 T5 4 T136 2 T43 2
auto[1342177280:1476395007] auto[1] 78 1 T62 2 T23 2 T213 2
auto[1476395008:1610612735] auto[0] 138 1 T13 2 T14 4 T16 2
auto[1476395008:1610612735] auto[1] 54 1 T16 2 T46 2 T56 4
auto[1610612736:1744830463] auto[0] 128 1 T12 2 T14 2 T16 6
auto[1610612736:1744830463] auto[1] 70 1 T3 2 T44 2 T143 2
auto[1744830464:1879048191] auto[0] 134 1 T5 4 T100 2 T19 2
auto[1744830464:1879048191] auto[1] 74 1 T66 2 T78 2 T54 4
auto[1879048192:2013265919] auto[0] 156 1 T16 4 T85 2 T44 2
auto[1879048192:2013265919] auto[1] 56 1 T12 2 T16 2 T117 2
auto[2013265920:2147483647] auto[0] 156 1 T16 2 T85 2 T5 2
auto[2013265920:2147483647] auto[1] 78 1 T138 2 T47 2 T56 2
auto[2147483648:2281701375] auto[0] 162 1 T16 4 T17 2 T141 2
auto[2147483648:2281701375] auto[1] 70 1 T3 2 T16 2 T44 2
auto[2281701376:2415919103] auto[0] 152 1 T13 2 T352 2 T50 2
auto[2281701376:2415919103] auto[1] 50 1 T35 2 T46 2 T62 2
auto[2415919104:2550136831] auto[0] 136 1 T47 2 T43 4 T250 4
auto[2415919104:2550136831] auto[1] 66 1 T3 2 T14 2 T16 2
auto[2550136832:2684354559] auto[0] 162 1 T16 2 T85 2 T5 6
auto[2550136832:2684354559] auto[1] 70 1 T43 2 T56 2 T127 2
auto[2684354560:2818572287] auto[0] 138 1 T16 2 T17 2 T116 4
auto[2684354560:2818572287] auto[1] 74 1 T16 2 T44 2 T5 2
auto[2818572288:2952790015] auto[0] 154 1 T4 4 T14 2 T16 2
auto[2818572288:2952790015] auto[1] 54 1 T18 2 T143 4 T43 2
auto[2952790016:3087007743] auto[0] 124 1 T14 2 T17 2 T44 2
auto[2952790016:3087007743] auto[1] 74 1 T3 2 T16 2 T5 2
auto[3087007744:3221225471] auto[0] 154 1 T16 2 T17 2 T132 2
auto[3087007744:3221225471] auto[1] 58 1 T16 2 T116 2 T5 2
auto[3221225472:3355443199] auto[0] 176 1 T14 2 T16 6 T5 4
auto[3221225472:3355443199] auto[1] 84 1 T5 2 T51 2 T77 2
auto[3355443200:3489660927] auto[0] 176 1 T13 2 T14 2 T16 2
auto[3355443200:3489660927] auto[1] 72 1 T35 2 T18 2 T20 2
auto[3489660928:3623878655] auto[0] 156 1 T85 2 T47 4 T51 2
auto[3489660928:3623878655] auto[1] 66 1 T3 4 T4 2 T16 2
auto[3623878656:3758096383] auto[0] 138 1 T16 2 T17 2 T5 2
auto[3623878656:3758096383] auto[1] 68 1 T132 2 T327 2 T56 4
auto[3758096384:3892314111] auto[0] 140 1 T42 2 T45 2 T5 2
auto[3758096384:3892314111] auto[1] 78 1 T16 2 T44 2 T49 2
auto[3892314112:4026531839] auto[0] 152 1 T16 4 T5 2 T49 2
auto[3892314112:4026531839] auto[1] 64 1 T44 2 T45 2 T304 2
auto[4026531840:4160749567] auto[0] 168 1 T4 2 T13 2 T16 4
auto[4026531840:4160749567] auto[1] 62 1 T117 2 T44 2 T5 2
auto[4160749568:4294967295] auto[0] 132 1 T4 4 T16 4 T5 4
auto[4160749568:4294967295] auto[1] 88 1 T16 2 T43 2 T38 2

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