Unified Coverage Report :: Group Instance : salt_4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3052

1

T3

7

T4

6

T12

2

auto[1]

221

1

T85

3

T116

2

T117

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	97	1			T16	1		T34	1		T44	2
auto[134217728:268435455]	116	1			T4	1		T16	1		T17	1
auto[268435456:402653183]	99	1			T16	1		T17	1		T85	1
auto[402653184:536870911]	99	1			T35	1		T44	1		T5	1
auto[536870912:671088639]	111	1			T13	1		T16	2		T116	1
auto[671088640:805306367]	97	1			T3	1		T14	1		T17	1
auto[805306368:939524095]	91	1			T116	1		T37	1		T44	1
auto[939524096:1073741823]	114	1			T12	1		T13	1		T16	2
auto[1073741824:1207959551]	117	1			T3	1		T44	1		T5	1
auto[1207959552:1342177279]	97	1			T4	1		T14	1		T16	4
auto[1342177280:1476395007]	111	1			T13	1		T138	1		T46	1
auto[1476395008:1610612735]	106	1			T16	2		T85	1		T44	1
auto[1610612736:1744830463]	98	1			T16	1		T117	1		T138	1
auto[1744830464:1879048191]	89	1			T3	1		T12	1		T13	1
auto[1879048192:2013265919]	93	1			T16	1		T138	1		T42	1
auto[2013265920:2147483647]	124	1			T4	1		T16	1		T44	1
auto[2147483648:2281701375]	111	1			T14	1		T16	3		T116	1
auto[2281701376:2415919103]	96	1			T16	2		T116	1		T117	1
auto[2415919104:2550136831]	110	1			T4	1		T16	2		T138	2
auto[2550136832:2684354559]	105	1			T138	1		T46	1		T143	1
auto[2684354560:2818572287]	105	1			T3	1		T16	1		T17	1
auto[2818572288:2952790015]	86	1			T14	1		T16	1		T45	1
auto[2952790016:3087007743]	90	1			T3	1		T16	3		T116	1
auto[3087007744:3221225471]	105	1			T14	1		T16	1		T85	1
auto[3221225472:3355443199]	99	1			T4	1		T13	1		T14	1
auto[3355443200:3489660927]	92	1			T16	3		T17	1		T85	2
auto[3489660928:3623878655]	111	1			T3	1		T14	1		T16	2
auto[3623878656:3758096383]	105	1			T14	1		T16	3		T17	1
auto[3758096384:3892314111]	103	1			T16	3		T44	1		T46	2
auto[3892314112:4026531839]	94	1			T14	1		T16	1		T116	1
auto[4026531840:4160749567]	110	1			T3	1		T4	1		T13	1
auto[4160749568:4294967295]	92	1			T13	1		T16	3		T44	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	95	1			T16	1		T34	1		T44	2
auto[0:134217727]	auto[1]	2	1			T410	1		T340	1		-	-
auto[134217728:268435455]	auto[0]	109	1			T4	1		T16	1		T17	1
auto[134217728:268435455]	auto[1]	7	1			T235	1		T276	1		T248	1
auto[268435456:402653183]	auto[0]	95	1			T16	1		T17	1		T85	1
auto[268435456:402653183]	auto[1]	4	1			T408	1		T401	1		T406	1
auto[402653184:536870911]	auto[0]	89	1			T35	1		T44	1		T5	1
auto[402653184:536870911]	auto[1]	10	1			T402	1		T387	1		T233	1
auto[536870912:671088639]	auto[0]	104	1			T13	1		T16	2		T116	1
auto[536870912:671088639]	auto[1]	7	1			T324	1		T248	2		T291	1
auto[671088640:805306367]	auto[0]	90	1			T3	1		T14	1		T17	1
auto[671088640:805306367]	auto[1]	7	1			T276	1		T387	1		T303	1
auto[805306368:939524095]	auto[0]	89	1			T116	1		T37	1		T44	1
auto[805306368:939524095]	auto[1]	2	1			T243	1		T410	1		-	-
auto[939524096:1073741823]	auto[0]	108	1			T12	1		T13	1		T16	2
auto[939524096:1073741823]	auto[1]	6	1			T251	1		T405	1		T232	1
auto[1073741824:1207959551]	auto[0]	111	1			T3	1		T44	1		T5	1
auto[1073741824:1207959551]	auto[1]	6	1			T324	1		T303	1		T248	1
auto[1207959552:1342177279]	auto[0]	91	1			T4	1		T14	1		T16	4
auto[1207959552:1342177279]	auto[1]	6	1			T85	1		T402	1		T399	1
auto[1342177280:1476395007]	auto[0]	101	1			T13	1		T46	1		T200	1
auto[1342177280:1476395007]	auto[1]	10	1			T138	1		T136	1		T251	1
auto[1476395008:1610612735]	auto[0]	97	1			T16	2		T85	1		T44	1
auto[1476395008:1610612735]	auto[1]	9	1			T243	1		T402	1		T248	1
auto[1610612736:1744830463]	auto[0]	94	1			T16	1		T117	1		T138	1
auto[1610612736:1744830463]	auto[1]	4	1			T250	1		T340	1		T414	1
auto[1744830464:1879048191]	auto[0]	86	1			T3	1		T12	1		T13	1
auto[1744830464:1879048191]	auto[1]	3	1			T117	1		T234	1		T413	1
auto[1879048192:2013265919]	auto[0]	88	1			T16	1		T138	1		T42	1
auto[1879048192:2013265919]	auto[1]	5	1			T401	1		T403	1		T415	1
auto[2013265920:2147483647]	auto[0]	112	1			T4	1		T16	1		T44	1
auto[2013265920:2147483647]	auto[1]	12	1			T136	2		T251	1		T405	1
auto[2147483648:2281701375]	auto[0]	104	1			T14	1		T16	3		T116	1
auto[2147483648:2281701375]	auto[1]	7	1			T190	1		T251	1		T402	1
auto[2281701376:2415919103]	auto[0]	85	1			T16	2		T116	1		T117	1
auto[2281701376:2415919103]	auto[1]	11	1			T251	1		T310	1		T279	1
auto[2415919104:2550136831]	auto[0]	103	1			T4	1		T16	2		T138	1
auto[2415919104:2550136831]	auto[1]	7	1			T138	1		T251	1		T398	1
auto[2550136832:2684354559]	auto[0]	95	1			T46	1		T143	1		T352	2
auto[2550136832:2684354559]	auto[1]	10	1			T138	1		T235	2		T251	1
auto[2684354560:2818572287]	auto[0]	96	1			T3	1		T16	1		T17	1
auto[2684354560:2818572287]	auto[1]	9	1			T85	1		T243	1		T232	1
auto[2818572288:2952790015]	auto[0]	81	1			T14	1		T16	1		T45	1
auto[2818572288:2952790015]	auto[1]	5	1			T243	2		T388	1		T410	1
auto[2952790016:3087007743]	auto[0]	82	1			T3	1		T16	3		T35	1
auto[2952790016:3087007743]	auto[1]	8	1			T116	1		T138	1		T243	1
auto[3087007744:3221225471]	auto[0]	98	1			T14	1		T16	1		T85	1
auto[3087007744:3221225471]	auto[1]	7	1			T117	1		T138	1		T232	1
auto[3221225472:3355443199]	auto[0]	95	1			T4	1		T13	1		T14	1
auto[3221225472:3355443199]	auto[1]	4	1			T243	1		T291	1		T410	1
auto[3355443200:3489660927]	auto[0]	85	1			T16	3		T17	1		T85	1
auto[3355443200:3489660927]	auto[1]	7	1			T85	1		T276	1		T234	1
auto[3489660928:3623878655]	auto[0]	104	1			T3	1		T14	1		T16	2
auto[3489660928:3623878655]	auto[1]	7	1			T251	1		T324	1		T232	1
auto[3623878656:3758096383]	auto[0]	97	1			T14	1		T16	3		T17	1
auto[3623878656:3758096383]	auto[1]	8	1			T235	1		T251	1		T310	1
auto[3758096384:3892314111]	auto[0]	97	1			T16	3		T44	1		T46	2
auto[3758096384:3892314111]	auto[1]	6	1			T190	1		T232	1		T303	1
auto[3892314112:4026531839]	auto[0]	86	1			T14	1		T16	1		T5	2
auto[3892314112:4026531839]	auto[1]	8	1			T116	1		T387	1		T291	3
auto[4026531840:4160749567]	auto[0]	102	1			T3	1		T4	1		T13	1
auto[4026531840:4160749567]	auto[1]	8	1			T117	1		T276	1		T324	1
auto[4160749568:4294967295]	auto[0]	83	1			T13	1		T16	3		T44	2
auto[4160749568:4294967295]	auto[1]	9	1			T243	2		T232	1		T248	1