Unified Coverage Report :: Group Instance : attest_sw_binding_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1680

1

T3

3

T4

3

T12

2

auto[1]

1795

1

T3

4

T4

3

T13

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	120	1			T4	1		T16	1		T17	1
auto[134217728:268435455]	126	1			T17	1		T44	4		T143	1
auto[268435456:402653183]	98	1			T3	1		T16	3		T117	1
auto[402653184:536870911]	113	1			T16	1		T116	1		T44	1
auto[536870912:671088639]	92	1			T16	1		T44	3		T5	1
auto[671088640:805306367]	113	1			T16	2		T5	2		T136	1
auto[805306368:939524095]	129	1			T4	1		T16	2		T17	1
auto[939524096:1073741823]	103	1			T16	1		T44	2		T5	2
auto[1073741824:1207959551]	134	1			T12	1		T13	1		T16	2
auto[1207959552:1342177279]	97	1			T3	1		T4	1		T13	1
auto[1342177280:1476395007]	96	1			T44	3		T130	1		T5	1
auto[1476395008:1610612735]	107	1			T16	1		T46	2		T5	1
auto[1610612736:1744830463]	119	1			T4	1		T14	2		T16	2
auto[1744830464:1879048191]	97	1			T16	2		T17	1		T85	1
auto[1879048192:2013265919]	112	1			T13	2		T16	1		T116	1
auto[2013265920:2147483647]	102	1			T17	1		T116	1		T138	1
auto[2147483648:2281701375]	110	1			T16	2		T141	2		T44	2
auto[2281701376:2415919103]	114	1			T13	1		T16	2		T5	2
auto[2415919104:2550136831]	89	1			T16	1		T85	1		T116	1
auto[2550136832:2684354559]	112	1			T4	1		T14	2		T16	1
auto[2684354560:2818572287]	113	1			T4	1		T16	1		T138	1
auto[2818572288:2952790015]	97	1			T14	1		T16	2		T85	1
auto[2952790016:3087007743]	105	1			T3	2		T14	1		T16	4
auto[3087007744:3221225471]	106	1			T14	1		T16	2		T17	1
auto[3221225472:3355443199]	105	1			T3	1		T12	1		T14	1
auto[3355443200:3489660927]	113	1			T16	3		T85	1		T37	1
auto[3489660928:3623878655]	109	1			T13	1		T14	1		T35	1
auto[3623878656:3758096383]	97	1			T16	1		T85	1		T5	2
auto[3758096384:3892314111]	101	1			T13	1		T16	2		T116	1
auto[3892314112:4026531839]	124	1			T16	1		T44	1		T18	1
auto[4026531840:4160749567]	107	1			T16	2		T5	3		T43	1
auto[4160749568:4294967295]	115	1			T3	2		T16	4		T17	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	61	1			T16	1		T47	1		T250	1
auto[0:134217727]	auto[1]	59	1			T4	1		T17	1		T42	1
auto[134217728:268435455]	auto[0]	69	1			T44	1		T110	1		T56	3
auto[134217728:268435455]	auto[1]	57	1			T17	1		T44	3		T143	1
auto[268435456:402653183]	auto[0]	52	1			T3	1		T16	3		T56	1
auto[268435456:402653183]	auto[1]	46	1			T117	1		T46	1		T200	1
auto[402653184:536870911]	auto[0]	54	1			T16	1		T44	1		T50	1
auto[402653184:536870911]	auto[1]	59	1			T116	1		T5	2		T90	1
auto[536870912:671088639]	auto[0]	44	1			T44	2		T5	1		T43	1
auto[536870912:671088639]	auto[1]	48	1			T16	1		T44	1		T63	1
auto[671088640:805306367]	auto[0]	48	1			T16	1		T49	1		T66	2
auto[671088640:805306367]	auto[1]	65	1			T16	1		T5	2		T136	1
auto[805306368:939524095]	auto[0]	63	1			T4	1		T17	1		T46	1
auto[805306368:939524095]	auto[1]	66	1			T16	2		T35	1		T44	1
auto[939524096:1073741823]	auto[0]	40	1			T5	1		T19	1		T43	1
auto[939524096:1073741823]	auto[1]	63	1			T16	1		T44	2		T5	1
auto[1073741824:1207959551]	auto[0]	65	1			T12	1		T16	1		T46	1
auto[1073741824:1207959551]	auto[1]	69	1			T13	1		T16	1		T85	1
auto[1207959552:1342177279]	auto[0]	37	1			T13	1		T16	1		T49	1
auto[1207959552:1342177279]	auto[1]	60	1			T3	1		T4	1		T116	1
auto[1342177280:1476395007]	auto[0]	40	1			T50	1		T240	2		T281	1
auto[1342177280:1476395007]	auto[1]	56	1			T44	3		T130	1		T5	1
auto[1476395008:1610612735]	auto[0]	53	1			T46	1		T5	1		T47	1
auto[1476395008:1610612735]	auto[1]	54	1			T16	1		T46	1		T200	1
auto[1610612736:1744830463]	auto[0]	63	1			T4	1		T14	1		T16	2
auto[1610612736:1744830463]	auto[1]	56	1			T14	1		T17	1		T141	1
auto[1744830464:1879048191]	auto[0]	46	1			T85	1		T132	1		T47	1
auto[1744830464:1879048191]	auto[1]	51	1			T16	2		T17	1		T132	1
auto[1879048192:2013265919]	auto[0]	58	1			T35	1		T44	1		T130	1
auto[1879048192:2013265919]	auto[1]	54	1			T13	2		T16	1		T116	1
auto[2013265920:2147483647]	auto[0]	53	1			T17	1		T5	1		T47	1
auto[2013265920:2147483647]	auto[1]	49	1			T116	1		T138	1		T44	1
auto[2147483648:2281701375]	auto[0]	46	1			T141	2		T45	1		T56	2
auto[2147483648:2281701375]	auto[1]	64	1			T16	2		T44	2		T130	1
auto[2281701376:2415919103]	auto[0]	51	1			T16	1		T49	1		T43	1
auto[2281701376:2415919103]	auto[1]	63	1			T13	1		T16	1		T5	2
auto[2415919104:2550136831]	auto[0]	42	1			T16	1		T85	1		T116	1
auto[2415919104:2550136831]	auto[1]	47	1			T44	1		T18	1		T56	2
auto[2550136832:2684354559]	auto[0]	58	1			T4	1		T14	1		T16	1
auto[2550136832:2684354559]	auto[1]	54	1			T14	1		T34	1		T44	1
auto[2684354560:2818572287]	auto[0]	51	1			T42	1		T5	3		T62	1
auto[2684354560:2818572287]	auto[1]	62	1			T4	1		T16	1		T138	1
auto[2818572288:2952790015]	auto[0]	42	1			T14	1		T85	1		T84	1
auto[2818572288:2952790015]	auto[1]	55	1			T16	2		T34	1		T44	1
auto[2952790016:3087007743]	auto[0]	53	1			T3	1		T16	3		T138	1
auto[2952790016:3087007743]	auto[1]	52	1			T3	1		T14	1		T16	1
auto[3087007744:3221225471]	auto[0]	48	1			T14	1		T16	1		T17	1
auto[3087007744:3221225471]	auto[1]	58	1			T16	1		T141	1		T44	1
auto[3221225472:3355443199]	auto[0]	44	1			T12	1		T14	1		T16	1
auto[3221225472:3355443199]	auto[1]	61	1			T3	1		T16	1		T85	1
auto[3355443200:3489660927]	auto[0]	52	1			T16	1		T85	1		T45	1
auto[3355443200:3489660927]	auto[1]	61	1			T16	2		T37	1		T44	1
auto[3489660928:3623878655]	auto[0]	61	1			T14	1		T35	1		T44	1
auto[3489660928:3623878655]	auto[1]	48	1			T13	1		T352	1		T20	1
auto[3623878656:3758096383]	auto[0]	45	1			T352	1		T84	1		T23	1
auto[3623878656:3758096383]	auto[1]	52	1			T16	1		T85	1		T5	2
auto[3758096384:3892314111]	auto[0]	54	1			T13	1		T16	2		T44	1
auto[3758096384:3892314111]	auto[1]	47	1			T116	1		T44	1		T43	1
auto[3892314112:4026531839]	auto[0]	65	1			T44	1		T18	1		T201	1
auto[3892314112:4026531839]	auto[1]	59	1			T16	1		T5	3		T200	1
auto[4026531840:4160749567]	auto[0]	60	1			T16	1		T5	3		T56	1
auto[4026531840:4160749567]	auto[1]	47	1			T16	1		T43	1		T66	2
auto[4160749568:4294967295]	auto[0]	62	1			T3	1		T44	1		T200	1
auto[4160749568:4294967295]	auto[1]	53	1			T3	1		T16	4		T17	1