Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7353

1

T3

13

T4

11

T12

3

auto[1]

222

1

T85

5

T117

2

T138

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	3074	1			T3	5		T4	4		T12	1
auto[134217728:268435455]	142	1			T3	1		T13	2		T14	1
auto[268435456:402653183]	189	1			T3	1		T13	1		T14	2
auto[402653184:536870911]	157	1			T14	1		T16	2		T17	2
auto[536870912:671088639]	164	1			T14	1		T16	1		T85	1
auto[671088640:805306367]	150	1			T13	1		T14	1		T17	1
auto[805306368:939524095]	153	1			T4	1		T13	1		T16	1
auto[939524096:1073741823]	138	1			T13	1		T14	1		T16	2
auto[1073741824:1207959551]	149	1			T3	1		T16	1		T85	1
auto[1207959552:1342177279]	142	1			T14	1		T16	1		T5	4
auto[1342177280:1476395007]	170	1			T4	2		T16	4		T117	1
auto[1476395008:1610612735]	135	1			T14	1		T16	1		T116	1
auto[1610612736:1744830463]	150	1			T14	1		T16	2		T141	1
auto[1744830464:1879048191]	150	1			T3	2		T12	1		T16	3
auto[1879048192:2013265919]	116	1			T16	1		T17	1		T34	1
auto[2013265920:2147483647]	120	1			T16	1		T141	1		T44	1
auto[2147483648:2281701375]	123	1			T4	1		T16	3		T85	1
auto[2281701376:2415919103]	156	1			T16	2		T85	1		T130	1
auto[2415919104:2550136831]	120	1			T16	3		T45	1		T5	1
auto[2550136832:2684354559]	150	1			T4	1		T16	2		T85	1
auto[2684354560:2818572287]	145	1			T3	2		T16	4		T17	1
auto[2818572288:2952790015]	136	1			T13	1		T14	1		T16	2
auto[2952790016:3087007743]	136	1			T14	1		T16	2		T116	1
auto[3087007744:3221225471]	135	1			T16	2		T138	1		T141	1
auto[3221225472:3355443199]	152	1			T13	1		T14	1		T16	2
auto[3355443200:3489660927]	140	1			T4	1		T16	5		T17	1
auto[3489660928:3623878655]	135	1			T16	2		T85	1		T138	1
auto[3623878656:3758096383]	142	1			T14	1		T16	1		T141	1
auto[3758096384:3892314111]	156	1			T12	1		T16	2		T85	1
auto[3892314112:4026531839]	132	1			T3	1		T4	1		T14	1
auto[4026531840:4160749567]	151	1			T14	1		T16	6		T138	1
auto[4160749568:4294967295]	167	1			T14	1		T16	1		T35	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	3065	1			T3	5		T4	4		T12	1
auto[0:134217727]	auto[1]	9	1			T138	1		T276	2		T405	2
auto[134217728:268435455]	auto[0]	136	1			T3	1		T13	2		T14	1
auto[134217728:268435455]	auto[1]	6	1			T138	1		T136	1		T250	1
auto[268435456:402653183]	auto[0]	180	1			T3	1		T13	1		T14	2
auto[268435456:402653183]	auto[1]	9	1			T251	2		T405	1		T234	1
auto[402653184:536870911]	auto[0]	151	1			T14	1		T16	2		T17	2
auto[402653184:536870911]	auto[1]	6	1			T85	1		T251	1		T243	1
auto[536870912:671088639]	auto[0]	157	1			T14	1		T16	1		T85	1
auto[536870912:671088639]	auto[1]	7	1			T243	1		T399	1		T406	1
auto[671088640:805306367]	auto[0]	142	1			T13	1		T14	1		T17	1
auto[671088640:805306367]	auto[1]	8	1			T235	1		T248	1		T291	1
auto[805306368:939524095]	auto[0]	142	1			T4	1		T13	1		T16	1
auto[805306368:939524095]	auto[1]	11	1			T251	1		T232	1		T402	1
auto[939524096:1073741823]	auto[0]	130	1			T13	1		T14	1		T16	2
auto[939524096:1073741823]	auto[1]	8	1			T190	1		T243	1		T279	1
auto[1073741824:1207959551]	auto[0]	143	1			T3	1		T16	1		T138	1
auto[1073741824:1207959551]	auto[1]	6	1			T85	1		T117	1		T405	1
auto[1207959552:1342177279]	auto[0]	137	1			T14	1		T16	1		T5	4
auto[1207959552:1342177279]	auto[1]	5	1			T136	1		T250	1		T387	1
auto[1342177280:1476395007]	auto[0]	163	1			T4	2		T16	4		T117	1
auto[1342177280:1476395007]	auto[1]	7	1			T243	1		T232	1		T399	1
auto[1476395008:1610612735]	auto[0]	131	1			T14	1		T16	1		T116	1
auto[1476395008:1610612735]	auto[1]	4	1			T251	1		T232	1		T407	1
auto[1610612736:1744830463]	auto[0]	138	1			T14	1		T16	2		T141	1
auto[1610612736:1744830463]	auto[1]	12	1			T250	1		T190	1		T276	2
auto[1744830464:1879048191]	auto[0]	143	1			T3	2		T12	1		T16	3
auto[1744830464:1879048191]	auto[1]	7	1			T402	1		T303	2		T248	1
auto[1879048192:2013265919]	auto[0]	109	1			T16	1		T17	1		T34	1
auto[1879048192:2013265919]	auto[1]	7	1			T143	1		T405	1		T402	1
auto[2013265920:2147483647]	auto[0]	115	1			T16	1		T141	1		T44	1
auto[2013265920:2147483647]	auto[1]	5	1			T235	1		T232	1		T248	1
auto[2147483648:2281701375]	auto[0]	117	1			T4	1		T16	3		T44	3
auto[2147483648:2281701375]	auto[1]	6	1			T85	1		T117	1		T138	1
auto[2281701376:2415919103]	auto[0]	149	1			T16	2		T85	1		T130	1
auto[2281701376:2415919103]	auto[1]	7	1			T235	1		T232	1		T369	1
auto[2415919104:2550136831]	auto[0]	107	1			T16	3		T45	1		T5	1
auto[2415919104:2550136831]	auto[1]	13	1			T251	1		T243	1		T279	1
auto[2550136832:2684354559]	auto[0]	147	1			T4	1		T16	2		T35	1
auto[2550136832:2684354559]	auto[1]	3	1			T85	1		T234	1		T400	1
auto[2684354560:2818572287]	auto[0]	136	1			T3	2		T16	4		T17	1
auto[2684354560:2818572287]	auto[1]	9	1			T136	1		T324	1		T243	1
auto[2818572288:2952790015]	auto[0]	130	1			T13	1		T14	1		T16	2
auto[2818572288:2952790015]	auto[1]	6	1			T232	1		T248	1		T291	1
auto[2952790016:3087007743]	auto[0]	131	1			T14	1		T16	2		T116	1
auto[2952790016:3087007743]	auto[1]	5	1			T138	1		T248	1		T291	1
auto[3087007744:3221225471]	auto[0]	128	1			T16	2		T138	1		T141	1
auto[3087007744:3221225471]	auto[1]	7	1			T250	1		T248	1		T408	1
auto[3221225472:3355443199]	auto[0]	149	1			T13	1		T14	1		T16	2
auto[3221225472:3355443199]	auto[1]	3	1			T190	1		T243	1		T403	1
auto[3355443200:3489660927]	auto[0]	130	1			T4	1		T16	5		T17	1
auto[3355443200:3489660927]	auto[1]	10	1			T85	1		T138	1		T136	1
auto[3489660928:3623878655]	auto[0]	129	1			T16	2		T85	1		T138	1
auto[3489660928:3623878655]	auto[1]	6	1			T190	1		T232	1		T409	1
auto[3623878656:3758096383]	auto[0]	137	1			T14	1		T16	1		T141	1
auto[3623878656:3758096383]	auto[1]	5	1			T276	1		T398	1		T410	1
auto[3758096384:3892314111]	auto[0]	150	1			T12	1		T16	2		T85	1
auto[3758096384:3892314111]	auto[1]	6	1			T369	1		T248	1		T233	1
auto[3892314112:4026531839]	auto[0]	128	1			T3	1		T4	1		T14	1
auto[3892314112:4026531839]	auto[1]	4	1			T251	1		T403	1		T404	1
auto[4026531840:4160749567]	auto[0]	143	1			T14	1		T16	6		T138	1
auto[4026531840:4160749567]	auto[1]	8	1			T143	1		T243	1		T310	1
auto[4160749568:4294967295]	auto[0]	160	1			T14	1		T16	1		T35	1
auto[4160749568:4294967295]	auto[1]	7	1			T190	1		T279	1		T398	1