Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4726

1

T3

12

T4

10

T12

2

auto[1]

2224

1

T3

2

T4

2

T12

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	226	1			T4	2		T16	2		T17	2
auto[134217728:268435455]	188	1			T14	2		T16	2		T34	2
auto[268435456:402653183]	194	1			T3	2		T14	2		T16	2
auto[402653184:536870911]	200	1			T85	2		T42	2		T18	2
auto[536870912:671088639]	208	1			T3	2		T16	2		T17	4
auto[671088640:805306367]	200	1			T16	4		T116	4		T34	2
auto[805306368:939524095]	204	1			T16	2		T5	2		T100	4
auto[939524096:1073741823]	234	1			T3	2		T16	6		T46	2
auto[1073741824:1207959551]	216	1			T3	2		T14	4		T16	4
auto[1207959552:1342177279]	246	1			T4	2		T16	6		T44	2
auto[1342177280:1476395007]	198	1			T4	2		T16	2		T130	2
auto[1476395008:1610612735]	236	1			T4	2		T13	2		T16	4
auto[1610612736:1744830463]	222	1			T16	6		T85	2		T42	2
auto[1744830464:1879048191]	200	1			T16	8		T17	2		T5	6
auto[1879048192:2013265919]	210	1			T17	2		T141	2		T35	2
auto[2013265920:2147483647]	280	1			T13	2		T14	2		T16	8
auto[2147483648:2281701375]	222	1			T13	2		T16	4		T138	2
auto[2281701376:2415919103]	232	1			T14	2		T16	4		T17	2
auto[2415919104:2550136831]	230	1			T14	2		T16	4		T44	2
auto[2550136832:2684354559]	218	1			T13	2		T16	4		T44	4
auto[2684354560:2818572287]	228	1			T14	2		T16	4		T37	2
auto[2818572288:2952790015]	184	1			T3	2		T13	2		T16	4
auto[2952790016:3087007743]	188	1			T16	6		T116	2		T141	2
auto[3087007744:3221225471]	204	1			T352	2		T43	2		T304	4
auto[3221225472:3355443199]	226	1			T3	2		T4	2		T12	2
auto[3355443200:3489660927]	228	1			T17	2		T44	2		T5	2
auto[3489660928:3623878655]	220	1			T3	2		T16	2		T44	2
auto[3623878656:3758096383]	218	1			T16	2		T85	2		T44	2
auto[3758096384:3892314111]	216	1			T4	2		T85	2		T117	2
auto[3892314112:4026531839]	218	1			T16	2		T35	2		T44	2
auto[4026531840:4160749567]	208	1			T13	2		T16	2		T62	2
auto[4160749568:4294967295]	248	1			T12	2		T13	2		T14	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	142	1			T4	2		T16	2		T17	2
auto[0:134217727]	auto[1]	84	1			T5	2		T143	2		T54	2
auto[134217728:268435455]	auto[0]	118	1			T14	2		T16	2		T34	2
auto[134217728:268435455]	auto[1]	70	1			T44	4		T45	2		T5	2
auto[268435456:402653183]	auto[0]	138	1			T3	2		T16	2		T22	2
auto[268435456:402653183]	auto[1]	56	1			T14	2		T138	2		T44	2
auto[402653184:536870911]	auto[0]	124	1			T85	2		T5	2		T352	2
auto[402653184:536870911]	auto[1]	76	1			T42	2		T18	2		T136	2
auto[536870912:671088639]	auto[0]	146	1			T3	2		T16	2		T17	4
auto[536870912:671088639]	auto[1]	62	1			T327	2		T110	2		T237	2
auto[671088640:805306367]	auto[0]	130	1			T16	2		T116	2		T34	2
auto[671088640:805306367]	auto[1]	70	1			T16	2		T116	2		T5	2
auto[805306368:939524095]	auto[0]	136	1			T16	2		T5	2		T100	2
auto[805306368:939524095]	auto[1]	68	1			T100	2		T110	2		T199	2
auto[939524096:1073741823]	auto[0]	156	1			T3	2		T16	6		T49	2
auto[939524096:1073741823]	auto[1]	78	1			T46	2		T18	2		T19	2
auto[1073741824:1207959551]	auto[0]	132	1			T14	2		T16	4		T44	4
auto[1073741824:1207959551]	auto[1]	84	1			T3	2		T14	2		T117	2
auto[1207959552:1342177279]	auto[0]	168	1			T4	2		T16	4		T44	2
auto[1207959552:1342177279]	auto[1]	78	1			T16	2		T43	4		T23	2
auto[1342177280:1476395007]	auto[0]	142	1			T16	2		T130	2		T5	2
auto[1342177280:1476395007]	auto[1]	56	1			T4	2		T79	2		T236	2
auto[1476395008:1610612735]	auto[0]	166	1			T4	2		T13	2		T16	2
auto[1476395008:1610612735]	auto[1]	70	1			T16	2		T138	2		T5	2
auto[1610612736:1744830463]	auto[0]	162	1			T16	6		T85	2		T42	2
auto[1610612736:1744830463]	auto[1]	60	1			T5	2		T43	2		T235	2
auto[1744830464:1879048191]	auto[0]	144	1			T16	6		T17	2		T5	2
auto[1744830464:1879048191]	auto[1]	56	1			T16	2		T5	4		T276	2
auto[1879048192:2013265919]	auto[0]	148	1			T17	2		T141	2		T35	2
auto[1879048192:2013265919]	auto[1]	62	1			T77	2		T84	2		T127	2
auto[2013265920:2147483647]	auto[0]	206	1			T13	2		T14	2		T16	8
auto[2013265920:2147483647]	auto[1]	74	1			T132	2		T239	2		T54	2
auto[2147483648:2281701375]	auto[0]	144	1			T13	2		T16	4		T44	4
auto[2147483648:2281701375]	auto[1]	78	1			T138	2		T5	2		T100	2
auto[2281701376:2415919103]	auto[0]	138	1			T14	2		T16	4		T17	2
auto[2281701376:2415919103]	auto[1]	94	1			T138	4		T34	2		T44	2
auto[2415919104:2550136831]	auto[0]	166	1			T14	2		T16	2		T44	2
auto[2415919104:2550136831]	auto[1]	64	1			T16	2		T130	2		T5	4
auto[2550136832:2684354559]	auto[0]	148	1			T13	2		T16	2		T44	2
auto[2550136832:2684354559]	auto[1]	70	1			T16	2		T44	2		T56	2
auto[2684354560:2818572287]	auto[0]	156	1			T14	2		T16	4		T37	2
auto[2684354560:2818572287]	auto[1]	72	1			T56	2		T275	2		T54	2
auto[2818572288:2952790015]	auto[0]	118	1			T3	2		T13	2		T16	2
auto[2818572288:2952790015]	auto[1]	66	1			T16	2		T116	4		T5	2
auto[2952790016:3087007743]	auto[0]	124	1			T16	6		T116	2		T141	2
auto[2952790016:3087007743]	auto[1]	64	1			T46	2		T5	2		T49	2
auto[3087007744:3221225471]	auto[0]	142	1			T304	2		T110	4		T77	2
auto[3087007744:3221225471]	auto[1]	62	1			T352	2		T43	2		T304	2
auto[3221225472:3355443199]	auto[0]	148	1			T3	2		T4	2		T141	2
auto[3221225472:3355443199]	auto[1]	78	1			T12	2		T16	2		T47	2
auto[3355443200:3489660927]	auto[0]	174	1			T17	2		T44	2		T5	2
auto[3355443200:3489660927]	auto[1]	54	1			T100	2		T411	2		T295	2
auto[3489660928:3623878655]	auto[0]	138	1			T3	2		T16	2		T5	2
auto[3489660928:3623878655]	auto[1]	82	1			T44	2		T46	2		T50	2
auto[3623878656:3758096383]	auto[0]	158	1			T16	2		T85	2		T44	2
auto[3623878656:3758096383]	auto[1]	60	1			T5	2		T47	2		T43	2
auto[3758096384:3892314111]	auto[0]	136	1			T4	2		T85	2		T117	2
auto[3758096384:3892314111]	auto[1]	80	1			T44	4		T5	2		T143	2
auto[3892314112:4026531839]	auto[0]	154	1			T16	2		T44	2		T47	2
auto[3892314112:4026531839]	auto[1]	64	1			T35	2		T132	2		T240	2
auto[4026531840:4160749567]	auto[0]	146	1			T13	2		T16	2		T62	2
auto[4026531840:4160749567]	auto[1]	62	1			T66	2		T213	2		T60	2
auto[4160749568:4294967295]	auto[0]	178	1			T12	2		T13	2		T14	2
auto[4160749568:4294967295]	auto[1]	70	1			T56	2		T77	2		T213	2