Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.74 99.04 98.11 98.40 100.00 99.02 98.41 91.22


Total test records in report: 1084
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T1005 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.722451313 Jul 30 06:47:04 PM PDT 24 Jul 30 06:47:06 PM PDT 24 64318746 ps
T1006 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1685175474 Jul 30 06:46:56 PM PDT 24 Jul 30 06:46:58 PM PDT 24 388476983 ps
T1007 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2426549649 Jul 30 06:46:50 PM PDT 24 Jul 30 06:46:59 PM PDT 24 235455065 ps
T1008 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2867756897 Jul 30 06:46:57 PM PDT 24 Jul 30 06:46:58 PM PDT 24 157781159 ps
T1009 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2375464591 Jul 30 06:46:44 PM PDT 24 Jul 30 06:46:45 PM PDT 24 16551504 ps
T163 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3739357098 Jul 30 06:46:38 PM PDT 24 Jul 30 06:46:44 PM PDT 24 176465452 ps
T1010 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.4138793972 Jul 30 06:46:52 PM PDT 24 Jul 30 06:46:54 PM PDT 24 81524053 ps
T1011 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3384521680 Jul 30 06:46:55 PM PDT 24 Jul 30 06:46:57 PM PDT 24 71529939 ps
T1012 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1973693414 Jul 30 06:46:37 PM PDT 24 Jul 30 06:46:38 PM PDT 24 30686767 ps
T1013 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1760105926 Jul 30 06:46:59 PM PDT 24 Jul 30 06:47:02 PM PDT 24 52969703 ps
T1014 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1731545230 Jul 30 06:47:02 PM PDT 24 Jul 30 06:47:04 PM PDT 24 27187486 ps
T1015 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.4100496500 Jul 30 06:47:01 PM PDT 24 Jul 30 06:47:05 PM PDT 24 139788789 ps
T1016 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1354524915 Jul 30 06:47:04 PM PDT 24 Jul 30 06:47:14 PM PDT 24 1265076790 ps
T1017 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.778794705 Jul 30 06:47:01 PM PDT 24 Jul 30 06:47:18 PM PDT 24 787116274 ps
T1018 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1322628533 Jul 30 06:47:00 PM PDT 24 Jul 30 06:47:01 PM PDT 24 12829474 ps
T1019 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.255194429 Jul 30 06:47:01 PM PDT 24 Jul 30 06:47:03 PM PDT 24 115054073 ps
T1020 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2356495682 Jul 30 06:47:02 PM PDT 24 Jul 30 06:47:04 PM PDT 24 36054158 ps
T1021 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3692957519 Jul 30 06:46:58 PM PDT 24 Jul 30 06:47:00 PM PDT 24 24867202 ps
T1022 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2259133743 Jul 30 06:46:58 PM PDT 24 Jul 30 06:47:01 PM PDT 24 107468181 ps
T1023 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3431566729 Jul 30 06:46:59 PM PDT 24 Jul 30 06:47:02 PM PDT 24 291027733 ps
T1024 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2283845720 Jul 30 06:46:57 PM PDT 24 Jul 30 06:46:58 PM PDT 24 10365235 ps
T1025 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2175550055 Jul 30 06:46:46 PM PDT 24 Jul 30 06:46:51 PM PDT 24 245528284 ps
T1026 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2509846781 Jul 30 06:46:58 PM PDT 24 Jul 30 06:47:02 PM PDT 24 2156969530 ps
T1027 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2514629883 Jul 30 06:46:59 PM PDT 24 Jul 30 06:47:01 PM PDT 24 22831087 ps
T1028 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2230647748 Jul 30 06:47:02 PM PDT 24 Jul 30 06:47:04 PM PDT 24 12592614 ps
T1029 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1472629015 Jul 30 06:46:40 PM PDT 24 Jul 30 06:46:47 PM PDT 24 249409776 ps
T1030 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.437551822 Jul 30 06:46:53 PM PDT 24 Jul 30 06:46:54 PM PDT 24 211821773 ps
T1031 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.950307960 Jul 30 06:46:55 PM PDT 24 Jul 30 06:46:56 PM PDT 24 149581103 ps
T1032 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1849037460 Jul 30 06:47:03 PM PDT 24 Jul 30 06:47:07 PM PDT 24 117035366 ps
T1033 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4208996585 Jul 30 06:46:54 PM PDT 24 Jul 30 06:46:57 PM PDT 24 91362353 ps
T1034 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.386507504 Jul 30 06:46:57 PM PDT 24 Jul 30 06:46:58 PM PDT 24 8235156 ps
T1035 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3066277875 Jul 30 06:46:44 PM PDT 24 Jul 30 06:46:59 PM PDT 24 256411504 ps
T1036 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3704021135 Jul 30 06:46:58 PM PDT 24 Jul 30 06:46:59 PM PDT 24 140865396 ps
T1037 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1913784396 Jul 30 06:46:53 PM PDT 24 Jul 30 06:46:54 PM PDT 24 23286894 ps
T1038 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2692677694 Jul 30 06:47:02 PM PDT 24 Jul 30 06:47:04 PM PDT 24 22349865 ps
T1039 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.370814612 Jul 30 06:47:00 PM PDT 24 Jul 30 06:47:02 PM PDT 24 18460748 ps
T175 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2529962697 Jul 30 06:46:59 PM PDT 24 Jul 30 06:47:08 PM PDT 24 392594847 ps
T1040 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3803960874 Jul 30 06:46:46 PM PDT 24 Jul 30 06:46:50 PM PDT 24 773395881 ps
T1041 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1457802331 Jul 30 06:46:49 PM PDT 24 Jul 30 06:46:51 PM PDT 24 241773506 ps
T1042 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3902024392 Jul 30 06:46:58 PM PDT 24 Jul 30 06:47:02 PM PDT 24 88800303 ps
T174 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1802072488 Jul 30 06:46:52 PM PDT 24 Jul 30 06:46:55 PM PDT 24 93166860 ps
T1043 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1165029508 Jul 30 06:47:04 PM PDT 24 Jul 30 06:47:05 PM PDT 24 9185361 ps
T1044 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.847253252 Jul 30 06:46:47 PM PDT 24 Jul 30 06:46:51 PM PDT 24 173863873 ps
T1045 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2482023202 Jul 30 06:47:05 PM PDT 24 Jul 30 06:47:13 PM PDT 24 529457412 ps
T168 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3095313345 Jul 30 06:46:55 PM PDT 24 Jul 30 06:47:00 PM PDT 24 402480737 ps
T1046 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1632573767 Jul 30 06:46:59 PM PDT 24 Jul 30 06:47:02 PM PDT 24 102781938 ps
T1047 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1454504284 Jul 30 06:46:47 PM PDT 24 Jul 30 06:46:49 PM PDT 24 37884521 ps
T1048 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1630027948 Jul 30 06:46:52 PM PDT 24 Jul 30 06:46:53 PM PDT 24 91890684 ps
T1049 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1449609530 Jul 30 06:47:01 PM PDT 24 Jul 30 06:47:06 PM PDT 24 420186028 ps
T1050 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2701540222 Jul 30 06:47:03 PM PDT 24 Jul 30 06:47:07 PM PDT 24 74462065 ps
T1051 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1567415992 Jul 30 06:46:53 PM PDT 24 Jul 30 06:46:54 PM PDT 24 11827217 ps
T1052 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3905382660 Jul 30 06:46:53 PM PDT 24 Jul 30 06:46:57 PM PDT 24 1610911825 ps
T1053 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2041044540 Jul 30 06:46:28 PM PDT 24 Jul 30 06:46:29 PM PDT 24 24214904 ps
T1054 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2333334021 Jul 30 06:47:01 PM PDT 24 Jul 30 06:47:03 PM PDT 24 15704051 ps
T1055 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1794231939 Jul 30 06:47:03 PM PDT 24 Jul 30 06:47:05 PM PDT 24 22579456 ps
T1056 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.4143086871 Jul 30 06:47:01 PM PDT 24 Jul 30 06:47:02 PM PDT 24 41951136 ps
T1057 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2548396834 Jul 30 06:46:58 PM PDT 24 Jul 30 06:47:00 PM PDT 24 55992986 ps
T1058 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3566839994 Jul 30 06:46:49 PM PDT 24 Jul 30 06:46:53 PM PDT 24 195537121 ps
T1059 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.827357941 Jul 30 06:46:50 PM PDT 24 Jul 30 06:46:51 PM PDT 24 93550661 ps
T1060 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2648366347 Jul 30 06:47:02 PM PDT 24 Jul 30 06:47:05 PM PDT 24 138387466 ps
T1061 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.217670968 Jul 30 06:46:58 PM PDT 24 Jul 30 06:47:04 PM PDT 24 759413317 ps
T1062 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1789360943 Jul 30 06:46:52 PM PDT 24 Jul 30 06:46:53 PM PDT 24 103637695 ps
T1063 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3463187133 Jul 30 06:47:05 PM PDT 24 Jul 30 06:47:06 PM PDT 24 12074062 ps
T1064 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.935251541 Jul 30 06:46:49 PM PDT 24 Jul 30 06:46:56 PM PDT 24 184013809 ps
T1065 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3531119768 Jul 30 06:47:07 PM PDT 24 Jul 30 06:47:08 PM PDT 24 9842059 ps
T1066 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3079382177 Jul 30 06:46:47 PM PDT 24 Jul 30 06:46:51 PM PDT 24 237529875 ps
T1067 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.678761850 Jul 30 06:47:04 PM PDT 24 Jul 30 06:47:06 PM PDT 24 50709335 ps
T1068 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3531324260 Jul 30 06:47:03 PM PDT 24 Jul 30 06:47:05 PM PDT 24 22633770 ps
T1069 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1204422661 Jul 30 06:46:59 PM PDT 24 Jul 30 06:47:01 PM PDT 24 29140665 ps
T1070 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.521970623 Jul 30 06:46:43 PM PDT 24 Jul 30 06:46:45 PM PDT 24 41505259 ps
T1071 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1199091999 Jul 30 06:46:50 PM PDT 24 Jul 30 06:46:56 PM PDT 24 198004447 ps
T1072 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.617853738 Jul 30 06:47:03 PM PDT 24 Jul 30 06:47:05 PM PDT 24 28086374 ps
T1073 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2825836574 Jul 30 06:47:01 PM PDT 24 Jul 30 06:47:03 PM PDT 24 32080153 ps
T1074 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3994237684 Jul 30 06:46:58 PM PDT 24 Jul 30 06:46:59 PM PDT 24 87129913 ps
T1075 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3506939118 Jul 30 06:46:52 PM PDT 24 Jul 30 06:46:54 PM PDT 24 82899117 ps
T1076 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3260713289 Jul 30 06:46:59 PM PDT 24 Jul 30 06:47:06 PM PDT 24 261962377 ps
T1077 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.455556774 Jul 30 06:46:59 PM PDT 24 Jul 30 06:47:01 PM PDT 24 35050765 ps
T1078 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3764206872 Jul 30 06:46:32 PM PDT 24 Jul 30 06:46:34 PM PDT 24 100395917 ps
T1079 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2726268847 Jul 30 06:46:53 PM PDT 24 Jul 30 06:46:54 PM PDT 24 54913614 ps
T1080 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2588167206 Jul 30 06:46:56 PM PDT 24 Jul 30 06:46:57 PM PDT 24 53834208 ps
T1081 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2516564828 Jul 30 06:46:58 PM PDT 24 Jul 30 06:46:59 PM PDT 24 52028687 ps
T1082 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2913615711 Jul 30 06:46:56 PM PDT 24 Jul 30 06:46:57 PM PDT 24 20762089 ps
T1083 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.4074633129 Jul 30 06:47:02 PM PDT 24 Jul 30 06:47:04 PM PDT 24 37555052 ps
T1084 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3277300089 Jul 30 06:47:04 PM PDT 24 Jul 30 06:47:05 PM PDT 24 9976268 ps

Test location /workspace/coverage/default/4.keymgr_stress_all.3052940798
Short name T16
Test name
Test status
Simulation time 2282655679 ps
CPU time 54.5 seconds
Started Jul 30 07:32:31 PM PDT 24
Finished Jul 30 07:33:25 PM PDT 24
Peak memory 222404 kb
Host smart-4560b88e-4e32-4be8-9008-91b043e5c2a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052940798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3052940798
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2084373004
Short name T43
Test name
Test status
Simulation time 5168521538 ps
CPU time 61.61 seconds
Started Jul 30 07:36:15 PM PDT 24
Finished Jul 30 07:37:16 PM PDT 24
Peak memory 222556 kb
Host smart-ffee454d-8413-4b4e-b6f6-f590331fc1c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084373004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2084373004
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.2594833236
Short name T128
Test name
Test status
Simulation time 5418119276 ps
CPU time 21.82 seconds
Started Jul 30 07:32:11 PM PDT 24
Finished Jul 30 07:32:33 PM PDT 24
Peak memory 222608 kb
Host smart-127c2e03-c54c-4488-921b-a6b64f4edbeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594833236 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.2594833236
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1297237418
Short name T10
Test name
Test status
Simulation time 4151436445 ps
CPU time 12.17 seconds
Started Jul 30 07:31:55 PM PDT 24
Finished Jul 30 07:32:07 PM PDT 24
Peak memory 239736 kb
Host smart-52360ae1-3403-4870-9dcf-77b41b378b2f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297237418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1297237418
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1056741963
Short name T54
Test name
Test status
Simulation time 18791366907 ps
CPU time 329.52 seconds
Started Jul 30 07:31:49 PM PDT 24
Finished Jul 30 07:37:19 PM PDT 24
Peak memory 222628 kb
Host smart-0114c7c6-18df-46b7-9779-9d1a1ae8c63a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056741963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1056741963
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2100852181
Short name T5
Test name
Test status
Simulation time 24910070421 ps
CPU time 388.38 seconds
Started Jul 30 07:36:24 PM PDT 24
Finished Jul 30 07:42:53 PM PDT 24
Peak memory 216612 kb
Host smart-87c0868e-b2d8-47e4-9d85-f997a01a8be6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100852181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2100852181
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.2217399529
Short name T127
Test name
Test status
Simulation time 1221150686 ps
CPU time 14.81 seconds
Started Jul 30 07:33:19 PM PDT 24
Finished Jul 30 07:33:34 PM PDT 24
Peak memory 222652 kb
Host smart-721b3e05-87f4-4ae3-9767-db5154c3deb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217399529 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.2217399529
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3534330195
Short name T138
Test name
Test status
Simulation time 152611763 ps
CPU time 8.5 seconds
Started Jul 30 07:32:50 PM PDT 24
Finished Jul 30 07:32:59 PM PDT 24
Peak memory 214292 kb
Host smart-f583792b-f103-4c42-b4e2-b6f89986ffd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3534330195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3534330195
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2939179422
Short name T19
Test name
Test status
Simulation time 233065911 ps
CPU time 6.17 seconds
Started Jul 30 07:36:04 PM PDT 24
Finished Jul 30 07:36:10 PM PDT 24
Peak memory 214916 kb
Host smart-9de70729-d733-4054-aec2-9b7f4dd2bea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939179422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2939179422
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2479488823
Short name T47
Test name
Test status
Simulation time 461586893 ps
CPU time 3.77 seconds
Started Jul 30 07:34:45 PM PDT 24
Finished Jul 30 07:34:49 PM PDT 24
Peak memory 214268 kb
Host smart-35e49904-bbbe-4f95-b4be-b158a217b7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479488823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2479488823
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.306298914
Short name T146
Test name
Test status
Simulation time 262718691 ps
CPU time 7.18 seconds
Started Jul 30 06:47:03 PM PDT 24
Finished Jul 30 06:47:12 PM PDT 24
Peak memory 214672 kb
Host smart-1e5bc545-fe65-42e4-83df-006fe079cfee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306298914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.306298914
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2267716988
Short name T8
Test name
Test status
Simulation time 467683338 ps
CPU time 3.73 seconds
Started Jul 30 07:36:13 PM PDT 24
Finished Jul 30 07:36:16 PM PDT 24
Peak memory 222672 kb
Host smart-d3e5617f-f7e0-4322-b717-a546b0a00f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267716988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2267716988
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3904328393
Short name T243
Test name
Test status
Simulation time 157329047 ps
CPU time 7.99 seconds
Started Jul 30 07:34:38 PM PDT 24
Finished Jul 30 07:34:46 PM PDT 24
Peak memory 214308 kb
Host smart-c9017bab-1078-49ba-9e2d-8876dc938891
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3904328393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3904328393
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3936242860
Short name T23
Test name
Test status
Simulation time 207357465 ps
CPU time 3.21 seconds
Started Jul 30 07:34:47 PM PDT 24
Finished Jul 30 07:34:50 PM PDT 24
Peak memory 222504 kb
Host smart-716fc94b-a1ba-437b-b1fe-37da6c99cd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936242860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3936242860
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2113884356
Short name T291
Test name
Test status
Simulation time 616009150 ps
CPU time 31.26 seconds
Started Jul 30 07:34:52 PM PDT 24
Finished Jul 30 07:35:24 PM PDT 24
Peak memory 216012 kb
Host smart-7a984a53-c888-4cfd-a5ea-4395dc318d49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2113884356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2113884356
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3324735740
Short name T56
Test name
Test status
Simulation time 6582111340 ps
CPU time 96.05 seconds
Started Jul 30 07:35:29 PM PDT 24
Finished Jul 30 07:37:06 PM PDT 24
Peak memory 222532 kb
Host smart-270a4373-b720-46cb-babc-9128ca45709e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324735740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3324735740
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.540734227
Short name T303
Test name
Test status
Simulation time 4100559882 ps
CPU time 53.67 seconds
Started Jul 30 07:35:07 PM PDT 24
Finished Jul 30 07:36:00 PM PDT 24
Peak memory 215184 kb
Host smart-f6a615eb-1db0-4ef4-bc5f-dae5ddeeb6e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=540734227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.540734227
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3189657192
Short name T15
Test name
Test status
Simulation time 1527471934 ps
CPU time 8.75 seconds
Started Jul 30 07:35:39 PM PDT 24
Finished Jul 30 07:35:47 PM PDT 24
Peak memory 210932 kb
Host smart-a858e055-56e1-4005-9c4a-f5b34d06f59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189657192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3189657192
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3999023050
Short name T124
Test name
Test status
Simulation time 176392247 ps
CPU time 2.3 seconds
Started Jul 30 06:46:29 PM PDT 24
Finished Jul 30 06:46:32 PM PDT 24
Peak memory 214740 kb
Host smart-c3046275-83b8-405c-922d-b23b45c15e3a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999023050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3999023050
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2407735436
Short name T362
Test name
Test status
Simulation time 1246629874 ps
CPU time 15.89 seconds
Started Jul 30 07:33:10 PM PDT 24
Finished Jul 30 07:33:26 PM PDT 24
Peak memory 214564 kb
Host smart-06329235-e4c7-45dc-a886-8f142beec5f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2407735436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2407735436
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2356171461
Short name T406
Test name
Test status
Simulation time 747124264 ps
CPU time 9.02 seconds
Started Jul 30 07:35:34 PM PDT 24
Finished Jul 30 07:35:44 PM PDT 24
Peak memory 214956 kb
Host smart-17327c87-1a46-4a83-8c89-a9bd59bbb09e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2356171461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2356171461
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.855209797
Short name T91
Test name
Test status
Simulation time 74114136 ps
CPU time 3.49 seconds
Started Jul 30 07:35:21 PM PDT 24
Finished Jul 30 07:35:25 PM PDT 24
Peak memory 222468 kb
Host smart-92b96651-512b-4b17-bccc-6374fef9cb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855209797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.855209797
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2118852151
Short name T39
Test name
Test status
Simulation time 1019135770 ps
CPU time 5 seconds
Started Jul 30 07:32:54 PM PDT 24
Finished Jul 30 07:32:59 PM PDT 24
Peak memory 221424 kb
Host smart-2b035101-3a05-4c94-a5bb-cb4bde8b9ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118852151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2118852151
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1857135687
Short name T400
Test name
Test status
Simulation time 595652343 ps
CPU time 9.02 seconds
Started Jul 30 07:35:31 PM PDT 24
Finished Jul 30 07:35:40 PM PDT 24
Peak memory 214944 kb
Host smart-3eb0337e-5ec6-4b16-a86f-93c2a4cbdea3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1857135687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1857135687
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.1789889565
Short name T70
Test name
Test status
Simulation time 6177338163 ps
CPU time 33.29 seconds
Started Jul 30 07:34:01 PM PDT 24
Finished Jul 30 07:34:34 PM PDT 24
Peak memory 230892 kb
Host smart-ce0f74aa-1bd0-477b-a547-b7facd684aed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789889565 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.1789889565
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3740034649
Short name T154
Test name
Test status
Simulation time 501443413 ps
CPU time 4.24 seconds
Started Jul 30 07:33:16 PM PDT 24
Finished Jul 30 07:33:21 PM PDT 24
Peak memory 218568 kb
Host smart-ab1bd632-7c6c-408c-b80d-f6fe2891321b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740034649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3740034649
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2174778759
Short name T20
Test name
Test status
Simulation time 75750527 ps
CPU time 3.23 seconds
Started Jul 30 07:35:11 PM PDT 24
Finished Jul 30 07:35:14 PM PDT 24
Peak memory 219036 kb
Host smart-3a0799d2-dfa7-459c-b954-5316d88b19a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174778759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2174778759
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3495782473
Short name T27
Test name
Test status
Simulation time 158413338 ps
CPU time 4.24 seconds
Started Jul 30 07:33:53 PM PDT 24
Finished Jul 30 07:33:57 PM PDT 24
Peak memory 210304 kb
Host smart-88f2ee75-83cd-4c9c-bbf4-c6b90dde97a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495782473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3495782473
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1095280605
Short name T410
Test name
Test status
Simulation time 285715293 ps
CPU time 14.32 seconds
Started Jul 30 07:33:56 PM PDT 24
Finished Jul 30 07:34:11 PM PDT 24
Peak memory 214300 kb
Host smart-3b8ce3bc-26c5-4cdf-bf6d-4f6bed04a832
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1095280605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1095280605
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.973875479
Short name T113
Test name
Test status
Simulation time 1518447547 ps
CPU time 5.57 seconds
Started Jul 30 06:46:53 PM PDT 24
Finished Jul 30 06:46:59 PM PDT 24
Peak memory 214656 kb
Host smart-ed3a4de6-f352-4e25-a10e-1447debdc8cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973875479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.973875479
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.432285777
Short name T7
Test name
Test status
Simulation time 3163954911 ps
CPU time 78.17 seconds
Started Jul 30 07:35:47 PM PDT 24
Finished Jul 30 07:37:05 PM PDT 24
Peak memory 216480 kb
Host smart-baf9af28-4e90-4d02-bee8-0c87e305215a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432285777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.432285777
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1660331525
Short name T232
Test name
Test status
Simulation time 282895266 ps
CPU time 6.83 seconds
Started Jul 30 07:31:58 PM PDT 24
Finished Jul 30 07:32:04 PM PDT 24
Peak memory 214800 kb
Host smart-acc5ab47-643b-4850-8cd4-9b93b6df8be9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1660331525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1660331525
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3538990515
Short name T181
Test name
Test status
Simulation time 5142686978 ps
CPU time 37.7 seconds
Started Jul 30 07:35:32 PM PDT 24
Finished Jul 30 07:36:10 PM PDT 24
Peak memory 215500 kb
Host smart-133d49f3-3e89-4551-adc8-243ae5a17108
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538990515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3538990515
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3581483010
Short name T413
Test name
Test status
Simulation time 176502127 ps
CPU time 9.1 seconds
Started Jul 30 07:33:58 PM PDT 24
Finished Jul 30 07:34:07 PM PDT 24
Peak memory 214660 kb
Host smart-35135d2e-cd1b-4c91-955f-582606610d84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3581483010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3581483010
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2064637501
Short name T60
Test name
Test status
Simulation time 4951468935 ps
CPU time 31.69 seconds
Started Jul 30 07:32:40 PM PDT 24
Finished Jul 30 07:33:12 PM PDT 24
Peak memory 214952 kb
Host smart-7ecd8478-93f4-4c4e-afdd-707bbb81d289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064637501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2064637501
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1760691575
Short name T80
Test name
Test status
Simulation time 13721504 ps
CPU time 0.76 seconds
Started Jul 30 07:34:44 PM PDT 24
Finished Jul 30 07:34:45 PM PDT 24
Peak memory 205992 kb
Host smart-f42bcf68-e1db-4c7f-97db-6a0d47c729eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760691575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1760691575
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.608069257
Short name T165
Test name
Test status
Simulation time 731017351 ps
CPU time 8.33 seconds
Started Jul 30 06:46:56 PM PDT 24
Finished Jul 30 06:47:05 PM PDT 24
Peak memory 206100 kb
Host smart-d3c02320-baa8-49bd-905c-8fd61b34bc0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608069257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.608069257
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.4080020897
Short name T22
Test name
Test status
Simulation time 2014230772 ps
CPU time 20.01 seconds
Started Jul 30 07:34:38 PM PDT 24
Finished Jul 30 07:34:58 PM PDT 24
Peak memory 221604 kb
Host smart-d46281a5-dfd2-496f-8e94-d7d8220fd1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080020897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.4080020897
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1269466797
Short name T136
Test name
Test status
Simulation time 4112181003 ps
CPU time 105.15 seconds
Started Jul 30 07:35:22 PM PDT 24
Finished Jul 30 07:37:08 PM PDT 24
Peak memory 217720 kb
Host smart-22fc9099-36ce-49a9-8e69-7c779fc4ae49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1269466797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1269466797
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.550476842
Short name T157
Test name
Test status
Simulation time 1543529093 ps
CPU time 5.85 seconds
Started Jul 30 06:46:47 PM PDT 24
Finished Jul 30 06:46:53 PM PDT 24
Peak memory 206124 kb
Host smart-c1509534-8e9f-4a01-86bb-549f6f43647a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550476842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.
550476842
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.2035592508
Short name T66
Test name
Test status
Simulation time 497863122 ps
CPU time 15.62 seconds
Started Jul 30 07:33:50 PM PDT 24
Finished Jul 30 07:34:05 PM PDT 24
Peak memory 220340 kb
Host smart-2a40d19b-4296-4106-b42d-95f2dcf8873e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035592508 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.2035592508
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2936466439
Short name T55
Test name
Test status
Simulation time 5103047421 ps
CPU time 63.65 seconds
Started Jul 30 07:33:59 PM PDT 24
Finished Jul 30 07:35:03 PM PDT 24
Peak memory 216368 kb
Host smart-6ac29069-c756-463e-9cdd-6b540f3ca12d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936466439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2936466439
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.4179737009
Short name T117
Test name
Test status
Simulation time 189555639 ps
CPU time 3.73 seconds
Started Jul 30 07:34:33 PM PDT 24
Finished Jul 30 07:34:37 PM PDT 24
Peak memory 214520 kb
Host smart-5175f9fb-c4f4-4115-8ba4-fa25a3e1d258
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4179737009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.4179737009
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3328373218
Short name T153
Test name
Test status
Simulation time 464857096 ps
CPU time 2.6 seconds
Started Jul 30 07:33:20 PM PDT 24
Finished Jul 30 07:33:22 PM PDT 24
Peak memory 216428 kb
Host smart-b56b66d8-8f2d-4746-832d-4299b1c2b02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328373218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3328373218
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.985812183
Short name T230
Test name
Test status
Simulation time 1083268514 ps
CPU time 26.8 seconds
Started Jul 30 07:32:09 PM PDT 24
Finished Jul 30 07:32:36 PM PDT 24
Peak memory 222424 kb
Host smart-4caaa849-41d3-454c-8be7-46957eb41a7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985812183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.985812183
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.501863789
Short name T248
Test name
Test status
Simulation time 243228453 ps
CPU time 13.58 seconds
Started Jul 30 07:34:48 PM PDT 24
Finished Jul 30 07:35:02 PM PDT 24
Peak memory 215624 kb
Host smart-b74a6522-ea9e-4857-b80a-f636d2411ca9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=501863789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.501863789
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1247755765
Short name T260
Test name
Test status
Simulation time 78649282 ps
CPU time 2.11 seconds
Started Jul 30 07:32:18 PM PDT 24
Finished Jul 30 07:32:21 PM PDT 24
Peak memory 214348 kb
Host smart-999ee19a-9c4f-4b0e-a56f-f933d3cf2ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247755765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1247755765
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3157542776
Short name T300
Test name
Test status
Simulation time 48385846 ps
CPU time 3.34 seconds
Started Jul 30 07:36:08 PM PDT 24
Finished Jul 30 07:36:12 PM PDT 24
Peak memory 214400 kb
Host smart-390786bd-4de3-41ae-ab0b-1cb0a10eb6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157542776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3157542776
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1155911432
Short name T164
Test name
Test status
Simulation time 1778070110 ps
CPU time 8.4 seconds
Started Jul 30 06:46:49 PM PDT 24
Finished Jul 30 06:46:58 PM PDT 24
Peak memory 206232 kb
Host smart-74c374de-1617-42f8-b325-9a618ac28af5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155911432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1155911432
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3665409945
Short name T61
Test name
Test status
Simulation time 312785742 ps
CPU time 3.1 seconds
Started Jul 30 07:33:17 PM PDT 24
Finished Jul 30 07:33:20 PM PDT 24
Peak memory 210328 kb
Host smart-1ca9050f-075b-4fdd-9c85-5e9458b2eb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665409945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3665409945
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1577116453
Short name T151
Test name
Test status
Simulation time 533059971 ps
CPU time 5.75 seconds
Started Jul 30 07:33:02 PM PDT 24
Finished Jul 30 07:33:08 PM PDT 24
Peak memory 222596 kb
Host smart-080f5640-133b-4c26-8c5c-4da5226e4bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577116453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1577116453
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1913896983
Short name T263
Test name
Test status
Simulation time 132617055 ps
CPU time 2.36 seconds
Started Jul 30 07:35:10 PM PDT 24
Finished Jul 30 07:35:13 PM PDT 24
Peak memory 214400 kb
Host smart-f50efef3-af6a-4e00-9fc4-a86b1b553617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913896983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1913896983
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3111569420
Short name T44
Test name
Test status
Simulation time 2174368151 ps
CPU time 22.94 seconds
Started Jul 30 07:35:52 PM PDT 24
Finished Jul 30 07:36:15 PM PDT 24
Peak memory 222276 kb
Host smart-3454f8d3-eefe-4d40-9cf7-9bd1a27c4768
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111569420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3111569420
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2320657936
Short name T286
Test name
Test status
Simulation time 127812424 ps
CPU time 2.78 seconds
Started Jul 30 07:36:24 PM PDT 24
Finished Jul 30 07:36:27 PM PDT 24
Peak memory 222428 kb
Host smart-4f42df77-5453-4951-8280-404d48270253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320657936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2320657936
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3136927677
Short name T40
Test name
Test status
Simulation time 871076404 ps
CPU time 9.31 seconds
Started Jul 30 07:32:01 PM PDT 24
Finished Jul 30 07:32:10 PM PDT 24
Peak memory 230296 kb
Host smart-65755748-ad7b-4cfe-8e30-6975a33cafb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136927677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3136927677
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.63247330
Short name T172
Test name
Test status
Simulation time 144983579 ps
CPU time 5.7 seconds
Started Jul 30 06:46:45 PM PDT 24
Finished Jul 30 06:46:51 PM PDT 24
Peak memory 214352 kb
Host smart-b6a21944-579b-4b62-a18d-40a4aeb53eac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63247330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.63247330
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3739357098
Short name T163
Test name
Test status
Simulation time 176465452 ps
CPU time 5.2 seconds
Started Jul 30 06:46:38 PM PDT 24
Finished Jul 30 06:46:44 PM PDT 24
Peak memory 215648 kb
Host smart-ed6655c1-0ab4-4752-9d2e-f4184bb48ba2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739357098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3739357098
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.902293441
Short name T167
Test name
Test status
Simulation time 97310287 ps
CPU time 5.38 seconds
Started Jul 30 06:46:54 PM PDT 24
Finished Jul 30 06:46:59 PM PDT 24
Peak memory 214432 kb
Host smart-281e8c54-d0c9-412a-b818-79c07bc5abcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902293441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err
.902293441
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.2102443552
Short name T408
Test name
Test status
Simulation time 172466920 ps
CPU time 2.51 seconds
Started Jul 30 07:34:01 PM PDT 24
Finished Jul 30 07:34:04 PM PDT 24
Peak memory 214452 kb
Host smart-014a808f-158a-4fce-85c4-daaa7c1347b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2102443552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2102443552
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.934370123
Short name T94
Test name
Test status
Simulation time 210676402 ps
CPU time 4.65 seconds
Started Jul 30 07:34:50 PM PDT 24
Finished Jul 30 07:34:54 PM PDT 24
Peak memory 214344 kb
Host smart-4e694246-ef49-40e8-80dd-e3d0dc35b08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934370123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.934370123
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.486843393
Short name T321
Test name
Test status
Simulation time 1864831718 ps
CPU time 29.13 seconds
Started Jul 30 07:35:21 PM PDT 24
Finished Jul 30 07:35:50 PM PDT 24
Peak memory 222548 kb
Host smart-1daf2bd5-1211-4036-9106-a7aaff80c625
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486843393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.486843393
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1154356494
Short name T231
Test name
Test status
Simulation time 751080719 ps
CPU time 30.71 seconds
Started Jul 30 07:36:24 PM PDT 24
Finished Jul 30 07:36:54 PM PDT 24
Peak memory 216496 kb
Host smart-4e483da3-5a2b-425a-a782-9bcdbe1be96d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154356494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1154356494
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3213339029
Short name T152
Test name
Test status
Simulation time 146506536 ps
CPU time 2.46 seconds
Started Jul 30 07:32:32 PM PDT 24
Finished Jul 30 07:32:34 PM PDT 24
Peak memory 214732 kb
Host smart-5611f45c-7d7c-4651-aa43-d59b0b015cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213339029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3213339029
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3077357077
Short name T156
Test name
Test status
Simulation time 136219644 ps
CPU time 2.45 seconds
Started Jul 30 07:35:47 PM PDT 24
Finished Jul 30 07:35:49 PM PDT 24
Peak memory 215632 kb
Host smart-0cfbf75e-7aee-4614-84de-3d5fd2e8775f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077357077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3077357077
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1299976716
Short name T285
Test name
Test status
Simulation time 794415399 ps
CPU time 3.85 seconds
Started Jul 30 07:33:11 PM PDT 24
Finished Jul 30 07:33:14 PM PDT 24
Peak memory 221132 kb
Host smart-32955d44-9056-4afe-89bb-88282f21a7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299976716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1299976716
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3746134147
Short name T283
Test name
Test status
Simulation time 208077095 ps
CPU time 2.9 seconds
Started Jul 30 07:34:03 PM PDT 24
Finished Jul 30 07:34:06 PM PDT 24
Peak memory 211216 kb
Host smart-6afb6a15-71a8-42b9-ae01-aefad35bc885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746134147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3746134147
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3142153464
Short name T763
Test name
Test status
Simulation time 4664953620 ps
CPU time 42.69 seconds
Started Jul 30 07:34:04 PM PDT 24
Finished Jul 30 07:34:47 PM PDT 24
Peak memory 217120 kb
Host smart-46469f1e-2b21-4327-8e1a-e6ff5c67ecf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142153464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3142153464
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1545372281
Short name T213
Test name
Test status
Simulation time 2401079702 ps
CPU time 25.47 seconds
Started Jul 30 07:35:11 PM PDT 24
Finished Jul 30 07:35:37 PM PDT 24
Peak memory 222448 kb
Host smart-a4c4dae4-be18-4c7d-8055-7e684349632c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545372281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1545372281
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3980008960
Short name T192
Test name
Test status
Simulation time 159327468 ps
CPU time 2.48 seconds
Started Jul 30 07:35:26 PM PDT 24
Finished Jul 30 07:35:28 PM PDT 24
Peak memory 207112 kb
Host smart-2a98691e-8482-4eca-b637-7e792469fe4f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980008960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3980008960
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_random.902101815
Short name T325
Test name
Test status
Simulation time 2730066738 ps
CPU time 86.25 seconds
Started Jul 30 07:35:35 PM PDT 24
Finished Jul 30 07:37:01 PM PDT 24
Peak memory 209528 kb
Host smart-738ddac0-7b21-4f7a-9148-23c819e3c430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902101815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.902101815
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.1824745021
Short name T226
Test name
Test status
Simulation time 1519715358 ps
CPU time 21.81 seconds
Started Jul 30 07:32:30 PM PDT 24
Finished Jul 30 07:32:52 PM PDT 24
Peak memory 222556 kb
Host smart-d85f9119-8a21-4146-8577-9a1bee878c11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824745021 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.1824745021
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2042973804
Short name T205
Test name
Test status
Simulation time 206225969 ps
CPU time 4.51 seconds
Started Jul 30 07:36:08 PM PDT 24
Finished Jul 30 07:36:13 PM PDT 24
Peak memory 214260 kb
Host smart-d3dafdf7-6286-45c3-bfe1-c3b720b01e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042973804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2042973804
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1634741658
Short name T409
Test name
Test status
Simulation time 184668485 ps
CPU time 3.72 seconds
Started Jul 30 07:36:15 PM PDT 24
Finished Jul 30 07:36:19 PM PDT 24
Peak memory 214328 kb
Host smart-9b0b53da-1682-4d96-858f-bf925648c244
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1634741658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1634741658
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1482422460
Short name T176
Test name
Test status
Simulation time 3274270674 ps
CPU time 6.01 seconds
Started Jul 30 06:46:58 PM PDT 24
Finished Jul 30 06:47:05 PM PDT 24
Peak memory 206224 kb
Host smart-d9d6681b-25a7-40d5-bc87-9a0c46166962
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482422460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1482422460
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1802072488
Short name T174
Test name
Test status
Simulation time 93166860 ps
CPU time 2.64 seconds
Started Jul 30 06:46:52 PM PDT 24
Finished Jul 30 06:46:55 PM PDT 24
Peak memory 206148 kb
Host smart-c3400145-702b-4278-aad1-179563a50bab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802072488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1802072488
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1687474938
Short name T661
Test name
Test status
Simulation time 147096184 ps
CPU time 4.08 seconds
Started Jul 30 07:32:10 PM PDT 24
Finished Jul 30 07:32:15 PM PDT 24
Peak memory 214572 kb
Host smart-e32a0c99-8e40-4b8a-83ec-43897ae9cd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687474938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1687474938
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1225417137
Short name T169
Test name
Test status
Simulation time 171964497 ps
CPU time 1.79 seconds
Started Jul 30 07:34:44 PM PDT 24
Finished Jul 30 07:34:46 PM PDT 24
Peak memory 210244 kb
Host smart-448a469b-d128-4664-871c-4d9a95fbbd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225417137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1225417137
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3355042156
Short name T170
Test name
Test status
Simulation time 45310295 ps
CPU time 1.63 seconds
Started Jul 30 07:35:50 PM PDT 24
Finished Jul 30 07:35:52 PM PDT 24
Peak memory 209756 kb
Host smart-fb72348f-b1d0-4fec-aa6b-ec38f54e03d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355042156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3355042156
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3271642796
Short name T155
Test name
Test status
Simulation time 128908748 ps
CPU time 2.47 seconds
Started Jul 30 07:32:49 PM PDT 24
Finished Jul 30 07:32:51 PM PDT 24
Peak memory 222568 kb
Host smart-2af0987e-0f81-4b2f-b17c-eea1843aa791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271642796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3271642796
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.655782506
Short name T251
Test name
Test status
Simulation time 2992411544 ps
CPU time 12.91 seconds
Started Jul 30 07:31:42 PM PDT 24
Finished Jul 30 07:31:55 PM PDT 24
Peak memory 214348 kb
Host smart-7f42e3cc-525b-47bb-9ee4-c299d33d3cb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=655782506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.655782506
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3374700361
Short name T360
Test name
Test status
Simulation time 468372601 ps
CPU time 5.48 seconds
Started Jul 30 07:31:43 PM PDT 24
Finished Jul 30 07:31:49 PM PDT 24
Peak memory 209036 kb
Host smart-8eb9a4b8-5bd3-4ceb-8803-b151bd66c31a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374700361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3374700361
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3499846901
Short name T374
Test name
Test status
Simulation time 403416671 ps
CPU time 3.32 seconds
Started Jul 30 07:31:58 PM PDT 24
Finished Jul 30 07:32:02 PM PDT 24
Peak memory 214360 kb
Host smart-678a0485-86a9-4c26-8ab9-17d30ca8b7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499846901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3499846901
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2164575677
Short name T73
Test name
Test status
Simulation time 5198288117 ps
CPU time 40.69 seconds
Started Jul 30 07:33:20 PM PDT 24
Finished Jul 30 07:34:01 PM PDT 24
Peak memory 215996 kb
Host smart-96cb68f6-97c3-474e-9640-c202e5e44cb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164575677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2164575677
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.470270897
Short name T190
Test name
Test status
Simulation time 158589762 ps
CPU time 2.81 seconds
Started Jul 30 07:33:23 PM PDT 24
Finished Jul 30 07:33:26 PM PDT 24
Peak memory 214664 kb
Host smart-69b4d0a5-1ebe-4990-8291-40d2eb2ad547
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=470270897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.470270897
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3585771499
Short name T651
Test name
Test status
Simulation time 1982971065 ps
CPU time 36.54 seconds
Started Jul 30 07:33:21 PM PDT 24
Finished Jul 30 07:33:58 PM PDT 24
Peak memory 222444 kb
Host smart-47cacfee-c9c0-43b3-8aa4-b31d656b1dab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585771499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3585771499
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.4086664897
Short name T318
Test name
Test status
Simulation time 1095555575 ps
CPU time 4.3 seconds
Started Jul 30 07:33:37 PM PDT 24
Finished Jul 30 07:33:41 PM PDT 24
Peak memory 222396 kb
Host smart-aef02636-c724-4e45-a2b8-54ec76bc08a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086664897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.4086664897
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1885978984
Short name T904
Test name
Test status
Simulation time 122766921 ps
CPU time 2.65 seconds
Started Jul 30 07:33:56 PM PDT 24
Finished Jul 30 07:33:59 PM PDT 24
Peak memory 218012 kb
Host smart-41fadd9a-24d0-49a2-bb2b-c18141b9a8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885978984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1885978984
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2238518885
Short name T105
Test name
Test status
Simulation time 180945580 ps
CPU time 4.7 seconds
Started Jul 30 07:33:44 PM PDT 24
Finished Jul 30 07:33:50 PM PDT 24
Peak memory 208928 kb
Host smart-52baebac-376a-42b7-b98e-81b497fc4954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238518885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2238518885
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3777360053
Short name T378
Test name
Test status
Simulation time 143905350 ps
CPU time 1.91 seconds
Started Jul 30 07:33:56 PM PDT 24
Finished Jul 30 07:33:58 PM PDT 24
Peak memory 210128 kb
Host smart-6ff6ae47-763f-4807-9ddc-b01751264523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777360053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3777360053
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.340891039
Short name T236
Test name
Test status
Simulation time 10993722075 ps
CPU time 312.23 seconds
Started Jul 30 07:34:32 PM PDT 24
Finished Jul 30 07:39:44 PM PDT 24
Peak memory 222516 kb
Host smart-9ea4920f-5b57-4efa-8cf9-c877d877a7da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340891039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.340891039
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1194324707
Short name T357
Test name
Test status
Simulation time 115286556 ps
CPU time 3.72 seconds
Started Jul 30 07:34:24 PM PDT 24
Finished Jul 30 07:34:28 PM PDT 24
Peak memory 222464 kb
Host smart-bec35912-851b-4226-9fdb-7fa53234a3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194324707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1194324707
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3808602259
Short name T59
Test name
Test status
Simulation time 90170772 ps
CPU time 3.27 seconds
Started Jul 30 07:34:49 PM PDT 24
Finished Jul 30 07:34:52 PM PDT 24
Peak memory 220340 kb
Host smart-edede058-c650-4352-9a94-464e498a65b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808602259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3808602259
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.31434199
Short name T355
Test name
Test status
Simulation time 126047366 ps
CPU time 4.62 seconds
Started Jul 30 07:34:52 PM PDT 24
Finished Jul 30 07:34:57 PM PDT 24
Peak memory 207680 kb
Host smart-016065c5-f711-4285-92a1-789e1fbd7264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31434199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.31434199
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.4093076755
Short name T75
Test name
Test status
Simulation time 7797200770 ps
CPU time 18.52 seconds
Started Jul 30 07:35:21 PM PDT 24
Finished Jul 30 07:35:40 PM PDT 24
Peak memory 222604 kb
Host smart-24b867f8-f439-423c-932a-4b153daa283d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093076755 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.4093076755
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3866648470
Short name T417
Test name
Test status
Simulation time 49325734 ps
CPU time 3.6 seconds
Started Jul 30 07:35:19 PM PDT 24
Finished Jul 30 07:35:23 PM PDT 24
Peak memory 214320 kb
Host smart-53fe31f0-b09a-40ca-938a-9af5ca7836f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3866648470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3866648470
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2875063543
Short name T223
Test name
Test status
Simulation time 362749318 ps
CPU time 3.39 seconds
Started Jul 30 07:35:49 PM PDT 24
Finished Jul 30 07:35:53 PM PDT 24
Peak memory 209440 kb
Host smart-8625cb22-2344-492b-ae64-dba370248655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875063543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2875063543
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2886432136
Short name T316
Test name
Test status
Simulation time 130202464 ps
CPU time 3.62 seconds
Started Jul 30 07:35:56 PM PDT 24
Finished Jul 30 07:36:00 PM PDT 24
Peak memory 211316 kb
Host smart-da41f52a-5788-4999-9a51-edefa89dfc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886432136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2886432136
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2594750266
Short name T143
Test name
Test status
Simulation time 104300179 ps
CPU time 2.82 seconds
Started Jul 30 07:35:59 PM PDT 24
Finished Jul 30 07:36:02 PM PDT 24
Peak memory 214384 kb
Host smart-55a282dd-a58c-4a20-8ec4-a97022c7bc7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2594750266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2594750266
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2034250175
Short name T212
Test name
Test status
Simulation time 477010537 ps
CPU time 4.03 seconds
Started Jul 30 07:36:22 PM PDT 24
Finished Jul 30 07:36:26 PM PDT 24
Peak memory 222580 kb
Host smart-57d7e151-1f64-4bec-8189-a2949e3d366f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034250175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2034250175
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3029784451
Short name T209
Test name
Test status
Simulation time 55337858 ps
CPU time 2.59 seconds
Started Jul 30 07:32:42 PM PDT 24
Finished Jul 30 07:32:45 PM PDT 24
Peak memory 214528 kb
Host smart-1687a688-3d73-444c-a2ac-5e5df193b356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029784451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3029784451
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.942198907
Short name T150
Test name
Test status
Simulation time 173967091 ps
CPU time 2.12 seconds
Started Jul 30 07:33:12 PM PDT 24
Finished Jul 30 07:33:14 PM PDT 24
Peak memory 217652 kb
Host smart-a188726a-a72f-46ad-8f97-b833a2f2cdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942198907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.942198907
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.929644810
Short name T68
Test name
Test status
Simulation time 36200092 ps
CPU time 2.44 seconds
Started Jul 30 07:35:49 PM PDT 24
Finished Jul 30 07:35:52 PM PDT 24
Peak memory 215496 kb
Host smart-ea2670aa-87eb-4ecc-beab-a3762d3d9cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929644810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.929644810
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3237227187
Short name T1001
Test name
Test status
Simulation time 504630677 ps
CPU time 7.36 seconds
Started Jul 30 06:46:48 PM PDT 24
Finished Jul 30 06:46:55 PM PDT 24
Peak memory 206268 kb
Host smart-d9579900-e389-4747-b301-d0ec72840a7c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237227187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
237227187
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3177422713
Short name T996
Test name
Test status
Simulation time 1323888275 ps
CPU time 18.06 seconds
Started Jul 30 06:46:50 PM PDT 24
Finished Jul 30 06:47:08 PM PDT 24
Peak memory 206092 kb
Host smart-34594b1f-0d72-4c16-9822-e1cecf7f2c6c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177422713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
177422713
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3231447094
Short name T928
Test name
Test status
Simulation time 133725082 ps
CPU time 1.18 seconds
Started Jul 30 06:46:39 PM PDT 24
Finished Jul 30 06:46:41 PM PDT 24
Peak memory 206124 kb
Host smart-812cc5ae-2f90-4bc1-ab89-39355af8869b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231447094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
231447094
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3544704753
Short name T1003
Test name
Test status
Simulation time 149365220 ps
CPU time 1.23 seconds
Started Jul 30 06:46:43 PM PDT 24
Finished Jul 30 06:46:45 PM PDT 24
Peak memory 214508 kb
Host smart-b1c9dbc1-45c4-4eac-9beb-fcfad15b8759
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544704753 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3544704753
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3404048273
Short name T982
Test name
Test status
Simulation time 55424759 ps
CPU time 1.28 seconds
Started Jul 30 06:46:30 PM PDT 24
Finished Jul 30 06:46:31 PM PDT 24
Peak memory 206140 kb
Host smart-c4394c1d-dd84-4de1-8e2a-d5503d62fb2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404048273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3404048273
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.412327345
Short name T951
Test name
Test status
Simulation time 11768010 ps
CPU time 0.73 seconds
Started Jul 30 06:46:29 PM PDT 24
Finished Jul 30 06:46:30 PM PDT 24
Peak memory 205936 kb
Host smart-e34e15a2-2d86-4119-a1a6-965b24ee4b93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412327345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.412327345
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.521970623
Short name T1070
Test name
Test status
Simulation time 41505259 ps
CPU time 1.56 seconds
Started Jul 30 06:46:43 PM PDT 24
Finished Jul 30 06:46:45 PM PDT 24
Peak memory 206172 kb
Host smart-5a0e36a7-4e8a-4089-bcc3-9980da4d09d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521970623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.521970623
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1434085981
Short name T957
Test name
Test status
Simulation time 1557470170 ps
CPU time 15.63 seconds
Started Jul 30 06:46:51 PM PDT 24
Finished Jul 30 06:47:07 PM PDT 24
Peak memory 214624 kb
Host smart-cfc6c234-0f2f-4c65-9ec1-e5315e135ede
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434085981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1434085981
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1472629015
Short name T1029
Test name
Test status
Simulation time 249409776 ps
CPU time 1.82 seconds
Started Jul 30 06:46:40 PM PDT 24
Finished Jul 30 06:46:47 PM PDT 24
Peak memory 214356 kb
Host smart-b17e3d69-bac7-4951-9108-71b170789a73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472629015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1472629015
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2601997960
Short name T972
Test name
Test status
Simulation time 412376953 ps
CPU time 7.24 seconds
Started Jul 30 06:46:51 PM PDT 24
Finished Jul 30 06:46:59 PM PDT 24
Peak memory 206196 kb
Host smart-a16c2595-5643-4b75-9e94-a169127a4acf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601997960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
601997960
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2663700662
Short name T926
Test name
Test status
Simulation time 6396996206 ps
CPU time 8.84 seconds
Started Jul 30 06:46:40 PM PDT 24
Finished Jul 30 06:46:49 PM PDT 24
Peak memory 206220 kb
Host smart-9a965977-a764-429d-a939-7063adb7615e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663700662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
663700662
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.437551822
Short name T1030
Test name
Test status
Simulation time 211821773 ps
CPU time 1.21 seconds
Started Jul 30 06:46:53 PM PDT 24
Finished Jul 30 06:46:54 PM PDT 24
Peak memory 206160 kb
Host smart-78132018-fde8-46bf-a479-d9c24fb6d532
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437551822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.437551822
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1973693414
Short name T1012
Test name
Test status
Simulation time 30686767 ps
CPU time 1.16 seconds
Started Jul 30 06:46:37 PM PDT 24
Finished Jul 30 06:46:38 PM PDT 24
Peak memory 206292 kb
Host smart-aeb3d63c-3707-496d-80b8-418ef0e30fa7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973693414 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1973693414
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2537813284
Short name T979
Test name
Test status
Simulation time 63016211 ps
CPU time 1.57 seconds
Started Jul 30 06:46:44 PM PDT 24
Finished Jul 30 06:46:46 PM PDT 24
Peak memory 206256 kb
Host smart-c434ce9e-44b4-4d70-baec-835f399a84fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537813284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2537813284
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1913784396
Short name T1037
Test name
Test status
Simulation time 23286894 ps
CPU time 0.86 seconds
Started Jul 30 06:46:53 PM PDT 24
Finished Jul 30 06:46:54 PM PDT 24
Peak memory 206092 kb
Host smart-bde03125-959b-4ec5-a934-bf09ddd9ecce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913784396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1913784396
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3566839994
Short name T1058
Test name
Test status
Simulation time 195537121 ps
CPU time 3.64 seconds
Started Jul 30 06:46:49 PM PDT 24
Finished Jul 30 06:46:53 PM PDT 24
Peak memory 206172 kb
Host smart-f538bcb3-0896-49b8-b77a-3f8ee0e8a1fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566839994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.3566839994
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.4135983487
Short name T960
Test name
Test status
Simulation time 62181827 ps
CPU time 1.64 seconds
Started Jul 30 06:46:47 PM PDT 24
Finished Jul 30 06:46:49 PM PDT 24
Peak memory 214556 kb
Host smart-25050941-d4ab-4baf-b532-d84390c912db
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135983487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.4135983487
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3764206872
Short name T1078
Test name
Test status
Simulation time 100395917 ps
CPU time 2.04 seconds
Started Jul 30 06:46:32 PM PDT 24
Finished Jul 30 06:46:34 PM PDT 24
Peak memory 206128 kb
Host smart-fab28064-e3db-4247-8e96-d1fbf2bc40e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764206872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3764206872
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3001906177
Short name T998
Test name
Test status
Simulation time 39763325 ps
CPU time 1.36 seconds
Started Jul 30 06:47:04 PM PDT 24
Finished Jul 30 06:47:06 PM PDT 24
Peak memory 214440 kb
Host smart-2945c55d-d54d-44ad-a05f-725acaf1791e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001906177 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3001906177
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2913615711
Short name T1082
Test name
Test status
Simulation time 20762089 ps
CPU time 0.96 seconds
Started Jul 30 06:46:56 PM PDT 24
Finished Jul 30 06:46:57 PM PDT 24
Peak memory 206008 kb
Host smart-c1d68726-ac03-4c97-a03e-f662317574e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913615711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2913615711
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1147286715
Short name T924
Test name
Test status
Simulation time 42146347 ps
CPU time 0.85 seconds
Started Jul 30 06:46:59 PM PDT 24
Finished Jul 30 06:47:00 PM PDT 24
Peak memory 205912 kb
Host smart-165769cd-de27-4474-90e6-6f62525b5a85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147286715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1147286715
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2574487884
Short name T935
Test name
Test status
Simulation time 202702980 ps
CPU time 2.68 seconds
Started Jul 30 06:47:04 PM PDT 24
Finished Jul 30 06:47:07 PM PDT 24
Peak memory 206088 kb
Host smart-fe2248f0-0694-45a1-b2b9-0efdfbdd3949
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574487884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2574487884
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2657645868
Short name T123
Test name
Test status
Simulation time 478043794 ps
CPU time 2.64 seconds
Started Jul 30 06:46:56 PM PDT 24
Finished Jul 30 06:46:58 PM PDT 24
Peak memory 214728 kb
Host smart-41f43aad-782f-43fe-af47-49f030e5d99d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657645868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2657645868
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1726616480
Short name T975
Test name
Test status
Simulation time 175315345 ps
CPU time 6.37 seconds
Started Jul 30 06:47:03 PM PDT 24
Finished Jul 30 06:47:11 PM PDT 24
Peak memory 214704 kb
Host smart-cda407ee-dc8a-4d54-99fe-0e76bab360f0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726616480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1726616480
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.4100496500
Short name T1015
Test name
Test status
Simulation time 139788789 ps
CPU time 2.78 seconds
Started Jul 30 06:47:01 PM PDT 24
Finished Jul 30 06:47:05 PM PDT 24
Peak memory 214444 kb
Host smart-fb1393c3-62b8-435c-a2da-46dc58879e20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100496500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.4100496500
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1449609530
Short name T1049
Test name
Test status
Simulation time 420186028 ps
CPU time 4.95 seconds
Started Jul 30 06:47:01 PM PDT 24
Finished Jul 30 06:47:06 PM PDT 24
Peak memory 214388 kb
Host smart-38cca88f-667e-4e31-8e57-7617871e8d01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449609530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1449609530
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.722451313
Short name T1005
Test name
Test status
Simulation time 64318746 ps
CPU time 0.97 seconds
Started Jul 30 06:47:04 PM PDT 24
Finished Jul 30 06:47:06 PM PDT 24
Peak memory 206044 kb
Host smart-80888377-74c6-4273-970c-f61f9281458d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722451313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.722451313
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2509219326
Short name T971
Test name
Test status
Simulation time 69276418 ps
CPU time 0.86 seconds
Started Jul 30 06:46:55 PM PDT 24
Finished Jul 30 06:46:56 PM PDT 24
Peak memory 205940 kb
Host smart-57af05fa-873e-45ca-b152-15808f151c29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509219326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2509219326
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.7126249
Short name T985
Test name
Test status
Simulation time 20307161 ps
CPU time 1.39 seconds
Started Jul 30 06:46:57 PM PDT 24
Finished Jul 30 06:46:59 PM PDT 24
Peak memory 206260 kb
Host smart-41f04b46-d955-4605-a011-2e870e482ccc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7126249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_same
_csr_outstanding.7126249
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1840043269
Short name T954
Test name
Test status
Simulation time 190310030 ps
CPU time 2.13 seconds
Started Jul 30 06:47:10 PM PDT 24
Finished Jul 30 06:47:12 PM PDT 24
Peak memory 214588 kb
Host smart-3688ae17-5dd6-40c5-bf92-e7968a946559
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840043269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1840043269
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2636222593
Short name T949
Test name
Test status
Simulation time 1580248532 ps
CPU time 14.22 seconds
Started Jul 30 06:47:02 PM PDT 24
Finished Jul 30 06:47:18 PM PDT 24
Peak memory 214712 kb
Host smart-1061c870-f80b-47c2-8315-df996f1b18ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636222593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2636222593
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.913480426
Short name T964
Test name
Test status
Simulation time 1004704222 ps
CPU time 3.43 seconds
Started Jul 30 06:46:57 PM PDT 24
Finished Jul 30 06:47:01 PM PDT 24
Peak memory 214456 kb
Host smart-182d5a38-8a01-40b0-b172-3e7555bd413d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913480426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.913480426
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.565818302
Short name T956
Test name
Test status
Simulation time 88292759 ps
CPU time 1.49 seconds
Started Jul 30 06:47:03 PM PDT 24
Finished Jul 30 06:47:05 PM PDT 24
Peak memory 214436 kb
Host smart-cd153c02-2174-4c80-b18b-0a59296421f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565818302 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.565818302
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3704021135
Short name T1036
Test name
Test status
Simulation time 140865396 ps
CPU time 1.04 seconds
Started Jul 30 06:46:58 PM PDT 24
Finished Jul 30 06:46:59 PM PDT 24
Peak memory 205964 kb
Host smart-504ccd59-187f-4e49-998a-b61e42ad038f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704021135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3704021135
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3254044916
Short name T938
Test name
Test status
Simulation time 9744028 ps
CPU time 0.72 seconds
Started Jul 30 06:47:01 PM PDT 24
Finished Jul 30 06:47:03 PM PDT 24
Peak memory 205940 kb
Host smart-0e27b094-0837-43e0-b794-c347cc6217f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254044916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3254044916
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3506939118
Short name T1075
Test name
Test status
Simulation time 82899117 ps
CPU time 2.22 seconds
Started Jul 30 06:46:52 PM PDT 24
Finished Jul 30 06:46:54 PM PDT 24
Peak memory 206208 kb
Host smart-a28cdba5-de98-44a5-8c52-f6989c2243ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506939118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3506939118
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2259133743
Short name T1022
Test name
Test status
Simulation time 107468181 ps
CPU time 2.15 seconds
Started Jul 30 06:46:58 PM PDT 24
Finished Jul 30 06:47:01 PM PDT 24
Peak memory 214516 kb
Host smart-4390b38d-6949-40e1-a3a1-695b101f97dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259133743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2259133743
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2812049461
Short name T993
Test name
Test status
Simulation time 515613007 ps
CPU time 7.79 seconds
Started Jul 30 06:46:58 PM PDT 24
Finished Jul 30 06:47:06 PM PDT 24
Peak memory 223016 kb
Host smart-b0556ed8-0549-4484-b79f-b9ddd1a3e01b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812049461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2812049461
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3431566729
Short name T1023
Test name
Test status
Simulation time 291027733 ps
CPU time 3.05 seconds
Started Jul 30 06:46:59 PM PDT 24
Finished Jul 30 06:47:02 PM PDT 24
Peak memory 214432 kb
Host smart-4ae5d8c8-74bc-43dc-9ed2-8045e206dc61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431566729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3431566729
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.571505125
Short name T963
Test name
Test status
Simulation time 38718014 ps
CPU time 2.83 seconds
Started Jul 30 06:46:58 PM PDT 24
Finished Jul 30 06:47:01 PM PDT 24
Peak memory 214344 kb
Host smart-996b4bfb-41ce-4d76-9b2c-69bd12834c50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571505125 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.571505125
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2692677694
Short name T1038
Test name
Test status
Simulation time 22349865 ps
CPU time 1.39 seconds
Started Jul 30 06:47:02 PM PDT 24
Finished Jul 30 06:47:04 PM PDT 24
Peak memory 206112 kb
Host smart-b3c45960-5f62-431b-a6fe-4a811d66006e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692677694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2692677694
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1567415992
Short name T1051
Test name
Test status
Simulation time 11827217 ps
CPU time 0.71 seconds
Started Jul 30 06:46:53 PM PDT 24
Finished Jul 30 06:46:54 PM PDT 24
Peak memory 205952 kb
Host smart-2a4214d1-f724-4be2-b7cb-da1788e01d5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567415992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1567415992
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4208996585
Short name T1033
Test name
Test status
Simulation time 91362353 ps
CPU time 2.47 seconds
Started Jul 30 06:46:54 PM PDT 24
Finished Jul 30 06:46:57 PM PDT 24
Peak memory 206208 kb
Host smart-cc756c0f-b4ce-4a37-8a26-2cde84284b8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208996585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.4208996585
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3005826680
Short name T120
Test name
Test status
Simulation time 339412994 ps
CPU time 3.49 seconds
Started Jul 30 06:47:03 PM PDT 24
Finished Jul 30 06:47:07 PM PDT 24
Peak memory 214612 kb
Host smart-e4ed5961-d725-4dcf-acfa-733fc4898f5f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005826680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.3005826680
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.4225467331
Short name T992
Test name
Test status
Simulation time 647850934 ps
CPU time 12.38 seconds
Started Jul 30 06:47:00 PM PDT 24
Finished Jul 30 06:47:13 PM PDT 24
Peak memory 214800 kb
Host smart-bc2ca38a-c852-4233-926f-6948fc313ed9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225467331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.4225467331
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.455556774
Short name T1077
Test name
Test status
Simulation time 35050765 ps
CPU time 1.88 seconds
Started Jul 30 06:46:59 PM PDT 24
Finished Jul 30 06:47:01 PM PDT 24
Peak memory 222552 kb
Host smart-8a0accdc-b771-4409-820a-0b72adbdce5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455556774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.455556774
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1760105926
Short name T1013
Test name
Test status
Simulation time 52969703 ps
CPU time 2.53 seconds
Started Jul 30 06:46:59 PM PDT 24
Finished Jul 30 06:47:02 PM PDT 24
Peak memory 206268 kb
Host smart-db3e5df6-eb0d-4011-8a1c-4b723c2aeffb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760105926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.1760105926
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3862664555
Short name T986
Test name
Test status
Simulation time 53333796 ps
CPU time 1.58 seconds
Started Jul 30 06:46:59 PM PDT 24
Finished Jul 30 06:47:01 PM PDT 24
Peak memory 214572 kb
Host smart-8ad0108a-a52a-4187-a655-79ffc3f02bb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862664555 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3862664555
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2514629883
Short name T1027
Test name
Test status
Simulation time 22831087 ps
CPU time 1.31 seconds
Started Jul 30 06:46:59 PM PDT 24
Finished Jul 30 06:47:01 PM PDT 24
Peak memory 206116 kb
Host smart-72dad6a6-d308-43f6-9f24-f7456bc5c40a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514629883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2514629883
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1165029508
Short name T1043
Test name
Test status
Simulation time 9185361 ps
CPU time 0.72 seconds
Started Jul 30 06:47:04 PM PDT 24
Finished Jul 30 06:47:05 PM PDT 24
Peak memory 205872 kb
Host smart-d6e7b3cf-d1f3-4e9c-809a-406101648eec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165029508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1165029508
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2661528746
Short name T969
Test name
Test status
Simulation time 54086599 ps
CPU time 2.31 seconds
Started Jul 30 06:47:03 PM PDT 24
Finished Jul 30 06:47:06 PM PDT 24
Peak memory 206152 kb
Host smart-f1404203-74fa-48d0-9997-a2964fb3a419
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661528746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2661528746
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2509846781
Short name T1026
Test name
Test status
Simulation time 2156969530 ps
CPU time 3.74 seconds
Started Jul 30 06:46:58 PM PDT 24
Finished Jul 30 06:47:02 PM PDT 24
Peak memory 214680 kb
Host smart-1837c1c0-3c7d-4e37-aa40-7f217db0d3f6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509846781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2509846781
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3245680155
Short name T111
Test name
Test status
Simulation time 200851857 ps
CPU time 5.3 seconds
Started Jul 30 06:47:03 PM PDT 24
Finished Jul 30 06:47:10 PM PDT 24
Peak memory 214688 kb
Host smart-72012791-e90c-4d6d-9b08-9f2aaf3e646a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245680155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3245680155
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1666648648
Short name T983
Test name
Test status
Simulation time 42267159 ps
CPU time 2.72 seconds
Started Jul 30 06:47:00 PM PDT 24
Finished Jul 30 06:47:03 PM PDT 24
Peak memory 214452 kb
Host smart-f12f8d01-8fd8-4b01-893f-0267ddc60611
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666648648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1666648648
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2529962697
Short name T175
Test name
Test status
Simulation time 392594847 ps
CPU time 8.35 seconds
Started Jul 30 06:46:59 PM PDT 24
Finished Jul 30 06:47:08 PM PDT 24
Peak memory 214356 kb
Host smart-78d641b9-5d72-46f7-bc6a-14ef0e2efce7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529962697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2529962697
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3994237684
Short name T1074
Test name
Test status
Simulation time 87129913 ps
CPU time 1.71 seconds
Started Jul 30 06:46:58 PM PDT 24
Finished Jul 30 06:46:59 PM PDT 24
Peak memory 214336 kb
Host smart-b6c756c2-7b36-48d5-9a59-a188b146a8b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994237684 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3994237684
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3692957519
Short name T1021
Test name
Test status
Simulation time 24867202 ps
CPU time 1.24 seconds
Started Jul 30 06:46:58 PM PDT 24
Finished Jul 30 06:47:00 PM PDT 24
Peak memory 206172 kb
Host smart-dc003d36-0eec-4101-9ce7-14e3f626bb8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692957519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3692957519
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2532752790
Short name T922
Test name
Test status
Simulation time 13522037 ps
CPU time 0.79 seconds
Started Jul 30 06:47:00 PM PDT 24
Finished Jul 30 06:47:02 PM PDT 24
Peak memory 206092 kb
Host smart-32fc3654-eadd-419f-b474-db8c3ed202b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532752790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2532752790
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1685175474
Short name T1006
Test name
Test status
Simulation time 388476983 ps
CPU time 1.68 seconds
Started Jul 30 06:46:56 PM PDT 24
Finished Jul 30 06:46:58 PM PDT 24
Peak memory 206196 kb
Host smart-88e9b844-4344-40af-aa54-221cde28b9e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685175474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1685175474
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.719262274
Short name T114
Test name
Test status
Simulation time 187438070 ps
CPU time 1.71 seconds
Started Jul 30 06:46:54 PM PDT 24
Finished Jul 30 06:46:56 PM PDT 24
Peak memory 214724 kb
Host smart-37399a3e-69fe-4263-b4d6-6612d57dca9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719262274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.719262274
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2113313178
Short name T118
Test name
Test status
Simulation time 83781761 ps
CPU time 4.48 seconds
Started Jul 30 06:46:43 PM PDT 24
Finished Jul 30 06:46:47 PM PDT 24
Peak memory 214648 kb
Host smart-949b2197-45d8-4115-b606-1d8d8c9cfb8e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113313178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2113313178
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2701540222
Short name T1050
Test name
Test status
Simulation time 74462065 ps
CPU time 2.63 seconds
Started Jul 30 06:47:03 PM PDT 24
Finished Jul 30 06:47:07 PM PDT 24
Peak memory 214472 kb
Host smart-ade66f50-8327-4927-af3e-97921476b5ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701540222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2701540222
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.379928590
Short name T947
Test name
Test status
Simulation time 58602668 ps
CPU time 2.22 seconds
Started Jul 30 06:46:57 PM PDT 24
Finished Jul 30 06:46:59 PM PDT 24
Peak memory 214376 kb
Host smart-9d8b889a-42a1-4a6a-98f8-5fdfff979c7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379928590 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.379928590
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1204422661
Short name T1069
Test name
Test status
Simulation time 29140665 ps
CPU time 0.9 seconds
Started Jul 30 06:46:59 PM PDT 24
Finished Jul 30 06:47:01 PM PDT 24
Peak memory 206084 kb
Host smart-b98ded25-9015-4dc7-917e-8a10f4b08ea0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204422661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1204422661
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2946283367
Short name T921
Test name
Test status
Simulation time 11261988 ps
CPU time 0.74 seconds
Started Jul 30 06:47:00 PM PDT 24
Finished Jul 30 06:47:01 PM PDT 24
Peak memory 205872 kb
Host smart-55db48f6-b051-4a48-9f5d-d1fe273f5e8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946283367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2946283367
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3803960874
Short name T1040
Test name
Test status
Simulation time 773395881 ps
CPU time 3.97 seconds
Started Jul 30 06:46:46 PM PDT 24
Finished Jul 30 06:46:50 PM PDT 24
Peak memory 206192 kb
Host smart-111e8bd5-117a-4bd0-be24-0f4042a70e34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803960874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3803960874
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3857271302
Short name T112
Test name
Test status
Simulation time 127028359 ps
CPU time 3.65 seconds
Started Jul 30 06:46:59 PM PDT 24
Finished Jul 30 06:47:04 PM PDT 24
Peak memory 218552 kb
Host smart-81b1574e-ed58-4f21-abb5-6450abfc9c86
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857271302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3857271302
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.4072593060
Short name T973
Test name
Test status
Simulation time 5014417943 ps
CPU time 13.22 seconds
Started Jul 30 06:47:01 PM PDT 24
Finished Jul 30 06:47:15 PM PDT 24
Peak memory 214672 kb
Host smart-45fa1ee2-5cb8-4d0f-8529-3ac65c24e33c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072593060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.4072593060
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1885569900
Short name T920
Test name
Test status
Simulation time 182234022 ps
CPU time 2.49 seconds
Started Jul 30 06:47:08 PM PDT 24
Finished Jul 30 06:47:10 PM PDT 24
Peak memory 214532 kb
Host smart-bc0b305d-3174-4dde-a1d3-9e19178d3ca8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885569900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1885569900
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3471993234
Short name T162
Test name
Test status
Simulation time 403513128 ps
CPU time 5.32 seconds
Started Jul 30 06:46:50 PM PDT 24
Finished Jul 30 06:46:56 PM PDT 24
Peak memory 214276 kb
Host smart-0ddaba44-132f-4a6f-9519-a1d8a773fa8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471993234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3471993234
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1632573767
Short name T1046
Test name
Test status
Simulation time 102781938 ps
CPU time 2.05 seconds
Started Jul 30 06:46:59 PM PDT 24
Finished Jul 30 06:47:02 PM PDT 24
Peak memory 214440 kb
Host smart-b40f4e44-c4dd-48db-8ff8-9686c9333e73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632573767 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1632573767
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3784516758
Short name T961
Test name
Test status
Simulation time 24501939 ps
CPU time 1.03 seconds
Started Jul 30 06:47:01 PM PDT 24
Finished Jul 30 06:47:03 PM PDT 24
Peak memory 206084 kb
Host smart-93ceb28d-ff69-42f5-9ce5-cc999511bb9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784516758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3784516758
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2726268847
Short name T1079
Test name
Test status
Simulation time 54913614 ps
CPU time 0.72 seconds
Started Jul 30 06:46:53 PM PDT 24
Finished Jul 30 06:46:54 PM PDT 24
Peak memory 205848 kb
Host smart-ddf7a064-729b-4735-ae6f-b1239545ff73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726268847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2726268847
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2586747761
Short name T943
Test name
Test status
Simulation time 42589717 ps
CPU time 1.28 seconds
Started Jul 30 06:46:58 PM PDT 24
Finished Jul 30 06:46:59 PM PDT 24
Peak memory 206236 kb
Host smart-ddbc34de-733d-423b-98ae-18e2ce5478b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586747761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2586747761
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3079382177
Short name T1066
Test name
Test status
Simulation time 237529875 ps
CPU time 3.7 seconds
Started Jul 30 06:46:47 PM PDT 24
Finished Jul 30 06:46:51 PM PDT 24
Peak memory 214456 kb
Host smart-c443f1c3-f730-4995-988b-66114de51370
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079382177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3079382177
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1310303376
Short name T919
Test name
Test status
Simulation time 90209416 ps
CPU time 1.49 seconds
Started Jul 30 06:46:59 PM PDT 24
Finished Jul 30 06:47:01 PM PDT 24
Peak memory 206324 kb
Host smart-7fd0952c-2586-4275-8574-1e568bc3e665
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310303376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1310303376
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1849037460
Short name T1032
Test name
Test status
Simulation time 117035366 ps
CPU time 2.75 seconds
Started Jul 30 06:47:03 PM PDT 24
Finished Jul 30 06:47:07 PM PDT 24
Peak memory 206288 kb
Host smart-c62f4eee-9b06-4b1f-8252-e0ac80de324a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849037460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1849037460
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2758830911
Short name T965
Test name
Test status
Simulation time 26719253 ps
CPU time 1.46 seconds
Started Jul 30 06:47:11 PM PDT 24
Finished Jul 30 06:47:12 PM PDT 24
Peak memory 206276 kb
Host smart-7285fbf5-fd33-4824-8018-fbd9bcc0bacb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758830911 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2758830911
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.4254828602
Short name T148
Test name
Test status
Simulation time 19394638 ps
CPU time 0.92 seconds
Started Jul 30 06:46:49 PM PDT 24
Finished Jul 30 06:46:50 PM PDT 24
Peak memory 205880 kb
Host smart-063a0aeb-5b16-4172-90f2-f919ee55ac79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254828602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.4254828602
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1756096931
Short name T955
Test name
Test status
Simulation time 49087027 ps
CPU time 0.72 seconds
Started Jul 30 06:46:54 PM PDT 24
Finished Jul 30 06:46:54 PM PDT 24
Peak memory 205992 kb
Host smart-94d4497d-63be-43e7-a30e-c2ed265f98f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756096931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1756096931
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1321344230
Short name T966
Test name
Test status
Simulation time 22557574 ps
CPU time 1.54 seconds
Started Jul 30 06:46:55 PM PDT 24
Finished Jul 30 06:46:57 PM PDT 24
Peak memory 206084 kb
Host smart-f8d0a624-d0a1-419f-bc85-304dd41757c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321344230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1321344230
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3902024392
Short name T1042
Test name
Test status
Simulation time 88800303 ps
CPU time 2.55 seconds
Started Jul 30 06:46:58 PM PDT 24
Finished Jul 30 06:47:02 PM PDT 24
Peak memory 214824 kb
Host smart-cbc094aa-0b66-47c9-9311-63b094a388a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902024392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3902024392
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.538340390
Short name T980
Test name
Test status
Simulation time 275708152 ps
CPU time 5.77 seconds
Started Jul 30 06:47:00 PM PDT 24
Finished Jul 30 06:47:06 PM PDT 24
Peak memory 214668 kb
Host smart-3c9886a2-bdbc-44b8-959e-6be426ae4b1f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538340390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_shadow_reg_errors_with_csr_rw.538340390
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1107514834
Short name T927
Test name
Test status
Simulation time 94242131 ps
CPU time 2.72 seconds
Started Jul 30 06:47:03 PM PDT 24
Finished Jul 30 06:47:07 PM PDT 24
Peak memory 214400 kb
Host smart-8b66b2cc-d696-4f50-b8eb-4009673c5d69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107514834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1107514834
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2169610025
Short name T177
Test name
Test status
Simulation time 627137591 ps
CPU time 4.44 seconds
Started Jul 30 06:46:56 PM PDT 24
Finished Jul 30 06:47:00 PM PDT 24
Peak memory 214372 kb
Host smart-2011fe1b-c641-4360-8cae-595f6f8554c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169610025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2169610025
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1702288532
Short name T976
Test name
Test status
Simulation time 193310980 ps
CPU time 1.44 seconds
Started Jul 30 06:47:08 PM PDT 24
Finished Jul 30 06:47:10 PM PDT 24
Peak memory 206264 kb
Host smart-eab3ce3a-b41e-4593-bc74-8192eec7d6fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702288532 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1702288532
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.626844573
Short name T147
Test name
Test status
Simulation time 68445873 ps
CPU time 1.06 seconds
Started Jul 30 06:47:02 PM PDT 24
Finished Jul 30 06:47:04 PM PDT 24
Peak memory 206144 kb
Host smart-77bc5f40-b977-4ad9-996c-d88de2e8c538
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626844573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.626844573
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3531119768
Short name T1065
Test name
Test status
Simulation time 9842059 ps
CPU time 0.68 seconds
Started Jul 30 06:47:07 PM PDT 24
Finished Jul 30 06:47:08 PM PDT 24
Peak memory 205964 kb
Host smart-8aaa3c8e-e8c6-4777-8b40-6a9f924d1c8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531119768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3531119768
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3993530378
Short name T932
Test name
Test status
Simulation time 174125212 ps
CPU time 2.03 seconds
Started Jul 30 06:46:53 PM PDT 24
Finished Jul 30 06:46:55 PM PDT 24
Peak memory 206260 kb
Host smart-fb06ebdb-ba9e-4d1c-8d88-1bc7e516d38f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993530378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.3993530378
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2084159619
Short name T959
Test name
Test status
Simulation time 130658304 ps
CPU time 2.78 seconds
Started Jul 30 06:46:59 PM PDT 24
Finished Jul 30 06:47:02 PM PDT 24
Peak memory 214692 kb
Host smart-7a84660a-3e6a-4cbd-9ae6-13381999fbc5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084159619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2084159619
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1354524915
Short name T1016
Test name
Test status
Simulation time 1265076790 ps
CPU time 8.91 seconds
Started Jul 30 06:47:04 PM PDT 24
Finished Jul 30 06:47:14 PM PDT 24
Peak memory 214572 kb
Host smart-15062446-fbd9-4833-a590-dba4595ff04e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354524915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1354524915
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2648366347
Short name T1060
Test name
Test status
Simulation time 138387466 ps
CPU time 2.05 seconds
Started Jul 30 06:47:02 PM PDT 24
Finished Jul 30 06:47:05 PM PDT 24
Peak memory 214420 kb
Host smart-bd9b982d-091e-4763-b5ae-84a091d6db7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648366347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2648366347
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3095313345
Short name T168
Test name
Test status
Simulation time 402480737 ps
CPU time 5.31 seconds
Started Jul 30 06:46:55 PM PDT 24
Finished Jul 30 06:47:00 PM PDT 24
Peak memory 214324 kb
Host smart-8a1dbad3-b0cb-4a47-bb4f-6f2a7618bc32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095313345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3095313345
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.217670968
Short name T1061
Test name
Test status
Simulation time 759413317 ps
CPU time 5.29 seconds
Started Jul 30 06:46:58 PM PDT 24
Finished Jul 30 06:47:04 PM PDT 24
Peak memory 205960 kb
Host smart-ca5e099a-e032-4047-9308-ca1a910d0af2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217670968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.217670968
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3260713289
Short name T1076
Test name
Test status
Simulation time 261962377 ps
CPU time 6.59 seconds
Started Jul 30 06:46:59 PM PDT 24
Finished Jul 30 06:47:06 PM PDT 24
Peak memory 206164 kb
Host smart-80b91a65-a4d8-4aa0-955c-2a11e401820c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260713289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
260713289
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2375464591
Short name T1009
Test name
Test status
Simulation time 16551504 ps
CPU time 1.22 seconds
Started Jul 30 06:46:44 PM PDT 24
Finished Jul 30 06:46:45 PM PDT 24
Peak memory 206148 kb
Host smart-ab4d15d5-b7b7-4c87-8116-06c69a8204ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375464591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2
375464591
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3883426960
Short name T990
Test name
Test status
Simulation time 29266878 ps
CPU time 1.34 seconds
Started Jul 30 06:46:38 PM PDT 24
Finished Jul 30 06:46:40 PM PDT 24
Peak memory 214412 kb
Host smart-9ef55a33-9a23-4017-8a03-383cf5ffb89c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883426960 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3883426960
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2041044540
Short name T1053
Test name
Test status
Simulation time 24214904 ps
CPU time 1.06 seconds
Started Jul 30 06:46:28 PM PDT 24
Finished Jul 30 06:46:29 PM PDT 24
Peak memory 206168 kb
Host smart-d274bd19-342e-4b8a-8ef4-ad598307c6b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041044540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2041044540
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.518795378
Short name T948
Test name
Test status
Simulation time 191329392 ps
CPU time 0.87 seconds
Started Jul 30 06:46:37 PM PDT 24
Finished Jul 30 06:46:38 PM PDT 24
Peak memory 206080 kb
Host smart-fb680fab-7c5e-4d9b-a41c-d7d77a7bee1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518795378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.518795378
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2516564828
Short name T1081
Test name
Test status
Simulation time 52028687 ps
CPU time 1.6 seconds
Started Jul 30 06:46:58 PM PDT 24
Finished Jul 30 06:46:59 PM PDT 24
Peak memory 206244 kb
Host smart-361616ab-6446-4da2-b6e8-db480cbd21fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516564828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2516564828
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3453530005
Short name T126
Test name
Test status
Simulation time 100724652 ps
CPU time 1.69 seconds
Started Jul 30 06:46:44 PM PDT 24
Finished Jul 30 06:46:46 PM PDT 24
Peak memory 214636 kb
Host smart-7744ec2e-f9fa-43ad-b2bb-326c6d924a16
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453530005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3453530005
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2426549649
Short name T1007
Test name
Test status
Simulation time 235455065 ps
CPU time 8.26 seconds
Started Jul 30 06:46:50 PM PDT 24
Finished Jul 30 06:46:59 PM PDT 24
Peak memory 220764 kb
Host smart-db929cbd-55aa-4e87-96d9-7d10acfd075d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426549649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2426549649
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3327466495
Short name T994
Test name
Test status
Simulation time 130919077 ps
CPU time 2.13 seconds
Started Jul 30 06:46:52 PM PDT 24
Finished Jul 30 06:46:55 PM PDT 24
Peak memory 214524 kb
Host smart-288ea959-1882-4f02-92aa-229ce833d1c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327466495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3327466495
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1731545230
Short name T1014
Test name
Test status
Simulation time 27187486 ps
CPU time 0.91 seconds
Started Jul 30 06:47:02 PM PDT 24
Finished Jul 30 06:47:04 PM PDT 24
Peak memory 206064 kb
Host smart-6e6a3fc0-0818-4faf-bf70-330671a27f95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731545230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1731545230
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.295684473
Short name T984
Test name
Test status
Simulation time 9166429 ps
CPU time 0.75 seconds
Started Jul 30 06:47:04 PM PDT 24
Finished Jul 30 06:47:05 PM PDT 24
Peak memory 205956 kb
Host smart-3d79f59c-7e46-4f07-828d-9e70a5e642d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295684473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.295684473
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2041834611
Short name T1000
Test name
Test status
Simulation time 13363796 ps
CPU time 0.73 seconds
Started Jul 30 06:46:59 PM PDT 24
Finished Jul 30 06:47:01 PM PDT 24
Peak memory 205912 kb
Host smart-9c2aed3a-104b-4925-8231-98a563218682
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041834611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2041834611
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1794231939
Short name T1055
Test name
Test status
Simulation time 22579456 ps
CPU time 0.74 seconds
Started Jul 30 06:47:03 PM PDT 24
Finished Jul 30 06:47:05 PM PDT 24
Peak memory 205948 kb
Host smart-895beaba-17f3-4aa1-8c9a-91217188cf6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794231939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1794231939
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3632517646
Short name T940
Test name
Test status
Simulation time 33652890 ps
CPU time 0.78 seconds
Started Jul 30 06:46:57 PM PDT 24
Finished Jul 30 06:46:58 PM PDT 24
Peak memory 205972 kb
Host smart-a42af26e-bf48-4ad5-8540-68ca2b49b322
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632517646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3632517646
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1422303979
Short name T929
Test name
Test status
Simulation time 33293156 ps
CPU time 0.79 seconds
Started Jul 30 06:47:00 PM PDT 24
Finished Jul 30 06:47:01 PM PDT 24
Peak memory 205960 kb
Host smart-68f1fb97-2c2b-43bc-9a8a-184203e62875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422303979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1422303979
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1949652880
Short name T997
Test name
Test status
Simulation time 117357993 ps
CPU time 0.75 seconds
Started Jul 30 06:46:56 PM PDT 24
Finished Jul 30 06:46:57 PM PDT 24
Peak memory 205944 kb
Host smart-67bed80f-f00e-42b9-95f3-73f8b8d65f47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949652880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1949652880
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3581246973
Short name T925
Test name
Test status
Simulation time 11743382 ps
CPU time 0.71 seconds
Started Jul 30 06:47:09 PM PDT 24
Finished Jul 30 06:47:09 PM PDT 24
Peak memory 205992 kb
Host smart-31d1319e-791d-4095-8bc5-8629f1cedce0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581246973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3581246973
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.950124708
Short name T937
Test name
Test status
Simulation time 12605491 ps
CPU time 0.73 seconds
Started Jul 30 06:47:01 PM PDT 24
Finished Jul 30 06:47:02 PM PDT 24
Peak memory 205976 kb
Host smart-32a95f06-95d7-4b31-b9b5-e9cb339d4bb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950124708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.950124708
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2356495682
Short name T1020
Test name
Test status
Simulation time 36054158 ps
CPU time 0.81 seconds
Started Jul 30 06:47:02 PM PDT 24
Finished Jul 30 06:47:04 PM PDT 24
Peak memory 205984 kb
Host smart-7647e548-e12d-4a74-bd7c-66ecbf5e363a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356495682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2356495682
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2482023202
Short name T1045
Test name
Test status
Simulation time 529457412 ps
CPU time 7.42 seconds
Started Jul 30 06:47:05 PM PDT 24
Finished Jul 30 06:47:13 PM PDT 24
Peak memory 206156 kb
Host smart-d6f8252e-6a42-4c68-9451-fa44eeb9baa2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482023202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
482023202
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3066277875
Short name T1035
Test name
Test status
Simulation time 256411504 ps
CPU time 14.36 seconds
Started Jul 30 06:46:44 PM PDT 24
Finished Jul 30 06:46:59 PM PDT 24
Peak memory 206108 kb
Host smart-ed96dae9-47eb-44b7-b73d-205ffacba4c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066277875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
066277875
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2110582001
Short name T981
Test name
Test status
Simulation time 43875171 ps
CPU time 1.23 seconds
Started Jul 30 06:47:01 PM PDT 24
Finished Jul 30 06:47:03 PM PDT 24
Peak memory 206148 kb
Host smart-aa05141d-8af3-4eee-940d-a941e3bb98e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110582001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
110582001
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.4081254222
Short name T974
Test name
Test status
Simulation time 195673845 ps
CPU time 1.64 seconds
Started Jul 30 06:46:53 PM PDT 24
Finished Jul 30 06:46:55 PM PDT 24
Peak memory 214488 kb
Host smart-b3c09bd2-b766-4907-be2d-c8221b1f13c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081254222 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.4081254222
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.549819767
Short name T1002
Test name
Test status
Simulation time 33793480 ps
CPU time 0.99 seconds
Started Jul 30 06:46:50 PM PDT 24
Finished Jul 30 06:46:51 PM PDT 24
Peak memory 206016 kb
Host smart-a4018a5d-1601-499c-bdc8-6c7a3890c003
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549819767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.549819767
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3917238332
Short name T942
Test name
Test status
Simulation time 8947901 ps
CPU time 0.85 seconds
Started Jul 30 06:46:45 PM PDT 24
Finished Jul 30 06:46:46 PM PDT 24
Peak memory 205976 kb
Host smart-d72ebba7-e329-49f2-a7da-81a75ab8113d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917238332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3917238332
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.748190719
Short name T149
Test name
Test status
Simulation time 62610389 ps
CPU time 1.7 seconds
Started Jul 30 06:46:47 PM PDT 24
Finished Jul 30 06:46:49 PM PDT 24
Peak memory 206120 kb
Host smart-8a5d4407-23c5-452c-b0db-209616401ecd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748190719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.748190719
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.847253252
Short name T1044
Test name
Test status
Simulation time 173863873 ps
CPU time 3.87 seconds
Started Jul 30 06:46:47 PM PDT 24
Finished Jul 30 06:46:51 PM PDT 24
Peak memory 214660 kb
Host smart-62346424-a50b-491b-b86e-035cef2f1969
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847253252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.847253252
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1030469090
Short name T945
Test name
Test status
Simulation time 432530149 ps
CPU time 5.49 seconds
Started Jul 30 06:46:46 PM PDT 24
Finished Jul 30 06:46:52 PM PDT 24
Peak memory 214672 kb
Host smart-157ab17c-cf07-4def-a3ef-821a3307dc64
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030469090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1030469090
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1518322763
Short name T967
Test name
Test status
Simulation time 417118553 ps
CPU time 2 seconds
Started Jul 30 06:46:49 PM PDT 24
Finished Jul 30 06:46:51 PM PDT 24
Peak memory 214296 kb
Host smart-a413a45a-8d40-42ea-a86a-8cc61cef4f35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518322763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1518322763
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1975851292
Short name T178
Test name
Test status
Simulation time 225124113 ps
CPU time 8.51 seconds
Started Jul 30 06:47:00 PM PDT 24
Finished Jul 30 06:47:09 PM PDT 24
Peak memory 214376 kb
Host smart-d5fe0280-f4be-42be-9d4c-982b994eef83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975851292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1975851292
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3084916607
Short name T918
Test name
Test status
Simulation time 23824138 ps
CPU time 0.87 seconds
Started Jul 30 06:47:01 PM PDT 24
Finished Jul 30 06:47:03 PM PDT 24
Peak memory 205956 kb
Host smart-91f09450-1116-4473-96d7-00f860d52e9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084916607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3084916607
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1322628533
Short name T1018
Test name
Test status
Simulation time 12829474 ps
CPU time 0.83 seconds
Started Jul 30 06:47:00 PM PDT 24
Finished Jul 30 06:47:01 PM PDT 24
Peak memory 206008 kb
Host smart-b9e015b7-8c90-4f4f-b56a-397b1542d95c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322628533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1322628533
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3277300089
Short name T1084
Test name
Test status
Simulation time 9976268 ps
CPU time 0.7 seconds
Started Jul 30 06:47:04 PM PDT 24
Finished Jul 30 06:47:05 PM PDT 24
Peak memory 205872 kb
Host smart-80d0717a-fb61-40e9-bd38-a0f7cbac84bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277300089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3277300089
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2230647748
Short name T1028
Test name
Test status
Simulation time 12592614 ps
CPU time 0.87 seconds
Started Jul 30 06:47:02 PM PDT 24
Finished Jul 30 06:47:04 PM PDT 24
Peak memory 205904 kb
Host smart-2cdeae16-264c-46df-91fd-b69b5fd67d86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230647748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2230647748
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.617853738
Short name T1072
Test name
Test status
Simulation time 28086374 ps
CPU time 0.87 seconds
Started Jul 30 06:47:03 PM PDT 24
Finished Jul 30 06:47:05 PM PDT 24
Peak memory 205888 kb
Host smart-50b5a30a-aed9-433f-8199-2026d4c3c60c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617853738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.617853738
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3531324260
Short name T1068
Test name
Test status
Simulation time 22633770 ps
CPU time 0.72 seconds
Started Jul 30 06:47:03 PM PDT 24
Finished Jul 30 06:47:05 PM PDT 24
Peak memory 205872 kb
Host smart-c5851930-0a3f-4972-baaa-ff8d3491ce16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531324260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3531324260
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2283845720
Short name T1024
Test name
Test status
Simulation time 10365235 ps
CPU time 0.83 seconds
Started Jul 30 06:46:57 PM PDT 24
Finished Jul 30 06:46:58 PM PDT 24
Peak memory 205936 kb
Host smart-90c74677-2d13-453e-a8c0-f33f06c02598
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283845720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2283845720
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.370814612
Short name T1039
Test name
Test status
Simulation time 18460748 ps
CPU time 0.87 seconds
Started Jul 30 06:47:00 PM PDT 24
Finished Jul 30 06:47:02 PM PDT 24
Peak memory 205948 kb
Host smart-7b06931d-72c0-4cf2-9da3-a406b31d6306
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370814612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.370814612
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.4030856396
Short name T987
Test name
Test status
Simulation time 12908424 ps
CPU time 0.87 seconds
Started Jul 30 06:47:03 PM PDT 24
Finished Jul 30 06:47:05 PM PDT 24
Peak memory 205848 kb
Host smart-22e9fe87-616b-4224-9806-619d4103957f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030856396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.4030856396
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2803033368
Short name T936
Test name
Test status
Simulation time 13885509 ps
CPU time 0.88 seconds
Started Jul 30 06:47:01 PM PDT 24
Finished Jul 30 06:47:03 PM PDT 24
Peak memory 206140 kb
Host smart-cc6c336f-84cf-4efd-9047-7c74070258c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803033368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2803033368
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2226656986
Short name T941
Test name
Test status
Simulation time 375852019 ps
CPU time 9.03 seconds
Started Jul 30 06:46:44 PM PDT 24
Finished Jul 30 06:46:53 PM PDT 24
Peak memory 206184 kb
Host smart-2930e139-f44b-4fdf-a9e6-2f49da0409af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226656986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
226656986
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.4250984308
Short name T939
Test name
Test status
Simulation time 640646625 ps
CPU time 14.7 seconds
Started Jul 30 06:46:50 PM PDT 24
Finished Jul 30 06:47:05 PM PDT 24
Peak memory 206200 kb
Host smart-d88fddbc-d1a2-42fa-8ca1-9f7cc7022a68
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250984308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.4
250984308
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2268412237
Short name T991
Test name
Test status
Simulation time 37471572 ps
CPU time 1.64 seconds
Started Jul 30 06:46:51 PM PDT 24
Finished Jul 30 06:46:53 PM PDT 24
Peak memory 206088 kb
Host smart-90252a80-9019-4867-a7fe-9a7319071e77
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268412237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
268412237
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.4032805771
Short name T160
Test name
Test status
Simulation time 27968236 ps
CPU time 1.24 seconds
Started Jul 30 06:46:51 PM PDT 24
Finished Jul 30 06:46:52 PM PDT 24
Peak memory 214412 kb
Host smart-17fda5a8-c4b4-4675-807d-bcf7d701b312
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032805771 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.4032805771
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3769855738
Short name T144
Test name
Test status
Simulation time 18623064 ps
CPU time 1.1 seconds
Started Jul 30 06:47:00 PM PDT 24
Finished Jul 30 06:47:01 PM PDT 24
Peak memory 206088 kb
Host smart-90d2a556-0ab4-437d-95f3-9264b1c45a88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769855738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3769855738
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.4172003276
Short name T930
Test name
Test status
Simulation time 24413670 ps
CPU time 0.69 seconds
Started Jul 30 06:46:48 PM PDT 24
Finished Jul 30 06:46:49 PM PDT 24
Peak memory 205832 kb
Host smart-334c0e87-8d25-4bad-a849-623822f4b628
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172003276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.4172003276
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1457802331
Short name T1041
Test name
Test status
Simulation time 241773506 ps
CPU time 2.47 seconds
Started Jul 30 06:46:49 PM PDT 24
Finished Jul 30 06:46:51 PM PDT 24
Peak memory 205920 kb
Host smart-6064c1b7-f35c-4741-b813-76da8a4e7558
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457802331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1457802331
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3066083797
Short name T950
Test name
Test status
Simulation time 500677716 ps
CPU time 2.63 seconds
Started Jul 30 06:46:45 PM PDT 24
Finished Jul 30 06:46:47 PM PDT 24
Peak memory 214552 kb
Host smart-a34b99d8-08c9-4713-85ce-067b06a9bd96
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066083797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3066083797
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1199091999
Short name T1071
Test name
Test status
Simulation time 198004447 ps
CPU time 5.32 seconds
Started Jul 30 06:46:50 PM PDT 24
Finished Jul 30 06:46:56 PM PDT 24
Peak memory 222924 kb
Host smart-4001f635-9fa2-4f0a-8f34-fa115912171b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199091999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1199091999
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2175550055
Short name T1025
Test name
Test status
Simulation time 245528284 ps
CPU time 4.55 seconds
Started Jul 30 06:46:46 PM PDT 24
Finished Jul 30 06:46:51 PM PDT 24
Peak memory 215488 kb
Host smart-83421f2b-ed8d-407c-bf7f-9d5621dfb7cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175550055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2175550055
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.722444560
Short name T946
Test name
Test status
Simulation time 151590304 ps
CPU time 3.74 seconds
Started Jul 30 06:46:45 PM PDT 24
Finished Jul 30 06:46:49 PM PDT 24
Peak memory 214432 kb
Host smart-2de60c89-3c3a-45cc-8116-43543cbc021e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722444560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
722444560
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1303004953
Short name T962
Test name
Test status
Simulation time 52046851 ps
CPU time 0.73 seconds
Started Jul 30 06:47:05 PM PDT 24
Finished Jul 30 06:47:06 PM PDT 24
Peak memory 205948 kb
Host smart-a3c9365a-60ab-456d-a697-f53a007705ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303004953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1303004953
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3463187133
Short name T1063
Test name
Test status
Simulation time 12074062 ps
CPU time 0.94 seconds
Started Jul 30 06:47:05 PM PDT 24
Finished Jul 30 06:47:06 PM PDT 24
Peak memory 205872 kb
Host smart-ccdd15c0-a8da-4854-8e1a-96acd8ac68a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463187133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3463187133
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2365829770
Short name T995
Test name
Test status
Simulation time 11025969 ps
CPU time 0.71 seconds
Started Jul 30 06:47:01 PM PDT 24
Finished Jul 30 06:47:03 PM PDT 24
Peak memory 205872 kb
Host smart-e50929e1-b136-4415-a19b-56f28361ba2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365829770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2365829770
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3399925110
Short name T923
Test name
Test status
Simulation time 33266280 ps
CPU time 0.7 seconds
Started Jul 30 06:47:01 PM PDT 24
Finished Jul 30 06:47:03 PM PDT 24
Peak memory 205948 kb
Host smart-baa7ecfa-2a44-4952-9188-ebdae4b97601
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399925110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3399925110
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2825836574
Short name T1073
Test name
Test status
Simulation time 32080153 ps
CPU time 0.71 seconds
Started Jul 30 06:47:01 PM PDT 24
Finished Jul 30 06:47:03 PM PDT 24
Peak memory 205856 kb
Host smart-3bffe2fd-de5a-4527-8068-408ef5d9de7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825836574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2825836574
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.386507504
Short name T1034
Test name
Test status
Simulation time 8235156 ps
CPU time 0.69 seconds
Started Jul 30 06:46:57 PM PDT 24
Finished Jul 30 06:46:58 PM PDT 24
Peak memory 205916 kb
Host smart-9cf382f2-8ec2-4216-8cb3-271fb92d714d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386507504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.386507504
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.4143086871
Short name T1056
Test name
Test status
Simulation time 41951136 ps
CPU time 0.75 seconds
Started Jul 30 06:47:01 PM PDT 24
Finished Jul 30 06:47:02 PM PDT 24
Peak memory 205968 kb
Host smart-ca95c3db-63d0-4b72-9975-d4771ddb32b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143086871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.4143086871
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2074114724
Short name T934
Test name
Test status
Simulation time 10710286 ps
CPU time 0.73 seconds
Started Jul 30 06:47:01 PM PDT 24
Finished Jul 30 06:47:02 PM PDT 24
Peak memory 205868 kb
Host smart-982e39e6-cbb3-46b5-8683-975310fb4c66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074114724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2074114724
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3600610527
Short name T958
Test name
Test status
Simulation time 39817700 ps
CPU time 0.75 seconds
Started Jul 30 06:47:02 PM PDT 24
Finished Jul 30 06:47:04 PM PDT 24
Peak memory 205944 kb
Host smart-32726c92-0d3a-4e73-bc66-5fda2d3813c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600610527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3600610527
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.4074633129
Short name T1083
Test name
Test status
Simulation time 37555052 ps
CPU time 0.83 seconds
Started Jul 30 06:47:02 PM PDT 24
Finished Jul 30 06:47:04 PM PDT 24
Peak memory 205872 kb
Host smart-9d0a2260-464e-4501-8b36-8b9bf60c3897
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074633129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.4074633129
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2987767304
Short name T161
Test name
Test status
Simulation time 78826775 ps
CPU time 1.64 seconds
Started Jul 30 06:46:50 PM PDT 24
Finished Jul 30 06:46:52 PM PDT 24
Peak memory 206332 kb
Host smart-b33e939b-0809-4fb5-80e0-e204cc1161d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987767304 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2987767304
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1244737059
Short name T968
Test name
Test status
Simulation time 41563169 ps
CPU time 1.3 seconds
Started Jul 30 06:46:55 PM PDT 24
Finished Jul 30 06:46:57 PM PDT 24
Peak memory 206132 kb
Host smart-b875d8ec-687d-43b2-b2d9-1474daf128c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244737059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1244737059
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.950307960
Short name T1031
Test name
Test status
Simulation time 149581103 ps
CPU time 0.74 seconds
Started Jul 30 06:46:55 PM PDT 24
Finished Jul 30 06:46:56 PM PDT 24
Peak memory 205920 kb
Host smart-e224733e-348a-490c-ab73-5c582bea60ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950307960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.950307960
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1548758078
Short name T953
Test name
Test status
Simulation time 210604682 ps
CPU time 1.75 seconds
Started Jul 30 06:46:52 PM PDT 24
Finished Jul 30 06:46:54 PM PDT 24
Peak memory 206188 kb
Host smart-a25dd72e-fb64-4e6f-9d66-53ce32a87638
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548758078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.1548758078
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3459316555
Short name T952
Test name
Test status
Simulation time 119014650 ps
CPU time 1.8 seconds
Started Jul 30 06:46:59 PM PDT 24
Finished Jul 30 06:47:01 PM PDT 24
Peak memory 214608 kb
Host smart-ca0c6bd3-49d4-43f2-ba7b-ef711c3a9f0c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459316555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3459316555
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.935251541
Short name T1064
Test name
Test status
Simulation time 184013809 ps
CPU time 7.15 seconds
Started Jul 30 06:46:49 PM PDT 24
Finished Jul 30 06:46:56 PM PDT 24
Peak memory 214660 kb
Host smart-48443946-1eb0-4ce4-8a83-b20d5b6a7231
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935251541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.935251541
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3817897898
Short name T978
Test name
Test status
Simulation time 163209183 ps
CPU time 2.76 seconds
Started Jul 30 06:46:52 PM PDT 24
Finished Jul 30 06:46:55 PM PDT 24
Peak memory 216976 kb
Host smart-f759fcef-2297-40b1-ae87-172aac506fee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817897898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3817897898
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1789360943
Short name T1062
Test name
Test status
Simulation time 103637695 ps
CPU time 1.17 seconds
Started Jul 30 06:46:52 PM PDT 24
Finished Jul 30 06:46:53 PM PDT 24
Peak memory 206276 kb
Host smart-ac8d1e97-327c-42ce-818e-e3e76f48797a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789360943 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1789360943
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1572124466
Short name T970
Test name
Test status
Simulation time 47201826 ps
CPU time 1.06 seconds
Started Jul 30 06:46:55 PM PDT 24
Finished Jul 30 06:46:56 PM PDT 24
Peak memory 206148 kb
Host smart-79595b9b-a51f-41ff-ac0b-1a9afde12de8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572124466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1572124466
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2333334021
Short name T1054
Test name
Test status
Simulation time 15704051 ps
CPU time 0.85 seconds
Started Jul 30 06:47:01 PM PDT 24
Finished Jul 30 06:47:03 PM PDT 24
Peak memory 206096 kb
Host smart-bdd47e27-1a8d-4176-b8a8-8b92f50ac18d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333334021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2333334021
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1454504284
Short name T1047
Test name
Test status
Simulation time 37884521 ps
CPU time 1.7 seconds
Started Jul 30 06:46:47 PM PDT 24
Finished Jul 30 06:46:49 PM PDT 24
Peak memory 206316 kb
Host smart-54c4a476-7b91-447b-9ab8-0e8dba9df59d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454504284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1454504284
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.966038237
Short name T121
Test name
Test status
Simulation time 67198930 ps
CPU time 2.08 seconds
Started Jul 30 06:47:03 PM PDT 24
Finished Jul 30 06:47:06 PM PDT 24
Peak memory 214748 kb
Host smart-99beae35-fbbf-4051-959f-fb3c20ab1d39
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966038237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.966038237
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2216439464
Short name T125
Test name
Test status
Simulation time 133167619 ps
CPU time 5.87 seconds
Started Jul 30 06:47:01 PM PDT 24
Finished Jul 30 06:47:08 PM PDT 24
Peak memory 214684 kb
Host smart-41a6fc0f-2057-4c64-9321-572c3d749797
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216439464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2216439464
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3132663997
Short name T1004
Test name
Test status
Simulation time 515240020 ps
CPU time 5.62 seconds
Started Jul 30 06:47:02 PM PDT 24
Finished Jul 30 06:47:09 PM PDT 24
Peak memory 214316 kb
Host smart-fd15b3a4-d2ab-46c3-b625-cf030b11f591
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132663997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3132663997
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.134738440
Short name T173
Test name
Test status
Simulation time 129221304 ps
CPU time 5.33 seconds
Started Jul 30 06:46:58 PM PDT 24
Finished Jul 30 06:47:04 PM PDT 24
Peak memory 214380 kb
Host smart-fb577567-c086-4b06-aa1c-ff376d986ebf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134738440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
134738440
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.261703430
Short name T977
Test name
Test status
Simulation time 45206050 ps
CPU time 1.35 seconds
Started Jul 30 06:47:02 PM PDT 24
Finished Jul 30 06:47:04 PM PDT 24
Peak memory 206160 kb
Host smart-f1cd5cdd-d5e8-4e12-a6a1-c5d056d9aa27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261703430 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.261703430
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1630027948
Short name T1048
Test name
Test status
Simulation time 91890684 ps
CPU time 1.17 seconds
Started Jul 30 06:46:52 PM PDT 24
Finished Jul 30 06:46:53 PM PDT 24
Peak memory 206060 kb
Host smart-3308570c-abf3-406b-bdf6-26e939d44d43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630027948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1630027948
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.255194429
Short name T1019
Test name
Test status
Simulation time 115054073 ps
CPU time 0.73 seconds
Started Jul 30 06:47:01 PM PDT 24
Finished Jul 30 06:47:03 PM PDT 24
Peak memory 205916 kb
Host smart-e122fd19-d7ca-4b24-8a01-a8f73501ab7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255194429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.255194429
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2497772262
Short name T145
Test name
Test status
Simulation time 79514326 ps
CPU time 1.52 seconds
Started Jul 30 06:46:59 PM PDT 24
Finished Jul 30 06:47:01 PM PDT 24
Peak memory 206276 kb
Host smart-a3f6b96b-499b-4e34-8851-904211b7bb02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497772262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2497772262
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.474722464
Short name T115
Test name
Test status
Simulation time 58423654 ps
CPU time 1.4 seconds
Started Jul 30 06:47:01 PM PDT 24
Finished Jul 30 06:47:04 PM PDT 24
Peak memory 206176 kb
Host smart-e6f4b8c1-9d36-42e6-8bb9-219127fc16cc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474722464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.474722464
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.778794705
Short name T1017
Test name
Test status
Simulation time 787116274 ps
CPU time 15.22 seconds
Started Jul 30 06:47:01 PM PDT 24
Finished Jul 30 06:47:18 PM PDT 24
Peak memory 221396 kb
Host smart-1e9d95d2-bdcb-4d48-95b7-c9d15cf5c0d5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778794705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.778794705
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3384521680
Short name T1011
Test name
Test status
Simulation time 71529939 ps
CPU time 1.59 seconds
Started Jul 30 06:46:55 PM PDT 24
Finished Jul 30 06:46:57 PM PDT 24
Peak memory 206120 kb
Host smart-ec6e9606-b111-41f5-aa08-5f089244e73d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384521680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3384521680
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.678761850
Short name T1067
Test name
Test status
Simulation time 50709335 ps
CPU time 1.27 seconds
Started Jul 30 06:47:04 PM PDT 24
Finished Jul 30 06:47:06 PM PDT 24
Peak memory 206328 kb
Host smart-db347a62-c5b7-4dce-9b68-fd1e041d3950
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678761850 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.678761850
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2588167206
Short name T1080
Test name
Test status
Simulation time 53834208 ps
CPU time 0.86 seconds
Started Jul 30 06:46:56 PM PDT 24
Finished Jul 30 06:46:57 PM PDT 24
Peak memory 205988 kb
Host smart-70fcf122-3f5c-40cc-9a1e-8d864d7bdf7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588167206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2588167206
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.168273425
Short name T988
Test name
Test status
Simulation time 11821105 ps
CPU time 0.7 seconds
Started Jul 30 06:46:50 PM PDT 24
Finished Jul 30 06:46:50 PM PDT 24
Peak memory 205968 kb
Host smart-f68ea56d-8c6f-4f95-9d3e-b31c15558392
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168273425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.168273425
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1325473090
Short name T944
Test name
Test status
Simulation time 26400131 ps
CPU time 1.7 seconds
Started Jul 30 06:46:54 PM PDT 24
Finished Jul 30 06:46:56 PM PDT 24
Peak memory 206208 kb
Host smart-3f69feae-5616-4284-ba19-8f7d9643d68c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325473090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1325473090
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.726636819
Short name T122
Test name
Test status
Simulation time 263084973 ps
CPU time 2.7 seconds
Started Jul 30 06:46:50 PM PDT 24
Finished Jul 30 06:46:53 PM PDT 24
Peak memory 214628 kb
Host smart-c7d9a6f7-1070-4c77-987a-8610726f8b19
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726636819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow
_reg_errors.726636819
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2942797886
Short name T999
Test name
Test status
Simulation time 751603782 ps
CPU time 4.82 seconds
Started Jul 30 06:46:51 PM PDT 24
Finished Jul 30 06:46:56 PM PDT 24
Peak memory 214788 kb
Host smart-e0d63a42-86df-4b45-8b7a-2d9aea41bc04
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942797886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.2942797886
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3564990126
Short name T931
Test name
Test status
Simulation time 79887363 ps
CPU time 2.78 seconds
Started Jul 30 06:46:55 PM PDT 24
Finished Jul 30 06:46:58 PM PDT 24
Peak memory 217516 kb
Host smart-c6a348e9-e90e-42e5-a057-517704d52781
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564990126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3564990126
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2114289381
Short name T159
Test name
Test status
Simulation time 225798002 ps
CPU time 3.49 seconds
Started Jul 30 06:46:55 PM PDT 24
Finished Jul 30 06:46:58 PM PDT 24
Peak memory 206164 kb
Host smart-00450570-f71f-4942-8d46-9f756311bad1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114289381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2114289381
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.827357941
Short name T1059
Test name
Test status
Simulation time 93550661 ps
CPU time 1.32 seconds
Started Jul 30 06:46:50 PM PDT 24
Finished Jul 30 06:46:51 PM PDT 24
Peak memory 214500 kb
Host smart-6bf46608-229d-44bb-b0d7-399bbd80be79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827357941 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.827357941
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2548396834
Short name T1057
Test name
Test status
Simulation time 55992986 ps
CPU time 1.05 seconds
Started Jul 30 06:46:58 PM PDT 24
Finished Jul 30 06:47:00 PM PDT 24
Peak memory 206308 kb
Host smart-63f2ac6d-9e3f-43d9-a690-073dc59490e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548396834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2548396834
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2867756897
Short name T1008
Test name
Test status
Simulation time 157781159 ps
CPU time 0.9 seconds
Started Jul 30 06:46:57 PM PDT 24
Finished Jul 30 06:46:58 PM PDT 24
Peak memory 205892 kb
Host smart-f517847f-0c18-46e4-8828-a425ab00dda8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867756897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2867756897
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.4282214033
Short name T933
Test name
Test status
Simulation time 93341909 ps
CPU time 3.47 seconds
Started Jul 30 06:46:52 PM PDT 24
Finished Jul 30 06:46:56 PM PDT 24
Peak memory 206208 kb
Host smart-5a5516d4-4e08-4ca0-a1e8-faa06f36f76c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282214033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.4282214033
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.4138793972
Short name T1010
Test name
Test status
Simulation time 81524053 ps
CPU time 1.66 seconds
Started Jul 30 06:46:52 PM PDT 24
Finished Jul 30 06:46:54 PM PDT 24
Peak memory 214820 kb
Host smart-ce3670ff-6e9d-4813-8882-0f5220045aac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138793972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.4138793972
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2605204306
Short name T119
Test name
Test status
Simulation time 741568264 ps
CPU time 5.35 seconds
Started Jul 30 06:47:02 PM PDT 24
Finished Jul 30 06:47:08 PM PDT 24
Peak memory 214704 kb
Host smart-85772c43-093e-4f36-8942-7a7725c60858
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605204306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2605204306
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3905382660
Short name T1052
Test name
Test status
Simulation time 1610911825 ps
CPU time 3.48 seconds
Started Jul 30 06:46:53 PM PDT 24
Finished Jul 30 06:46:57 PM PDT 24
Peak memory 214416 kb
Host smart-f720ea08-992e-43f0-a2b3-8544ee3a5254
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905382660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3905382660
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1649037790
Short name T989
Test name
Test status
Simulation time 418334150 ps
CPU time 3.6 seconds
Started Jul 30 06:46:54 PM PDT 24
Finished Jul 30 06:46:57 PM PDT 24
Peak memory 206156 kb
Host smart-9304b568-ac97-4369-90df-daee4b90c6ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649037790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1649037790
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.529242107
Short name T531
Test name
Test status
Simulation time 16808883 ps
CPU time 0.78 seconds
Started Jul 30 07:31:54 PM PDT 24
Finished Jul 30 07:31:54 PM PDT 24
Peak memory 205936 kb
Host smart-69b25ee5-cade-406a-a432-3c039991fcd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529242107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.529242107
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.3459025115
Short name T876
Test name
Test status
Simulation time 58228411 ps
CPU time 2.48 seconds
Started Jul 30 07:31:46 PM PDT 24
Finished Jul 30 07:31:49 PM PDT 24
Peak memory 208032 kb
Host smart-5a831dfa-b8fb-4b51-a4e5-288e9e2a9312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459025115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3459025115
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1145821568
Short name T737
Test name
Test status
Simulation time 836504689 ps
CPU time 10.14 seconds
Started Jul 30 07:31:44 PM PDT 24
Finished Jul 30 07:31:55 PM PDT 24
Peak memory 214424 kb
Host smart-3bf24eb7-6e93-4368-bf90-2090d53b21fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145821568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1145821568
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.554793321
Short name T742
Test name
Test status
Simulation time 1160623035 ps
CPU time 7.69 seconds
Started Jul 30 07:31:46 PM PDT 24
Finished Jul 30 07:31:54 PM PDT 24
Peak memory 208644 kb
Host smart-6898d626-da0a-4586-8d83-d9e2d858011f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554793321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.554793321
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3478154426
Short name T644
Test name
Test status
Simulation time 97289257 ps
CPU time 2.13 seconds
Started Jul 30 07:31:45 PM PDT 24
Finished Jul 30 07:31:48 PM PDT 24
Peak memory 214292 kb
Host smart-0e23cd0a-bad6-42c0-a460-3c615a3cd082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478154426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3478154426
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.4226475058
Short name T877
Test name
Test status
Simulation time 346206490 ps
CPU time 4.82 seconds
Started Jul 30 07:31:42 PM PDT 24
Finished Jul 30 07:31:47 PM PDT 24
Peak memory 214408 kb
Host smart-b9d7ed8d-4ec9-4fdf-89fc-5587757adb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226475058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.4226475058
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.440088488
Short name T199
Test name
Test status
Simulation time 400746147 ps
CPU time 11.13 seconds
Started Jul 30 07:31:45 PM PDT 24
Finished Jul 30 07:31:56 PM PDT 24
Peak memory 209328 kb
Host smart-5b7b84d9-fb1d-4d5a-a8a0-8a0c4121ec12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440088488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.440088488
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.607583800
Short name T635
Test name
Test status
Simulation time 55593184 ps
CPU time 2.62 seconds
Started Jul 30 07:31:42 PM PDT 24
Finished Jul 30 07:31:45 PM PDT 24
Peak memory 208540 kb
Host smart-50d07d6e-b68f-478a-afa8-131049575b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607583800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.607583800
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.2062450095
Short name T695
Test name
Test status
Simulation time 65050817 ps
CPU time 2.88 seconds
Started Jul 30 07:31:43 PM PDT 24
Finished Jul 30 07:31:46 PM PDT 24
Peak memory 206928 kb
Host smart-aed2bb56-3d3f-4a5f-9eb9-cb8d597c6d29
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062450095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2062450095
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1104938898
Short name T878
Test name
Test status
Simulation time 158251261 ps
CPU time 5 seconds
Started Jul 30 07:31:43 PM PDT 24
Finished Jul 30 07:31:48 PM PDT 24
Peak memory 207928 kb
Host smart-bfb95f69-3009-4bf4-b460-223d946eeb1d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104938898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1104938898
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1077136148
Short name T522
Test name
Test status
Simulation time 357515191 ps
CPU time 2.59 seconds
Started Jul 30 07:31:50 PM PDT 24
Finished Jul 30 07:31:53 PM PDT 24
Peak memory 209680 kb
Host smart-60a8173b-dcae-45d9-943c-89b34cfef0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077136148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1077136148
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3025911843
Short name T793
Test name
Test status
Simulation time 78530517 ps
CPU time 2.77 seconds
Started Jul 30 07:31:38 PM PDT 24
Finished Jul 30 07:31:41 PM PDT 24
Peak memory 208968 kb
Host smart-0ad348c8-69c1-4ae6-b965-266d480e0176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025911843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3025911843
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.3717389206
Short name T184
Test name
Test status
Simulation time 300146554 ps
CPU time 8.57 seconds
Started Jul 30 07:31:49 PM PDT 24
Finished Jul 30 07:31:58 PM PDT 24
Peak memory 222128 kb
Host smart-fc15e3f6-114b-41b6-9613-9d2da3cd91af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717389206 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.3717389206
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2553222144
Short name T363
Test name
Test status
Simulation time 360171588 ps
CPU time 3.73 seconds
Started Jul 30 07:31:42 PM PDT 24
Finished Jul 30 07:31:46 PM PDT 24
Peak memory 214280 kb
Host smart-bd954f07-694a-4147-b3db-75f0f4e19a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553222144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2553222144
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1949091271
Short name T564
Test name
Test status
Simulation time 171311317 ps
CPU time 2.3 seconds
Started Jul 30 07:31:50 PM PDT 24
Finished Jul 30 07:31:53 PM PDT 24
Peak memory 209956 kb
Host smart-ae3f3c82-8bc4-448b-aab0-70f4cbcc4f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949091271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1949091271
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2234620438
Short name T597
Test name
Test status
Simulation time 28548924 ps
CPU time 0.7 seconds
Started Jul 30 07:32:02 PM PDT 24
Finished Jul 30 07:32:03 PM PDT 24
Peak memory 205964 kb
Host smart-ba5e42e6-2347-47ca-b13e-1039654dcc90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234620438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2234620438
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2878966527
Short name T726
Test name
Test status
Simulation time 1433605820 ps
CPU time 14.64 seconds
Started Jul 30 07:32:02 PM PDT 24
Finished Jul 30 07:32:17 PM PDT 24
Peak memory 214396 kb
Host smart-0f41f9f0-1637-4062-8bb0-01c8fee6ee10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878966527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2878966527
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1929388498
Short name T709
Test name
Test status
Simulation time 947145331 ps
CPU time 16.16 seconds
Started Jul 30 07:31:59 PM PDT 24
Finished Jul 30 07:32:16 PM PDT 24
Peak memory 218420 kb
Host smart-022c88da-bc80-416b-bb97-387e782746db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929388498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1929388498
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3034307326
Short name T525
Test name
Test status
Simulation time 420447474 ps
CPU time 4.73 seconds
Started Jul 30 07:32:02 PM PDT 24
Finished Jul 30 07:32:07 PM PDT 24
Peak memory 209180 kb
Host smart-69073e69-3d11-4afa-b981-43ced7897cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034307326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3034307326
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1180582553
Short name T227
Test name
Test status
Simulation time 175765221 ps
CPU time 4.83 seconds
Started Jul 30 07:32:01 PM PDT 24
Finished Jul 30 07:32:06 PM PDT 24
Peak memory 209952 kb
Host smart-efd00832-4c18-41f8-bf7b-145d510ccdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180582553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1180582553
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3174516419
Short name T821
Test name
Test status
Simulation time 290551412 ps
CPU time 7.09 seconds
Started Jul 30 07:31:57 PM PDT 24
Finished Jul 30 07:32:05 PM PDT 24
Peak memory 209652 kb
Host smart-cf154396-e219-4e2e-a919-9c226e15e4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174516419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3174516419
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3949421735
Short name T868
Test name
Test status
Simulation time 93900373 ps
CPU time 3.05 seconds
Started Jul 30 07:32:01 PM PDT 24
Finished Jul 30 07:32:04 PM PDT 24
Peak memory 206924 kb
Host smart-4f232c8b-63fc-4364-812f-79233c161733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949421735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3949421735
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1042589301
Short name T713
Test name
Test status
Simulation time 53178004 ps
CPU time 2.14 seconds
Started Jul 30 07:32:02 PM PDT 24
Finished Jul 30 07:32:04 PM PDT 24
Peak memory 208952 kb
Host smart-5b7ab843-294f-4acc-a07b-82bcf292012b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042589301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1042589301
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2540317326
Short name T851
Test name
Test status
Simulation time 226880837 ps
CPU time 6.6 seconds
Started Jul 30 07:32:01 PM PDT 24
Finished Jul 30 07:32:08 PM PDT 24
Peak memory 207956 kb
Host smart-36625c17-ea38-4523-b4b2-ff2a046b61d0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540317326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2540317326
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3053368690
Short name T104
Test name
Test status
Simulation time 119228226 ps
CPU time 2.28 seconds
Started Jul 30 07:32:03 PM PDT 24
Finished Jul 30 07:32:05 PM PDT 24
Peak memory 206924 kb
Host smart-8e2ad8f6-faad-481a-8773-4ebc3dfc1fcd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053368690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3053368690
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.4147768665
Short name T249
Test name
Test status
Simulation time 229891095 ps
CPU time 2.97 seconds
Started Jul 30 07:32:03 PM PDT 24
Finished Jul 30 07:32:06 PM PDT 24
Peak memory 218320 kb
Host smart-70489737-f542-4618-a25d-7561f125ada4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147768665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.4147768665
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.312730083
Short name T866
Test name
Test status
Simulation time 100425478 ps
CPU time 2.35 seconds
Started Jul 30 07:31:54 PM PDT 24
Finished Jul 30 07:31:56 PM PDT 24
Peak memory 206904 kb
Host smart-7320e1fc-b2a7-4245-9736-b2f11286f63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312730083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.312730083
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2489856182
Short name T63
Test name
Test status
Simulation time 245485139 ps
CPU time 4.22 seconds
Started Jul 30 07:32:02 PM PDT 24
Finished Jul 30 07:32:06 PM PDT 24
Peak memory 216356 kb
Host smart-e313bcbd-b457-46ec-8068-6a2d44559232
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489856182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2489856182
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.47758401
Short name T100
Test name
Test status
Simulation time 187565406 ps
CPU time 12.1 seconds
Started Jul 30 07:32:06 PM PDT 24
Finished Jul 30 07:32:18 PM PDT 24
Peak memory 219628 kb
Host smart-17aef686-738f-4b6c-b753-dcd559721ba9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47758401 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.47758401
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.688191420
Short name T810
Test name
Test status
Simulation time 2621583214 ps
CPU time 25.79 seconds
Started Jul 30 07:32:02 PM PDT 24
Finished Jul 30 07:32:28 PM PDT 24
Peak memory 219844 kb
Host smart-9a36c235-365e-44a7-a1bb-0a18365c6280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688191420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.688191420
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2461477963
Short name T652
Test name
Test status
Simulation time 45721442 ps
CPU time 2.34 seconds
Started Jul 30 07:32:02 PM PDT 24
Finished Jul 30 07:32:04 PM PDT 24
Peak memory 209932 kb
Host smart-1a432335-4d03-45aa-8e3b-451ffc612cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461477963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2461477963
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2075225841
Short name T550
Test name
Test status
Simulation time 32792334 ps
CPU time 0.84 seconds
Started Jul 30 07:33:13 PM PDT 24
Finished Jul 30 07:33:14 PM PDT 24
Peak memory 205948 kb
Host smart-4c50136a-6b4a-429c-b652-edfd0e1ecd86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075225841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2075225841
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.822346123
Short name T721
Test name
Test status
Simulation time 145070647 ps
CPU time 1.94 seconds
Started Jul 30 07:33:10 PM PDT 24
Finished Jul 30 07:33:12 PM PDT 24
Peak memory 214376 kb
Host smart-58717e11-ba0f-4455-ad59-962940de9356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822346123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.822346123
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3027733294
Short name T92
Test name
Test status
Simulation time 66693053 ps
CPU time 3.39 seconds
Started Jul 30 07:33:09 PM PDT 24
Finished Jul 30 07:33:13 PM PDT 24
Peak memory 209680 kb
Host smart-3d6ba9e2-7ab5-4402-9de9-f6dd4219cfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027733294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3027733294
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2019905659
Short name T211
Test name
Test status
Simulation time 105524967 ps
CPU time 2.82 seconds
Started Jul 30 07:33:08 PM PDT 24
Finished Jul 30 07:33:11 PM PDT 24
Peak memory 222476 kb
Host smart-ab8eddcb-ccaa-49e1-a57a-65f5156bf23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019905659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2019905659
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.257921838
Short name T254
Test name
Test status
Simulation time 119330180 ps
CPU time 5.84 seconds
Started Jul 30 07:33:09 PM PDT 24
Finished Jul 30 07:33:15 PM PDT 24
Peak memory 208824 kb
Host smart-afe0c344-da64-42c9-a1c7-db0be91e74be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257921838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.257921838
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3999205667
Short name T135
Test name
Test status
Simulation time 324589733 ps
CPU time 6.44 seconds
Started Jul 30 07:33:08 PM PDT 24
Finished Jul 30 07:33:15 PM PDT 24
Peak memory 208560 kb
Host smart-4d803386-efba-4cbd-b3d2-028243bb87f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999205667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3999205667
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3808051375
Short name T511
Test name
Test status
Simulation time 69355970 ps
CPU time 2.9 seconds
Started Jul 30 07:33:11 PM PDT 24
Finished Jul 30 07:33:14 PM PDT 24
Peak memory 208232 kb
Host smart-5cf1ba75-4de7-42db-9900-009ec3399c22
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808051375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3808051375
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.824134937
Short name T507
Test name
Test status
Simulation time 61712355 ps
CPU time 3.14 seconds
Started Jul 30 07:33:07 PM PDT 24
Finished Jul 30 07:33:10 PM PDT 24
Peak memory 207012 kb
Host smart-a14e5d00-198f-44e5-9dc4-57fd0233c7c5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824134937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.824134937
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.520024058
Short name T630
Test name
Test status
Simulation time 171863901 ps
CPU time 3.95 seconds
Started Jul 30 07:33:10 PM PDT 24
Finished Jul 30 07:33:14 PM PDT 24
Peak memory 208832 kb
Host smart-ebfe5e01-d697-4732-a5b7-3e5e393c21d9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520024058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.520024058
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2432131030
Short name T322
Test name
Test status
Simulation time 116208041 ps
CPU time 2.75 seconds
Started Jul 30 07:33:13 PM PDT 24
Finished Jul 30 07:33:16 PM PDT 24
Peak memory 208620 kb
Host smart-05aea46f-e01f-4470-b9c5-dfd290f9027a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432131030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2432131030
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.827510593
Short name T534
Test name
Test status
Simulation time 192352844 ps
CPU time 4.53 seconds
Started Jul 30 07:33:08 PM PDT 24
Finished Jul 30 07:33:13 PM PDT 24
Peak memory 208140 kb
Host smart-8eae6a49-f566-4438-9632-71bbcb55ad8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827510593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.827510593
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3008893788
Short name T77
Test name
Test status
Simulation time 2500695355 ps
CPU time 27.12 seconds
Started Jul 30 07:33:12 PM PDT 24
Finished Jul 30 07:33:39 PM PDT 24
Peak memory 216104 kb
Host smart-37639a4a-2435-46e4-a69b-aeffbe47276b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008893788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3008893788
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.4170322566
Short name T634
Test name
Test status
Simulation time 482216309 ps
CPU time 18.72 seconds
Started Jul 30 07:33:12 PM PDT 24
Finished Jul 30 07:33:31 PM PDT 24
Peak memory 221016 kb
Host smart-ec219202-146f-4424-a8d2-7491d4e8de6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170322566 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.4170322566
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2482691178
Short name T520
Test name
Test status
Simulation time 538322890 ps
CPU time 7.29 seconds
Started Jul 30 07:33:09 PM PDT 24
Finished Jul 30 07:33:16 PM PDT 24
Peak memory 218668 kb
Host smart-a6ef3118-5bd5-4378-80bc-8a87e17f61b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482691178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2482691178
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.592507277
Short name T898
Test name
Test status
Simulation time 56004155 ps
CPU time 2.25 seconds
Started Jul 30 07:33:12 PM PDT 24
Finished Jul 30 07:33:14 PM PDT 24
Peak memory 209832 kb
Host smart-9f58ec7a-6c64-4211-931e-bd4cb4ab4c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592507277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.592507277
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1171515756
Short name T829
Test name
Test status
Simulation time 45520731 ps
CPU time 0.75 seconds
Started Jul 30 07:33:21 PM PDT 24
Finished Jul 30 07:33:21 PM PDT 24
Peak memory 205992 kb
Host smart-7cee4e48-77ca-4582-96c9-9fc05e07c063
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171515756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1171515756
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2057623273
Short name T276
Test name
Test status
Simulation time 107597208 ps
CPU time 5.83 seconds
Started Jul 30 07:33:19 PM PDT 24
Finished Jul 30 07:33:25 PM PDT 24
Peak memory 215324 kb
Host smart-d49a7be0-3fd7-4f5b-9824-e5d9e744c35f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2057623273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2057623273
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.402392589
Short name T445
Test name
Test status
Simulation time 2099707640 ps
CPU time 5.34 seconds
Started Jul 30 07:33:18 PM PDT 24
Finished Jul 30 07:33:24 PM PDT 24
Peak memory 222468 kb
Host smart-86027322-498a-453c-a6c1-d3be3fc4d5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402392589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.402392589
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3123559453
Short name T102
Test name
Test status
Simulation time 47138123 ps
CPU time 2.73 seconds
Started Jul 30 07:33:18 PM PDT 24
Finished Jul 30 07:33:21 PM PDT 24
Peak memory 222480 kb
Host smart-5fcc44ae-1c95-45fc-90a1-7122729f0263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123559453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3123559453
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2655594861
Short name T261
Test name
Test status
Simulation time 264897910 ps
CPU time 4.35 seconds
Started Jul 30 07:33:20 PM PDT 24
Finished Jul 30 07:33:24 PM PDT 24
Peak memory 214220 kb
Host smart-974f9dd9-0109-4c68-ba7e-13ca17a3b75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655594861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2655594861
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.714859014
Short name T914
Test name
Test status
Simulation time 38663545 ps
CPU time 2.65 seconds
Started Jul 30 07:33:19 PM PDT 24
Finished Jul 30 07:33:22 PM PDT 24
Peak memory 219936 kb
Host smart-1d152f13-b5d7-4301-b7a0-037ed442f7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714859014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.714859014
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3072910245
Short name T785
Test name
Test status
Simulation time 77376365 ps
CPU time 3.74 seconds
Started Jul 30 07:33:19 PM PDT 24
Finished Jul 30 07:33:23 PM PDT 24
Peak memory 209596 kb
Host smart-252c5143-5df6-4227-9ee8-5093ed415a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072910245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3072910245
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.3488140955
Short name T593
Test name
Test status
Simulation time 622720427 ps
CPU time 10.64 seconds
Started Jul 30 07:33:13 PM PDT 24
Finished Jul 30 07:33:24 PM PDT 24
Peak memory 208920 kb
Host smart-11bfbe18-204a-41a8-89d6-896c32f59eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488140955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3488140955
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3854173550
Short name T733
Test name
Test status
Simulation time 82307780 ps
CPU time 3.65 seconds
Started Jul 30 07:33:19 PM PDT 24
Finished Jul 30 07:33:23 PM PDT 24
Peak memory 208764 kb
Host smart-35f01804-4601-467f-acb9-37c2f59d9d1b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854173550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3854173550
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3702399439
Short name T328
Test name
Test status
Simulation time 2416530266 ps
CPU time 23.74 seconds
Started Jul 30 07:33:17 PM PDT 24
Finished Jul 30 07:33:41 PM PDT 24
Peak memory 208296 kb
Host smart-954ad4fe-d475-4d96-bf37-3e06f01134e5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702399439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3702399439
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.949750266
Short name T748
Test name
Test status
Simulation time 8011131621 ps
CPU time 74.89 seconds
Started Jul 30 07:33:17 PM PDT 24
Finished Jul 30 07:34:32 PM PDT 24
Peak memory 209032 kb
Host smart-1dbf05a2-7615-406c-a600-56e6f8cf3783
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949750266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.949750266
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2080060549
Short name T917
Test name
Test status
Simulation time 50200294 ps
CPU time 2.21 seconds
Started Jul 30 07:33:18 PM PDT 24
Finished Jul 30 07:33:20 PM PDT 24
Peak memory 215716 kb
Host smart-c712b3ac-fc26-497d-b153-ad26b0f981b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080060549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2080060549
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.207345270
Short name T684
Test name
Test status
Simulation time 78997254 ps
CPU time 1.65 seconds
Started Jul 30 07:33:14 PM PDT 24
Finished Jul 30 07:33:15 PM PDT 24
Peak memory 206852 kb
Host smart-c3829184-a9d1-4a9c-9272-d95ced1d6ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207345270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.207345270
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.500571011
Short name T350
Test name
Test status
Simulation time 2178616203 ps
CPU time 57.23 seconds
Started Jul 30 07:33:18 PM PDT 24
Finished Jul 30 07:34:15 PM PDT 24
Peak memory 221100 kb
Host smart-7dd3c081-bc3a-4561-a7c9-6fd94b50af6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500571011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.500571011
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1797511131
Short name T561
Test name
Test status
Simulation time 23749653 ps
CPU time 0.89 seconds
Started Jul 30 07:33:50 PM PDT 24
Finished Jul 30 07:33:51 PM PDT 24
Peak memory 205936 kb
Host smart-770ef2df-efd2-4d96-b154-97f8e42358ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797511131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1797511131
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2607819826
Short name T304
Test name
Test status
Simulation time 97641764 ps
CPU time 4.33 seconds
Started Jul 30 07:33:20 PM PDT 24
Finished Jul 30 07:33:25 PM PDT 24
Peak memory 210208 kb
Host smart-0b9ba97b-94bf-4a6b-91f6-bed7c5eff054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607819826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2607819826
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3097218963
Short name T87
Test name
Test status
Simulation time 33479479 ps
CPU time 2.54 seconds
Started Jul 30 07:33:22 PM PDT 24
Finished Jul 30 07:33:24 PM PDT 24
Peak memory 215468 kb
Host smart-f3a2350f-507d-4cc2-9bec-e27d41111bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097218963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3097218963
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1464817794
Short name T238
Test name
Test status
Simulation time 134269638 ps
CPU time 2.57 seconds
Started Jul 30 07:33:22 PM PDT 24
Finished Jul 30 07:33:25 PM PDT 24
Peak memory 214232 kb
Host smart-5e2c8640-c1a6-4673-b3a4-7f46dcdfa8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464817794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1464817794
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3604649732
Short name T471
Test name
Test status
Simulation time 176800138 ps
CPU time 3.22 seconds
Started Jul 30 07:33:24 PM PDT 24
Finished Jul 30 07:33:27 PM PDT 24
Peak memory 220664 kb
Host smart-2b56f619-04c0-4ead-8ea3-13f81bea72c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604649732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3604649732
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.2563632008
Short name T366
Test name
Test status
Simulation time 525036034 ps
CPU time 6.01 seconds
Started Jul 30 07:33:20 PM PDT 24
Finished Jul 30 07:33:26 PM PDT 24
Peak memory 209332 kb
Host smart-08574d8a-fbd5-4884-8448-7f06c548d261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563632008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2563632008
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1417219380
Short name T888
Test name
Test status
Simulation time 64184348 ps
CPU time 2.37 seconds
Started Jul 30 07:33:23 PM PDT 24
Finished Jul 30 07:33:26 PM PDT 24
Peak memory 208516 kb
Host smart-94d971e0-1cd6-4347-97d0-e39c1d5eae80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417219380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1417219380
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2813656286
Short name T82
Test name
Test status
Simulation time 73459603 ps
CPU time 3.24 seconds
Started Jul 30 07:33:19 PM PDT 24
Finished Jul 30 07:33:23 PM PDT 24
Peak memory 208824 kb
Host smart-d48156da-41cc-46e0-8b00-5334d28df624
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813656286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2813656286
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2938631432
Short name T555
Test name
Test status
Simulation time 142648373 ps
CPU time 5.41 seconds
Started Jul 30 07:33:22 PM PDT 24
Finished Jul 30 07:33:28 PM PDT 24
Peak memory 208700 kb
Host smart-6f7ff69c-46ab-43dd-a4ac-3367c35fb418
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938631432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2938631432
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.511977451
Short name T786
Test name
Test status
Simulation time 218427123 ps
CPU time 2.88 seconds
Started Jul 30 07:33:20 PM PDT 24
Finished Jul 30 07:33:23 PM PDT 24
Peak memory 206856 kb
Host smart-e470e535-1ee6-4bab-b669-b15b57aa3995
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511977451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.511977451
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3828679855
Short name T818
Test name
Test status
Simulation time 44766571 ps
CPU time 2.23 seconds
Started Jul 30 07:33:25 PM PDT 24
Finished Jul 30 07:33:27 PM PDT 24
Peak memory 208144 kb
Host smart-572a883d-1fdf-4c19-97c5-e5a5bf9850a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828679855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3828679855
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2268083484
Short name T682
Test name
Test status
Simulation time 100254193 ps
CPU time 2.35 seconds
Started Jul 30 07:33:22 PM PDT 24
Finished Jul 30 07:33:24 PM PDT 24
Peak memory 206872 kb
Host smart-dd0ce584-a8fa-4f7b-823b-b3c8e9386100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268083484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2268083484
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.337636764
Short name T515
Test name
Test status
Simulation time 9600384680 ps
CPU time 37.85 seconds
Started Jul 30 07:33:24 PM PDT 24
Finished Jul 30 07:34:02 PM PDT 24
Peak memory 214380 kb
Host smart-d345aa73-a85d-4a33-8894-2fd71608d63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337636764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.337636764
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.143607453
Short name T729
Test name
Test status
Simulation time 60447456 ps
CPU time 1.85 seconds
Started Jul 30 07:33:23 PM PDT 24
Finished Jul 30 07:33:25 PM PDT 24
Peak memory 209716 kb
Host smart-12b334d3-25e5-442a-b5fc-6666e434e778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143607453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.143607453
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.226208029
Short name T770
Test name
Test status
Simulation time 53041600 ps
CPU time 0.73 seconds
Started Jul 30 07:33:50 PM PDT 24
Finished Jul 30 07:33:51 PM PDT 24
Peak memory 205988 kb
Host smart-a0a37ac5-559c-4940-8b4e-2c40a006e2b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226208029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.226208029
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.799130646
Short name T234
Test name
Test status
Simulation time 131080732 ps
CPU time 3.2 seconds
Started Jul 30 07:33:49 PM PDT 24
Finished Jul 30 07:33:53 PM PDT 24
Peak memory 214364 kb
Host smart-2d43d36c-aad1-43ad-90d1-fe794a5c5450
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=799130646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.799130646
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1754680674
Short name T38
Test name
Test status
Simulation time 79344344 ps
CPU time 4.03 seconds
Started Jul 30 07:33:49 PM PDT 24
Finished Jul 30 07:33:53 PM PDT 24
Peak memory 210048 kb
Host smart-faa26d30-6ce3-4d32-b073-0113aef79c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754680674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1754680674
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.2359601838
Short name T331
Test name
Test status
Simulation time 96801854 ps
CPU time 1.91 seconds
Started Jul 30 07:33:44 PM PDT 24
Finished Jul 30 07:33:47 PM PDT 24
Peak memory 218172 kb
Host smart-9554d704-f6e1-4289-b973-9a5e979511a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359601838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2359601838
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3063152006
Short name T915
Test name
Test status
Simulation time 160881460 ps
CPU time 3.14 seconds
Started Jul 30 07:33:50 PM PDT 24
Finished Jul 30 07:33:53 PM PDT 24
Peak memory 214292 kb
Host smart-d89edc10-f471-48a7-b3cc-129d24667833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063152006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3063152006
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2717586112
Short name T338
Test name
Test status
Simulation time 187447520 ps
CPU time 2.38 seconds
Started Jul 30 07:33:49 PM PDT 24
Finished Jul 30 07:33:52 PM PDT 24
Peak memory 222376 kb
Host smart-88482b37-8ac9-4654-b06f-c6245aea054e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717586112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2717586112
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1592692920
Short name T57
Test name
Test status
Simulation time 391536574 ps
CPU time 4.01 seconds
Started Jul 30 07:33:42 PM PDT 24
Finished Jul 30 07:33:46 PM PDT 24
Peak memory 215552 kb
Host smart-6d387b78-19a7-4ccf-adf5-59fc60f171b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592692920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1592692920
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.453433249
Short name T341
Test name
Test status
Simulation time 908503219 ps
CPU time 5.73 seconds
Started Jul 30 07:33:26 PM PDT 24
Finished Jul 30 07:33:32 PM PDT 24
Peak memory 209704 kb
Host smart-9432efb0-04c5-485e-830f-2208ae8b823d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453433249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.453433249
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.497403136
Short name T191
Test name
Test status
Simulation time 30145585 ps
CPU time 2.19 seconds
Started Jul 30 07:33:50 PM PDT 24
Finished Jul 30 07:33:53 PM PDT 24
Peak memory 206968 kb
Host smart-cb1d898a-5adb-46d0-87eb-55139159d1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497403136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.497403136
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1054561239
Short name T361
Test name
Test status
Simulation time 425348292 ps
CPU time 5.13 seconds
Started Jul 30 07:33:51 PM PDT 24
Finished Jul 30 07:33:56 PM PDT 24
Peak memory 208860 kb
Host smart-932b03df-ac69-4429-a5a1-5a5c560b66dd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054561239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1054561239
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1245865203
Short name T716
Test name
Test status
Simulation time 889892411 ps
CPU time 2.98 seconds
Started Jul 30 07:33:52 PM PDT 24
Finished Jul 30 07:33:55 PM PDT 24
Peak memory 206920 kb
Host smart-df768ac4-5369-4302-8eeb-16943bbb75c0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245865203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1245865203
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3315588540
Short name T508
Test name
Test status
Simulation time 1122730323 ps
CPU time 19.07 seconds
Started Jul 30 07:33:49 PM PDT 24
Finished Jul 30 07:34:08 PM PDT 24
Peak memory 208308 kb
Host smart-5c8b59c5-810f-47c2-832d-37cdf6f705f3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315588540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3315588540
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2882686748
Short name T730
Test name
Test status
Simulation time 191512388 ps
CPU time 4.29 seconds
Started Jul 30 07:33:28 PM PDT 24
Finished Jul 30 07:33:32 PM PDT 24
Peak memory 214200 kb
Host smart-fb93e8b7-52c7-447b-b175-2f0bac9fea05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882686748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2882686748
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2138856699
Short name T879
Test name
Test status
Simulation time 462406262 ps
CPU time 10.89 seconds
Started Jul 30 07:33:49 PM PDT 24
Finished Jul 30 07:34:00 PM PDT 24
Peak memory 206860 kb
Host smart-70180a8e-a566-4967-9390-0e4fc19cbed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138856699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2138856699
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.139295650
Short name T825
Test name
Test status
Simulation time 965016945 ps
CPU time 31.14 seconds
Started Jul 30 07:33:42 PM PDT 24
Finished Jul 30 07:34:13 PM PDT 24
Peak memory 222452 kb
Host smart-b3e84ed1-6d8e-4c58-b38d-5a257aaf9f13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139295650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.139295650
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1902767206
Short name T187
Test name
Test status
Simulation time 1465838538 ps
CPU time 7.09 seconds
Started Jul 30 07:33:41 PM PDT 24
Finished Jul 30 07:33:48 PM PDT 24
Peak memory 222436 kb
Host smart-ef9f9497-5e91-4134-be75-81914f635b90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902767206 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1902767206
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2583801398
Short name T884
Test name
Test status
Simulation time 1206994879 ps
CPU time 7.11 seconds
Started Jul 30 07:33:48 PM PDT 24
Finished Jul 30 07:33:55 PM PDT 24
Peak memory 214284 kb
Host smart-4d2ddc28-9881-46e0-ac54-3db8285cc05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583801398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2583801398
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3070282163
Short name T382
Test name
Test status
Simulation time 226214349 ps
CPU time 3 seconds
Started Jul 30 07:33:49 PM PDT 24
Finished Jul 30 07:33:52 PM PDT 24
Peak memory 210236 kb
Host smart-d3297199-f882-42dc-919c-5586161d75d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070282163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3070282163
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3015399487
Short name T754
Test name
Test status
Simulation time 25417731 ps
CPU time 0.75 seconds
Started Jul 30 07:33:55 PM PDT 24
Finished Jul 30 07:33:55 PM PDT 24
Peak memory 205976 kb
Host smart-33ebabcb-0909-48fe-b6a9-40429de6f0bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015399487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3015399487
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3502714343
Short name T826
Test name
Test status
Simulation time 70808138 ps
CPU time 2.64 seconds
Started Jul 30 07:33:51 PM PDT 24
Finished Jul 30 07:33:54 PM PDT 24
Peak memory 210036 kb
Host smart-8dcc282a-313b-4c99-a8a2-5023128eee60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502714343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3502714343
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3423183290
Short name T595
Test name
Test status
Simulation time 133715341 ps
CPU time 4.49 seconds
Started Jul 30 07:33:51 PM PDT 24
Finished Jul 30 07:33:55 PM PDT 24
Peak memory 222464 kb
Host smart-0782b037-c6b0-4a28-9d51-f9fbe93b07f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423183290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3423183290
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3630547181
Short name T510
Test name
Test status
Simulation time 1064303458 ps
CPU time 3.32 seconds
Started Jul 30 07:34:07 PM PDT 24
Finished Jul 30 07:34:11 PM PDT 24
Peak memory 215948 kb
Host smart-6ff94b19-d8e4-4b4c-874f-bd7d7ced7e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630547181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3630547181
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.476459579
Short name T849
Test name
Test status
Simulation time 253806762 ps
CPU time 3.48 seconds
Started Jul 30 07:33:53 PM PDT 24
Finished Jul 30 07:33:56 PM PDT 24
Peak memory 207812 kb
Host smart-841ec662-1284-4eae-aeac-06f7fa4c4d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476459579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.476459579
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.684224277
Short name T728
Test name
Test status
Simulation time 108395128 ps
CPU time 1.8 seconds
Started Jul 30 07:33:42 PM PDT 24
Finished Jul 30 07:33:44 PM PDT 24
Peak memory 207000 kb
Host smart-dfc240bf-1c7b-4e94-88c4-68a51ef8be38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684224277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.684224277
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.557893349
Short name T629
Test name
Test status
Simulation time 65771848 ps
CPU time 3.24 seconds
Started Jul 30 07:33:51 PM PDT 24
Finished Jul 30 07:33:54 PM PDT 24
Peak memory 208752 kb
Host smart-70047d23-fa9c-4d0c-93e6-8c98e4441378
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557893349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.557893349
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1433037999
Short name T444
Test name
Test status
Simulation time 195222795 ps
CPU time 2.72 seconds
Started Jul 30 07:33:49 PM PDT 24
Finished Jul 30 07:33:52 PM PDT 24
Peak memory 206756 kb
Host smart-125a5cdd-c1af-431d-bf1f-dc7b5cfdb3e9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433037999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1433037999
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3565788435
Short name T612
Test name
Test status
Simulation time 206158199 ps
CPU time 5.5 seconds
Started Jul 30 07:33:52 PM PDT 24
Finished Jul 30 07:33:58 PM PDT 24
Peak memory 207840 kb
Host smart-4a50b662-64ed-405d-84a1-829e5cad213a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565788435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3565788435
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2042659596
Short name T494
Test name
Test status
Simulation time 37948339 ps
CPU time 1.86 seconds
Started Jul 30 07:33:52 PM PDT 24
Finished Jul 30 07:33:54 PM PDT 24
Peak memory 216028 kb
Host smart-3db3a037-0c29-43e0-9e08-f577eae3374e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042659596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2042659596
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3365939393
Short name T676
Test name
Test status
Simulation time 60317139 ps
CPU time 2.32 seconds
Started Jul 30 07:33:51 PM PDT 24
Finished Jul 30 07:33:54 PM PDT 24
Peak memory 206688 kb
Host smart-5d159248-2eac-4be2-b29b-2cd736ebb360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365939393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3365939393
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1137206330
Short name T718
Test name
Test status
Simulation time 665165765 ps
CPU time 7.12 seconds
Started Jul 30 07:33:33 PM PDT 24
Finished Jul 30 07:33:40 PM PDT 24
Peak memory 216484 kb
Host smart-2983f4ef-2a6b-497d-9c6a-e5fa871be465
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137206330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1137206330
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.1975731514
Short name T183
Test name
Test status
Simulation time 193345931 ps
CPU time 6.29 seconds
Started Jul 30 07:33:52 PM PDT 24
Finished Jul 30 07:33:59 PM PDT 24
Peak memory 219648 kb
Host smart-3e5a4d12-8e67-4895-9d91-08a3188d0a72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975731514 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.1975731514
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.128770906
Short name T348
Test name
Test status
Simulation time 1536126130 ps
CPU time 34.17 seconds
Started Jul 30 07:33:45 PM PDT 24
Finished Jul 30 07:34:19 PM PDT 24
Peak memory 209548 kb
Host smart-86adc742-ccdc-4cad-99b0-23bc17820511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128770906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.128770906
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3766992936
Short name T97
Test name
Test status
Simulation time 176539941 ps
CPU time 3.4 seconds
Started Jul 30 07:33:53 PM PDT 24
Finished Jul 30 07:33:56 PM PDT 24
Peak memory 210248 kb
Host smart-ec0a6490-5121-44a0-ad6c-d119edfdec0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766992936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3766992936
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1300090452
Short name T473
Test name
Test status
Simulation time 11407690 ps
CPU time 0.84 seconds
Started Jul 30 07:33:59 PM PDT 24
Finished Jul 30 07:34:00 PM PDT 24
Peak memory 205984 kb
Host smart-2eb5236e-5684-4092-9f61-566fa60e4797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300090452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1300090452
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2620549808
Short name T282
Test name
Test status
Simulation time 49521311 ps
CPU time 1.96 seconds
Started Jul 30 07:33:54 PM PDT 24
Finished Jul 30 07:33:56 PM PDT 24
Peak memory 214384 kb
Host smart-d1ff4ebe-def9-4701-a53c-32c14ef25384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620549808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2620549808
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.4039054475
Short name T351
Test name
Test status
Simulation time 136230377 ps
CPU time 6.07 seconds
Started Jul 30 07:33:54 PM PDT 24
Finished Jul 30 07:34:00 PM PDT 24
Peak memory 214308 kb
Host smart-f64ad51a-fcab-432a-b4cc-1e5de96ed392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039054475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.4039054475
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3068209110
Short name T46
Test name
Test status
Simulation time 362042597 ps
CPU time 3.81 seconds
Started Jul 30 07:33:52 PM PDT 24
Finished Jul 30 07:33:56 PM PDT 24
Peak memory 214352 kb
Host smart-7f37e6c2-325c-4827-9b61-027e44e54b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068209110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3068209110
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1750917035
Short name T563
Test name
Test status
Simulation time 324591449 ps
CPU time 3.02 seconds
Started Jul 30 07:33:58 PM PDT 24
Finished Jul 30 07:34:01 PM PDT 24
Peak memory 220360 kb
Host smart-ce40f39a-36e1-4078-81c6-d68d557503b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750917035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1750917035
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.4263172876
Short name T499
Test name
Test status
Simulation time 211531470 ps
CPU time 3.91 seconds
Started Jul 30 07:33:55 PM PDT 24
Finished Jul 30 07:33:59 PM PDT 24
Peak memory 214400 kb
Host smart-e16dccb3-b8f8-42f2-a499-48271578439c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263172876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.4263172876
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1785611843
Short name T867
Test name
Test status
Simulation time 57875806 ps
CPU time 2.16 seconds
Started Jul 30 07:33:53 PM PDT 24
Finished Jul 30 07:33:55 PM PDT 24
Peak memory 207040 kb
Host smart-4b2e5549-a7e2-4ad0-89e6-9a47d5e48629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785611843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1785611843
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2514327272
Short name T692
Test name
Test status
Simulation time 1022076355 ps
CPU time 22.85 seconds
Started Jul 30 07:33:53 PM PDT 24
Finished Jul 30 07:34:16 PM PDT 24
Peak memory 208020 kb
Host smart-e941dc86-7005-4843-bc61-bea36a2d4181
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514327272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2514327272
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2135237381
Short name T677
Test name
Test status
Simulation time 37905299 ps
CPU time 2.52 seconds
Started Jul 30 07:33:52 PM PDT 24
Finished Jul 30 07:33:54 PM PDT 24
Peak memory 207060 kb
Host smart-4962e488-50f9-4c59-b2d7-fa5836a61c67
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135237381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2135237381
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1006733906
Short name T437
Test name
Test status
Simulation time 163096453 ps
CPU time 4.81 seconds
Started Jul 30 07:33:46 PM PDT 24
Finished Jul 30 07:33:51 PM PDT 24
Peak memory 208004 kb
Host smart-356da234-6410-4b54-b73c-fc2ce6235de1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006733906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1006733906
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3520379695
Short name T640
Test name
Test status
Simulation time 46592093 ps
CPU time 2.12 seconds
Started Jul 30 07:33:51 PM PDT 24
Finished Jul 30 07:33:53 PM PDT 24
Peak memory 207004 kb
Host smart-9ff6b14d-d376-4f1c-8402-f699cd123952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520379695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3520379695
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1062817703
Short name T800
Test name
Test status
Simulation time 1629516760 ps
CPU time 9.03 seconds
Started Jul 30 07:33:52 PM PDT 24
Finished Jul 30 07:34:01 PM PDT 24
Peak memory 208156 kb
Host smart-3f348b75-8b3f-4464-bee4-3bf551f54803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062817703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1062817703
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2182470496
Short name T72
Test name
Test status
Simulation time 2965748276 ps
CPU time 53.44 seconds
Started Jul 30 07:33:56 PM PDT 24
Finished Jul 30 07:34:49 PM PDT 24
Peak memory 222536 kb
Host smart-17b3014c-4042-443b-980e-76778535bd8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182470496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2182470496
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.811746538
Short name T663
Test name
Test status
Simulation time 15119747 ps
CPU time 0.8 seconds
Started Jul 30 07:34:02 PM PDT 24
Finished Jul 30 07:34:03 PM PDT 24
Peak memory 205940 kb
Host smart-b1956e79-3891-4964-ac59-e1d5b002ecdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811746538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.811746538
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.2599607761
Short name T744
Test name
Test status
Simulation time 85556587 ps
CPU time 3.7 seconds
Started Jul 30 07:33:59 PM PDT 24
Finished Jul 30 07:34:03 PM PDT 24
Peak memory 220052 kb
Host smart-58283132-fbcc-400d-a1dc-64307895f4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599607761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.2599607761
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2440191007
Short name T293
Test name
Test status
Simulation time 186149797 ps
CPU time 4.17 seconds
Started Jul 30 07:33:56 PM PDT 24
Finished Jul 30 07:34:00 PM PDT 24
Peak memory 209752 kb
Host smart-c6e41ff6-0d89-4cc6-9c16-7a810baef019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440191007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2440191007
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1550070206
Short name T764
Test name
Test status
Simulation time 297935195 ps
CPU time 2.49 seconds
Started Jul 30 07:33:57 PM PDT 24
Finished Jul 30 07:33:59 PM PDT 24
Peak memory 214304 kb
Host smart-4431395e-4131-4184-9997-78566e526f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550070206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1550070206
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.757432665
Short name T391
Test name
Test status
Simulation time 187328466 ps
CPU time 5.9 seconds
Started Jul 30 07:33:58 PM PDT 24
Finished Jul 30 07:34:04 PM PDT 24
Peak memory 221724 kb
Host smart-7c92e1aa-045c-4909-9cc1-9aaef92ec5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757432665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.757432665
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3026963174
Short name T225
Test name
Test status
Simulation time 2256892204 ps
CPU time 15.13 seconds
Started Jul 30 07:33:59 PM PDT 24
Finished Jul 30 07:34:15 PM PDT 24
Peak memory 220520 kb
Host smart-979064cf-ac2e-4c42-b71a-8feaf8a3c1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026963174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3026963174
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3655034208
Short name T472
Test name
Test status
Simulation time 131254504 ps
CPU time 5.72 seconds
Started Jul 30 07:33:57 PM PDT 24
Finished Jul 30 07:34:03 PM PDT 24
Peak memory 207516 kb
Host smart-e0f4c11a-b516-4e34-835f-7901390bf474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655034208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3655034208
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.348895312
Short name T732
Test name
Test status
Simulation time 137605970 ps
CPU time 3.94 seconds
Started Jul 30 07:33:57 PM PDT 24
Finished Jul 30 07:34:01 PM PDT 24
Peak memory 206992 kb
Host smart-4afe9c8b-ba45-4cba-b4a1-234ae8bae763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348895312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.348895312
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2449582083
Short name T306
Test name
Test status
Simulation time 81625532 ps
CPU time 3.49 seconds
Started Jul 30 07:33:57 PM PDT 24
Finished Jul 30 07:34:01 PM PDT 24
Peak memory 206788 kb
Host smart-96d13309-9457-4205-9556-dd38e85ef76f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449582083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2449582083
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3813451648
Short name T841
Test name
Test status
Simulation time 47116563 ps
CPU time 2.25 seconds
Started Jul 30 07:33:58 PM PDT 24
Finished Jul 30 07:34:00 PM PDT 24
Peak memory 206932 kb
Host smart-33ba77a7-6405-4869-945a-428f9280515e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813451648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3813451648
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.4006801741
Short name T710
Test name
Test status
Simulation time 736879120 ps
CPU time 5.77 seconds
Started Jul 30 07:33:57 PM PDT 24
Finished Jul 30 07:34:03 PM PDT 24
Peak memory 209108 kb
Host smart-4ac46c63-4e89-423c-8793-78fd4d02d3e4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006801741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.4006801741
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.573287618
Short name T631
Test name
Test status
Simulation time 82274260 ps
CPU time 3.82 seconds
Started Jul 30 07:33:58 PM PDT 24
Finished Jul 30 07:34:02 PM PDT 24
Peak memory 218560 kb
Host smart-c9f16bda-f660-414b-8c1d-b57e93f2abcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573287618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.573287618
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1697805556
Short name T495
Test name
Test status
Simulation time 1104614842 ps
CPU time 16.68 seconds
Started Jul 30 07:33:56 PM PDT 24
Finished Jul 30 07:34:13 PM PDT 24
Peak memory 207784 kb
Host smart-1e03eaee-1dd6-4727-8787-a20e5982bba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697805556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1697805556
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.741268960
Short name T425
Test name
Test status
Simulation time 72448396 ps
CPU time 2.82 seconds
Started Jul 30 07:33:58 PM PDT 24
Finished Jul 30 07:34:01 PM PDT 24
Peak memory 207408 kb
Host smart-54c425d5-4318-4ad3-b565-049f42f0cc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741268960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.741268960
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3554249312
Short name T383
Test name
Test status
Simulation time 179235111 ps
CPU time 2.54 seconds
Started Jul 30 07:34:00 PM PDT 24
Finished Jul 30 07:34:02 PM PDT 24
Peak memory 210176 kb
Host smart-8e06e66b-e63a-40a3-97b2-971e01e8c71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554249312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3554249312
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2704409417
Short name T616
Test name
Test status
Simulation time 34539305 ps
CPU time 0.72 seconds
Started Jul 30 07:34:05 PM PDT 24
Finished Jul 30 07:34:05 PM PDT 24
Peak memory 205932 kb
Host smart-4873583a-7bdd-4f8e-8fd3-66105b572141
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704409417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2704409417
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1529973889
Short name T783
Test name
Test status
Simulation time 232166147 ps
CPU time 4.92 seconds
Started Jul 30 07:33:59 PM PDT 24
Finished Jul 30 07:34:05 PM PDT 24
Peak memory 210360 kb
Host smart-346678fa-588b-4207-b863-1297d2c48709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529973889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1529973889
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.211269683
Short name T617
Test name
Test status
Simulation time 439314833 ps
CPU time 2.48 seconds
Started Jul 30 07:34:00 PM PDT 24
Finished Jul 30 07:34:03 PM PDT 24
Peak memory 222476 kb
Host smart-ab654490-c387-481d-ab5e-60783f56f511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211269683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.211269683
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1171338901
Short name T86
Test name
Test status
Simulation time 230114060 ps
CPU time 3.34 seconds
Started Jul 30 07:34:05 PM PDT 24
Finished Jul 30 07:34:08 PM PDT 24
Peak memory 214360 kb
Host smart-58a9e66c-a16f-460a-b9d2-4ac7e27e6fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171338901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1171338901
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1432207190
Short name T393
Test name
Test status
Simulation time 317096857 ps
CPU time 2.51 seconds
Started Jul 30 07:34:05 PM PDT 24
Finished Jul 30 07:34:08 PM PDT 24
Peak memory 214324 kb
Host smart-16c273cf-d1ba-4b49-85e8-f588f979ac12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432207190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1432207190
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.4240704323
Short name T330
Test name
Test status
Simulation time 833801817 ps
CPU time 8.93 seconds
Started Jul 30 07:34:01 PM PDT 24
Finished Jul 30 07:34:10 PM PDT 24
Peak memory 208536 kb
Host smart-d0710727-0a88-4d1d-a8ab-5375f257577c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240704323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.4240704323
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.873017391
Short name T802
Test name
Test status
Simulation time 199629376 ps
CPU time 2.53 seconds
Started Jul 30 07:34:02 PM PDT 24
Finished Jul 30 07:34:04 PM PDT 24
Peak memory 208332 kb
Host smart-ec372b42-572e-477a-8eea-2154f5dd277e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873017391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.873017391
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.238666784
Short name T442
Test name
Test status
Simulation time 240860576 ps
CPU time 6.72 seconds
Started Jul 30 07:33:59 PM PDT 24
Finished Jul 30 07:34:06 PM PDT 24
Peak memory 208592 kb
Host smart-d34580fe-9149-44b3-a09b-c99de08671d1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238666784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.238666784
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1686439633
Short name T588
Test name
Test status
Simulation time 282231913 ps
CPU time 1.71 seconds
Started Jul 30 07:34:04 PM PDT 24
Finished Jul 30 07:34:06 PM PDT 24
Peak memory 206812 kb
Host smart-388d3cc3-0fd9-44d5-ad21-82daa4127026
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686439633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1686439633
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.450766748
Short name T683
Test name
Test status
Simulation time 24044416 ps
CPU time 1.9 seconds
Started Jul 30 07:34:05 PM PDT 24
Finished Jul 30 07:34:07 PM PDT 24
Peak memory 206820 kb
Host smart-5ef284b1-6c71-4002-8297-8ae10192839f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450766748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.450766748
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3838154957
Short name T792
Test name
Test status
Simulation time 408533808 ps
CPU time 3.33 seconds
Started Jul 30 07:34:05 PM PDT 24
Finished Jul 30 07:34:09 PM PDT 24
Peak memory 208584 kb
Host smart-24e93f99-f46b-4969-b05c-475b635a4a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838154957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3838154957
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.995652480
Short name T611
Test name
Test status
Simulation time 61949115 ps
CPU time 2.98 seconds
Started Jul 30 07:34:01 PM PDT 24
Finished Jul 30 07:34:04 PM PDT 24
Peak memory 208516 kb
Host smart-b5894edc-5d86-4650-8dd1-8795eb85575a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995652480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.995652480
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1746534342
Short name T853
Test name
Test status
Simulation time 144731660 ps
CPU time 4.51 seconds
Started Jul 30 07:34:00 PM PDT 24
Finished Jul 30 07:34:04 PM PDT 24
Peak memory 209240 kb
Host smart-c13d0839-fca6-44a0-ba66-c08ff09169da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746534342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1746534342
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3507654445
Short name T384
Test name
Test status
Simulation time 533495297 ps
CPU time 3.87 seconds
Started Jul 30 07:34:03 PM PDT 24
Finished Jul 30 07:34:07 PM PDT 24
Peak memory 210300 kb
Host smart-ffd36470-5be5-454f-b040-cf914f435bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507654445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3507654445
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.688845890
Short name T791
Test name
Test status
Simulation time 56821534 ps
CPU time 0.74 seconds
Started Jul 30 07:34:30 PM PDT 24
Finished Jul 30 07:34:31 PM PDT 24
Peak memory 205952 kb
Host smart-c9431f4a-f7e9-4159-8650-c27ad0e4e233
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688845890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.688845890
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2076991237
Short name T268
Test name
Test status
Simulation time 66417865 ps
CPU time 4.59 seconds
Started Jul 30 07:34:03 PM PDT 24
Finished Jul 30 07:34:07 PM PDT 24
Peak memory 215408 kb
Host smart-b61e9db4-5146-4901-a42e-ec515401bcd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2076991237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2076991237
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.221731307
Short name T861
Test name
Test status
Simulation time 63247765 ps
CPU time 3.43 seconds
Started Jul 30 07:34:30 PM PDT 24
Finished Jul 30 07:34:34 PM PDT 24
Peak memory 208592 kb
Host smart-f0652c72-3221-4436-89b7-cef870647980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221731307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.221731307
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3326800838
Short name T847
Test name
Test status
Simulation time 75207290 ps
CPU time 1.48 seconds
Started Jul 30 07:34:32 PM PDT 24
Finished Jul 30 07:34:33 PM PDT 24
Peak memory 207484 kb
Host smart-f3c27d47-e748-4397-9f13-a375789654c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326800838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3326800838
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3714260174
Short name T93
Test name
Test status
Simulation time 10075259078 ps
CPU time 38.93 seconds
Started Jul 30 07:34:18 PM PDT 24
Finished Jul 30 07:34:57 PM PDT 24
Peak memory 209712 kb
Host smart-8aad9e17-a1d5-4cd3-abe9-a44977d14e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714260174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3714260174
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2449080800
Short name T596
Test name
Test status
Simulation time 139592117 ps
CPU time 5.54 seconds
Started Jul 30 07:34:36 PM PDT 24
Finished Jul 30 07:34:41 PM PDT 24
Peak memory 214244 kb
Host smart-0fb6e02e-20d4-4c85-a04b-c75ef4182f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449080800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2449080800
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.880062386
Short name T869
Test name
Test status
Simulation time 71327743 ps
CPU time 3.21 seconds
Started Jul 30 07:34:28 PM PDT 24
Finished Jul 30 07:34:31 PM PDT 24
Peak memory 214420 kb
Host smart-44674c1f-6c8e-4dc5-afb0-9dd4529a603b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880062386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.880062386
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3325515698
Short name T467
Test name
Test status
Simulation time 1592332294 ps
CPU time 39.05 seconds
Started Jul 30 07:34:02 PM PDT 24
Finished Jul 30 07:34:41 PM PDT 24
Peak memory 208804 kb
Host smart-cb69e763-9823-4bf5-b034-42be7c267af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325515698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3325515698
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.103489104
Short name T610
Test name
Test status
Simulation time 61196985 ps
CPU time 2.4 seconds
Started Jul 30 07:34:02 PM PDT 24
Finished Jul 30 07:34:05 PM PDT 24
Peak memory 206240 kb
Host smart-68782868-2cf8-4375-8eb2-d6deaf8dd4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103489104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.103489104
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.9060524
Short name T365
Test name
Test status
Simulation time 215336064 ps
CPU time 6.33 seconds
Started Jul 30 07:34:02 PM PDT 24
Finished Jul 30 07:34:09 PM PDT 24
Peak memory 208096 kb
Host smart-4620cfeb-e122-441c-9d1e-4178201d20e8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9060524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.9060524
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3619406551
Short name T576
Test name
Test status
Simulation time 7121176432 ps
CPU time 72.41 seconds
Started Jul 30 07:34:03 PM PDT 24
Finished Jul 30 07:35:16 PM PDT 24
Peak memory 208700 kb
Host smart-3d52a51a-ed04-4396-9570-9284e6950ac2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619406551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3619406551
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.698021768
Short name T294
Test name
Test status
Simulation time 909855827 ps
CPU time 3.72 seconds
Started Jul 30 07:34:02 PM PDT 24
Finished Jul 30 07:34:06 PM PDT 24
Peak memory 208428 kb
Host smart-c00ce98b-c919-4451-91e8-d7a9d5463b7d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698021768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.698021768
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1115777518
Short name T779
Test name
Test status
Simulation time 194833623 ps
CPU time 2.57 seconds
Started Jul 30 07:34:30 PM PDT 24
Finished Jul 30 07:34:32 PM PDT 24
Peak memory 208824 kb
Host smart-42fd3cb2-0a31-40c4-b822-70b738d05435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115777518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1115777518
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2962990598
Short name T614
Test name
Test status
Simulation time 162536898 ps
CPU time 2.69 seconds
Started Jul 30 07:34:02 PM PDT 24
Finished Jul 30 07:34:05 PM PDT 24
Peak memory 208680 kb
Host smart-ad37a541-1e2d-45f7-be6e-dbed43d61367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962990598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2962990598
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1061614580
Short name T364
Test name
Test status
Simulation time 2698404918 ps
CPU time 56.63 seconds
Started Jul 30 07:34:12 PM PDT 24
Finished Jul 30 07:35:09 PM PDT 24
Peak memory 215520 kb
Host smart-9ac960bd-4f46-42e8-a6b8-34df4cdfbe89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061614580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1061614580
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3320430240
Short name T613
Test name
Test status
Simulation time 366834532 ps
CPU time 5.6 seconds
Started Jul 30 07:34:33 PM PDT 24
Finished Jul 30 07:34:38 PM PDT 24
Peak memory 209064 kb
Host smart-a20113a5-7df3-42af-975d-cfcbdbc21c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320430240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3320430240
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.367128181
Short name T380
Test name
Test status
Simulation time 226133657 ps
CPU time 4.35 seconds
Started Jul 30 07:34:29 PM PDT 24
Finished Jul 30 07:34:33 PM PDT 24
Peak memory 211012 kb
Host smart-0d536be3-07a5-4dc5-980e-66ea53c78d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367128181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.367128181
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.829321406
Short name T585
Test name
Test status
Simulation time 26437466 ps
CPU time 0.73 seconds
Started Jul 30 07:34:33 PM PDT 24
Finished Jul 30 07:34:34 PM PDT 24
Peak memory 205980 kb
Host smart-24457a04-b964-4e4a-abb7-53d962c0e0a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829321406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.829321406
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.352070393
Short name T405
Test name
Test status
Simulation time 123536578 ps
CPU time 3.85 seconds
Started Jul 30 07:34:34 PM PDT 24
Finished Jul 30 07:34:38 PM PDT 24
Peak memory 214344 kb
Host smart-4b7a92de-a061-436a-b1d0-c16648f85d26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=352070393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.352070393
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2124471268
Short name T26
Test name
Test status
Simulation time 744637775 ps
CPU time 6.11 seconds
Started Jul 30 07:34:33 PM PDT 24
Finished Jul 30 07:34:39 PM PDT 24
Peak memory 220076 kb
Host smart-40d49228-0e0a-4a31-ac67-902ca8ca2762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124471268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2124471268
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2191149546
Short name T798
Test name
Test status
Simulation time 190696149 ps
CPU time 3.75 seconds
Started Jul 30 07:34:33 PM PDT 24
Finished Jul 30 07:34:37 PM PDT 24
Peak memory 214400 kb
Host smart-93772a86-09d0-4a1f-8985-547f7a67dcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191149546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2191149546
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1382171121
Short name T88
Test name
Test status
Simulation time 26441752 ps
CPU time 2.07 seconds
Started Jul 30 07:34:32 PM PDT 24
Finished Jul 30 07:34:34 PM PDT 24
Peak memory 214428 kb
Host smart-06aae872-14ac-4bc3-acdd-b860807f5b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382171121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1382171121
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.4001289661
Short name T916
Test name
Test status
Simulation time 919155036 ps
CPU time 3.55 seconds
Started Jul 30 07:34:35 PM PDT 24
Finished Jul 30 07:34:38 PM PDT 24
Peak memory 214248 kb
Host smart-83085946-e1fc-4b18-ba95-bd76b04173ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001289661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.4001289661
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.476181181
Short name T650
Test name
Test status
Simulation time 121330331 ps
CPU time 2.12 seconds
Started Jul 30 07:34:32 PM PDT 24
Finished Jul 30 07:34:34 PM PDT 24
Peak memory 220088 kb
Host smart-271b4623-bf5e-4f88-bf02-5e91d5083cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476181181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.476181181
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1750487223
Short name T750
Test name
Test status
Simulation time 1007580669 ps
CPU time 16.94 seconds
Started Jul 30 07:34:33 PM PDT 24
Finished Jul 30 07:34:50 PM PDT 24
Peak memory 207976 kb
Host smart-0852ebd7-ab71-40f4-8d7d-a0dfc0887655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750487223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1750487223
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1400726024
Short name T573
Test name
Test status
Simulation time 60266445 ps
CPU time 3.01 seconds
Started Jul 30 07:34:32 PM PDT 24
Finished Jul 30 07:34:35 PM PDT 24
Peak memory 208608 kb
Host smart-583c3cf9-06ba-480e-91dc-e2c79d12298e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400726024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1400726024
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1325511976
Short name T880
Test name
Test status
Simulation time 244526880 ps
CPU time 3.13 seconds
Started Jul 30 07:34:33 PM PDT 24
Finished Jul 30 07:34:36 PM PDT 24
Peak memory 208888 kb
Host smart-104b421b-a9ab-47fc-8500-3b127b23450a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325511976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1325511976
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1721453995
Short name T605
Test name
Test status
Simulation time 111315108 ps
CPU time 4.08 seconds
Started Jul 30 07:34:20 PM PDT 24
Finished Jul 30 07:34:25 PM PDT 24
Peak memory 208904 kb
Host smart-e374f339-d895-4ca8-b579-5064c2f3c069
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721453995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1721453995
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1292666564
Short name T452
Test name
Test status
Simulation time 198691387 ps
CPU time 3.24 seconds
Started Jul 30 07:34:27 PM PDT 24
Finished Jul 30 07:34:31 PM PDT 24
Peak memory 207120 kb
Host smart-7c65724d-3098-4f6c-b521-5d7656effe04
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292666564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1292666564
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.3743315143
Short name T822
Test name
Test status
Simulation time 85084844 ps
CPU time 3.16 seconds
Started Jul 30 07:34:24 PM PDT 24
Finished Jul 30 07:34:27 PM PDT 24
Peak memory 210276 kb
Host smart-860839e1-4da8-4c4d-9cc1-60e0aa300a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743315143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3743315143
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3973938259
Short name T628
Test name
Test status
Simulation time 140593452 ps
CPU time 3.35 seconds
Started Jul 30 07:34:13 PM PDT 24
Finished Jul 30 07:34:17 PM PDT 24
Peak memory 208580 kb
Host smart-2982226a-16d1-4a72-bb18-136344c39f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973938259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3973938259
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2091813243
Short name T312
Test name
Test status
Simulation time 2644786486 ps
CPU time 28.9 seconds
Started Jul 30 07:34:24 PM PDT 24
Finished Jul 30 07:34:53 PM PDT 24
Peak memory 209380 kb
Host smart-a46aec04-aa80-4ccf-a5a3-8c5aa94c7a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091813243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2091813243
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3947100924
Short name T538
Test name
Test status
Simulation time 168195117 ps
CPU time 2.02 seconds
Started Jul 30 07:34:33 PM PDT 24
Finished Jul 30 07:34:35 PM PDT 24
Peak memory 209924 kb
Host smart-8168e100-312c-4a4c-9732-efdda2363f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947100924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3947100924
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1483707414
Short name T784
Test name
Test status
Simulation time 37543162 ps
CPU time 0.74 seconds
Started Jul 30 07:32:13 PM PDT 24
Finished Jul 30 07:32:14 PM PDT 24
Peak memory 205940 kb
Host smart-17fbf5ca-92fe-4057-94b2-81e9749f253d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483707414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1483707414
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1490344966
Short name T388
Test name
Test status
Simulation time 83738382 ps
CPU time 3.36 seconds
Started Jul 30 07:32:06 PM PDT 24
Finished Jul 30 07:32:10 PM PDT 24
Peak memory 215308 kb
Host smart-9885f2f4-a68c-41db-af9a-8d85d5a6ce0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1490344966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1490344966
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1853347883
Short name T443
Test name
Test status
Simulation time 379485757 ps
CPU time 3.29 seconds
Started Jul 30 07:32:07 PM PDT 24
Finished Jul 30 07:32:10 PM PDT 24
Peak memory 214164 kb
Host smart-598cbc92-ce70-4a73-aacf-362ba3e874ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853347883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1853347883
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.4188335350
Short name T462
Test name
Test status
Simulation time 64751152 ps
CPU time 2.4 seconds
Started Jul 30 07:32:07 PM PDT 24
Finished Jul 30 07:32:10 PM PDT 24
Peak memory 214336 kb
Host smart-aadb616e-12ed-4fb9-bad5-312f7bdd9735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188335350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.4188335350
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2944296796
Short name T843
Test name
Test status
Simulation time 4065293646 ps
CPU time 38.56 seconds
Started Jul 30 07:32:06 PM PDT 24
Finished Jul 30 07:32:45 PM PDT 24
Peak memory 222468 kb
Host smart-c6f12928-731e-4866-9453-18629742a9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944296796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2944296796
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.985428027
Short name T278
Test name
Test status
Simulation time 104371379 ps
CPU time 3.17 seconds
Started Jul 30 07:32:08 PM PDT 24
Finished Jul 30 07:32:11 PM PDT 24
Peak memory 209644 kb
Host smart-12f87c65-bea4-456d-b114-163935dc7017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985428027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.985428027
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1772486824
Short name T518
Test name
Test status
Simulation time 366873750 ps
CPU time 4.2 seconds
Started Jul 30 07:32:01 PM PDT 24
Finished Jul 30 07:32:06 PM PDT 24
Peak memory 210144 kb
Host smart-fcbe8ef4-741e-4d69-86cd-084fdde72f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772486824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1772486824
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3134428509
Short name T11
Test name
Test status
Simulation time 410061108 ps
CPU time 6.93 seconds
Started Jul 30 07:32:09 PM PDT 24
Finished Jul 30 07:32:16 PM PDT 24
Peak memory 237296 kb
Host smart-006f531f-34b4-474c-bf2f-6a09f2b10da4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134428509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3134428509
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.6968015
Short name T454
Test name
Test status
Simulation time 217441615 ps
CPU time 3.1 seconds
Started Jul 30 07:32:02 PM PDT 24
Finished Jul 30 07:32:06 PM PDT 24
Peak memory 206912 kb
Host smart-2b7cfdc2-b8b8-494b-a223-ff8e7d8e6e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6968015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.6968015
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1402390426
Short name T1
Test name
Test status
Simulation time 1226585089 ps
CPU time 30.65 seconds
Started Jul 30 07:32:05 PM PDT 24
Finished Jul 30 07:32:36 PM PDT 24
Peak memory 209168 kb
Host smart-e2c3c09e-95ca-4448-97ed-baf8395c06db
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402390426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1402390426
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2466859878
Short name T266
Test name
Test status
Simulation time 161485118 ps
CPU time 3.7 seconds
Started Jul 30 07:32:02 PM PDT 24
Finished Jul 30 07:32:06 PM PDT 24
Peak memory 209008 kb
Host smart-8ec64b56-2971-4389-8eba-5a5e0ff4a968
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466859878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2466859878
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3154072091
Short name T461
Test name
Test status
Simulation time 1110195867 ps
CPU time 14.85 seconds
Started Jul 30 07:32:03 PM PDT 24
Finished Jul 30 07:32:18 PM PDT 24
Peak memory 208032 kb
Host smart-166a9fb1-696f-4c01-821f-a005a1173cab
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154072091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3154072091
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.357676878
Short name T894
Test name
Test status
Simulation time 32474270 ps
CPU time 2.07 seconds
Started Jul 30 07:32:11 PM PDT 24
Finished Jul 30 07:32:13 PM PDT 24
Peak memory 214396 kb
Host smart-98852cb6-a127-4f24-bea1-c3058ac4c677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357676878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.357676878
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1415946730
Short name T465
Test name
Test status
Simulation time 795297927 ps
CPU time 11.59 seconds
Started Jul 30 07:32:03 PM PDT 24
Finished Jul 30 07:32:14 PM PDT 24
Peak memory 208024 kb
Host smart-525507d8-1b42-4185-9c51-c605d5425ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415946730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1415946730
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.829944843
Short name T526
Test name
Test status
Simulation time 383090848 ps
CPU time 4.53 seconds
Started Jul 30 07:32:07 PM PDT 24
Finished Jul 30 07:32:11 PM PDT 24
Peak memory 214304 kb
Host smart-f141a3d5-d105-4975-897a-fc4b2dac062b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829944843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.829944843
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2587565884
Short name T669
Test name
Test status
Simulation time 276348437 ps
CPU time 1.99 seconds
Started Jul 30 07:32:11 PM PDT 24
Finished Jul 30 07:32:13 PM PDT 24
Peak memory 209604 kb
Host smart-155e312e-49c0-4a8c-a332-34788d47db87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587565884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2587565884
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2396831906
Short name T618
Test name
Test status
Simulation time 45710554 ps
CPU time 0.85 seconds
Started Jul 30 07:34:35 PM PDT 24
Finished Jul 30 07:34:36 PM PDT 24
Peak memory 205980 kb
Host smart-47c9fba5-1c66-44b4-bea5-a82af0e71ab5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396831906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2396831906
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1743260980
Short name T505
Test name
Test status
Simulation time 113199021 ps
CPU time 2.04 seconds
Started Jul 30 07:34:35 PM PDT 24
Finished Jul 30 07:34:37 PM PDT 24
Peak memory 209240 kb
Host smart-bcfef163-ae65-4b38-9191-4a823c9e530a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743260980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1743260980
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1259055667
Short name T912
Test name
Test status
Simulation time 663524505 ps
CPU time 4 seconds
Started Jul 30 07:34:33 PM PDT 24
Finished Jul 30 07:34:37 PM PDT 24
Peak memory 208936 kb
Host smart-47ea1f1b-8d04-41a9-93f7-afe84c51ee40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259055667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1259055667
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.816695227
Short name T81
Test name
Test status
Simulation time 232489916 ps
CPU time 3.24 seconds
Started Jul 30 07:34:32 PM PDT 24
Finished Jul 30 07:34:35 PM PDT 24
Peak memory 208972 kb
Host smart-fa6687bb-6524-4771-995c-0b66519c3225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816695227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.816695227
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2581892202
Short name T335
Test name
Test status
Simulation time 243476359 ps
CPU time 4.27 seconds
Started Jul 30 07:34:36 PM PDT 24
Finished Jul 30 07:34:40 PM PDT 24
Peak memory 222380 kb
Host smart-a9c7b7b0-24e2-4bd9-a643-ad18d36aa1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581892202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2581892202
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3830499289
Short name T535
Test name
Test status
Simulation time 109344028 ps
CPU time 2.36 seconds
Started Jul 30 07:34:26 PM PDT 24
Finished Jul 30 07:34:29 PM PDT 24
Peak memory 220120 kb
Host smart-4b8ab021-008b-44ea-9e03-13d622dcf4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830499289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3830499289
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3629251735
Short name T552
Test name
Test status
Simulation time 953862183 ps
CPU time 4.96 seconds
Started Jul 30 07:34:20 PM PDT 24
Finished Jul 30 07:34:25 PM PDT 24
Peak memory 207656 kb
Host smart-6c642d98-c976-4884-bc8a-f948a1953cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629251735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3629251735
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.577767873
Short name T430
Test name
Test status
Simulation time 150373935 ps
CPU time 5.33 seconds
Started Jul 30 07:34:31 PM PDT 24
Finished Jul 30 07:34:36 PM PDT 24
Peak memory 206740 kb
Host smart-628aa9ad-006f-469c-9150-f457c9383a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577767873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.577767873
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.464036669
Short name T433
Test name
Test status
Simulation time 158026583 ps
CPU time 5.27 seconds
Started Jul 30 07:34:02 PM PDT 24
Finished Jul 30 07:34:07 PM PDT 24
Peak memory 208176 kb
Host smart-aa87f9e2-84b3-4c04-9330-ae2a45038804
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464036669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.464036669
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.1092447980
Short name T524
Test name
Test status
Simulation time 80322053 ps
CPU time 2.88 seconds
Started Jul 30 07:34:32 PM PDT 24
Finished Jul 30 07:34:35 PM PDT 24
Peak memory 208612 kb
Host smart-6da3189d-6a08-47f2-9851-be1141dfda5a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092447980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1092447980
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1712168286
Short name T579
Test name
Test status
Simulation time 41386664 ps
CPU time 2.57 seconds
Started Jul 30 07:34:25 PM PDT 24
Finished Jul 30 07:34:28 PM PDT 24
Peak memory 208840 kb
Host smart-ae8d028f-c2bf-41e4-8b61-8e1f611342bd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712168286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1712168286
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3092350965
Short name T295
Test name
Test status
Simulation time 376703861 ps
CPU time 3.17 seconds
Started Jul 30 07:34:34 PM PDT 24
Finished Jul 30 07:34:37 PM PDT 24
Peak memory 218460 kb
Host smart-25ac9857-d7e3-4428-9f87-1198f0624448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092350965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3092350965
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2913095262
Short name T542
Test name
Test status
Simulation time 48153627 ps
CPU time 2.61 seconds
Started Jul 30 07:34:00 PM PDT 24
Finished Jul 30 07:34:03 PM PDT 24
Peak memory 208824 kb
Host smart-d5d4d3d7-511f-49d4-88f2-4b9c31569d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913095262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2913095262
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1667938037
Short name T195
Test name
Test status
Simulation time 4143372629 ps
CPU time 24.99 seconds
Started Jul 30 07:34:33 PM PDT 24
Finished Jul 30 07:34:58 PM PDT 24
Peak memory 217100 kb
Host smart-1fc7e0c2-a574-496d-bba5-781394165e1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667938037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1667938037
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2270813825
Short name T815
Test name
Test status
Simulation time 515772119 ps
CPU time 6.51 seconds
Started Jul 30 07:34:35 PM PDT 24
Finished Jul 30 07:34:41 PM PDT 24
Peak memory 210224 kb
Host smart-e3e4d813-8802-4539-bfab-74e48450bc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270813825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2270813825
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3947422881
Short name T198
Test name
Test status
Simulation time 181657925 ps
CPU time 2.22 seconds
Started Jul 30 07:34:32 PM PDT 24
Finished Jul 30 07:34:34 PM PDT 24
Peak memory 210068 kb
Host smart-58d178d7-37d7-4010-ab55-c19fd8b30aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947422881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3947422881
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1659797553
Short name T65
Test name
Test status
Simulation time 222264806 ps
CPU time 3.1 seconds
Started Jul 30 07:34:41 PM PDT 24
Finished Jul 30 07:34:44 PM PDT 24
Peak memory 222600 kb
Host smart-c38f04e5-702b-4602-8970-55710cdba6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659797553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1659797553
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1506676329
Short name T342
Test name
Test status
Simulation time 73422699 ps
CPU time 2.31 seconds
Started Jul 30 07:34:41 PM PDT 24
Finished Jul 30 07:34:43 PM PDT 24
Peak memory 218456 kb
Host smart-d6a7eb1e-c62c-4d4e-ba1d-a610b972df87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506676329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1506676329
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.4077500822
Short name T203
Test name
Test status
Simulation time 144243478 ps
CPU time 2.87 seconds
Started Jul 30 07:34:38 PM PDT 24
Finished Jul 30 07:34:41 PM PDT 24
Peak memory 214308 kb
Host smart-bf26a66e-002d-4652-8515-eef6598e3e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077500822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.4077500822
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2258241521
Short name T896
Test name
Test status
Simulation time 463084646 ps
CPU time 3.31 seconds
Started Jul 30 07:34:38 PM PDT 24
Finished Jul 30 07:34:41 PM PDT 24
Peak memory 214704 kb
Host smart-7673a967-ecd0-4685-bfae-956de1706b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258241521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2258241521
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2579517949
Short name T353
Test name
Test status
Simulation time 54576261 ps
CPU time 3.26 seconds
Started Jul 30 07:34:36 PM PDT 24
Finished Jul 30 07:34:39 PM PDT 24
Peak memory 207092 kb
Host smart-7a91980a-2dba-496c-bd36-1f6930b1faf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579517949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2579517949
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3317609655
Short name T772
Test name
Test status
Simulation time 338183256 ps
CPU time 6.92 seconds
Started Jul 30 07:34:37 PM PDT 24
Finished Jul 30 07:34:44 PM PDT 24
Peak memory 206928 kb
Host smart-fda16521-08d6-4017-82be-e5d3cee8a334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317609655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3317609655
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.383031463
Short name T506
Test name
Test status
Simulation time 494341985 ps
CPU time 4.56 seconds
Started Jul 30 07:34:36 PM PDT 24
Finished Jul 30 07:34:40 PM PDT 24
Peak memory 208660 kb
Host smart-47384018-86fb-4fb4-b352-ed6a0dd78f61
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383031463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.383031463
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.101472381
Short name T479
Test name
Test status
Simulation time 76000917 ps
CPU time 2.72 seconds
Started Jul 30 07:34:36 PM PDT 24
Finished Jul 30 07:34:39 PM PDT 24
Peak memory 207036 kb
Host smart-ff769880-b634-4b89-b21f-0b7123abdba3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101472381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.101472381
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1027226375
Short name T108
Test name
Test status
Simulation time 90288530 ps
CPU time 3.26 seconds
Started Jul 30 07:34:38 PM PDT 24
Finished Jul 30 07:34:41 PM PDT 24
Peak memory 206844 kb
Host smart-b0fc38c8-d1d6-4548-afa9-2379f0a11226
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027226375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1027226375
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1430557184
Short name T521
Test name
Test status
Simulation time 402268197 ps
CPU time 3.94 seconds
Started Jul 30 07:34:39 PM PDT 24
Finished Jul 30 07:34:43 PM PDT 24
Peak memory 215428 kb
Host smart-2976337a-9b0f-4718-bb48-fff741b1df19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430557184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1430557184
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3210376214
Short name T427
Test name
Test status
Simulation time 650703517 ps
CPU time 11.59 seconds
Started Jul 30 07:34:34 PM PDT 24
Finished Jul 30 07:34:46 PM PDT 24
Peak memory 208068 kb
Host smart-c8b76fc8-2a4b-4dca-9af0-5489d8240e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210376214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3210376214
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.4068675190
Short name T723
Test name
Test status
Simulation time 25991201410 ps
CPU time 68.88 seconds
Started Jul 30 07:34:26 PM PDT 24
Finished Jul 30 07:35:35 PM PDT 24
Peak memory 217196 kb
Host smart-9959bf0d-531d-4b7b-a3f2-e308c7f8d70b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068675190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.4068675190
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.341827572
Short name T42
Test name
Test status
Simulation time 302909956 ps
CPU time 7.34 seconds
Started Jul 30 07:34:42 PM PDT 24
Finished Jul 30 07:34:50 PM PDT 24
Peak memory 222652 kb
Host smart-a4f750c6-d600-4deb-b5f2-920175963125
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341827572 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.341827572
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.4107101667
Short name T448
Test name
Test status
Simulation time 187216273 ps
CPU time 2.61 seconds
Started Jul 30 07:34:40 PM PDT 24
Finished Jul 30 07:34:43 PM PDT 24
Peak memory 214376 kb
Host smart-1eebc63f-4dba-4ec0-b7df-be389e842924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107101667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.4107101667
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2359058698
Short name T897
Test name
Test status
Simulation time 205052623 ps
CPU time 4.43 seconds
Started Jul 30 07:34:39 PM PDT 24
Finished Jul 30 07:34:43 PM PDT 24
Peak memory 210696 kb
Host smart-c5052cb7-c395-4be9-9102-30043495cbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359058698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2359058698
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.2608718422
Short name T487
Test name
Test status
Simulation time 11503877 ps
CPU time 0.85 seconds
Started Jul 30 07:34:45 PM PDT 24
Finished Jul 30 07:34:46 PM PDT 24
Peak memory 205952 kb
Host smart-b9c12ce5-0974-4997-80b5-b25b7a87adf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608718422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.2608718422
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2252848778
Short name T233
Test name
Test status
Simulation time 137788199 ps
CPU time 2.22 seconds
Started Jul 30 07:34:44 PM PDT 24
Finished Jul 30 07:34:47 PM PDT 24
Peak memory 214352 kb
Host smart-7db5f00c-b958-4556-aeb3-2fad34f0b971
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2252848778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2252848778
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.912221218
Short name T758
Test name
Test status
Simulation time 42882822 ps
CPU time 2.36 seconds
Started Jul 30 07:34:46 PM PDT 24
Finished Jul 30 07:34:49 PM PDT 24
Peak memory 208608 kb
Host smart-1ac0cf75-6b98-4bb1-907d-25f41a5fbb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912221218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.912221218
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3852952181
Short name T51
Test name
Test status
Simulation time 29672202 ps
CPU time 1.97 seconds
Started Jul 30 07:34:42 PM PDT 24
Finished Jul 30 07:34:44 PM PDT 24
Peak memory 209884 kb
Host smart-45b77509-e8e5-4ec8-9201-cff963f19e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852952181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3852952181
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2000326363
Short name T239
Test name
Test status
Simulation time 229907439 ps
CPU time 5.21 seconds
Started Jul 30 07:34:43 PM PDT 24
Finished Jul 30 07:34:48 PM PDT 24
Peak memory 214348 kb
Host smart-1fba8f31-30a8-4eb6-be99-a6e252e86ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000326363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2000326363
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1311372865
Short name T262
Test name
Test status
Simulation time 466647635 ps
CPU time 4.38 seconds
Started Jul 30 07:34:43 PM PDT 24
Finished Jul 30 07:34:47 PM PDT 24
Peak memory 214496 kb
Host smart-eb84fa16-b20a-411f-a799-8b6bf47e4111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311372865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1311372865
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1079493612
Short name T720
Test name
Test status
Simulation time 664372920 ps
CPU time 9.04 seconds
Started Jul 30 07:34:43 PM PDT 24
Finished Jul 30 07:34:52 PM PDT 24
Peak memory 214276 kb
Host smart-c6682876-7c39-4aad-a4dd-ddb58f2031ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079493612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1079493612
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.1427016765
Short name T776
Test name
Test status
Simulation time 89302095 ps
CPU time 4.11 seconds
Started Jul 30 07:34:45 PM PDT 24
Finished Jul 30 07:34:49 PM PDT 24
Peak memory 210200 kb
Host smart-3fb0532e-d139-4f86-9166-c1c5247af854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427016765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1427016765
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1695968106
Short name T747
Test name
Test status
Simulation time 32725710 ps
CPU time 2.3 seconds
Started Jul 30 07:34:43 PM PDT 24
Finished Jul 30 07:34:46 PM PDT 24
Peak memory 206984 kb
Host smart-f996ddbd-bafa-4ea2-8c58-142089f8e0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695968106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1695968106
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3216449055
Short name T194
Test name
Test status
Simulation time 6073523534 ps
CPU time 55.03 seconds
Started Jul 30 07:34:42 PM PDT 24
Finished Jul 30 07:35:38 PM PDT 24
Peak memory 208592 kb
Host smart-eb930d86-9835-4c89-ba7a-90361e57267c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216449055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3216449055
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3045129185
Short name T858
Test name
Test status
Simulation time 1504748633 ps
CPU time 43.16 seconds
Started Jul 30 07:34:41 PM PDT 24
Finished Jul 30 07:35:25 PM PDT 24
Peak memory 208548 kb
Host smart-066ae86b-1271-4454-96e5-7f0c6eb367f3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045129185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3045129185
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.351769743
Short name T458
Test name
Test status
Simulation time 116237477 ps
CPU time 4.03 seconds
Started Jul 30 07:34:44 PM PDT 24
Finished Jul 30 07:34:48 PM PDT 24
Peak memory 208728 kb
Host smart-02547a3b-a464-480c-a497-6cbf9757c6cd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351769743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.351769743
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1887179177
Short name T587
Test name
Test status
Simulation time 122516343 ps
CPU time 1.83 seconds
Started Jul 30 07:34:42 PM PDT 24
Finished Jul 30 07:34:44 PM PDT 24
Peak memory 207564 kb
Host smart-ad994de9-31cf-492e-b2e8-3f10b44eeb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887179177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1887179177
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2406941389
Short name T519
Test name
Test status
Simulation time 185307352 ps
CPU time 1.73 seconds
Started Jul 30 07:34:43 PM PDT 24
Finished Jul 30 07:34:45 PM PDT 24
Peak memory 206084 kb
Host smart-0c7aced4-95b6-43ea-9d3d-76c17b0af01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406941389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2406941389
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2481812100
Short name T870
Test name
Test status
Simulation time 265535546 ps
CPU time 6.32 seconds
Started Jul 30 07:34:45 PM PDT 24
Finished Jul 30 07:34:51 PM PDT 24
Peak memory 214236 kb
Host smart-20e92cbb-6b75-46ad-9809-ce173dba79c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481812100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2481812100
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.3623041509
Short name T469
Test name
Test status
Simulation time 1821018968 ps
CPU time 21.49 seconds
Started Jul 30 07:34:41 PM PDT 24
Finished Jul 30 07:35:03 PM PDT 24
Peak memory 222576 kb
Host smart-93f702e1-e9f2-46cc-89a4-3cdf6ba8c871
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623041509 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.3623041509
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1243877890
Short name T141
Test name
Test status
Simulation time 2668462063 ps
CPU time 52.81 seconds
Started Jul 30 07:34:42 PM PDT 24
Finished Jul 30 07:35:35 PM PDT 24
Peak memory 214372 kb
Host smart-7a44d94f-05f0-4b41-b699-fed86e7b5a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243877890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1243877890
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1670802419
Short name T33
Test name
Test status
Simulation time 540122916 ps
CPU time 3.54 seconds
Started Jul 30 07:34:43 PM PDT 24
Finished Jul 30 07:34:46 PM PDT 24
Peak memory 210536 kb
Host smart-3581add4-9b41-44c9-ba00-4bbad9aef2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670802419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1670802419
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.789867607
Short name T438
Test name
Test status
Simulation time 72037010 ps
CPU time 0.75 seconds
Started Jul 30 07:34:49 PM PDT 24
Finished Jul 30 07:34:50 PM PDT 24
Peak memory 205936 kb
Host smart-d65da9f0-823d-4e15-a8e9-f98b25a1162f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789867607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.789867607
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.35113448
Short name T369
Test name
Test status
Simulation time 854833844 ps
CPU time 44.95 seconds
Started Jul 30 07:34:42 PM PDT 24
Finished Jul 30 07:35:27 PM PDT 24
Peak memory 214944 kb
Host smart-88aa7bd0-a93d-4b7a-ac78-2750c5a10324
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=35113448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.35113448
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2216787272
Short name T32
Test name
Test status
Simulation time 43236122 ps
CPU time 2.92 seconds
Started Jul 30 07:34:43 PM PDT 24
Finished Jul 30 07:34:47 PM PDT 24
Peak memory 216660 kb
Host smart-052e3656-d242-4369-a247-7ed364065836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216787272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2216787272
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1634740663
Short name T488
Test name
Test status
Simulation time 179654471 ps
CPU time 3.95 seconds
Started Jul 30 07:34:46 PM PDT 24
Finished Jul 30 07:34:50 PM PDT 24
Peak memory 208836 kb
Host smart-7c31dea7-e40a-4cc8-a9a5-d967c8b70417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634740663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1634740663
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.4186938148
Short name T89
Test name
Test status
Simulation time 34495091 ps
CPU time 1.98 seconds
Started Jul 30 07:34:45 PM PDT 24
Finished Jul 30 07:34:47 PM PDT 24
Peak memory 214272 kb
Host smart-c3c6b23d-0548-433d-b21f-b222525c5dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186938148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.4186938148
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2037050839
Short name T215
Test name
Test status
Simulation time 272433234 ps
CPU time 3.33 seconds
Started Jul 30 07:34:43 PM PDT 24
Finished Jul 30 07:34:46 PM PDT 24
Peak memory 209868 kb
Host smart-5b61990c-9d40-47a3-a688-174b3de48da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037050839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2037050839
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.1060830464
Short name T686
Test name
Test status
Simulation time 369015787 ps
CPU time 4.88 seconds
Started Jul 30 07:34:44 PM PDT 24
Finished Jul 30 07:34:49 PM PDT 24
Peak memory 218516 kb
Host smart-4f323de2-9ff6-4c44-b3e5-ee6bd76e8f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060830464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1060830464
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1252238135
Short name T719
Test name
Test status
Simulation time 251713276 ps
CPU time 3.38 seconds
Started Jul 30 07:34:46 PM PDT 24
Finished Jul 30 07:34:50 PM PDT 24
Peak memory 208800 kb
Host smart-a909898b-a7b0-455a-b2f5-9c05024e5cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252238135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1252238135
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.89101802
Short name T831
Test name
Test status
Simulation time 95597713 ps
CPU time 3.55 seconds
Started Jul 30 07:34:45 PM PDT 24
Finished Jul 30 07:34:49 PM PDT 24
Peak memory 208036 kb
Host smart-ecce1cbe-e35c-4865-8105-dad86522d9f4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89101802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.89101802
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2562107906
Short name T590
Test name
Test status
Simulation time 168757274 ps
CPU time 2.52 seconds
Started Jul 30 07:34:40 PM PDT 24
Finished Jul 30 07:34:43 PM PDT 24
Peak memory 206944 kb
Host smart-fd6993bb-5e47-43ea-a63d-091e9c043606
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562107906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2562107906
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1071011526
Short name T762
Test name
Test status
Simulation time 619752797 ps
CPU time 3.13 seconds
Started Jul 30 07:34:45 PM PDT 24
Finished Jul 30 07:34:48 PM PDT 24
Peak memory 207040 kb
Host smart-d3f08a94-20cb-4786-a203-ced19c9a1e08
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071011526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1071011526
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2051032356
Short name T761
Test name
Test status
Simulation time 1034630883 ps
CPU time 3.4 seconds
Started Jul 30 07:34:43 PM PDT 24
Finished Jul 30 07:34:47 PM PDT 24
Peak memory 210228 kb
Host smart-07c0db0a-1c2d-49be-84b8-aa1ce0d8bfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051032356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2051032356
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.812107604
Short name T514
Test name
Test status
Simulation time 46122283 ps
CPU time 2.26 seconds
Started Jul 30 07:34:46 PM PDT 24
Finished Jul 30 07:34:49 PM PDT 24
Peak memory 206828 kb
Host smart-cbff4aac-c1b5-4657-8d78-5912be7f1f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812107604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.812107604
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1881202800
Short name T228
Test name
Test status
Simulation time 1208755565 ps
CPU time 11.69 seconds
Started Jul 30 07:34:46 PM PDT 24
Finished Jul 30 07:34:58 PM PDT 24
Peak memory 216276 kb
Host smart-776776d2-64af-4863-b945-5a8c201ef9ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881202800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1881202800
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.4262905314
Short name T493
Test name
Test status
Simulation time 336621221 ps
CPU time 3.55 seconds
Started Jul 30 07:34:42 PM PDT 24
Finished Jul 30 07:34:46 PM PDT 24
Peak memory 209444 kb
Host smart-2e3f958b-299e-4b9a-96bf-ede10b04cd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262905314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.4262905314
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.4099580383
Short name T665
Test name
Test status
Simulation time 22470181 ps
CPU time 0.73 seconds
Started Jul 30 07:34:48 PM PDT 24
Finished Jul 30 07:34:49 PM PDT 24
Peak memory 205936 kb
Host smart-9d662c22-0a32-46ad-9a13-6fad85006df2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099580383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.4099580383
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1433406465
Short name T657
Test name
Test status
Simulation time 697257689 ps
CPU time 6.42 seconds
Started Jul 30 07:34:48 PM PDT 24
Finished Jul 30 07:34:55 PM PDT 24
Peak memory 217884 kb
Host smart-2ed013d2-41fd-4173-a782-615116f36d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433406465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1433406465
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2825929743
Short name T394
Test name
Test status
Simulation time 57687335 ps
CPU time 2.08 seconds
Started Jul 30 07:34:46 PM PDT 24
Finished Jul 30 07:34:48 PM PDT 24
Peak memory 207568 kb
Host smart-07e99849-17bf-4210-8f3f-2bdf79f02262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825929743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2825929743
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2238893490
Short name T103
Test name
Test status
Simulation time 91081541 ps
CPU time 1.76 seconds
Started Jul 30 07:34:45 PM PDT 24
Finished Jul 30 07:34:47 PM PDT 24
Peak memory 214260 kb
Host smart-9a0f5592-a7ee-4c92-a36d-62d911d73112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238893490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2238893490
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_random.3589759145
Short name T13
Test name
Test status
Simulation time 560964899 ps
CPU time 7.61 seconds
Started Jul 30 07:34:49 PM PDT 24
Finished Jul 30 07:34:56 PM PDT 24
Peak memory 214428 kb
Host smart-a74501a5-efe1-4188-8149-947589cf0aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589759145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3589759145
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2353545059
Short name T672
Test name
Test status
Simulation time 907272690 ps
CPU time 25.78 seconds
Started Jul 30 07:34:45 PM PDT 24
Finished Jul 30 07:35:11 PM PDT 24
Peak memory 207868 kb
Host smart-3555be23-9cca-4237-97de-df0a2cf1ad80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353545059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2353545059
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.96127072
Short name T426
Test name
Test status
Simulation time 2332314945 ps
CPU time 43.15 seconds
Started Jul 30 07:34:44 PM PDT 24
Finished Jul 30 07:35:27 PM PDT 24
Peak memory 208184 kb
Host smart-9888dbaa-fe36-456f-ad3a-fee898e043af
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96127072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.96127072
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2151712666
Short name T553
Test name
Test status
Simulation time 612866511 ps
CPU time 11.92 seconds
Started Jul 30 07:34:48 PM PDT 24
Finished Jul 30 07:35:01 PM PDT 24
Peak memory 208880 kb
Host smart-3c22cd5a-b9d9-440f-b9db-fd81b35be3c1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151712666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2151712666
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1828889789
Short name T463
Test name
Test status
Simulation time 38267079 ps
CPU time 2.52 seconds
Started Jul 30 07:34:51 PM PDT 24
Finished Jul 30 07:34:53 PM PDT 24
Peak memory 206964 kb
Host smart-7217a108-e10c-4849-93a2-5f0346fe6d82
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828889789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1828889789
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.505870130
Short name T431
Test name
Test status
Simulation time 44584941 ps
CPU time 2.17 seconds
Started Jul 30 07:34:49 PM PDT 24
Finished Jul 30 07:34:51 PM PDT 24
Peak memory 209124 kb
Host smart-e8518511-b764-4366-9f68-23b7fc0fec6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505870130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.505870130
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1483181233
Short name T598
Test name
Test status
Simulation time 334246413 ps
CPU time 3.68 seconds
Started Jul 30 07:34:51 PM PDT 24
Finished Jul 30 07:34:54 PM PDT 24
Peak memory 206664 kb
Host smart-3319b471-8268-42c9-a9f2-335c4dd65f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483181233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1483181233
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1056744415
Short name T349
Test name
Test status
Simulation time 993807825 ps
CPU time 31.41 seconds
Started Jul 30 07:34:44 PM PDT 24
Finished Jul 30 07:35:16 PM PDT 24
Peak memory 215736 kb
Host smart-df58db43-e39d-4d6f-9c4a-a84b84c758fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056744415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1056744415
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1197049120
Short name T301
Test name
Test status
Simulation time 502041238 ps
CPU time 4.84 seconds
Started Jul 30 07:34:48 PM PDT 24
Finished Jul 30 07:34:53 PM PDT 24
Peak memory 214304 kb
Host smart-c21e587e-910c-4d2f-876c-b24a73da9759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197049120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1197049120
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3885622065
Short name T58
Test name
Test status
Simulation time 29633246 ps
CPU time 1.78 seconds
Started Jul 30 07:34:49 PM PDT 24
Finished Jul 30 07:34:51 PM PDT 24
Peak memory 209848 kb
Host smart-43b2db77-c10e-4eac-a634-d554fd9beb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885622065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3885622065
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1654745013
Short name T99
Test name
Test status
Simulation time 20513626 ps
CPU time 0.86 seconds
Started Jul 30 07:34:50 PM PDT 24
Finished Jul 30 07:34:51 PM PDT 24
Peak memory 205924 kb
Host smart-5f4f89f5-7da8-4b6f-9f84-c09a0d5a246b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654745013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1654745013
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3894493948
Short name T860
Test name
Test status
Simulation time 2305177097 ps
CPU time 5.92 seconds
Started Jul 30 07:34:49 PM PDT 24
Finished Jul 30 07:34:55 PM PDT 24
Peak memory 214412 kb
Host smart-ce410628-7149-4d7d-85f6-a51615b01e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894493948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3894493948
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.2592261980
Short name T777
Test name
Test status
Simulation time 2814386198 ps
CPU time 27.49 seconds
Started Jul 30 07:34:48 PM PDT 24
Finished Jul 30 07:35:15 PM PDT 24
Peak memory 208948 kb
Host smart-ff5c0556-aed0-40c2-abc2-2c4a18a224ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592261980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2592261980
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1086682167
Short name T288
Test name
Test status
Simulation time 229969460 ps
CPU time 3.25 seconds
Started Jul 30 07:34:53 PM PDT 24
Finished Jul 30 07:34:57 PM PDT 24
Peak memory 214264 kb
Host smart-6e41fd5c-e280-4ff9-99d6-c5b747b87e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086682167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1086682167
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1354704540
Short name T182
Test name
Test status
Simulation time 26196980 ps
CPU time 1.72 seconds
Started Jul 30 07:34:50 PM PDT 24
Finished Jul 30 07:34:52 PM PDT 24
Peak memory 220436 kb
Host smart-0493e46c-add7-44bb-9c2a-e3df2933bab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354704540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1354704540
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2120493043
Short name T637
Test name
Test status
Simulation time 186289560 ps
CPU time 7.14 seconds
Started Jul 30 07:34:53 PM PDT 24
Finished Jul 30 07:35:01 PM PDT 24
Peak memory 208936 kb
Host smart-634166e0-9a7b-43c9-856c-5091dea005d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120493043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2120493043
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.102398642
Short name T741
Test name
Test status
Simulation time 870160324 ps
CPU time 14.42 seconds
Started Jul 30 07:34:49 PM PDT 24
Finished Jul 30 07:35:03 PM PDT 24
Peak memory 207844 kb
Host smart-c0da422c-49a4-47ef-ac8a-37dec9a551df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102398642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.102398642
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3078177787
Short name T496
Test name
Test status
Simulation time 455168258 ps
CPU time 6.38 seconds
Started Jul 30 07:34:51 PM PDT 24
Finished Jul 30 07:34:57 PM PDT 24
Peak memory 208900 kb
Host smart-92ee62df-e268-49ba-98d1-5177ed646f18
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078177787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3078177787
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2470881046
Short name T395
Test name
Test status
Simulation time 66361016 ps
CPU time 2.41 seconds
Started Jul 30 07:34:50 PM PDT 24
Finished Jul 30 07:34:53 PM PDT 24
Peak memory 206956 kb
Host smart-844749be-29ad-472a-b874-312a92f00ce1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470881046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2470881046
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3104373836
Short name T603
Test name
Test status
Simulation time 238799842 ps
CPU time 6.57 seconds
Started Jul 30 07:34:50 PM PDT 24
Finished Jul 30 07:34:56 PM PDT 24
Peak memory 208852 kb
Host smart-6bb30f61-1e19-415a-975c-da4a4296441f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104373836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3104373836
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.192713653
Short name T649
Test name
Test status
Simulation time 79473786 ps
CPU time 3.67 seconds
Started Jul 30 07:34:47 PM PDT 24
Finished Jul 30 07:34:51 PM PDT 24
Peak memory 218100 kb
Host smart-3c5d1780-e308-4784-999e-0e64fb563df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192713653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.192713653
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1256674101
Short name T722
Test name
Test status
Simulation time 103571839 ps
CPU time 2.38 seconds
Started Jul 30 07:34:49 PM PDT 24
Finished Jul 30 07:34:52 PM PDT 24
Peak memory 206752 kb
Host smart-e72aae2c-6708-49c9-a344-a82a697778b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256674101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1256674101
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3853614682
Short name T560
Test name
Test status
Simulation time 88912132 ps
CPU time 2.74 seconds
Started Jul 30 07:34:49 PM PDT 24
Finished Jul 30 07:34:52 PM PDT 24
Peak memory 208536 kb
Host smart-aad86929-c4ae-48ad-930f-bdfeb0564ab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853614682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3853614682
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2277155631
Short name T185
Test name
Test status
Simulation time 489112603 ps
CPU time 16.14 seconds
Started Jul 30 07:34:49 PM PDT 24
Finished Jul 30 07:35:05 PM PDT 24
Peak memory 222488 kb
Host smart-8f25fb4c-dc46-432b-a546-782040522782
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277155631 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2277155631
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2782677172
Short name T789
Test name
Test status
Simulation time 389224658 ps
CPU time 4.8 seconds
Started Jul 30 07:34:54 PM PDT 24
Finished Jul 30 07:34:58 PM PDT 24
Peak memory 208136 kb
Host smart-2372b8a5-da4c-44f5-9d7b-1e8fd3712360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782677172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2782677172
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.174867825
Short name T180
Test name
Test status
Simulation time 64935505 ps
CPU time 2.91 seconds
Started Jul 30 07:34:50 PM PDT 24
Finished Jul 30 07:34:53 PM PDT 24
Peak memory 210568 kb
Host smart-3f579368-c9ab-4f3e-aec8-fae9b0bcad00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174867825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.174867825
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1517857152
Short name T83
Test name
Test status
Simulation time 32951789 ps
CPU time 0.72 seconds
Started Jul 30 07:34:52 PM PDT 24
Finished Jul 30 07:34:53 PM PDT 24
Peak memory 205956 kb
Host smart-deb86a2e-8ff7-47e9-b82c-bcf5f3660168
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517857152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1517857152
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.1272203727
Short name T85
Test name
Test status
Simulation time 232071240 ps
CPU time 4.16 seconds
Started Jul 30 07:34:51 PM PDT 24
Finished Jul 30 07:34:55 PM PDT 24
Peak memory 215496 kb
Host smart-44b6dd8d-a156-4953-a1bd-0ca61ff2ec13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1272203727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.1272203727
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1564844004
Short name T210
Test name
Test status
Simulation time 88992562 ps
CPU time 1.8 seconds
Started Jul 30 07:34:47 PM PDT 24
Finished Jul 30 07:34:49 PM PDT 24
Peak memory 222372 kb
Host smart-55ae7064-16ed-4e11-b508-d4e212aaafdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564844004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1564844004
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3769453888
Short name T107
Test name
Test status
Simulation time 280438213 ps
CPU time 3.24 seconds
Started Jul 30 07:34:52 PM PDT 24
Finished Jul 30 07:34:55 PM PDT 24
Peak memory 210544 kb
Host smart-7282e34a-d72e-411f-b029-b1c2fed8c4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769453888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3769453888
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2667224926
Short name T358
Test name
Test status
Simulation time 770131621 ps
CPU time 3.4 seconds
Started Jul 30 07:34:51 PM PDT 24
Finished Jul 30 07:34:55 PM PDT 24
Peak memory 214420 kb
Host smart-96a453b9-3901-4baf-bf6d-43fd6f037089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667224926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2667224926
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3645009175
Short name T855
Test name
Test status
Simulation time 340510202 ps
CPU time 2.83 seconds
Started Jul 30 07:34:52 PM PDT 24
Finished Jul 30 07:34:54 PM PDT 24
Peak memory 222496 kb
Host smart-95dff424-85b3-447c-9924-90e82cf17805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645009175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3645009175
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2057012212
Short name T432
Test name
Test status
Simulation time 302525336 ps
CPU time 3.68 seconds
Started Jul 30 07:34:54 PM PDT 24
Finished Jul 30 07:34:57 PM PDT 24
Peak memory 208432 kb
Host smart-11ef05bb-affd-4281-9937-199aa4b3fbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057012212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2057012212
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1820384807
Short name T883
Test name
Test status
Simulation time 185086164 ps
CPU time 3.49 seconds
Started Jul 30 07:34:46 PM PDT 24
Finished Jul 30 07:34:50 PM PDT 24
Peak memory 208960 kb
Host smart-aae1aebb-7ae8-456f-a625-bb003b7d4aea
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820384807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1820384807
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3572785971
Short name T101
Test name
Test status
Simulation time 85389761 ps
CPU time 2.19 seconds
Started Jul 30 07:34:54 PM PDT 24
Finished Jul 30 07:34:56 PM PDT 24
Peak memory 208776 kb
Host smart-616ca951-4bbe-4bc6-9d77-fe6e17815513
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572785971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3572785971
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2524757371
Short name T799
Test name
Test status
Simulation time 249260291 ps
CPU time 2.82 seconds
Started Jul 30 07:34:50 PM PDT 24
Finished Jul 30 07:34:52 PM PDT 24
Peak memory 206800 kb
Host smart-8316a266-e536-4bb4-b56d-767c187946fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524757371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2524757371
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3176813548
Short name T697
Test name
Test status
Simulation time 302348030 ps
CPU time 2.4 seconds
Started Jul 30 07:34:53 PM PDT 24
Finished Jul 30 07:34:55 PM PDT 24
Peak memory 208004 kb
Host smart-d18f2e8b-50fa-4278-b016-0557e29aeb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176813548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3176813548
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.693235995
Short name T565
Test name
Test status
Simulation time 73862840 ps
CPU time 2.16 seconds
Started Jul 30 07:34:52 PM PDT 24
Finished Jul 30 07:34:55 PM PDT 24
Peak memory 206800 kb
Host smart-4fa565d9-af3e-49e3-8090-70df880a27e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693235995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.693235995
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.563424606
Short name T674
Test name
Test status
Simulation time 132876499 ps
CPU time 7.5 seconds
Started Jul 30 07:34:47 PM PDT 24
Finished Jul 30 07:34:55 PM PDT 24
Peak memory 220600 kb
Host smart-4f3f31d2-8b8f-42d1-9fe8-d271abf2d5d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563424606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.563424606
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.805619013
Short name T556
Test name
Test status
Simulation time 765704283 ps
CPU time 11.16 seconds
Started Jul 30 07:34:52 PM PDT 24
Finished Jul 30 07:35:03 PM PDT 24
Peak memory 222644 kb
Host smart-bdeb955e-dc4d-442c-9a65-5133fd5c508d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805619013 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.805619013
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1005345516
Short name T546
Test name
Test status
Simulation time 87595844 ps
CPU time 3.56 seconds
Started Jul 30 07:34:52 PM PDT 24
Finished Jul 30 07:34:56 PM PDT 24
Peak memory 208024 kb
Host smart-106be3bd-4f74-47af-a526-b49765caf541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005345516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1005345516
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1351964747
Short name T812
Test name
Test status
Simulation time 678212163 ps
CPU time 6.87 seconds
Started Jul 30 07:34:48 PM PDT 24
Finished Jul 30 07:34:55 PM PDT 24
Peak memory 211024 kb
Host smart-a5b0bddc-922a-46a4-b88e-f6fe87ad4fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351964747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1351964747
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3988064201
Short name T864
Test name
Test status
Simulation time 41092448 ps
CPU time 0.83 seconds
Started Jul 30 07:35:03 PM PDT 24
Finished Jul 30 07:35:04 PM PDT 24
Peak memory 205936 kb
Host smart-1b41b0e7-36b4-476e-8644-fee13286247a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988064201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3988064201
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.3782567296
Short name T235
Test name
Test status
Simulation time 160694878 ps
CPU time 3.39 seconds
Started Jul 30 07:34:48 PM PDT 24
Finished Jul 30 07:34:51 PM PDT 24
Peak memory 214316 kb
Host smart-a7667bda-10c8-42e9-9411-764c675131d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3782567296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3782567296
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1549571340
Short name T37
Test name
Test status
Simulation time 367306497 ps
CPU time 2.27 seconds
Started Jul 30 07:34:56 PM PDT 24
Finished Jul 30 07:34:58 PM PDT 24
Peak memory 209820 kb
Host smart-6e8fad22-9d70-49f9-8216-ddab1fd5c876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549571340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1549571340
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1031321008
Short name T790
Test name
Test status
Simulation time 674963567 ps
CPU time 3.85 seconds
Started Jul 30 07:34:49 PM PDT 24
Finished Jul 30 07:34:53 PM PDT 24
Peak memory 208444 kb
Host smart-d3db0cce-2bca-48fa-9653-792104ef7838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031321008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1031321008
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1200657035
Short name T207
Test name
Test status
Simulation time 526584005 ps
CPU time 2.6 seconds
Started Jul 30 07:34:50 PM PDT 24
Finished Jul 30 07:34:53 PM PDT 24
Peak memory 209484 kb
Host smart-955449b9-aa04-451d-97c3-cf2fac79a874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200657035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1200657035
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2594191844
Short name T240
Test name
Test status
Simulation time 93311957 ps
CPU time 1.72 seconds
Started Jul 30 07:34:52 PM PDT 24
Finished Jul 30 07:34:54 PM PDT 24
Peak memory 214232 kb
Host smart-3013ab7c-fefc-4003-b05a-501fdf280d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594191844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2594191844
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1386091479
Short name T272
Test name
Test status
Simulation time 35613602 ps
CPU time 2.83 seconds
Started Jul 30 07:34:52 PM PDT 24
Finished Jul 30 07:34:55 PM PDT 24
Peak memory 218636 kb
Host smart-205e2d6f-320c-4565-8e14-5cb1d59424fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386091479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1386091479
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.252389969
Short name T827
Test name
Test status
Simulation time 120161889 ps
CPU time 4.98 seconds
Started Jul 30 07:34:52 PM PDT 24
Finished Jul 30 07:34:57 PM PDT 24
Peak memory 208608 kb
Host smart-b7f43d3f-e55d-4385-8105-9895d023b458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252389969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.252389969
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3391067514
Short name T905
Test name
Test status
Simulation time 48822783 ps
CPU time 2.63 seconds
Started Jul 30 07:34:50 PM PDT 24
Finished Jul 30 07:34:52 PM PDT 24
Peak memory 206976 kb
Host smart-c903fb29-1edf-4605-8f69-ce412f837f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391067514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3391067514
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3536565831
Short name T738
Test name
Test status
Simulation time 107367499 ps
CPU time 2.22 seconds
Started Jul 30 07:34:52 PM PDT 24
Finished Jul 30 07:34:55 PM PDT 24
Peak memory 206868 kb
Host smart-7ae74eb6-fde9-4731-8ea9-5fe39f54add6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536565831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3536565831
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.4200705084
Short name T765
Test name
Test status
Simulation time 137071501 ps
CPU time 3.96 seconds
Started Jul 30 07:34:52 PM PDT 24
Finished Jul 30 07:34:56 PM PDT 24
Peak memory 208004 kb
Host smart-59b1c997-e60b-4744-afb0-79298646b9a3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200705084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.4200705084
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3601561267
Short name T547
Test name
Test status
Simulation time 160891148 ps
CPU time 3.18 seconds
Started Jul 30 07:34:50 PM PDT 24
Finished Jul 30 07:34:54 PM PDT 24
Peak memory 207012 kb
Host smart-06e8e66e-f9ab-4c19-a916-25d9266f3c48
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601561267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3601561267
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1001187381
Short name T735
Test name
Test status
Simulation time 863299331 ps
CPU time 3.65 seconds
Started Jul 30 07:35:00 PM PDT 24
Finished Jul 30 07:35:03 PM PDT 24
Peak memory 214296 kb
Host smart-adf65fea-a193-4153-8aae-0189c48cfcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001187381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1001187381
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3731538439
Short name T906
Test name
Test status
Simulation time 86627211 ps
CPU time 1.86 seconds
Started Jul 30 07:34:52 PM PDT 24
Finished Jul 30 07:34:54 PM PDT 24
Peak memory 206932 kb
Host smart-9ff4eab3-50cf-4650-a058-53b4320032d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731538439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3731538439
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.417999500
Short name T71
Test name
Test status
Simulation time 1515127351 ps
CPU time 11.3 seconds
Started Jul 30 07:35:00 PM PDT 24
Finished Jul 30 07:35:12 PM PDT 24
Peak memory 221336 kb
Host smart-4725a017-be9f-442d-83ac-2368467824e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417999500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.417999500
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.3036369075
Short name T214
Test name
Test status
Simulation time 5723620458 ps
CPU time 19.16 seconds
Started Jul 30 07:35:01 PM PDT 24
Finished Jul 30 07:35:21 PM PDT 24
Peak memory 222664 kb
Host smart-f158d7c1-c372-445c-b1e5-6f674ba304b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036369075 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.3036369075
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3598731421
Short name T489
Test name
Test status
Simulation time 178050146 ps
CPU time 2.99 seconds
Started Jul 30 07:34:51 PM PDT 24
Finished Jul 30 07:34:54 PM PDT 24
Peak memory 218340 kb
Host smart-806993bf-3072-4028-9b09-1bd585eafd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598731421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3598731421
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1653535355
Short name T566
Test name
Test status
Simulation time 121630963 ps
CPU time 3.53 seconds
Started Jul 30 07:35:00 PM PDT 24
Finished Jul 30 07:35:04 PM PDT 24
Peak memory 210836 kb
Host smart-ac716c06-d769-499e-a2b3-05a5edb291f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653535355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1653535355
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2228070065
Short name T450
Test name
Test status
Simulation time 12282809 ps
CPU time 0.9 seconds
Started Jul 30 07:35:10 PM PDT 24
Finished Jul 30 07:35:11 PM PDT 24
Peak memory 205952 kb
Host smart-0e224010-f212-4e5e-ac5d-edb348fc50d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228070065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2228070065
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.285674745
Short name T18
Test name
Test status
Simulation time 204502336 ps
CPU time 7.45 seconds
Started Jul 30 07:35:03 PM PDT 24
Finished Jul 30 07:35:11 PM PDT 24
Peak memory 210212 kb
Host smart-7bc3a888-3bd5-48a4-9ba2-bea077dc590c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285674745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.285674745
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1202737282
Short name T50
Test name
Test status
Simulation time 246302172 ps
CPU time 7.55 seconds
Started Jul 30 07:35:04 PM PDT 24
Finished Jul 30 07:35:12 PM PDT 24
Peak memory 210156 kb
Host smart-20f736d6-6585-4384-ae02-0cda6ff5d22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202737282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1202737282
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.244521673
Short name T337
Test name
Test status
Simulation time 86695752 ps
CPU time 4.28 seconds
Started Jul 30 07:35:05 PM PDT 24
Finished Jul 30 07:35:09 PM PDT 24
Peak memory 214624 kb
Host smart-b4d33953-81b0-43b7-abe3-3dc7b857bc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244521673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.244521673
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3464457959
Short name T221
Test name
Test status
Simulation time 304304120 ps
CPU time 3.88 seconds
Started Jul 30 07:35:05 PM PDT 24
Finished Jul 30 07:35:09 PM PDT 24
Peak memory 214332 kb
Host smart-24e46150-d88c-44d4-b0bc-41a8a7540231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464457959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3464457959
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2862452429
Short name T583
Test name
Test status
Simulation time 3389523388 ps
CPU time 10.35 seconds
Started Jul 30 07:35:03 PM PDT 24
Finished Jul 30 07:35:13 PM PDT 24
Peak memory 218316 kb
Host smart-90d5bf39-08fd-42f4-95ce-a985b28123a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862452429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2862452429
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.4185547990
Short name T632
Test name
Test status
Simulation time 594946310 ps
CPU time 3.8 seconds
Started Jul 30 07:35:05 PM PDT 24
Finished Jul 30 07:35:09 PM PDT 24
Peak memory 206840 kb
Host smart-8d42ac1e-7812-4d21-a42f-32a4468d0502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185547990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.4185547990
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2122314465
Short name T643
Test name
Test status
Simulation time 88346823 ps
CPU time 1.94 seconds
Started Jul 30 07:35:00 PM PDT 24
Finished Jul 30 07:35:02 PM PDT 24
Peak memory 207148 kb
Host smart-225663f7-0e53-4c4b-a27c-a438186d2ba0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122314465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2122314465
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1567385928
Short name T265
Test name
Test status
Simulation time 296184064 ps
CPU time 5.06 seconds
Started Jul 30 07:35:05 PM PDT 24
Finished Jul 30 07:35:10 PM PDT 24
Peak memory 208500 kb
Host smart-c435766c-6f95-4005-b0bd-69f38206f29c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567385928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1567385928
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3108796525
Short name T562
Test name
Test status
Simulation time 383801960 ps
CPU time 3.62 seconds
Started Jul 30 07:35:03 PM PDT 24
Finished Jul 30 07:35:07 PM PDT 24
Peak memory 206924 kb
Host smart-934169e5-d5c3-4238-9ddd-a87e79856747
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108796525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3108796525
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3228738383
Short name T352
Test name
Test status
Simulation time 108732672 ps
CPU time 3.35 seconds
Started Jul 30 07:35:05 PM PDT 24
Finished Jul 30 07:35:09 PM PDT 24
Peak memory 218320 kb
Host smart-722df12e-c721-4f2a-81e3-2cd5bf11073b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228738383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3228738383
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1324663528
Short name T678
Test name
Test status
Simulation time 603759240 ps
CPU time 2.81 seconds
Started Jul 30 07:35:02 PM PDT 24
Finished Jul 30 07:35:05 PM PDT 24
Peak memory 206908 kb
Host smart-ad9f87ed-6a63-46f0-ae17-5d032dae531b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324663528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1324663528
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3410373452
Short name T570
Test name
Test status
Simulation time 255630888 ps
CPU time 3.22 seconds
Started Jul 30 07:35:10 PM PDT 24
Finished Jul 30 07:35:14 PM PDT 24
Peak memory 206868 kb
Host smart-9ed82992-0f11-4bdf-b110-5b7752257ee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410373452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3410373452
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1557786286
Short name T292
Test name
Test status
Simulation time 9537336008 ps
CPU time 27.88 seconds
Started Jul 30 07:35:09 PM PDT 24
Finished Jul 30 07:35:37 PM PDT 24
Peak memory 218244 kb
Host smart-f27e7314-5468-4b24-bf22-07325c317733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557786286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1557786286
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.4002183530
Short name T449
Test name
Test status
Simulation time 119755085 ps
CPU time 1.64 seconds
Started Jul 30 07:35:10 PM PDT 24
Finished Jul 30 07:35:12 PM PDT 24
Peak memory 209832 kb
Host smart-769064d6-5e44-4465-aac0-26ceeb0927db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002183530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.4002183530
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2195644192
Short name T497
Test name
Test status
Simulation time 44330189 ps
CPU time 0.73 seconds
Started Jul 30 07:35:10 PM PDT 24
Finished Jul 30 07:35:11 PM PDT 24
Peak memory 205976 kb
Host smart-4e208860-dba8-423d-abb0-0aab58bb236f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195644192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2195644192
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.499430809
Short name T74
Test name
Test status
Simulation time 436650330 ps
CPU time 2.68 seconds
Started Jul 30 07:35:11 PM PDT 24
Finished Jul 30 07:35:14 PM PDT 24
Peak memory 208076 kb
Host smart-aac2366e-6d0f-4ea6-892f-8beafc39bd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499430809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.499430809
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.648462998
Short name T307
Test name
Test status
Simulation time 119187695 ps
CPU time 4.5 seconds
Started Jul 30 07:35:11 PM PDT 24
Finished Jul 30 07:35:15 PM PDT 24
Peak memory 221268 kb
Host smart-27f1f7d7-6bbc-435f-9572-b829c03a180a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648462998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.648462998
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2323087833
Short name T375
Test name
Test status
Simulation time 52189172 ps
CPU time 3.04 seconds
Started Jul 30 07:35:11 PM PDT 24
Finished Jul 30 07:35:14 PM PDT 24
Peak memory 206044 kb
Host smart-cccdd8b6-562a-4534-b257-113cff3acd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323087833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2323087833
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2266189885
Short name T62
Test name
Test status
Simulation time 116654185 ps
CPU time 5.34 seconds
Started Jul 30 07:35:11 PM PDT 24
Finished Jul 30 07:35:17 PM PDT 24
Peak memory 214312 kb
Host smart-bf194dc6-2361-488c-b67d-19004ef180b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266189885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2266189885
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.563522135
Short name T237
Test name
Test status
Simulation time 2512881830 ps
CPU time 4.51 seconds
Started Jul 30 07:35:09 PM PDT 24
Finished Jul 30 07:35:13 PM PDT 24
Peak memory 208128 kb
Host smart-c914ac79-8632-40ff-860d-16c2db6d4b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563522135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.563522135
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2552626209
Short name T137
Test name
Test status
Simulation time 420272341 ps
CPU time 5.03 seconds
Started Jul 30 07:35:10 PM PDT 24
Finished Jul 30 07:35:16 PM PDT 24
Peak memory 206968 kb
Host smart-169d10a1-f043-4fe6-bf92-061dabb52e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552626209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2552626209
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3919331301
Short name T625
Test name
Test status
Simulation time 273604377 ps
CPU time 3.61 seconds
Started Jul 30 07:35:07 PM PDT 24
Finished Jul 30 07:35:11 PM PDT 24
Peak memory 209108 kb
Host smart-8bd100ca-6fc7-450d-837f-6fbbf4751d26
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919331301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3919331301
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3182006221
Short name T871
Test name
Test status
Simulation time 120426485 ps
CPU time 3.39 seconds
Started Jul 30 07:35:09 PM PDT 24
Finished Jul 30 07:35:13 PM PDT 24
Peak memory 209124 kb
Host smart-a27d6fe6-b7f2-4172-821a-99f20c07c313
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182006221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3182006221
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.240026632
Short name T725
Test name
Test status
Simulation time 45118143 ps
CPU time 2.59 seconds
Started Jul 30 07:35:11 PM PDT 24
Finished Jul 30 07:35:14 PM PDT 24
Peak memory 206888 kb
Host smart-13974df9-919a-4d4b-8832-185630459abf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240026632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.240026632
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3132086111
Short name T646
Test name
Test status
Simulation time 111355054 ps
CPU time 4.53 seconds
Started Jul 30 07:35:21 PM PDT 24
Finished Jul 30 07:35:25 PM PDT 24
Peak memory 218220 kb
Host smart-7ff3709b-a00c-445d-a1b2-ff3a4178e3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132086111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3132086111
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2660880956
Short name T418
Test name
Test status
Simulation time 36737847 ps
CPU time 1.64 seconds
Started Jul 30 07:35:07 PM PDT 24
Finished Jul 30 07:35:09 PM PDT 24
Peak memory 206708 kb
Host smart-1fe8d46c-82ed-4923-b8ab-4211bf135b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660880956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2660880956
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.1156542025
Short name T6
Test name
Test status
Simulation time 1972640306 ps
CPU time 10.35 seconds
Started Jul 30 07:35:12 PM PDT 24
Finished Jul 30 07:35:23 PM PDT 24
Peak memory 222460 kb
Host smart-9be5184b-2228-4823-81e2-676aaf3f5cae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156542025 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.1156542025
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1933333128
Short name T691
Test name
Test status
Simulation time 383292937 ps
CPU time 5.3 seconds
Started Jul 30 07:35:09 PM PDT 24
Finished Jul 30 07:35:15 PM PDT 24
Peak memory 207640 kb
Host smart-5b8116bb-94b4-4fb4-bb4a-2681703d1ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933333128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1933333128
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3302329039
Short name T179
Test name
Test status
Simulation time 83616136 ps
CPU time 2.44 seconds
Started Jul 30 07:35:13 PM PDT 24
Finished Jul 30 07:35:16 PM PDT 24
Peak memory 209912 kb
Host smart-b43f3162-19c2-4668-893c-ac7fe1ca0066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302329039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3302329039
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1703317500
Short name T633
Test name
Test status
Simulation time 39364780 ps
CPU time 0.86 seconds
Started Jul 30 07:32:22 PM PDT 24
Finished Jul 30 07:32:23 PM PDT 24
Peak memory 205976 kb
Host smart-09e5fea2-d73c-4e44-a5a7-8c9115f3f765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703317500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1703317500
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2392959255
Short name T407
Test name
Test status
Simulation time 143857026 ps
CPU time 2.98 seconds
Started Jul 30 07:32:18 PM PDT 24
Finished Jul 30 07:32:21 PM PDT 24
Peak memory 214300 kb
Host smart-26445a0c-84fe-41eb-8493-e707ef4d2413
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2392959255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2392959255
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.4080079932
Short name T52
Test name
Test status
Simulation time 110508156 ps
CPU time 3.9 seconds
Started Jul 30 07:32:22 PM PDT 24
Finished Jul 30 07:32:26 PM PDT 24
Peak memory 210144 kb
Host smart-ece53f4e-402b-488c-8c7b-eeb519bb81b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080079932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.4080079932
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.4121864628
Short name T503
Test name
Test status
Simulation time 246802308 ps
CPU time 3.22 seconds
Started Jul 30 07:32:22 PM PDT 24
Finished Jul 30 07:32:25 PM PDT 24
Peak memory 207560 kb
Host smart-7bc7a95b-4651-487b-a56f-2bfe009ed571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121864628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.4121864628
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.840782540
Short name T903
Test name
Test status
Simulation time 250187125 ps
CPU time 2.47 seconds
Started Jul 30 07:32:17 PM PDT 24
Finished Jul 30 07:32:20 PM PDT 24
Peak memory 214312 kb
Host smart-3de69f65-c11c-4582-953b-505f17d63b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840782540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.840782540
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.3954719687
Short name T477
Test name
Test status
Simulation time 105733636 ps
CPU time 2.67 seconds
Started Jul 30 07:32:22 PM PDT 24
Finished Jul 30 07:32:24 PM PDT 24
Peak memory 220204 kb
Host smart-e37f638d-f1a2-4275-a6a5-f7c08b5cfc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954719687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3954719687
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3808694415
Short name T913
Test name
Test status
Simulation time 4592785689 ps
CPU time 11.25 seconds
Started Jul 30 07:32:16 PM PDT 24
Finished Jul 30 07:32:28 PM PDT 24
Peak memory 208220 kb
Host smart-8bc6f03a-d0d8-464d-9854-208b4494c0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808694415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3808694415
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.4261908989
Short name T9
Test name
Test status
Simulation time 986623155 ps
CPU time 20.47 seconds
Started Jul 30 07:32:24 PM PDT 24
Finished Jul 30 07:32:44 PM PDT 24
Peak memory 234472 kb
Host smart-61c110d1-fffe-4c36-b6c9-948f6dfb7c17
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261908989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.4261908989
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.32800552
Short name T486
Test name
Test status
Simulation time 364847401 ps
CPU time 2.52 seconds
Started Jul 30 07:32:15 PM PDT 24
Finished Jul 30 07:32:18 PM PDT 24
Peak memory 206784 kb
Host smart-2334fe7a-da7e-439f-9ff9-243b17fa6f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32800552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.32800552
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3623079241
Short name T681
Test name
Test status
Simulation time 1579278334 ps
CPU time 13.22 seconds
Started Jul 30 07:32:15 PM PDT 24
Finished Jul 30 07:32:29 PM PDT 24
Peak memory 208256 kb
Host smart-2bbf44ec-c2ba-4773-b665-7726a1fa709e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623079241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3623079241
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2855489124
Short name T606
Test name
Test status
Simulation time 413389328 ps
CPU time 3.84 seconds
Started Jul 30 07:32:15 PM PDT 24
Finished Jul 30 07:32:19 PM PDT 24
Peak memory 208928 kb
Host smart-a96387a5-64de-4c36-b6f9-d0aa5ee1fa1b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855489124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2855489124
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1091690205
Short name T419
Test name
Test status
Simulation time 60652305 ps
CPU time 2.92 seconds
Started Jul 30 07:32:14 PM PDT 24
Finished Jul 30 07:32:17 PM PDT 24
Peak memory 208132 kb
Host smart-0cd8f258-fcc3-48a3-beee-6f9cb58fc914
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091690205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1091690205
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.347146321
Short name T895
Test name
Test status
Simulation time 516710077 ps
CPU time 9.9 seconds
Started Jul 30 07:32:18 PM PDT 24
Finished Jul 30 07:32:28 PM PDT 24
Peak memory 209264 kb
Host smart-e47a86b5-a65a-49c3-b4c3-e6f3fc019094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347146321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.347146321
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2519291583
Short name T539
Test name
Test status
Simulation time 343681775 ps
CPU time 3.93 seconds
Started Jul 30 07:32:14 PM PDT 24
Finished Jul 30 07:32:18 PM PDT 24
Peak memory 206928 kb
Host smart-3463f01b-2490-4e97-a501-48d191ae5c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519291583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2519291583
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1976297450
Short name T314
Test name
Test status
Simulation time 4152941688 ps
CPU time 32.4 seconds
Started Jul 30 07:32:22 PM PDT 24
Finished Jul 30 07:32:54 PM PDT 24
Peak memory 222508 kb
Host smart-7dd5748b-a5c5-4bc4-94d2-f3daea03a2d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976297450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1976297450
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.953193300
Short name T188
Test name
Test status
Simulation time 964267356 ps
CPU time 16.36 seconds
Started Jul 30 07:32:24 PM PDT 24
Finished Jul 30 07:32:41 PM PDT 24
Peak memory 219668 kb
Host smart-2f71826b-5f15-4476-a592-2f791a781bea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953193300 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.953193300
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.4237437735
Short name T343
Test name
Test status
Simulation time 121179372 ps
CPU time 5.55 seconds
Started Jul 30 07:32:19 PM PDT 24
Finished Jul 30 07:32:25 PM PDT 24
Peak memory 209928 kb
Host smart-6b3a795c-0eef-41b4-90b6-71fcbf5488ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237437735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.4237437735
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1090885935
Short name T158
Test name
Test status
Simulation time 89171192 ps
CPU time 2.57 seconds
Started Jul 30 07:32:18 PM PDT 24
Finished Jul 30 07:32:21 PM PDT 24
Peak memory 210288 kb
Host smart-b713069c-89cf-4ff8-8876-540e25398582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090885935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1090885935
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2983176629
Short name T474
Test name
Test status
Simulation time 14267754 ps
CPU time 0.77 seconds
Started Jul 30 07:35:16 PM PDT 24
Finished Jul 30 07:35:17 PM PDT 24
Peak memory 206004 kb
Host smart-58e042b2-33c3-4f3f-b825-e13e1d7957c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983176629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2983176629
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.3031764894
Short name T324
Test name
Test status
Simulation time 536691145 ps
CPU time 7.97 seconds
Started Jul 30 07:35:16 PM PDT 24
Finished Jul 30 07:35:24 PM PDT 24
Peak memory 215588 kb
Host smart-fdda1d83-f2fb-4f66-9f51-27fc29f878cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3031764894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3031764894
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.28928303
Short name T675
Test name
Test status
Simulation time 93499829 ps
CPU time 4.46 seconds
Started Jul 30 07:35:15 PM PDT 24
Finished Jul 30 07:35:20 PM PDT 24
Peak memory 214264 kb
Host smart-ff336427-f00a-4e7e-b0d5-10bbba72d138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28928303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.28928303
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2026852879
Short name T705
Test name
Test status
Simulation time 23330863 ps
CPU time 1.69 seconds
Started Jul 30 07:35:15 PM PDT 24
Finished Jul 30 07:35:17 PM PDT 24
Peak memory 208324 kb
Host smart-ab9116b9-aa83-4d0d-b147-f5fb1f4a1485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026852879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2026852879
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.361985109
Short name T336
Test name
Test status
Simulation time 95652856 ps
CPU time 2.11 seconds
Started Jul 30 07:35:15 PM PDT 24
Finished Jul 30 07:35:17 PM PDT 24
Peak memory 214240 kb
Host smart-63c497ca-4f6f-45de-8e44-aa241de94af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361985109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.361985109
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.148176964
Short name T241
Test name
Test status
Simulation time 180331376 ps
CPU time 2.93 seconds
Started Jul 30 07:35:14 PM PDT 24
Finished Jul 30 07:35:17 PM PDT 24
Peak memory 209844 kb
Host smart-5b74c14a-6a68-4b62-90cd-6d5deb5ded80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148176964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.148176964
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1743529395
Short name T201
Test name
Test status
Simulation time 40904523 ps
CPU time 2.92 seconds
Started Jul 30 07:35:15 PM PDT 24
Finished Jul 30 07:35:18 PM PDT 24
Peak memory 218452 kb
Host smart-2d25d60d-a029-41f9-be46-b02b85f87532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743529395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1743529395
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.805433253
Short name T568
Test name
Test status
Simulation time 586700121 ps
CPU time 3.18 seconds
Started Jul 30 07:35:12 PM PDT 24
Finished Jul 30 07:35:16 PM PDT 24
Peak memory 208800 kb
Host smart-088a3209-5df7-4efd-a59f-14c9cfca7b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805433253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.805433253
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3064597510
Short name T309
Test name
Test status
Simulation time 445660194 ps
CPU time 5.29 seconds
Started Jul 30 07:35:12 PM PDT 24
Finished Jul 30 07:35:18 PM PDT 24
Peak memory 208580 kb
Host smart-04fe985f-949a-4bc8-afbc-dc345351c0d2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064597510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3064597510
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2281857342
Short name T809
Test name
Test status
Simulation time 324907886 ps
CPU time 10.61 seconds
Started Jul 30 07:35:11 PM PDT 24
Finished Jul 30 07:35:22 PM PDT 24
Peak memory 208664 kb
Host smart-9fb9d7f0-6637-4071-a230-bc50899f6c79
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281857342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2281857342
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1527460328
Short name T544
Test name
Test status
Simulation time 91009755 ps
CPU time 3.13 seconds
Started Jul 30 07:35:13 PM PDT 24
Finished Jul 30 07:35:16 PM PDT 24
Peak memory 208800 kb
Host smart-3302dac9-474c-485b-9367-0bee1b809fe3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527460328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1527460328
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3673075195
Short name T517
Test name
Test status
Simulation time 587151572 ps
CPU time 1.82 seconds
Started Jul 30 07:35:22 PM PDT 24
Finished Jul 30 07:35:24 PM PDT 24
Peak memory 207640 kb
Host smart-fc910029-187f-40a7-9d2b-0b5e002db1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673075195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3673075195
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2966931364
Short name T543
Test name
Test status
Simulation time 78480695 ps
CPU time 3.5 seconds
Started Jul 30 07:35:14 PM PDT 24
Finished Jul 30 07:35:18 PM PDT 24
Peak memory 208212 kb
Host smart-319a6e08-273e-45fa-993b-1e27074a8cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966931364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2966931364
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2780083870
Short name T327
Test name
Test status
Simulation time 134587505 ps
CPU time 4.01 seconds
Started Jul 30 07:35:15 PM PDT 24
Finished Jul 30 07:35:19 PM PDT 24
Peak memory 208376 kb
Host smart-b76f8e58-63c7-487e-b74e-cce1e253d5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780083870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2780083870
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2766645782
Short name T828
Test name
Test status
Simulation time 157881489 ps
CPU time 2.02 seconds
Started Jul 30 07:35:16 PM PDT 24
Finished Jul 30 07:35:18 PM PDT 24
Peak memory 209896 kb
Host smart-af940d76-bf66-4337-bf23-4f789a2d99ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766645782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2766645782
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2982277853
Short name T504
Test name
Test status
Simulation time 233358627 ps
CPU time 0.78 seconds
Started Jul 30 07:35:20 PM PDT 24
Finished Jul 30 07:35:21 PM PDT 24
Peak memory 205888 kb
Host smart-f695efd0-e729-4a17-bc82-a577d24690e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982277853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2982277853
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2704487407
Short name T648
Test name
Test status
Simulation time 67249922 ps
CPU time 2.36 seconds
Started Jul 30 07:35:22 PM PDT 24
Finished Jul 30 07:35:25 PM PDT 24
Peak memory 222616 kb
Host smart-c19237ae-3257-4f1f-a72a-f11a41afb4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704487407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2704487407
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3261929247
Short name T67
Test name
Test status
Simulation time 84863275 ps
CPU time 2.89 seconds
Started Jul 30 07:35:20 PM PDT 24
Finished Jul 30 07:35:23 PM PDT 24
Peak memory 208968 kb
Host smart-afbc4701-8396-4eb3-9259-5c2fb8ab09be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261929247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3261929247
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1033831380
Short name T206
Test name
Test status
Simulation time 801751416 ps
CPU time 8.99 seconds
Started Jul 30 07:35:19 PM PDT 24
Finished Jul 30 07:35:28 PM PDT 24
Peak memory 214316 kb
Host smart-d069dc31-c2b0-49a4-bab9-2b49aea85571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033831380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1033831380
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1476895186
Short name T745
Test name
Test status
Simulation time 105337765 ps
CPU time 2.22 seconds
Started Jul 30 07:35:21 PM PDT 24
Finished Jul 30 07:35:23 PM PDT 24
Peak memory 219728 kb
Host smart-d7634491-2983-42fa-be9d-eb7a24360f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476895186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1476895186
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3602417095
Short name T428
Test name
Test status
Simulation time 235946753 ps
CPU time 3.27 seconds
Started Jul 30 07:35:21 PM PDT 24
Finished Jul 30 07:35:24 PM PDT 24
Peak memory 217640 kb
Host smart-f616768b-6db4-47e1-8bf9-0e1b274c241d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602417095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3602417095
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.1301008046
Short name T862
Test name
Test status
Simulation time 859167283 ps
CPU time 10.47 seconds
Started Jul 30 07:35:22 PM PDT 24
Finished Jul 30 07:35:33 PM PDT 24
Peak memory 214288 kb
Host smart-bbff70fd-4590-4793-8dbc-776880e7079b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301008046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1301008046
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.188037222
Short name T523
Test name
Test status
Simulation time 1516793448 ps
CPU time 23.27 seconds
Started Jul 30 07:35:15 PM PDT 24
Finished Jul 30 07:35:39 PM PDT 24
Peak memory 207908 kb
Host smart-8425804d-682b-4d8e-83f3-f19e8b7b1e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188037222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.188037222
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3496392293
Short name T447
Test name
Test status
Simulation time 168636749 ps
CPU time 3.71 seconds
Started Jul 30 07:35:22 PM PDT 24
Finished Jul 30 07:35:26 PM PDT 24
Peak memory 206996 kb
Host smart-81930e41-f467-4b47-9d0f-8e4b915438cd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496392293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3496392293
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.743866076
Short name T475
Test name
Test status
Simulation time 2303177876 ps
CPU time 15.06 seconds
Started Jul 30 07:35:16 PM PDT 24
Finished Jul 30 07:35:31 PM PDT 24
Peak memory 208384 kb
Host smart-7bbc9df0-3c88-4a36-9bbb-37346d908fcf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743866076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.743866076
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.408386868
Short name T619
Test name
Test status
Simulation time 927059948 ps
CPU time 31.88 seconds
Started Jul 30 07:35:22 PM PDT 24
Finished Jul 30 07:35:54 PM PDT 24
Peak memory 208616 kb
Host smart-a8338132-071d-463a-8e40-b3502594be3f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408386868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.408386868
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2817143481
Short name T766
Test name
Test status
Simulation time 73082981 ps
CPU time 3.36 seconds
Started Jul 30 07:35:22 PM PDT 24
Finished Jul 30 07:35:25 PM PDT 24
Peak memory 208724 kb
Host smart-9ccd7ddd-a50f-48f9-a58e-e43bcdb719b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817143481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2817143481
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1892301939
Short name T865
Test name
Test status
Simulation time 247982868 ps
CPU time 2.31 seconds
Started Jul 30 07:35:17 PM PDT 24
Finished Jul 30 07:35:19 PM PDT 24
Peak memory 208600 kb
Host smart-c6c96f74-83b7-4966-81e9-62e7c8b5c977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892301939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1892301939
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.587943502
Short name T689
Test name
Test status
Simulation time 436512419 ps
CPU time 10.61 seconds
Started Jul 30 07:35:25 PM PDT 24
Finished Jul 30 07:35:36 PM PDT 24
Peak memory 214304 kb
Host smart-d5aae994-960a-4cc9-bc75-f3d24359ddb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587943502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.587943502
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1032114596
Short name T540
Test name
Test status
Simulation time 126336652 ps
CPU time 3.86 seconds
Started Jul 30 07:35:18 PM PDT 24
Finished Jul 30 07:35:22 PM PDT 24
Peak memory 209552 kb
Host smart-3d6d14f9-2697-4944-a283-da38e45ce328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032114596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1032114596
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.13066425
Short name T142
Test name
Test status
Simulation time 66806496 ps
CPU time 1.43 seconds
Started Jul 30 07:35:24 PM PDT 24
Finished Jul 30 07:35:26 PM PDT 24
Peak memory 209784 kb
Host smart-bae1ccf4-790b-4a79-baa9-72ed4b4664e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13066425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.13066425
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2281683255
Short name T435
Test name
Test status
Simulation time 21989491 ps
CPU time 0.88 seconds
Started Jul 30 07:35:27 PM PDT 24
Finished Jul 30 07:35:28 PM PDT 24
Peak memory 205896 kb
Host smart-48251d9f-68ec-46fc-a0d6-f96a7bd32263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281683255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2281683255
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.180322968
Short name T817
Test name
Test status
Simulation time 95720498 ps
CPU time 1.81 seconds
Started Jul 30 07:35:22 PM PDT 24
Finished Jul 30 07:35:24 PM PDT 24
Peak memory 209836 kb
Host smart-a3fb34df-48de-41cf-93f1-b5d6e52ebd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180322968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.180322968
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1586742718
Short name T845
Test name
Test status
Simulation time 129297913 ps
CPU time 2.79 seconds
Started Jul 30 07:35:20 PM PDT 24
Finished Jul 30 07:35:23 PM PDT 24
Peak memory 208520 kb
Host smart-5f58591a-10d8-409d-9f10-ef645851f7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586742718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1586742718
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.928994243
Short name T202
Test name
Test status
Simulation time 952643938 ps
CPU time 4.23 seconds
Started Jul 30 07:35:25 PM PDT 24
Finished Jul 30 07:35:29 PM PDT 24
Peak memory 209412 kb
Host smart-3c6ff04b-8bc6-4eb7-8b25-3fd7c91fc0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928994243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.928994243
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.489755800
Short name T339
Test name
Test status
Simulation time 285875610 ps
CPU time 3.92 seconds
Started Jul 30 07:35:24 PM PDT 24
Finished Jul 30 07:35:28 PM PDT 24
Peak memory 220132 kb
Host smart-4adc7780-bc16-48f4-a684-ebea7366a43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489755800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.489755800
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1146157226
Short name T411
Test name
Test status
Simulation time 473729427 ps
CPU time 4.05 seconds
Started Jul 30 07:35:19 PM PDT 24
Finished Jul 30 07:35:23 PM PDT 24
Peak memory 208644 kb
Host smart-640dd27c-0005-4a52-84e7-36f0dae61faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146157226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1146157226
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3922106300
Short name T811
Test name
Test status
Simulation time 320040785 ps
CPU time 3.81 seconds
Started Jul 30 07:35:25 PM PDT 24
Finished Jul 30 07:35:29 PM PDT 24
Peak memory 208288 kb
Host smart-073dbd36-f484-4314-96c1-753eaea0d2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922106300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3922106300
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.31524898
Short name T464
Test name
Test status
Simulation time 27473448 ps
CPU time 2 seconds
Started Jul 30 07:35:20 PM PDT 24
Finished Jul 30 07:35:23 PM PDT 24
Peak memory 208816 kb
Host smart-d7decc32-8922-4f55-9f91-163cf0af9535
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31524898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.31524898
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3552453235
Short name T460
Test name
Test status
Simulation time 1951590574 ps
CPU time 22.34 seconds
Started Jul 30 07:35:19 PM PDT 24
Finished Jul 30 07:35:41 PM PDT 24
Peak memory 208084 kb
Host smart-fcf42c4a-4042-48ab-aabc-67a7a1c656e2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552453235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3552453235
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3687637841
Short name T751
Test name
Test status
Simulation time 2071674503 ps
CPU time 43.68 seconds
Started Jul 30 07:35:26 PM PDT 24
Finished Jul 30 07:36:10 PM PDT 24
Peak memory 208480 kb
Host smart-3e99c4f4-eddc-42bc-9b3d-4b21394e4308
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687637841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3687637841
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.67446177
Short name T557
Test name
Test status
Simulation time 153461095 ps
CPU time 2.38 seconds
Started Jul 30 07:35:25 PM PDT 24
Finished Jul 30 07:35:28 PM PDT 24
Peak memory 209636 kb
Host smart-b405c297-0992-409a-af6c-ee947e0d00ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67446177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.67446177
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1357952447
Short name T773
Test name
Test status
Simulation time 111062922 ps
CPU time 3.21 seconds
Started Jul 30 07:35:20 PM PDT 24
Finished Jul 30 07:35:23 PM PDT 24
Peak memory 208592 kb
Host smart-1b4682a0-e17a-488e-bb3a-07a8e842eb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357952447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1357952447
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3651278752
Short name T780
Test name
Test status
Simulation time 218297868 ps
CPU time 11.39 seconds
Started Jul 30 07:35:24 PM PDT 24
Finished Jul 30 07:35:36 PM PDT 24
Peak memory 216304 kb
Host smart-52045002-3516-487f-b6b8-748978acf4b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651278752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3651278752
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.4192683512
Short name T14
Test name
Test status
Simulation time 1491158933 ps
CPU time 9.3 seconds
Started Jul 30 07:35:19 PM PDT 24
Finished Jul 30 07:35:28 PM PDT 24
Peak memory 210532 kb
Host smart-8ae0d5b4-73de-4d87-af58-433bc5d16841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192683512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.4192683512
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.4165098446
Short name T397
Test name
Test status
Simulation time 86668595 ps
CPU time 2.26 seconds
Started Jul 30 07:35:26 PM PDT 24
Finished Jul 30 07:35:29 PM PDT 24
Peak memory 210072 kb
Host smart-eb1d6f47-0ccd-41f5-963b-06a5fdc8aad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165098446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.4165098446
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2175538017
Short name T424
Test name
Test status
Simulation time 10969531 ps
CPU time 0.72 seconds
Started Jul 30 07:35:24 PM PDT 24
Finished Jul 30 07:35:24 PM PDT 24
Peak memory 205940 kb
Host smart-37c82e62-ecc6-4ee7-af22-c3d06b9f1709
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175538017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2175538017
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3573672952
Short name T412
Test name
Test status
Simulation time 94575374 ps
CPU time 2.68 seconds
Started Jul 30 07:35:26 PM PDT 24
Finished Jul 30 07:35:29 PM PDT 24
Peak memory 214384 kb
Host smart-4ea8b32d-d7de-4563-a7ae-1260143b065b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3573672952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3573672952
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.733271372
Short name T29
Test name
Test status
Simulation time 672191051 ps
CPU time 6.22 seconds
Started Jul 30 07:35:23 PM PDT 24
Finished Jul 30 07:35:29 PM PDT 24
Peak memory 214520 kb
Host smart-e07aa4ee-8996-4dab-914c-ded7bf1ed576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733271372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.733271372
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.284676963
Short name T654
Test name
Test status
Simulation time 111518687 ps
CPU time 3.09 seconds
Started Jul 30 07:35:25 PM PDT 24
Finished Jul 30 07:35:28 PM PDT 24
Peak memory 218268 kb
Host smart-9388ac01-59f9-47a4-87f9-09941af509f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284676963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.284676963
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1395413706
Short name T204
Test name
Test status
Simulation time 291023027 ps
CPU time 5.08 seconds
Started Jul 30 07:35:23 PM PDT 24
Finished Jul 30 07:35:29 PM PDT 24
Peak memory 220640 kb
Host smart-b6324932-9127-4e24-a46a-fcde8a049a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395413706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1395413706
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2402235727
Short name T874
Test name
Test status
Simulation time 148490907 ps
CPU time 2.69 seconds
Started Jul 30 07:35:26 PM PDT 24
Finished Jul 30 07:35:29 PM PDT 24
Peak memory 214264 kb
Host smart-d5da62c8-afbc-4be2-9145-56c03b6ea436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402235727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2402235727
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2313120837
Short name T794
Test name
Test status
Simulation time 575904956 ps
CPU time 3.62 seconds
Started Jul 30 07:35:26 PM PDT 24
Finished Jul 30 07:35:30 PM PDT 24
Peak memory 217992 kb
Host smart-34e1ef39-60b3-48ec-bbd6-b27010414ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313120837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2313120837
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.811322271
Short name T727
Test name
Test status
Simulation time 819392199 ps
CPU time 4.25 seconds
Started Jul 30 07:35:26 PM PDT 24
Finished Jul 30 07:35:31 PM PDT 24
Peak memory 209396 kb
Host smart-565c2771-2b7f-4daa-aa48-9d108f523d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811322271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.811322271
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3214863930
Short name T2
Test name
Test status
Simulation time 61873106 ps
CPU time 1.72 seconds
Started Jul 30 07:35:23 PM PDT 24
Finished Jul 30 07:35:25 PM PDT 24
Peak memory 207024 kb
Host smart-14e22355-9f93-4a1d-92e3-ccf61662dbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214863930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3214863930
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2213215698
Short name T302
Test name
Test status
Simulation time 175538548 ps
CPU time 6.44 seconds
Started Jul 30 07:35:22 PM PDT 24
Finished Jul 30 07:35:29 PM PDT 24
Peak memory 208920 kb
Host smart-93487c71-87ca-4664-8db2-7fc6d63f386a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213215698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2213215698
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3938447683
Short name T666
Test name
Test status
Simulation time 166636468 ps
CPU time 4.94 seconds
Started Jul 30 07:35:23 PM PDT 24
Finished Jul 30 07:35:28 PM PDT 24
Peak memory 206784 kb
Host smart-0db2dcd9-7e6f-4287-af9d-a77da7af6fbf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938447683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3938447683
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.3039042692
Short name T436
Test name
Test status
Simulation time 597618129 ps
CPU time 14.92 seconds
Started Jul 30 07:35:23 PM PDT 24
Finished Jul 30 07:35:38 PM PDT 24
Peak memory 208884 kb
Host smart-4328666a-cded-4175-bcaa-8d530fe3972a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039042692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3039042692
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1504083814
Short name T875
Test name
Test status
Simulation time 83121942 ps
CPU time 1.64 seconds
Started Jul 30 07:35:25 PM PDT 24
Finished Jul 30 07:35:27 PM PDT 24
Peak memory 206120 kb
Host smart-6b2702bd-cf7e-4ecf-9762-cf8b598e268d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504083814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1504083814
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2819302972
Short name T208
Test name
Test status
Simulation time 639787831 ps
CPU time 14.24 seconds
Started Jul 30 07:35:25 PM PDT 24
Finished Jul 30 07:35:40 PM PDT 24
Peak memory 215604 kb
Host smart-09a9eea7-c9be-47ce-b5e9-0f8911f3a275
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819302972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2819302972
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1370572520
Short name T600
Test name
Test status
Simulation time 1869599374 ps
CPU time 22.48 seconds
Started Jul 30 07:35:24 PM PDT 24
Finished Jul 30 07:35:46 PM PDT 24
Peak memory 222640 kb
Host smart-ac315d83-3d19-4e90-b22c-b48bed2a1bd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370572520 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1370572520
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1979650076
Short name T816
Test name
Test status
Simulation time 2141110709 ps
CPU time 40.2 seconds
Started Jul 30 07:35:24 PM PDT 24
Finished Jul 30 07:36:04 PM PDT 24
Peak memory 209756 kb
Host smart-b314fd6c-0783-4430-b82f-32919bfd038b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979650076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1979650076
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1211961302
Short name T623
Test name
Test status
Simulation time 41692577 ps
CPU time 2 seconds
Started Jul 30 07:35:26 PM PDT 24
Finished Jul 30 07:35:29 PM PDT 24
Peak memory 209724 kb
Host smart-15e7460d-e7d1-4387-abbf-79ad7544b831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211961302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1211961302
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1281853722
Short name T699
Test name
Test status
Simulation time 12021052 ps
CPU time 0.78 seconds
Started Jul 30 07:35:28 PM PDT 24
Finished Jul 30 07:35:29 PM PDT 24
Peak memory 205980 kb
Host smart-da8fbf0f-64be-411d-b463-ae16c0c1a36b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281853722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1281853722
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1126963809
Short name T298
Test name
Test status
Simulation time 53161787 ps
CPU time 3.85 seconds
Started Jul 30 07:35:26 PM PDT 24
Finished Jul 30 07:35:30 PM PDT 24
Peak memory 214292 kb
Host smart-b95e88ee-5656-4625-9e1a-c2b88aa522e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1126963809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1126963809
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3150227453
Short name T216
Test name
Test status
Simulation time 708047705 ps
CPU time 5.15 seconds
Started Jul 30 07:35:27 PM PDT 24
Finished Jul 30 07:35:32 PM PDT 24
Peak memory 209528 kb
Host smart-bb241395-beee-4ec7-9d62-8d0358e42991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150227453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3150227453
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2805280203
Short name T429
Test name
Test status
Simulation time 544768452 ps
CPU time 5.13 seconds
Started Jul 30 07:35:29 PM PDT 24
Finished Jul 30 07:35:35 PM PDT 24
Peak memory 209324 kb
Host smart-0c858e59-cc69-4811-a013-c38fdd4b6a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805280203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2805280203
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.4059268732
Short name T881
Test name
Test status
Simulation time 64067436 ps
CPU time 3.41 seconds
Started Jul 30 07:35:30 PM PDT 24
Finished Jul 30 07:35:33 PM PDT 24
Peak memory 222468 kb
Host smart-015ae943-35e9-485a-ae39-3d49c77b547b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059268732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.4059268732
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1656920038
Short name T376
Test name
Test status
Simulation time 59438255 ps
CPU time 3.78 seconds
Started Jul 30 07:35:26 PM PDT 24
Finished Jul 30 07:35:30 PM PDT 24
Peak memory 214328 kb
Host smart-508231c7-9b7e-48ea-b661-25c9c8512c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656920038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1656920038
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.4079987758
Short name T656
Test name
Test status
Simulation time 356920189 ps
CPU time 2.99 seconds
Started Jul 30 07:35:27 PM PDT 24
Finished Jul 30 07:35:30 PM PDT 24
Peak memory 209592 kb
Host smart-104fc023-682f-45b2-90f5-9e60eee543e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079987758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.4079987758
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2228659526
Short name T711
Test name
Test status
Simulation time 167713305 ps
CPU time 5.92 seconds
Started Jul 30 07:35:27 PM PDT 24
Finished Jul 30 07:35:33 PM PDT 24
Peak memory 209080 kb
Host smart-6495c8a7-75d9-461e-a1fa-af7c732d8ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228659526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2228659526
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2700485441
Short name T244
Test name
Test status
Simulation time 314617725 ps
CPU time 4.23 seconds
Started Jul 30 07:35:27 PM PDT 24
Finished Jul 30 07:35:32 PM PDT 24
Peak memory 208608 kb
Host smart-f85dd225-a786-4ad7-b2df-fa9d021d22bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700485441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2700485441
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2580564162
Short name T746
Test name
Test status
Simulation time 2316476691 ps
CPU time 5.45 seconds
Started Jul 30 07:35:26 PM PDT 24
Finished Jul 30 07:35:32 PM PDT 24
Peak memory 208448 kb
Host smart-30336834-54e7-4864-8750-02171cebecd4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580564162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2580564162
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2309490426
Short name T502
Test name
Test status
Simulation time 126072814 ps
CPU time 4.02 seconds
Started Jul 30 07:35:28 PM PDT 24
Finished Jul 30 07:35:32 PM PDT 24
Peak memory 206904 kb
Host smart-02e4e3cb-4fe5-4aad-afe0-2abf0c9922d9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309490426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2309490426
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3479853932
Short name T638
Test name
Test status
Simulation time 84714080 ps
CPU time 3.39 seconds
Started Jul 30 07:35:26 PM PDT 24
Finished Jul 30 07:35:30 PM PDT 24
Peak memory 208632 kb
Host smart-4be295b3-e3d9-4ce2-bd1b-35ca2645c412
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479853932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3479853932
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.2942501067
Short name T830
Test name
Test status
Simulation time 1168092921 ps
CPU time 2.37 seconds
Started Jul 30 07:35:27 PM PDT 24
Finished Jul 30 07:35:29 PM PDT 24
Peak memory 210104 kb
Host smart-9da1f090-3863-4089-be2d-c973ab8afe6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942501067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2942501067
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.929043499
Short name T717
Test name
Test status
Simulation time 1702451362 ps
CPU time 4.21 seconds
Started Jul 30 07:35:27 PM PDT 24
Finished Jul 30 07:35:31 PM PDT 24
Peak memory 208260 kb
Host smart-5d24a55d-4952-4d9b-9977-f742f8265dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929043499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.929043499
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3427794085
Short name T320
Test name
Test status
Simulation time 1049839686 ps
CPU time 5.46 seconds
Started Jul 30 07:35:28 PM PDT 24
Finished Jul 30 07:35:33 PM PDT 24
Peak memory 214428 kb
Host smart-37af981f-229a-4ad4-a0ac-8dcde9e5985c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427794085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3427794085
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1473959891
Short name T653
Test name
Test status
Simulation time 434076261 ps
CPU time 2.78 seconds
Started Jul 30 07:35:27 PM PDT 24
Finished Jul 30 07:35:30 PM PDT 24
Peak memory 210352 kb
Host smart-96e240e2-8311-43aa-9080-ae62fc13fb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473959891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1473959891
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1095845250
Short name T696
Test name
Test status
Simulation time 11421890 ps
CPU time 0.86 seconds
Started Jul 30 07:35:32 PM PDT 24
Finished Jul 30 07:35:33 PM PDT 24
Peak memory 205940 kb
Host smart-70878a2b-492c-4ccb-b004-57d4e48729c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095845250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1095845250
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.4142153553
Short name T848
Test name
Test status
Simulation time 221524835 ps
CPU time 3.51 seconds
Started Jul 30 07:35:35 PM PDT 24
Finished Jul 30 07:35:39 PM PDT 24
Peak memory 210376 kb
Host smart-3ff308d9-a90a-42af-a18d-d25ebc155d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142153553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.4142153553
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1122593532
Short name T698
Test name
Test status
Simulation time 75888764 ps
CPU time 2.14 seconds
Started Jul 30 07:35:29 PM PDT 24
Finished Jul 30 07:35:31 PM PDT 24
Peak memory 214352 kb
Host smart-102a4825-5752-43a3-a6ed-0a3aa98c5b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122593532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1122593532
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3806077431
Short name T911
Test name
Test status
Simulation time 47549576 ps
CPU time 2.25 seconds
Started Jul 30 07:35:32 PM PDT 24
Finished Jul 30 07:35:35 PM PDT 24
Peak memory 214320 kb
Host smart-f7593b94-c5cb-4a5d-a3dc-893b055205ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806077431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3806077431
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3161095987
Short name T609
Test name
Test status
Simulation time 55205230 ps
CPU time 1.95 seconds
Started Jul 30 07:35:30 PM PDT 24
Finished Jul 30 07:35:32 PM PDT 24
Peak memory 214208 kb
Host smart-0111865e-c06c-4670-9e98-1f1c12259a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161095987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3161095987
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2909926613
Short name T615
Test name
Test status
Simulation time 199649126 ps
CPU time 3.34 seconds
Started Jul 30 07:35:29 PM PDT 24
Finished Jul 30 07:35:33 PM PDT 24
Peak memory 214396 kb
Host smart-8cae1bfb-49b8-409a-b6b2-9b6476abc7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909926613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2909926613
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.4247116683
Short name T887
Test name
Test status
Simulation time 546398709 ps
CPU time 7.27 seconds
Started Jul 30 07:35:30 PM PDT 24
Finished Jul 30 07:35:37 PM PDT 24
Peak memory 207436 kb
Host smart-1ebe6698-a46f-4b23-a806-f63b32a61e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247116683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.4247116683
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2565827593
Short name T909
Test name
Test status
Simulation time 360073570 ps
CPU time 7.71 seconds
Started Jul 30 07:35:27 PM PDT 24
Finished Jul 30 07:35:35 PM PDT 24
Peak memory 207900 kb
Host smart-a301abf4-4a0f-4890-9587-389ec51cc89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565827593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2565827593
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1514552496
Short name T824
Test name
Test status
Simulation time 3518449512 ps
CPU time 36.34 seconds
Started Jul 30 07:35:26 PM PDT 24
Finished Jul 30 07:36:03 PM PDT 24
Peak memory 208796 kb
Host smart-39dd0297-30b4-4f77-8c7e-3902c5715646
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514552496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1514552496
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3831122574
Short name T131
Test name
Test status
Simulation time 77760401 ps
CPU time 1.95 seconds
Started Jul 30 07:35:27 PM PDT 24
Finished Jul 30 07:35:29 PM PDT 24
Peak memory 207740 kb
Host smart-cd510595-c0aa-43f2-be8a-d233093374e5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831122574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3831122574
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1941042242
Short name T813
Test name
Test status
Simulation time 3689710349 ps
CPU time 32.51 seconds
Started Jul 30 07:35:56 PM PDT 24
Finished Jul 30 07:36:29 PM PDT 24
Peak memory 208956 kb
Host smart-14466ae4-446e-41d2-a740-84a8d436f11f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941042242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1941042242
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.198796766
Short name T551
Test name
Test status
Simulation time 1530033562 ps
CPU time 18 seconds
Started Jul 30 07:35:30 PM PDT 24
Finished Jul 30 07:35:48 PM PDT 24
Peak memory 208588 kb
Host smart-6ca87249-1df8-44a4-8af0-9bdb1a2f4d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198796766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.198796766
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2757267294
Short name T140
Test name
Test status
Simulation time 75297090 ps
CPU time 2.88 seconds
Started Jul 30 07:35:29 PM PDT 24
Finished Jul 30 07:35:32 PM PDT 24
Peak memory 206828 kb
Host smart-ca3eb618-9383-45d6-8883-e61e7f540199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757267294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2757267294
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3519704636
Short name T79
Test name
Test status
Simulation time 384266231 ps
CPU time 11.78 seconds
Started Jul 30 07:35:31 PM PDT 24
Finished Jul 30 07:35:43 PM PDT 24
Peak memory 222556 kb
Host smart-a3e52e92-c51c-4423-bc71-6a09f436a979
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519704636 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3519704636
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2852135292
Short name T498
Test name
Test status
Simulation time 221075696 ps
CPU time 3.63 seconds
Started Jul 30 07:35:33 PM PDT 24
Finished Jul 30 07:35:37 PM PDT 24
Peak memory 208088 kb
Host smart-1ff70a0f-4730-4163-ac5d-f878c5a8e933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852135292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2852135292
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2526041270
Short name T171
Test name
Test status
Simulation time 50374336 ps
CPU time 2.42 seconds
Started Jul 30 07:35:31 PM PDT 24
Finished Jul 30 07:35:34 PM PDT 24
Peak memory 210072 kb
Host smart-a20ca644-f304-4762-86ac-35947a6c7726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526041270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2526041270
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.588438495
Short name T476
Test name
Test status
Simulation time 17678368 ps
CPU time 0.68 seconds
Started Jul 30 07:35:31 PM PDT 24
Finished Jul 30 07:35:32 PM PDT 24
Peak memory 205940 kb
Host smart-df4b22e8-437e-45d4-9acc-aac766561f28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588438495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.588438495
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.4184561264
Short name T252
Test name
Test status
Simulation time 923610175 ps
CPU time 3.36 seconds
Started Jul 30 07:35:32 PM PDT 24
Finished Jul 30 07:35:36 PM PDT 24
Peak memory 209684 kb
Host smart-d06e3740-555c-40be-baaa-82f9e629147e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184561264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.4184561264
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.372815343
Short name T109
Test name
Test status
Simulation time 79992979 ps
CPU time 2.01 seconds
Started Jul 30 07:35:33 PM PDT 24
Finished Jul 30 07:35:35 PM PDT 24
Peak memory 214280 kb
Host smart-f56a0325-0c5c-4e6d-8253-50724c80ca70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372815343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.372815343
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.634420322
Short name T844
Test name
Test status
Simulation time 287480791 ps
CPU time 2.83 seconds
Started Jul 30 07:35:31 PM PDT 24
Finished Jul 30 07:35:34 PM PDT 24
Peak memory 214280 kb
Host smart-6219aec0-a26e-4812-aeeb-885670972f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634420322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.634420322
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.4225384905
Short name T736
Test name
Test status
Simulation time 825999343 ps
CPU time 3.24 seconds
Started Jul 30 07:35:35 PM PDT 24
Finished Jul 30 07:35:39 PM PDT 24
Peak memory 214376 kb
Host smart-54892298-8ba8-4258-a8f4-001f12e7bc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225384905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.4225384905
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.782565920
Short name T218
Test name
Test status
Simulation time 451101609 ps
CPU time 3.67 seconds
Started Jul 30 07:35:32 PM PDT 24
Finished Jul 30 07:35:36 PM PDT 24
Peak memory 218920 kb
Host smart-97b16f16-d7c1-432d-8ae1-40f536b7be69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782565920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.782565920
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1876322052
Short name T370
Test name
Test status
Simulation time 526192895 ps
CPU time 5.86 seconds
Started Jul 30 07:35:31 PM PDT 24
Finished Jul 30 07:35:37 PM PDT 24
Peak memory 214396 kb
Host smart-a06506ed-b7d9-4719-92bb-e5fb961f542f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876322052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1876322052
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.400125449
Short name T326
Test name
Test status
Simulation time 32598944 ps
CPU time 2.56 seconds
Started Jul 30 07:35:32 PM PDT 24
Finished Jul 30 07:35:34 PM PDT 24
Peak memory 209060 kb
Host smart-61874e3b-140a-4d36-babb-31bafdbe8064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400125449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.400125449
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.650604070
Short name T833
Test name
Test status
Simulation time 81950272 ps
CPU time 1.8 seconds
Started Jul 30 07:35:32 PM PDT 24
Finished Jul 30 07:35:33 PM PDT 24
Peak memory 206956 kb
Host smart-427998a6-7b88-4d8b-b8da-0bff63596751
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650604070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.650604070
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2611715512
Short name T592
Test name
Test status
Simulation time 192435140 ps
CPU time 2.83 seconds
Started Jul 30 07:35:35 PM PDT 24
Finished Jul 30 07:35:38 PM PDT 24
Peak memory 209052 kb
Host smart-35f2edc2-cc3b-43f9-a0da-3c5f7510dc71
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611715512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2611715512
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.582116535
Short name T724
Test name
Test status
Simulation time 222233052 ps
CPU time 3.88 seconds
Started Jul 30 07:35:34 PM PDT 24
Finished Jul 30 07:35:38 PM PDT 24
Peak memory 206820 kb
Host smart-3bab35e8-364b-4b76-91d0-6c7ffd655b15
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582116535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.582116535
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.75122181
Short name T193
Test name
Test status
Simulation time 135404300 ps
CPU time 2.73 seconds
Started Jul 30 07:35:31 PM PDT 24
Finished Jul 30 07:35:34 PM PDT 24
Peak memory 218144 kb
Host smart-1ece5047-4978-48ec-ad73-0484ae700357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75122181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.75122181
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.263481230
Short name T743
Test name
Test status
Simulation time 4169741678 ps
CPU time 36.04 seconds
Started Jul 30 07:35:33 PM PDT 24
Finished Jul 30 07:36:10 PM PDT 24
Peak memory 209072 kb
Host smart-e1a8d99d-94c1-4deb-bf39-9cfed7b8b703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263481230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.263481230
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.559878286
Short name T659
Test name
Test status
Simulation time 50081327 ps
CPU time 3.02 seconds
Started Jul 30 07:35:32 PM PDT 24
Finished Jul 30 07:35:35 PM PDT 24
Peak memory 208264 kb
Host smart-e9cad27b-6594-43a3-bde5-9df6a59a868b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559878286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.559878286
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1500409405
Short name T512
Test name
Test status
Simulation time 3938624772 ps
CPU time 13.33 seconds
Started Jul 30 07:35:33 PM PDT 24
Finished Jul 30 07:35:46 PM PDT 24
Peak memory 222508 kb
Host smart-613fe212-9051-4257-94d8-6ea50bc877cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500409405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1500409405
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2611528710
Short name T379
Test name
Test status
Simulation time 59742896 ps
CPU time 1.88 seconds
Started Jul 30 07:35:33 PM PDT 24
Finished Jul 30 07:35:35 PM PDT 24
Peak memory 210012 kb
Host smart-62694555-90c8-48e0-8186-a43e2469a802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611528710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2611528710
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.220240555
Short name T421
Test name
Test status
Simulation time 31161259 ps
CPU time 1.01 seconds
Started Jul 30 07:35:40 PM PDT 24
Finished Jul 30 07:35:42 PM PDT 24
Peak memory 206100 kb
Host smart-977e1ff1-5478-44ae-903f-855146f8eee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220240555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.220240555
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1254217631
Short name T415
Test name
Test status
Simulation time 802954885 ps
CPU time 9.42 seconds
Started Jul 30 07:35:36 PM PDT 24
Finished Jul 30 07:35:45 PM PDT 24
Peak memory 215472 kb
Host smart-9853d5ad-fb41-41e8-9750-add6a2402bd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1254217631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1254217631
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3839103923
Short name T64
Test name
Test status
Simulation time 386726041 ps
CPU time 4.61 seconds
Started Jul 30 07:35:41 PM PDT 24
Finished Jul 30 07:35:46 PM PDT 24
Peak memory 221776 kb
Host smart-6bedffe3-2f33-444c-b2b9-0e5cdf1322ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839103923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3839103923
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1100375089
Short name T49
Test name
Test status
Simulation time 704650285 ps
CPU time 3.96 seconds
Started Jul 30 07:35:35 PM PDT 24
Finished Jul 30 07:35:39 PM PDT 24
Peak memory 218136 kb
Host smart-a3d472bd-96c7-40c1-9a15-2314711b1fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100375089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1100375089
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3902482684
Short name T264
Test name
Test status
Simulation time 189968589 ps
CPU time 2.99 seconds
Started Jul 30 07:35:41 PM PDT 24
Finished Jul 30 07:35:44 PM PDT 24
Peak memory 215032 kb
Host smart-96c36f72-49bf-4bf5-aefa-6776a71fb13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902482684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3902482684
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2986268213
Short name T334
Test name
Test status
Simulation time 570181588 ps
CPU time 5.19 seconds
Started Jul 30 07:35:38 PM PDT 24
Finished Jul 30 07:35:43 PM PDT 24
Peak memory 214252 kb
Host smart-d2b6151e-3346-4217-bf5e-d0485cb77e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986268213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2986268213
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.1762033924
Short name T532
Test name
Test status
Simulation time 468556403 ps
CPU time 4.87 seconds
Started Jul 30 07:35:41 PM PDT 24
Finished Jul 30 07:35:45 PM PDT 24
Peak memory 209784 kb
Host smart-373d141b-940d-4924-a3e1-6d6d53e4101a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762033924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.1762033924
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_sideload.227686307
Short name T371
Test name
Test status
Simulation time 372244395 ps
CPU time 2.37 seconds
Started Jul 30 07:35:34 PM PDT 24
Finished Jul 30 07:35:37 PM PDT 24
Peak memory 206972 kb
Host smart-6c7f1c3f-8da3-4913-ab5a-bca99318278c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227686307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.227686307
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1033259719
Short name T271
Test name
Test status
Simulation time 320660163 ps
CPU time 3.84 seconds
Started Jul 30 07:35:36 PM PDT 24
Finished Jul 30 07:35:40 PM PDT 24
Peak memory 208620 kb
Host smart-41b25bf1-1c6e-4bf3-aa84-83e6fdffb143
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033259719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1033259719
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2034909074
Short name T700
Test name
Test status
Simulation time 140682474 ps
CPU time 2.6 seconds
Started Jul 30 07:35:37 PM PDT 24
Finished Jul 30 07:35:39 PM PDT 24
Peak memory 208744 kb
Host smart-04986fda-d69e-4a08-a358-ed7890430af8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034909074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2034909074
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3515919390
Short name T806
Test name
Test status
Simulation time 530403334 ps
CPU time 6.32 seconds
Started Jul 30 07:35:36 PM PDT 24
Finished Jul 30 07:35:43 PM PDT 24
Peak memory 208036 kb
Host smart-74a8b6d0-7b63-4f0c-b2bb-0803e75d801d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515919390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3515919390
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.834409119
Short name T529
Test name
Test status
Simulation time 301203584 ps
CPU time 2.81 seconds
Started Jul 30 07:35:41 PM PDT 24
Finished Jul 30 07:35:43 PM PDT 24
Peak memory 215852 kb
Host smart-a6601e69-1d8b-4559-9f45-bc18c75fffe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834409119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.834409119
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.4110315262
Short name T420
Test name
Test status
Simulation time 247051785 ps
CPU time 2.86 seconds
Started Jul 30 07:35:36 PM PDT 24
Finished Jul 30 07:35:39 PM PDT 24
Peak memory 208340 kb
Host smart-ca75e8b3-a68c-463d-9393-bbf9b6e8de50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110315262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.4110315262
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.1372087586
Short name T345
Test name
Test status
Simulation time 12438013698 ps
CPU time 136.81 seconds
Started Jul 30 07:35:39 PM PDT 24
Finished Jul 30 07:37:56 PM PDT 24
Peak memory 222676 kb
Host smart-2c8f0199-d856-497c-b635-58a859c59c04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372087586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.1372087586
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2664726321
Short name T329
Test name
Test status
Simulation time 95003397 ps
CPU time 4.43 seconds
Started Jul 30 07:35:40 PM PDT 24
Finished Jul 30 07:35:44 PM PDT 24
Peak memory 208796 kb
Host smart-5c21047f-9177-429c-9765-5fbe1f2401df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664726321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2664726321
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.3336989422
Short name T466
Test name
Test status
Simulation time 12782747 ps
CPU time 0.86 seconds
Started Jul 30 07:35:45 PM PDT 24
Finished Jul 30 07:35:45 PM PDT 24
Peak memory 205940 kb
Host smart-52449882-feeb-431f-a7e3-4804b52b46f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336989422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3336989422
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3160427911
Short name T250
Test name
Test status
Simulation time 60335872 ps
CPU time 4.53 seconds
Started Jul 30 07:35:42 PM PDT 24
Finished Jul 30 07:35:47 PM PDT 24
Peak memory 214384 kb
Host smart-a0b776e4-9eb8-4db4-bd18-dea8eb56f8b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3160427911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3160427911
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.274314784
Short name T76
Test name
Test status
Simulation time 1779312235 ps
CPU time 14.02 seconds
Started Jul 30 07:35:42 PM PDT 24
Finished Jul 30 07:35:56 PM PDT 24
Peak memory 218612 kb
Host smart-82337a1a-63ba-4a01-a5c5-6720880519af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274314784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.274314784
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2839430747
Short name T907
Test name
Test status
Simulation time 196343443 ps
CPU time 3.52 seconds
Started Jul 30 07:35:47 PM PDT 24
Finished Jul 30 07:35:51 PM PDT 24
Peak memory 214352 kb
Host smart-a079eb5d-e317-4071-ad88-cf75370a0795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839430747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2839430747
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2780472928
Short name T655
Test name
Test status
Simulation time 35404112 ps
CPU time 2.2 seconds
Started Jul 30 07:35:46 PM PDT 24
Finished Jul 30 07:35:49 PM PDT 24
Peak memory 214244 kb
Host smart-fa2610b7-6b64-4348-b222-eebcab8d9052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780472928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2780472928
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2909066212
Short name T607
Test name
Test status
Simulation time 57976854 ps
CPU time 2.92 seconds
Started Jul 30 07:35:41 PM PDT 24
Finished Jul 30 07:35:44 PM PDT 24
Peak memory 222572 kb
Host smart-34d3f4dc-3ee6-46c4-b78e-c1711625d0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909066212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2909066212
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.2574663774
Short name T891
Test name
Test status
Simulation time 341616717 ps
CPU time 3.92 seconds
Started Jul 30 07:35:43 PM PDT 24
Finished Jul 30 07:35:47 PM PDT 24
Peak memory 208116 kb
Host smart-2c56b72b-ea09-4d61-a8f4-33333ca35595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574663774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2574663774
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3461451849
Short name T354
Test name
Test status
Simulation time 365838342 ps
CPU time 5.14 seconds
Started Jul 30 07:35:44 PM PDT 24
Finished Jul 30 07:35:50 PM PDT 24
Peak memory 207940 kb
Host smart-432fe2c9-fdc5-44f4-878e-ba166284ab31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461451849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3461451849
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.59793674
Short name T712
Test name
Test status
Simulation time 170999371 ps
CPU time 6.24 seconds
Started Jul 30 07:35:42 PM PDT 24
Finished Jul 30 07:35:49 PM PDT 24
Peak memory 208012 kb
Host smart-4cfa0fbe-fce9-4723-a0d3-1f49bb193860
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59793674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.59793674
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2730434689
Short name T389
Test name
Test status
Simulation time 90610720 ps
CPU time 3.67 seconds
Started Jul 30 07:35:45 PM PDT 24
Finished Jul 30 07:35:48 PM PDT 24
Peak memory 206840 kb
Host smart-800985e3-76e2-40c7-8cf9-db004f6198e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730434689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2730434689
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2166393792
Short name T577
Test name
Test status
Simulation time 496330860 ps
CPU time 4.18 seconds
Started Jul 30 07:35:45 PM PDT 24
Finished Jul 30 07:35:49 PM PDT 24
Peak memory 208676 kb
Host smart-9f4d3974-0da5-44ff-8911-81476e33f6ce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166393792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2166393792
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1033678995
Short name T513
Test name
Test status
Simulation time 1696457594 ps
CPU time 8.5 seconds
Started Jul 30 07:35:48 PM PDT 24
Finished Jul 30 07:35:56 PM PDT 24
Peak memory 218144 kb
Host smart-f8bb077c-587d-4d59-a365-984c66687a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033678995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1033678995
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3351749978
Short name T639
Test name
Test status
Simulation time 57796031 ps
CPU time 2.55 seconds
Started Jul 30 07:35:41 PM PDT 24
Finished Jul 30 07:35:44 PM PDT 24
Peak memory 208636 kb
Host smart-2598875e-f5cd-4647-a0f5-8f28680a1270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351749978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3351749978
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2012273087
Short name T859
Test name
Test status
Simulation time 10659124670 ps
CPU time 25.71 seconds
Started Jul 30 07:35:47 PM PDT 24
Finished Jul 30 07:36:13 PM PDT 24
Peak memory 209732 kb
Host smart-ffe048db-5645-4d5d-a0d0-2240b4a3149f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012273087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2012273087
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1024537887
Short name T731
Test name
Test status
Simulation time 83136851 ps
CPU time 2.03 seconds
Started Jul 30 07:35:47 PM PDT 24
Finished Jul 30 07:35:49 PM PDT 24
Peak memory 209932 kb
Host smart-e9937762-5ff4-44c4-abf7-b7b9520f8258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024537887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1024537887
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2956885234
Short name T624
Test name
Test status
Simulation time 9859142 ps
CPU time 0.74 seconds
Started Jul 30 07:35:50 PM PDT 24
Finished Jul 30 07:35:50 PM PDT 24
Peak memory 205968 kb
Host smart-ea0cf875-3568-471b-95b3-eb700ffbdd6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956885234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2956885234
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2644765930
Short name T356
Test name
Test status
Simulation time 52750810 ps
CPU time 3.42 seconds
Started Jul 30 07:35:44 PM PDT 24
Finished Jul 30 07:35:48 PM PDT 24
Peak memory 215340 kb
Host smart-e2b9c1b7-2dec-4e05-8456-b27b5476672b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2644765930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2644765930
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1135652782
Short name T670
Test name
Test status
Simulation time 46953037 ps
CPU time 1.96 seconds
Started Jul 30 07:35:49 PM PDT 24
Finished Jul 30 07:35:51 PM PDT 24
Peak memory 208268 kb
Host smart-e25a171b-d8e3-49b8-9795-851bd74bc7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135652782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1135652782
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1832374294
Short name T90
Test name
Test status
Simulation time 1192487060 ps
CPU time 6.52 seconds
Started Jul 30 07:35:51 PM PDT 24
Finished Jul 30 07:35:57 PM PDT 24
Peak memory 217992 kb
Host smart-ac66ec04-ff41-4604-b8a7-41a333935964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832374294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1832374294
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.908382826
Short name T106
Test name
Test status
Simulation time 1296265369 ps
CPU time 4.26 seconds
Started Jul 30 07:35:50 PM PDT 24
Finished Jul 30 07:35:54 PM PDT 24
Peak memory 222448 kb
Host smart-f22e4f6d-1aba-4a1f-9a50-ac0a5066e36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908382826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.908382826
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_random.1782391818
Short name T662
Test name
Test status
Simulation time 177128046 ps
CPU time 2.59 seconds
Started Jul 30 07:35:52 PM PDT 24
Finished Jul 30 07:35:55 PM PDT 24
Peak memory 208176 kb
Host smart-f15639da-5d37-490d-931f-6e34bce89597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782391818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1782391818
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3719636614
Short name T516
Test name
Test status
Simulation time 117266660 ps
CPU time 3.67 seconds
Started Jul 30 07:35:51 PM PDT 24
Finished Jul 30 07:35:55 PM PDT 24
Peak memory 206844 kb
Host smart-a4b72b73-cb55-4fba-9dbf-ad39d444f7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719636614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3719636614
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1326270603
Short name T701
Test name
Test status
Simulation time 101043682 ps
CPU time 3.56 seconds
Started Jul 30 07:35:45 PM PDT 24
Finished Jul 30 07:35:49 PM PDT 24
Peak memory 206956 kb
Host smart-bec8b7e8-b3a2-482b-bca9-d747f91272fc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326270603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1326270603
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1854755693
Short name T703
Test name
Test status
Simulation time 3311791656 ps
CPU time 37.67 seconds
Started Jul 30 07:35:45 PM PDT 24
Finished Jul 30 07:36:23 PM PDT 24
Peak memory 208040 kb
Host smart-b0b5e91d-573d-4df8-bacf-0ec1a04cde2f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854755693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1854755693
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3099981052
Short name T671
Test name
Test status
Simulation time 830808471 ps
CPU time 24.8 seconds
Started Jul 30 07:35:45 PM PDT 24
Finished Jul 30 07:36:10 PM PDT 24
Peak memory 209144 kb
Host smart-0398ec52-39a1-455e-a55e-9f7e1153da1d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099981052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3099981052
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1464244912
Short name T795
Test name
Test status
Simulation time 169196586 ps
CPU time 4.1 seconds
Started Jul 30 07:35:49 PM PDT 24
Finished Jul 30 07:35:53 PM PDT 24
Peak memory 214336 kb
Host smart-165c2fb6-dc15-47eb-bc77-4cbcb189ed08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464244912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1464244912
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2064040427
Short name T422
Test name
Test status
Simulation time 46212372 ps
CPU time 1.92 seconds
Started Jul 30 07:35:46 PM PDT 24
Finished Jul 30 07:35:48 PM PDT 24
Peak memory 208644 kb
Host smart-373f3e6a-7418-441c-9361-b78b9ba02f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064040427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2064040427
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.605106475
Short name T308
Test name
Test status
Simulation time 2890827394 ps
CPU time 87.11 seconds
Started Jul 30 07:35:50 PM PDT 24
Finished Jul 30 07:37:17 PM PDT 24
Peak memory 215656 kb
Host smart-5645462a-2d49-4681-9cef-ea6db0966ca0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605106475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.605106475
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.332722370
Short name T491
Test name
Test status
Simulation time 962137829 ps
CPU time 6.8 seconds
Started Jul 30 07:35:49 PM PDT 24
Finished Jul 30 07:35:56 PM PDT 24
Peak memory 207112 kb
Host smart-d77c4933-0df7-4050-bcae-388175689bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332722370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.332722370
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2685894672
Short name T707
Test name
Test status
Simulation time 9056627 ps
CPU time 0.82 seconds
Started Jul 30 07:32:31 PM PDT 24
Finished Jul 30 07:32:32 PM PDT 24
Peak memory 205940 kb
Host smart-5e2849f0-05f7-462d-9969-e4f1f7bc7ce4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685894672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2685894672
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3352533334
Short name T116
Test name
Test status
Simulation time 150094507 ps
CPU time 2.99 seconds
Started Jul 30 07:32:23 PM PDT 24
Finished Jul 30 07:32:26 PM PDT 24
Peak memory 222348 kb
Host smart-4e766af0-96f4-4aee-80bd-9fdb689fef13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3352533334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3352533334
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1682742327
Short name T69
Test name
Test status
Simulation time 49690443 ps
CPU time 1.85 seconds
Started Jul 30 07:32:32 PM PDT 24
Finished Jul 30 07:32:34 PM PDT 24
Peak memory 208144 kb
Host smart-7971e713-171e-495c-a411-f0989054b868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682742327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1682742327
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2199950128
Short name T96
Test name
Test status
Simulation time 180224104 ps
CPU time 4.18 seconds
Started Jul 30 07:32:31 PM PDT 24
Finished Jul 30 07:32:36 PM PDT 24
Peak memory 222488 kb
Host smart-db20ed6d-25ad-417e-8e69-4bf53fdd5a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199950128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2199950128
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1443137464
Short name T53
Test name
Test status
Simulation time 51693321 ps
CPU time 3.31 seconds
Started Jul 30 07:32:31 PM PDT 24
Finished Jul 30 07:32:35 PM PDT 24
Peak memory 221932 kb
Host smart-bcca19fe-e7cd-4bb9-a86f-28035c09b282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443137464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1443137464
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3788988941
Short name T242
Test name
Test status
Simulation time 407709562 ps
CPU time 2.75 seconds
Started Jul 30 07:32:32 PM PDT 24
Finished Jul 30 07:32:35 PM PDT 24
Peak memory 222408 kb
Host smart-e3d3dbc9-72a5-4240-8638-fe3bd5a91bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788988941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3788988941
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.1216561243
Short name T3
Test name
Test status
Simulation time 300051122 ps
CPU time 5.72 seconds
Started Jul 30 07:32:30 PM PDT 24
Finished Jul 30 07:32:36 PM PDT 24
Peak memory 218192 kb
Host smart-82784d91-3eb7-4009-922a-17fb44c86142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216561243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1216561243
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.462854170
Short name T41
Test name
Test status
Simulation time 1161504028 ps
CPU time 12.08 seconds
Started Jul 30 07:32:31 PM PDT 24
Finished Jul 30 07:32:43 PM PDT 24
Peak memory 234316 kb
Host smart-5ff2ca83-edeb-4b8e-9dd0-d12c3e888df3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462854170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.462854170
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.899280628
Short name T567
Test name
Test status
Simulation time 4368157651 ps
CPU time 28.71 seconds
Started Jul 30 07:32:21 PM PDT 24
Finished Jul 30 07:32:50 PM PDT 24
Peak memory 208532 kb
Host smart-36a5c189-7bd0-4a1a-b7f9-d7bbe305b69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899280628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.899280628
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3625178796
Short name T667
Test name
Test status
Simulation time 943456632 ps
CPU time 7.73 seconds
Started Jul 30 07:32:21 PM PDT 24
Finished Jul 30 07:32:29 PM PDT 24
Peak memory 208520 kb
Host smart-59397228-a551-43c8-a750-933423dca54b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625178796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3625178796
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3353526197
Short name T297
Test name
Test status
Simulation time 36303097 ps
CPU time 2.44 seconds
Started Jul 30 07:32:22 PM PDT 24
Finished Jul 30 07:32:25 PM PDT 24
Peak memory 207024 kb
Host smart-ee9c0414-9b80-43da-91d5-2153cdc99449
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353526197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3353526197
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3874524791
Short name T189
Test name
Test status
Simulation time 65247654 ps
CPU time 3.22 seconds
Started Jul 30 07:32:21 PM PDT 24
Finished Jul 30 07:32:24 PM PDT 24
Peak memory 208116 kb
Host smart-a7fedf6f-9838-4db4-9be2-060b1d1eb548
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874524791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3874524791
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.4153907355
Short name T296
Test name
Test status
Simulation time 808805512 ps
CPU time 5.68 seconds
Started Jul 30 07:32:32 PM PDT 24
Finished Jul 30 07:32:38 PM PDT 24
Peak memory 207892 kb
Host smart-3e883e05-f19a-4f8c-82c3-ec1bb0863769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153907355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.4153907355
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.4018415735
Short name T863
Test name
Test status
Simulation time 35192702 ps
CPU time 2.21 seconds
Started Jul 30 07:32:22 PM PDT 24
Finished Jul 30 07:32:25 PM PDT 24
Peak memory 208560 kb
Host smart-fa0afb06-406c-468a-bef6-fb850357ee0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018415735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.4018415735
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.887682996
Short name T774
Test name
Test status
Simulation time 160052482 ps
CPU time 6.47 seconds
Started Jul 30 07:32:31 PM PDT 24
Finished Jul 30 07:32:38 PM PDT 24
Peak memory 208812 kb
Host smart-66727951-6f50-4101-b10d-b09b8e8cf814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887682996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.887682996
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3016217417
Short name T381
Test name
Test status
Simulation time 75797611 ps
CPU time 2.18 seconds
Started Jul 30 07:32:34 PM PDT 24
Finished Jul 30 07:32:36 PM PDT 24
Peak memory 210088 kb
Host smart-2fbb2247-b4b0-440a-aa6c-5363b0aa5cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016217417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3016217417
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.36733941
Short name T708
Test name
Test status
Simulation time 36773937 ps
CPU time 0.77 seconds
Started Jul 30 07:35:54 PM PDT 24
Finished Jul 30 07:35:54 PM PDT 24
Peak memory 205960 kb
Host smart-b8766b9f-733a-4349-97fa-f55aa65b25ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36733941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.36733941
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1827125036
Short name T416
Test name
Test status
Simulation time 493835610 ps
CPU time 3.83 seconds
Started Jul 30 07:35:49 PM PDT 24
Finished Jul 30 07:35:53 PM PDT 24
Peak memory 215700 kb
Host smart-5ec9d4cc-8f8a-485e-ac14-7cda05e7ce14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1827125036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1827125036
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3312494554
Short name T621
Test name
Test status
Simulation time 125941010 ps
CPU time 2.63 seconds
Started Jul 30 07:35:53 PM PDT 24
Finished Jul 30 07:35:55 PM PDT 24
Peak memory 214544 kb
Host smart-29d76853-39fb-4696-b7ef-40fd38292ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312494554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3312494554
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1732491916
Short name T45
Test name
Test status
Simulation time 173392176 ps
CPU time 4.83 seconds
Started Jul 30 07:35:54 PM PDT 24
Finished Jul 30 07:35:59 PM PDT 24
Peak memory 218440 kb
Host smart-e2e50d56-4377-4cec-80e2-f379d90ad8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732491916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1732491916
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2720944943
Short name T95
Test name
Test status
Simulation time 37158424 ps
CPU time 2.78 seconds
Started Jul 30 07:35:54 PM PDT 24
Finished Jul 30 07:35:56 PM PDT 24
Peak memory 209640 kb
Host smart-62bb2cbc-360e-4800-9c38-f39882ec484a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720944943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2720944943
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2689401668
Short name T846
Test name
Test status
Simulation time 215775785 ps
CPU time 5.02 seconds
Started Jul 30 07:35:52 PM PDT 24
Finished Jul 30 07:35:57 PM PDT 24
Peak memory 222472 kb
Host smart-0d6fa965-c08b-4481-8c72-2537e2a33884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689401668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2689401668
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1773566610
Short name T647
Test name
Test status
Simulation time 156248057 ps
CPU time 3.82 seconds
Started Jul 30 07:35:53 PM PDT 24
Finished Jul 30 07:35:57 PM PDT 24
Peak memory 209844 kb
Host smart-ddf688f9-5470-41f6-b900-9bd05e7738d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773566610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1773566610
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.4144908889
Short name T245
Test name
Test status
Simulation time 639172888 ps
CPU time 4.31 seconds
Started Jul 30 07:35:49 PM PDT 24
Finished Jul 30 07:35:53 PM PDT 24
Peak memory 218236 kb
Host smart-b43492a7-e7f4-4c14-8e21-44c495534474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144908889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.4144908889
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3728882137
Short name T755
Test name
Test status
Simulation time 314499361 ps
CPU time 3.65 seconds
Started Jul 30 07:35:48 PM PDT 24
Finished Jul 30 07:35:52 PM PDT 24
Peak memory 208840 kb
Host smart-bb7d6453-09ac-402a-9edc-944515326d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728882137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3728882137
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.4040816955
Short name T269
Test name
Test status
Simulation time 60038182 ps
CPU time 2.91 seconds
Started Jul 30 07:35:52 PM PDT 24
Finished Jul 30 07:35:55 PM PDT 24
Peak memory 208752 kb
Host smart-a1bbbd72-7e5f-4e32-a67d-f62f89bbc757
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040816955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.4040816955
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.314233121
Short name T693
Test name
Test status
Simulation time 1046379706 ps
CPU time 7.87 seconds
Started Jul 30 07:35:52 PM PDT 24
Finished Jul 30 07:36:00 PM PDT 24
Peak memory 206932 kb
Host smart-f60f1075-b024-4d6c-92f1-e8fad7a256cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314233121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.314233121
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2293586515
Short name T478
Test name
Test status
Simulation time 179827428 ps
CPU time 4.45 seconds
Started Jul 30 07:35:50 PM PDT 24
Finished Jul 30 07:35:54 PM PDT 24
Peak memory 207964 kb
Host smart-9c8c4f77-82bf-4c68-be61-1ad530d5f78e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293586515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2293586515
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.4251768001
Short name T901
Test name
Test status
Simulation time 132762949 ps
CPU time 3.3 seconds
Started Jul 30 07:35:56 PM PDT 24
Finished Jul 30 07:35:59 PM PDT 24
Peak memory 218300 kb
Host smart-ca196051-cdba-46a8-a81b-9d7ec5cc06f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251768001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.4251768001
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3041103903
Short name T771
Test name
Test status
Simulation time 3410276394 ps
CPU time 10.22 seconds
Started Jul 30 07:35:49 PM PDT 24
Finished Jul 30 07:35:59 PM PDT 24
Peak memory 208516 kb
Host smart-d43def87-32f9-449b-9765-c4fd2d606303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041103903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3041103903
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.3284220565
Short name T267
Test name
Test status
Simulation time 248041911 ps
CPU time 12.9 seconds
Started Jul 30 07:35:54 PM PDT 24
Finished Jul 30 07:36:07 PM PDT 24
Peak memory 222600 kb
Host smart-b8995380-cb93-4afd-8178-accbd165c48c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284220565 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.3284220565
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.176611810
Short name T313
Test name
Test status
Simulation time 198151289 ps
CPU time 6.57 seconds
Started Jul 30 07:35:52 PM PDT 24
Finished Jul 30 07:35:59 PM PDT 24
Peak memory 208552 kb
Host smart-6a0b5a91-7299-4467-a953-87e4c6266790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176611810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.176611810
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.79372044
Short name T385
Test name
Test status
Simulation time 122848203 ps
CPU time 1.66 seconds
Started Jul 30 07:35:53 PM PDT 24
Finished Jul 30 07:35:55 PM PDT 24
Peak memory 210000 kb
Host smart-65faaf54-02f7-41ca-9daa-62b1f612e2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79372044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.79372044
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2122573872
Short name T872
Test name
Test status
Simulation time 14344413 ps
CPU time 0.9 seconds
Started Jul 30 07:36:00 PM PDT 24
Finished Jul 30 07:36:01 PM PDT 24
Peak memory 206012 kb
Host smart-a1ae2a48-8ea0-4533-b30c-90966724a4f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122573872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2122573872
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.577343634
Short name T279
Test name
Test status
Simulation time 89344715 ps
CPU time 3.61 seconds
Started Jul 30 07:36:01 PM PDT 24
Finished Jul 30 07:36:04 PM PDT 24
Peak memory 214192 kb
Host smart-6aeb85db-3e8e-4ae8-923f-987629f0f610
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=577343634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.577343634
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2163198531
Short name T21
Test name
Test status
Simulation time 402585257 ps
CPU time 3.47 seconds
Started Jul 30 07:35:57 PM PDT 24
Finished Jul 30 07:36:01 PM PDT 24
Peak memory 209956 kb
Host smart-ef32a8db-fd10-409b-ac82-803d63fd475e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163198531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2163198531
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1986587595
Short name T423
Test name
Test status
Simulation time 70399955 ps
CPU time 2.39 seconds
Started Jul 30 07:35:58 PM PDT 24
Finished Jul 30 07:36:01 PM PDT 24
Peak memory 206972 kb
Host smart-c075c59d-8d4e-40da-b124-078df252739a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986587595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1986587595
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2543130379
Short name T575
Test name
Test status
Simulation time 355701800 ps
CPU time 4.06 seconds
Started Jul 30 07:36:00 PM PDT 24
Finished Jul 30 07:36:04 PM PDT 24
Peak memory 214308 kb
Host smart-a99a0d5f-5bd6-4ce8-aa5a-20085bd98566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543130379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2543130379
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2958506473
Short name T453
Test name
Test status
Simulation time 116475889 ps
CPU time 2.29 seconds
Started Jul 30 07:36:00 PM PDT 24
Finished Jul 30 07:36:02 PM PDT 24
Peak memory 215480 kb
Host smart-48e948ba-7cb9-43b2-b316-75342dcec4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958506473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2958506473
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1381667926
Short name T12
Test name
Test status
Simulation time 152147943 ps
CPU time 5.13 seconds
Started Jul 30 07:35:56 PM PDT 24
Finished Jul 30 07:36:01 PM PDT 24
Peak memory 208488 kb
Host smart-13f69ec8-0275-4c7e-ba54-931025ae71ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381667926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1381667926
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1973370466
Short name T344
Test name
Test status
Simulation time 45749329 ps
CPU time 2.39 seconds
Started Jul 30 07:36:00 PM PDT 24
Finished Jul 30 07:36:02 PM PDT 24
Peak memory 208472 kb
Host smart-e755f5ba-efd3-424b-9cc7-1dcd7791bf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973370466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1973370466
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3497590657
Short name T694
Test name
Test status
Simulation time 206890221 ps
CPU time 2.8 seconds
Started Jul 30 07:35:57 PM PDT 24
Finished Jul 30 07:36:00 PM PDT 24
Peak memory 206964 kb
Host smart-2a32f48d-bfc6-4d9d-ac0a-a64a4248f77d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497590657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3497590657
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.2213275128
Short name T885
Test name
Test status
Simulation time 308491273 ps
CPU time 4.03 seconds
Started Jul 30 07:36:01 PM PDT 24
Finished Jul 30 07:36:05 PM PDT 24
Peak memory 206876 kb
Host smart-65fcfb71-df8c-4b21-a40a-0099338c976a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213275128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2213275128
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3307880285
Short name T582
Test name
Test status
Simulation time 51796216 ps
CPU time 2.92 seconds
Started Jul 30 07:35:59 PM PDT 24
Finished Jul 30 07:36:02 PM PDT 24
Peak memory 206940 kb
Host smart-ab60dfa2-7bca-4258-913e-f7676337e872
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307880285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3307880285
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.979644273
Short name T558
Test name
Test status
Simulation time 201276412 ps
CPU time 5.72 seconds
Started Jul 30 07:35:57 PM PDT 24
Finished Jul 30 07:36:02 PM PDT 24
Peak memory 209388 kb
Host smart-66cb29c6-d909-42cc-a3bb-67a054c78044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979644273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.979644273
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3618608004
Short name T882
Test name
Test status
Simulation time 48656758 ps
CPU time 2.42 seconds
Started Jul 30 07:35:57 PM PDT 24
Finished Jul 30 07:36:00 PM PDT 24
Peak memory 208096 kb
Host smart-f0919a75-1c5e-4fe3-9590-2629d7634d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618608004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3618608004
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2046035484
Short name T4
Test name
Test status
Simulation time 935315176 ps
CPU time 8.09 seconds
Started Jul 30 07:36:00 PM PDT 24
Finished Jul 30 07:36:08 PM PDT 24
Peak memory 208700 kb
Host smart-13637e0a-8d9a-42c9-982c-a0cc1f920898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046035484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2046035484
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.832938803
Short name T599
Test name
Test status
Simulation time 232000986 ps
CPU time 1.72 seconds
Started Jul 30 07:35:57 PM PDT 24
Finished Jul 30 07:35:59 PM PDT 24
Peak memory 210156 kb
Host smart-bee83d40-178c-4feb-be5b-e17dc228dc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832938803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.832938803
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.6383845
Short name T702
Test name
Test status
Simulation time 109251279 ps
CPU time 0.89 seconds
Started Jul 30 07:36:01 PM PDT 24
Finished Jul 30 07:36:02 PM PDT 24
Peak memory 206040 kb
Host smart-d47d0312-dc8f-48f2-a332-36cb9ddbe1ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6383845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.6383845
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2975046837
Short name T340
Test name
Test status
Simulation time 2318241496 ps
CPU time 9.28 seconds
Started Jul 30 07:36:01 PM PDT 24
Finished Jul 30 07:36:11 PM PDT 24
Peak memory 214404 kb
Host smart-88c8bb7b-3555-4dfc-a95c-44c710492eee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2975046837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2975046837
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.4030292826
Short name T25
Test name
Test status
Simulation time 146556597 ps
CPU time 3.25 seconds
Started Jul 30 07:36:07 PM PDT 24
Finished Jul 30 07:36:11 PM PDT 24
Peak memory 218876 kb
Host smart-80533413-95a7-4342-92fc-4a939ed6100c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030292826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.4030292826
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2502662540
Short name T332
Test name
Test status
Simulation time 156739181 ps
CPU time 4.47 seconds
Started Jul 30 07:36:02 PM PDT 24
Finished Jul 30 07:36:06 PM PDT 24
Peak memory 214292 kb
Host smart-122da743-3980-4014-b418-fdf955c60bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502662540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2502662540
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3000199401
Short name T373
Test name
Test status
Simulation time 144042286 ps
CPU time 3.51 seconds
Started Jul 30 07:36:00 PM PDT 24
Finished Jul 30 07:36:03 PM PDT 24
Peak memory 214364 kb
Host smart-eead5098-7a81-4fbc-b2b0-8e0fed96d88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000199401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3000199401
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1822542902
Short name T873
Test name
Test status
Simulation time 42214330 ps
CPU time 2.41 seconds
Started Jul 30 07:36:01 PM PDT 24
Finished Jul 30 07:36:04 PM PDT 24
Peak memory 214264 kb
Host smart-155916ec-92cb-4c02-8b48-f67aae0b950b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822542902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1822542902
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1328282017
Short name T680
Test name
Test status
Simulation time 157252974 ps
CPU time 2.57 seconds
Started Jul 30 07:36:01 PM PDT 24
Finished Jul 30 07:36:04 PM PDT 24
Peak memory 214364 kb
Host smart-dd1bb01b-212b-4b2b-8050-f1bb2a46ab40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328282017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1328282017
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2415752006
Short name T837
Test name
Test status
Simulation time 134774610 ps
CPU time 5.69 seconds
Started Jul 30 07:36:02 PM PDT 24
Finished Jul 30 07:36:08 PM PDT 24
Peak memory 208772 kb
Host smart-f46d5bc2-198f-404f-a3f3-3310d18fca90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415752006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2415752006
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2596458316
Short name T530
Test name
Test status
Simulation time 315188418 ps
CPU time 4.05 seconds
Started Jul 30 07:35:56 PM PDT 24
Finished Jul 30 07:36:00 PM PDT 24
Peak memory 206936 kb
Host smart-1530fcfb-5380-443d-a8d0-c6fae9d8a80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596458316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2596458316
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3679264350
Short name T392
Test name
Test status
Simulation time 241609743 ps
CPU time 3.81 seconds
Started Jul 30 07:36:00 PM PDT 24
Finished Jul 30 07:36:03 PM PDT 24
Peak memory 206768 kb
Host smart-7e6a062d-ea87-4f39-82e0-e36d7ea7ecea
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679264350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3679264350
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3101771450
Short name T572
Test name
Test status
Simulation time 590322973 ps
CPU time 3.96 seconds
Started Jul 30 07:36:01 PM PDT 24
Finished Jul 30 07:36:05 PM PDT 24
Peak memory 208660 kb
Host smart-39e4544f-ad3d-4e75-9966-a0de21b56e3d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101771450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3101771450
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2417852167
Short name T589
Test name
Test status
Simulation time 6740522640 ps
CPU time 31.68 seconds
Started Jul 30 07:35:57 PM PDT 24
Finished Jul 30 07:36:29 PM PDT 24
Peak memory 209116 kb
Host smart-c66750cf-cdb3-4e64-a49a-8affdf86c232
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417852167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2417852167
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.3634362922
Short name T850
Test name
Test status
Simulation time 45000886 ps
CPU time 2.1 seconds
Started Jul 30 07:36:01 PM PDT 24
Finished Jul 30 07:36:03 PM PDT 24
Peak memory 207612 kb
Host smart-7d11e8ca-24bf-43cc-8748-2343cdeb528b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634362922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3634362922
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3694491993
Short name T451
Test name
Test status
Simulation time 73631758 ps
CPU time 1.74 seconds
Started Jul 30 07:35:58 PM PDT 24
Finished Jul 30 07:36:00 PM PDT 24
Peak memory 207116 kb
Host smart-723f1ef6-3ebd-4610-9217-d82fe3ef2c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694491993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3694491993
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.353134992
Short name T290
Test name
Test status
Simulation time 2443768871 ps
CPU time 49.34 seconds
Started Jul 30 07:36:03 PM PDT 24
Finished Jul 30 07:36:53 PM PDT 24
Peak memory 214632 kb
Host smart-e86b55fe-5210-4dc2-943f-e4e61ac69301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353134992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.353134992
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.198438466
Short name T482
Test name
Test status
Simulation time 1690060198 ps
CPU time 13.27 seconds
Started Jul 30 07:36:07 PM PDT 24
Finished Jul 30 07:36:21 PM PDT 24
Peak memory 222548 kb
Host smart-e8b67d35-8bb0-4476-96ca-e7a72679f337
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198438466 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.198438466
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.399436149
Short name T311
Test name
Test status
Simulation time 382699501 ps
CPU time 5.59 seconds
Started Jul 30 07:36:00 PM PDT 24
Finished Jul 30 07:36:06 PM PDT 24
Peak memory 218544 kb
Host smart-38e504ef-57fc-456f-aab3-d4fb84456307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399436149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.399436149
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.623867159
Short name T197
Test name
Test status
Simulation time 1380484861 ps
CPU time 6.84 seconds
Started Jul 30 07:36:01 PM PDT 24
Finished Jul 30 07:36:08 PM PDT 24
Peak memory 210764 kb
Host smart-5a17c68e-3c16-4bfe-b801-09a539bfdc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623867159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.623867159
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3780539186
Short name T533
Test name
Test status
Simulation time 49084511 ps
CPU time 0.73 seconds
Started Jul 30 07:36:03 PM PDT 24
Finished Jul 30 07:36:04 PM PDT 24
Peak memory 205940 kb
Host smart-4fc9ad8f-ed5a-4292-b1d3-bb8191788ebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780539186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3780539186
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.75358726
Short name T256
Test name
Test status
Simulation time 197526391 ps
CPU time 2.62 seconds
Started Jul 30 07:36:00 PM PDT 24
Finished Jul 30 07:36:03 PM PDT 24
Peak memory 222496 kb
Host smart-ace8be0d-67c7-497f-88ba-0e6947ebaa33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75358726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.75358726
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.4122336752
Short name T787
Test name
Test status
Simulation time 470012546 ps
CPU time 4.01 seconds
Started Jul 30 07:36:06 PM PDT 24
Finished Jul 30 07:36:10 PM PDT 24
Peak memory 209500 kb
Host smart-29928f39-5234-4de3-828a-cc415f1faf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122336752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.4122336752
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2682879955
Short name T591
Test name
Test status
Simulation time 441350412 ps
CPU time 3.26 seconds
Started Jul 30 07:36:06 PM PDT 24
Finished Jul 30 07:36:09 PM PDT 24
Peak memory 220548 kb
Host smart-99b89e59-33e5-4813-acbf-2a1620dc0bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682879955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2682879955
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3142662435
Short name T222
Test name
Test status
Simulation time 97167872 ps
CPU time 3.23 seconds
Started Jul 30 07:36:07 PM PDT 24
Finished Jul 30 07:36:10 PM PDT 24
Peak memory 209752 kb
Host smart-5bc171d8-ebcf-42e6-9280-a7250594ecba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142662435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3142662435
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.64969587
Short name T857
Test name
Test status
Simulation time 186218693 ps
CPU time 5.79 seconds
Started Jul 30 07:36:02 PM PDT 24
Finished Jul 30 07:36:07 PM PDT 24
Peak memory 208212 kb
Host smart-11db236d-2fd3-48f5-a32d-5cbb8ee33481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64969587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.64969587
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.649077209
Short name T690
Test name
Test status
Simulation time 146331294 ps
CPU time 4.58 seconds
Started Jul 30 07:36:03 PM PDT 24
Finished Jul 30 07:36:08 PM PDT 24
Peak memory 208824 kb
Host smart-6aa8a3ad-cd4f-40e9-8c6d-98690a106be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649077209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.649077209
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.4265130102
Short name T481
Test name
Test status
Simulation time 47755378 ps
CPU time 2.93 seconds
Started Jul 30 07:36:07 PM PDT 24
Finished Jul 30 07:36:10 PM PDT 24
Peak memory 207024 kb
Host smart-f7bed784-7c82-4128-8f57-981b60cdba61
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265130102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.4265130102
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.4107798296
Short name T396
Test name
Test status
Simulation time 118448912 ps
CPU time 3 seconds
Started Jul 30 07:35:59 PM PDT 24
Finished Jul 30 07:36:02 PM PDT 24
Peak memory 208148 kb
Host smart-646c1989-05c2-4a3e-bfe7-57c88ca5bcb3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107798296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.4107798296
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.4087797843
Short name T578
Test name
Test status
Simulation time 27546259 ps
CPU time 2.17 seconds
Started Jul 30 07:36:07 PM PDT 24
Finished Jul 30 07:36:09 PM PDT 24
Peak memory 208756 kb
Host smart-15fc7d61-c021-4dac-baeb-0505856ea965
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087797843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.4087797843
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.96162035
Short name T246
Test name
Test status
Simulation time 1657728300 ps
CPU time 11.11 seconds
Started Jul 30 07:36:06 PM PDT 24
Finished Jul 30 07:36:17 PM PDT 24
Peak memory 210416 kb
Host smart-b9c541ac-4c7b-4831-beea-aaad0d89a95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96162035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.96162035
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3702818120
Short name T434
Test name
Test status
Simulation time 67292969 ps
CPU time 2.91 seconds
Started Jul 30 07:36:03 PM PDT 24
Finished Jul 30 07:36:06 PM PDT 24
Peak memory 208360 kb
Host smart-e1540efd-f0b8-4e41-88c7-4a5f5daf8cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702818120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3702818120
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1809438620
Short name T347
Test name
Test status
Simulation time 2517786765 ps
CPU time 26.18 seconds
Started Jul 30 07:36:05 PM PDT 24
Finished Jul 30 07:36:32 PM PDT 24
Peak memory 216664 kb
Host smart-1a9e1aee-d057-4c37-a1b5-f2c1222a8851
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809438620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1809438620
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.872197738
Short name T48
Test name
Test status
Simulation time 241477950 ps
CPU time 6.04 seconds
Started Jul 30 07:36:05 PM PDT 24
Finished Jul 30 07:36:11 PM PDT 24
Peak memory 222532 kb
Host smart-0820840c-0cd2-4a6b-a4f7-bc73fa1ecf59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872197738 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.872197738
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.4109916057
Short name T500
Test name
Test status
Simulation time 49062903 ps
CPU time 3.13 seconds
Started Jul 30 07:36:08 PM PDT 24
Finished Jul 30 07:36:11 PM PDT 24
Peak memory 207480 kb
Host smart-67ec23c3-286b-41d5-a887-a84f5664b4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109916057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.4109916057
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3188101462
Short name T166
Test name
Test status
Simulation time 132852951 ps
CPU time 3.34 seconds
Started Jul 30 07:36:06 PM PDT 24
Finished Jul 30 07:36:10 PM PDT 24
Peak memory 210248 kb
Host smart-eef2d579-97fc-40b0-9819-619912cb5a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188101462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3188101462
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2457494599
Short name T893
Test name
Test status
Simulation time 60983442 ps
CPU time 0.77 seconds
Started Jul 30 07:36:06 PM PDT 24
Finished Jul 30 07:36:07 PM PDT 24
Peak memory 205932 kb
Host smart-f8b06bdf-f527-48a6-8a2f-15a24a0d42c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457494599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2457494599
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.236623240
Short name T404
Test name
Test status
Simulation time 488201162 ps
CPU time 4.07 seconds
Started Jul 30 07:36:11 PM PDT 24
Finished Jul 30 07:36:15 PM PDT 24
Peak memory 214300 kb
Host smart-11e9eec6-d9e5-4f5c-aa2e-45b86ce6a3ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=236623240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.236623240
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.61097215
Short name T734
Test name
Test status
Simulation time 757299874 ps
CPU time 6.19 seconds
Started Jul 30 07:36:06 PM PDT 24
Finished Jul 30 07:36:12 PM PDT 24
Peak memory 218628 kb
Host smart-4bd4e0a8-fa27-4d6e-9e39-531029b1f1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61097215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.61097215
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.259175344
Short name T281
Test name
Test status
Simulation time 409382630 ps
CPU time 3.18 seconds
Started Jul 30 07:36:07 PM PDT 24
Finished Jul 30 07:36:10 PM PDT 24
Peak memory 209644 kb
Host smart-c989ee1b-68a5-499d-a31b-aadb391141ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259175344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.259175344
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.4018044867
Short name T34
Test name
Test status
Simulation time 204185259 ps
CPU time 4.59 seconds
Started Jul 30 07:36:12 PM PDT 24
Finished Jul 30 07:36:16 PM PDT 24
Peak memory 222332 kb
Host smart-8b3a3225-dae1-4c80-a01a-0f298012dca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018044867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.4018044867
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3950219074
Short name T767
Test name
Test status
Simulation time 138220494 ps
CPU time 5.29 seconds
Started Jul 30 07:36:05 PM PDT 24
Finished Jul 30 07:36:10 PM PDT 24
Peak memory 220008 kb
Host smart-4fe422d1-4923-4a29-bb33-9c3c9bd5966f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950219074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3950219074
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1206666936
Short name T886
Test name
Test status
Simulation time 160869422 ps
CPU time 4.8 seconds
Started Jul 30 07:36:06 PM PDT 24
Finished Jul 30 07:36:11 PM PDT 24
Peak memory 209792 kb
Host smart-a9460040-50e9-4446-9277-c280270c2962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206666936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1206666936
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2172268541
Short name T910
Test name
Test status
Simulation time 441591127 ps
CPU time 2.32 seconds
Started Jul 30 07:36:08 PM PDT 24
Finished Jul 30 07:36:11 PM PDT 24
Peak memory 206892 kb
Host smart-7f4fc457-5a0c-49f8-84fc-64a4a9be851d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172268541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2172268541
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1551451139
Short name T658
Test name
Test status
Simulation time 178989115 ps
CPU time 4.56 seconds
Started Jul 30 07:36:07 PM PDT 24
Finished Jul 30 07:36:11 PM PDT 24
Peak memory 206984 kb
Host smart-570be7c9-a0bc-4b19-a832-7be44d7268d0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551451139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1551451139
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3945687224
Short name T902
Test name
Test status
Simulation time 183145564 ps
CPU time 1.9 seconds
Started Jul 30 07:36:05 PM PDT 24
Finished Jul 30 07:36:07 PM PDT 24
Peak memory 207432 kb
Host smart-794882fd-2a21-4138-a531-93b253c0e007
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945687224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3945687224
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1265370877
Short name T571
Test name
Test status
Simulation time 1338790723 ps
CPU time 33.55 seconds
Started Jul 30 07:36:05 PM PDT 24
Finished Jul 30 07:36:38 PM PDT 24
Peak memory 209104 kb
Host smart-70ad734b-efc0-4965-b84d-634a8a7b18d0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265370877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1265370877
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.56753315
Short name T130
Test name
Test status
Simulation time 215984193 ps
CPU time 2.73 seconds
Started Jul 30 07:36:11 PM PDT 24
Finished Jul 30 07:36:14 PM PDT 24
Peak memory 208816 kb
Host smart-7ed8551c-83b2-46af-894f-e75a5f458ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56753315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.56753315
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3524317644
Short name T856
Test name
Test status
Simulation time 234369732 ps
CPU time 2.47 seconds
Started Jul 30 07:36:10 PM PDT 24
Finished Jul 30 07:36:12 PM PDT 24
Peak memory 208268 kb
Host smart-5dab4771-397f-4896-bd75-f594f551eecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524317644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3524317644
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.870625491
Short name T368
Test name
Test status
Simulation time 659117435 ps
CPU time 9.16 seconds
Started Jul 30 07:36:07 PM PDT 24
Finished Jul 30 07:36:16 PM PDT 24
Peak memory 215420 kb
Host smart-0b3994da-441f-471c-81e7-229b2108ddcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870625491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.870625491
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1017734115
Short name T367
Test name
Test status
Simulation time 135865765 ps
CPU time 4.63 seconds
Started Jul 30 07:36:04 PM PDT 24
Finished Jul 30 07:36:09 PM PDT 24
Peak memory 210620 kb
Host smart-d45374cd-deed-4096-bfd7-7a9dd37e3027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017734115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1017734115
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1889584655
Short name T645
Test name
Test status
Simulation time 85187630 ps
CPU time 1.76 seconds
Started Jul 30 07:36:06 PM PDT 24
Finished Jul 30 07:36:08 PM PDT 24
Peak memory 209752 kb
Host smart-5fa591b9-032d-45a9-abc6-03b568f23c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889584655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1889584655
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2753796445
Short name T753
Test name
Test status
Simulation time 14303646 ps
CPU time 0.76 seconds
Started Jul 30 07:36:11 PM PDT 24
Finished Jul 30 07:36:12 PM PDT 24
Peak memory 205956 kb
Host smart-e69e5a30-f844-4bc0-8d31-ff4a4c178034
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753796445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2753796445
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1110653545
Short name T387
Test name
Test status
Simulation time 111714750 ps
CPU time 4.07 seconds
Started Jul 30 07:36:14 PM PDT 24
Finished Jul 30 07:36:18 PM PDT 24
Peak memory 214360 kb
Host smart-c78f3fdb-ab74-4c04-91c7-9a90303a7bea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1110653545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1110653545
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.702048784
Short name T273
Test name
Test status
Simulation time 26830742 ps
CPU time 1.76 seconds
Started Jul 30 07:36:08 PM PDT 24
Finished Jul 30 07:36:09 PM PDT 24
Peak memory 209052 kb
Host smart-75db174f-ea7e-4ae9-87c5-7cfe2dfcac8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702048784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.702048784
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.785066856
Short name T760
Test name
Test status
Simulation time 220776621 ps
CPU time 2.23 seconds
Started Jul 30 07:36:09 PM PDT 24
Finished Jul 30 07:36:12 PM PDT 24
Peak memory 207168 kb
Host smart-569d3d16-3cf5-408d-ae7d-074d5f7ec868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785066856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.785066856
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1152637837
Short name T287
Test name
Test status
Simulation time 95610234 ps
CPU time 4.91 seconds
Started Jul 30 07:36:15 PM PDT 24
Finished Jul 30 07:36:20 PM PDT 24
Peak memory 214120 kb
Host smart-2b13b731-c7da-45f5-a486-a7bd6ee4ea5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152637837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1152637837
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2399049776
Short name T756
Test name
Test status
Simulation time 152411889 ps
CPU time 2.72 seconds
Started Jul 30 07:36:07 PM PDT 24
Finished Jul 30 07:36:10 PM PDT 24
Peak memory 214448 kb
Host smart-17cfe30a-791d-45dc-804f-e986b9aaadcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399049776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2399049776
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2037496963
Short name T299
Test name
Test status
Simulation time 1308281657 ps
CPU time 4.53 seconds
Started Jul 30 07:36:11 PM PDT 24
Finished Jul 30 07:36:16 PM PDT 24
Peak memory 207756 kb
Host smart-befb37e0-1e85-4080-81dc-36b327a3a22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037496963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2037496963
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3408089479
Short name T819
Test name
Test status
Simulation time 1091392219 ps
CPU time 6.76 seconds
Started Jul 30 07:36:06 PM PDT 24
Finished Jul 30 07:36:13 PM PDT 24
Peak memory 208920 kb
Host smart-f17d7a60-d5e3-43e7-b620-353f61845d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408089479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3408089479
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.850003804
Short name T890
Test name
Test status
Simulation time 1540084830 ps
CPU time 16.78 seconds
Started Jul 30 07:36:10 PM PDT 24
Finished Jul 30 07:36:27 PM PDT 24
Peak memory 208520 kb
Host smart-63e0f099-c7b9-4b06-a884-1f8024f30bc7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850003804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.850003804
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3237528889
Short name T346
Test name
Test status
Simulation time 347190934 ps
CPU time 2.57 seconds
Started Jul 30 07:36:06 PM PDT 24
Finished Jul 30 07:36:08 PM PDT 24
Peak memory 206960 kb
Host smart-7e3b710d-b5b8-45f9-9caf-1db4c63f2df5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237528889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3237528889
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1274071135
Short name T620
Test name
Test status
Simulation time 226956806 ps
CPU time 5.98 seconds
Started Jul 30 07:36:09 PM PDT 24
Finished Jul 30 07:36:15 PM PDT 24
Peak memory 207796 kb
Host smart-f9e9b40c-18e2-41ec-a559-f149280aa6be
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274071135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1274071135
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2462706557
Short name T604
Test name
Test status
Simulation time 1834218297 ps
CPU time 9.48 seconds
Started Jul 30 07:36:08 PM PDT 24
Finished Jul 30 07:36:18 PM PDT 24
Peak memory 208376 kb
Host smart-11c6088f-ea23-48f5-9eb8-d6c74726a9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462706557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2462706557
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1951723463
Short name T834
Test name
Test status
Simulation time 113355811 ps
CPU time 3.64 seconds
Started Jul 30 07:36:12 PM PDT 24
Finished Jul 30 07:36:16 PM PDT 24
Peak memory 207080 kb
Host smart-2db647f2-9f4f-47f1-a20a-34a75a18b635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951723463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1951723463
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.1549067786
Short name T220
Test name
Test status
Simulation time 647954251 ps
CPU time 14.54 seconds
Started Jul 30 07:36:07 PM PDT 24
Finished Jul 30 07:36:22 PM PDT 24
Peak memory 222404 kb
Host smart-4f7f1de5-16c4-40ca-870a-cea1217aa1b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549067786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.1549067786
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.3105082975
Short name T134
Test name
Test status
Simulation time 1275497924 ps
CPU time 10.17 seconds
Started Jul 30 07:36:10 PM PDT 24
Finished Jul 30 07:36:20 PM PDT 24
Peak memory 222456 kb
Host smart-b29b35fb-e69a-47c8-bfbf-2860a76af550
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105082975 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.3105082975
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3602889667
Short name T782
Test name
Test status
Simulation time 1168909287 ps
CPU time 4.3 seconds
Started Jul 30 07:36:10 PM PDT 24
Finished Jul 30 07:36:14 PM PDT 24
Peak memory 209812 kb
Host smart-92e9a3ab-3985-41d2-acbb-908da6195ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602889667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3602889667
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1598237389
Short name T641
Test name
Test status
Simulation time 650391870 ps
CPU time 2.36 seconds
Started Jul 30 07:36:08 PM PDT 24
Finished Jul 30 07:36:10 PM PDT 24
Peak memory 210168 kb
Host smart-4f5daf15-5090-4db6-afb1-6b23fdc6967e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598237389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1598237389
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.403934687
Short name T554
Test name
Test status
Simulation time 30008527 ps
CPU time 0.79 seconds
Started Jul 30 07:36:11 PM PDT 24
Finished Jul 30 07:36:12 PM PDT 24
Peak memory 205964 kb
Host smart-3708d06f-67f6-420a-86a2-7820dff95473
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403934687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.403934687
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.4163109268
Short name T399
Test name
Test status
Simulation time 283430427 ps
CPU time 4.41 seconds
Started Jul 30 07:36:13 PM PDT 24
Finished Jul 30 07:36:18 PM PDT 24
Peak memory 215284 kb
Host smart-db8bb06a-e942-4345-95ff-521ec2f57e4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4163109268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.4163109268
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1257002202
Short name T769
Test name
Test status
Simulation time 136728297 ps
CPU time 3.34 seconds
Started Jul 30 07:36:09 PM PDT 24
Finished Jul 30 07:36:13 PM PDT 24
Peak memory 214288 kb
Host smart-bd6f5c1e-3170-4f9e-bc87-7bc233a1f470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257002202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1257002202
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.525510445
Short name T838
Test name
Test status
Simulation time 309743409 ps
CPU time 3.67 seconds
Started Jul 30 07:36:10 PM PDT 24
Finished Jul 30 07:36:13 PM PDT 24
Peak memory 214256 kb
Host smart-c3bc2684-cb7f-4515-9b87-d81b23e18391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525510445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.525510445
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2052789173
Short name T636
Test name
Test status
Simulation time 75832799 ps
CPU time 3.07 seconds
Started Jul 30 07:36:15 PM PDT 24
Finished Jul 30 07:36:18 PM PDT 24
Peak memory 214588 kb
Host smart-1b6c8714-b346-4a11-aaf3-31000c233c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052789173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2052789173
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2619561950
Short name T219
Test name
Test status
Simulation time 68841322 ps
CPU time 3.08 seconds
Started Jul 30 07:36:09 PM PDT 24
Finished Jul 30 07:36:12 PM PDT 24
Peak memory 214388 kb
Host smart-007d730f-d3e6-4050-bc51-7f3cb61477e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619561950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2619561950
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.4164835513
Short name T17
Test name
Test status
Simulation time 4848077155 ps
CPU time 46.5 seconds
Started Jul 30 07:36:15 PM PDT 24
Finished Jul 30 07:37:02 PM PDT 24
Peak memory 210784 kb
Host smart-26217970-2388-4f45-afdd-1b4d7df5bec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164835513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.4164835513
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3441689775
Short name T673
Test name
Test status
Simulation time 233472411 ps
CPU time 8.17 seconds
Started Jul 30 07:36:13 PM PDT 24
Finished Jul 30 07:36:21 PM PDT 24
Peak memory 208676 kb
Host smart-aa364579-8e6e-426e-9a68-6e18276e86ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441689775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3441689775
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3158500403
Short name T820
Test name
Test status
Simulation time 24511872 ps
CPU time 1.86 seconds
Started Jul 30 07:36:15 PM PDT 24
Finished Jul 30 07:36:17 PM PDT 24
Peak memory 207772 kb
Host smart-2aae8611-3f80-4346-956b-d975260a8eef
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158500403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3158500403
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3932784354
Short name T255
Test name
Test status
Simulation time 337643895 ps
CPU time 5.52 seconds
Started Jul 30 07:36:10 PM PDT 24
Finished Jul 30 07:36:16 PM PDT 24
Peak memory 207956 kb
Host smart-a78fe3e7-5654-49f8-a1c6-55c2f59b8508
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932784354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3932784354
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3678834430
Short name T490
Test name
Test status
Simulation time 93651744 ps
CPU time 1.98 seconds
Started Jul 30 07:36:09 PM PDT 24
Finished Jul 30 07:36:12 PM PDT 24
Peak memory 207692 kb
Host smart-65e1b676-4bb7-4350-8e23-a4c0bafe529d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678834430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3678834430
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.1618708416
Short name T549
Test name
Test status
Simulation time 310558626 ps
CPU time 2.91 seconds
Started Jul 30 07:36:13 PM PDT 24
Finished Jul 30 07:36:15 PM PDT 24
Peak memory 215752 kb
Host smart-b2d12e0f-2073-4ef1-a751-e886d9877202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618708416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1618708416
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.25564487
Short name T574
Test name
Test status
Simulation time 10270708796 ps
CPU time 39.38 seconds
Started Jul 30 07:36:08 PM PDT 24
Finished Jul 30 07:36:47 PM PDT 24
Peak memory 208456 kb
Host smart-fcf67184-3dcd-4268-ab17-4696a773f0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25564487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.25564487
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1309726365
Short name T315
Test name
Test status
Simulation time 510371954 ps
CPU time 23.87 seconds
Started Jul 30 07:36:12 PM PDT 24
Finished Jul 30 07:36:36 PM PDT 24
Peak memory 222480 kb
Host smart-9a95828a-3a7d-4046-871f-0dbc45b1e27d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309726365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1309726365
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3765560923
Short name T439
Test name
Test status
Simulation time 904856313 ps
CPU time 25.89 seconds
Started Jul 30 07:36:08 PM PDT 24
Finished Jul 30 07:36:34 PM PDT 24
Peak memory 209444 kb
Host smart-2d3ee5e7-9bf4-40f1-aed2-9d59bd5cf22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765560923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3765560923
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1458631880
Short name T468
Test name
Test status
Simulation time 131759160 ps
CPU time 2.29 seconds
Started Jul 30 07:36:12 PM PDT 24
Finished Jul 30 07:36:14 PM PDT 24
Peak memory 210128 kb
Host smart-74d5d911-7317-4674-888a-5dee17e71e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458631880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1458631880
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3606325879
Short name T98
Test name
Test status
Simulation time 13087527 ps
CPU time 0.87 seconds
Started Jul 30 07:36:15 PM PDT 24
Finished Jul 30 07:36:16 PM PDT 24
Peak memory 205940 kb
Host smart-78ba5407-ab31-4b77-9739-b659e5085d9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606325879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3606325879
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2141437135
Short name T414
Test name
Test status
Simulation time 55285185 ps
CPU time 3.73 seconds
Started Jul 30 07:36:12 PM PDT 24
Finished Jul 30 07:36:16 PM PDT 24
Peak memory 214380 kb
Host smart-075a1091-bd89-4a53-b300-46b082cf6833
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2141437135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2141437135
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2182958596
Short name T31
Test name
Test status
Simulation time 133459353 ps
CPU time 2.78 seconds
Started Jul 30 07:36:12 PM PDT 24
Finished Jul 30 07:36:15 PM PDT 24
Peak memory 221012 kb
Host smart-9b416f7e-ec64-4f2b-be30-7d8fe9f7c97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182958596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2182958596
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1710503216
Short name T836
Test name
Test status
Simulation time 289663122 ps
CPU time 3.07 seconds
Started Jul 30 07:36:10 PM PDT 24
Finished Jul 30 07:36:14 PM PDT 24
Peak memory 209124 kb
Host smart-6e266c62-08dc-4e21-af11-9330c6bd2316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710503216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1710503216
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.260273127
Short name T284
Test name
Test status
Simulation time 61968624 ps
CPU time 3.42 seconds
Started Jul 30 07:36:14 PM PDT 24
Finished Jul 30 07:36:18 PM PDT 24
Peak memory 214380 kb
Host smart-648db4ae-8a89-4bf8-8c84-b8cc3ebe5fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260273127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.260273127
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.2397252278
Short name T84
Test name
Test status
Simulation time 206452285 ps
CPU time 3.14 seconds
Started Jul 30 07:36:14 PM PDT 24
Finished Jul 30 07:36:17 PM PDT 24
Peak memory 214296 kb
Host smart-5610673f-d9e8-44c5-9754-78bbafe4318c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397252278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.2397252278
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2634701511
Short name T797
Test name
Test status
Simulation time 275581070 ps
CPU time 3.23 seconds
Started Jul 30 07:36:14 PM PDT 24
Finished Jul 30 07:36:18 PM PDT 24
Peak memory 220412 kb
Host smart-84237b89-230a-4519-923d-4240a76d1087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634701511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2634701511
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.825835290
Short name T594
Test name
Test status
Simulation time 100782246 ps
CPU time 4.57 seconds
Started Jul 30 07:36:13 PM PDT 24
Finished Jul 30 07:36:17 PM PDT 24
Peak memory 208776 kb
Host smart-0454f427-db15-4d5d-876e-c9aacd65cfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825835290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.825835290
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1127362262
Short name T685
Test name
Test status
Simulation time 569023288 ps
CPU time 5.91 seconds
Started Jul 30 07:36:11 PM PDT 24
Finished Jul 30 07:36:17 PM PDT 24
Peak memory 208368 kb
Host smart-f572f6e3-82c0-4549-8bd0-d5c38f136217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127362262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1127362262
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1370951118
Short name T775
Test name
Test status
Simulation time 119191451 ps
CPU time 2.33 seconds
Started Jul 30 07:36:11 PM PDT 24
Finished Jul 30 07:36:13 PM PDT 24
Peak memory 206956 kb
Host smart-104b185b-1bf7-4ed0-9b7e-4df588e8b95a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370951118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1370951118
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.304901450
Short name T270
Test name
Test status
Simulation time 88981779 ps
CPU time 3.6 seconds
Started Jul 30 07:36:11 PM PDT 24
Finished Jul 30 07:36:15 PM PDT 24
Peak memory 208652 kb
Host smart-de2ff320-63b4-4cd6-96af-9a78837cad27
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304901450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.304901450
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1114039354
Short name T569
Test name
Test status
Simulation time 293180929 ps
CPU time 3.99 seconds
Started Jul 30 07:36:12 PM PDT 24
Finished Jul 30 07:36:16 PM PDT 24
Peak memory 208876 kb
Host smart-4e46e187-ea05-4553-9a67-90d7fd4157f2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114039354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1114039354
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1516108954
Short name T78
Test name
Test status
Simulation time 288048568 ps
CPU time 3.98 seconds
Started Jul 30 07:36:13 PM PDT 24
Finished Jul 30 07:36:17 PM PDT 24
Peak memory 215868 kb
Host smart-81bb65d3-fbab-48e3-93cd-afca6f4b98ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516108954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1516108954
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1999714144
Short name T622
Test name
Test status
Simulation time 503875010 ps
CPU time 3.13 seconds
Started Jul 30 07:36:12 PM PDT 24
Finished Jul 30 07:36:15 PM PDT 24
Peak memory 206936 kb
Host smart-292c3184-7a89-4d58-8172-c1311e4a7ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999714144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1999714144
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.1143383836
Short name T229
Test name
Test status
Simulation time 207496172 ps
CPU time 13.53 seconds
Started Jul 30 07:36:17 PM PDT 24
Finished Jul 30 07:36:30 PM PDT 24
Peak memory 222636 kb
Host smart-030ace65-f031-47a2-952e-9af73ba09e28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143383836 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.1143383836
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.3483013066
Short name T823
Test name
Test status
Simulation time 100377531 ps
CPU time 3.19 seconds
Started Jul 30 07:36:13 PM PDT 24
Finished Jul 30 07:36:16 PM PDT 24
Peak memory 207580 kb
Host smart-d1212b8b-d18e-460c-8d7e-51ed9711ecd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483013066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3483013066
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3136656781
Short name T129
Test name
Test status
Simulation time 29509108 ps
CPU time 1.35 seconds
Started Jul 30 07:36:14 PM PDT 24
Finished Jul 30 07:36:16 PM PDT 24
Peak memory 208488 kb
Host smart-30a4b91a-2224-45de-95ae-c9b60501e047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136656781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3136656781
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.4159545864
Short name T480
Test name
Test status
Simulation time 31019904 ps
CPU time 0.73 seconds
Started Jul 30 07:36:20 PM PDT 24
Finished Jul 30 07:36:21 PM PDT 24
Peak memory 205944 kb
Host smart-059a97fd-074f-4b1f-90ee-813e8ec80afb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159545864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.4159545864
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.4201212356
Short name T706
Test name
Test status
Simulation time 2550875074 ps
CPU time 30.71 seconds
Started Jul 30 07:36:19 PM PDT 24
Finished Jul 30 07:36:49 PM PDT 24
Peak memory 214400 kb
Host smart-d719d832-61e2-4883-8b1f-bb9cf264310d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201212356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.4201212356
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3868431635
Short name T289
Test name
Test status
Simulation time 70885039 ps
CPU time 2.78 seconds
Started Jul 30 07:36:17 PM PDT 24
Finished Jul 30 07:36:20 PM PDT 24
Peak memory 214316 kb
Host smart-2e459282-7adb-4819-9fe3-3e553dba66be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868431635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3868431635
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.635951094
Short name T377
Test name
Test status
Simulation time 257421135 ps
CPU time 3.57 seconds
Started Jul 30 07:36:19 PM PDT 24
Finished Jul 30 07:36:22 PM PDT 24
Peak memory 214240 kb
Host smart-3876afb2-bbfd-4991-ba61-8cbf5fc467ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635951094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.635951094
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2095760284
Short name T446
Test name
Test status
Simulation time 70533577 ps
CPU time 1.37 seconds
Started Jul 30 07:36:22 PM PDT 24
Finished Jul 30 07:36:24 PM PDT 24
Peak memory 206100 kb
Host smart-20f05396-661b-4ace-a8c0-f6355c7fe178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095760284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2095760284
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1072992183
Short name T688
Test name
Test status
Simulation time 220591825 ps
CPU time 4.53 seconds
Started Jul 30 07:36:17 PM PDT 24
Finished Jul 30 07:36:22 PM PDT 24
Peak memory 214424 kb
Host smart-61de55c2-65f4-4957-bdb3-73ebc82ddfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072992183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1072992183
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.3509012913
Short name T805
Test name
Test status
Simulation time 647593097 ps
CPU time 4.83 seconds
Started Jul 30 07:36:14 PM PDT 24
Finished Jul 30 07:36:19 PM PDT 24
Peak memory 208932 kb
Host smart-1e6eedb9-c65f-4198-bba0-6e57fad684ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509012913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.3509012913
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3314120691
Short name T740
Test name
Test status
Simulation time 145134846 ps
CPU time 5.17 seconds
Started Jul 30 07:36:16 PM PDT 24
Finished Jul 30 07:36:21 PM PDT 24
Peak memory 208896 kb
Host smart-f7fbfb34-e326-4ea4-86a3-f0c8528e8cae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314120691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3314120691
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1359845568
Short name T602
Test name
Test status
Simulation time 83537918 ps
CPU time 3.11 seconds
Started Jul 30 07:36:14 PM PDT 24
Finished Jul 30 07:36:17 PM PDT 24
Peak memory 206944 kb
Host smart-30482c6f-36bb-48ba-8dbb-ea0a9ff4db8e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359845568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1359845568
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3805706727
Short name T390
Test name
Test status
Simulation time 397768921 ps
CPU time 3.61 seconds
Started Jul 30 07:36:17 PM PDT 24
Finished Jul 30 07:36:21 PM PDT 24
Peak memory 206960 kb
Host smart-ff3d6fa8-9d44-46ec-af20-f7d20f24fbca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805706727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3805706727
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1775537253
Short name T803
Test name
Test status
Simulation time 214781269 ps
CPU time 4.35 seconds
Started Jul 30 07:36:20 PM PDT 24
Finished Jul 30 07:36:24 PM PDT 24
Peak memory 209364 kb
Host smart-814c8790-403c-4e4e-8329-ebd1ee4f1fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775537253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1775537253
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2490498421
Short name T804
Test name
Test status
Simulation time 195427184 ps
CPU time 2.49 seconds
Started Jul 30 07:36:15 PM PDT 24
Finished Jul 30 07:36:17 PM PDT 24
Peak memory 208532 kb
Host smart-fdb1592a-def8-4443-b7e0-fe1a0593a4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490498421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2490498421
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1135932586
Short name T200
Test name
Test status
Simulation time 205356092 ps
CPU time 5.88 seconds
Started Jul 30 07:36:18 PM PDT 24
Finished Jul 30 07:36:24 PM PDT 24
Peak memory 214292 kb
Host smart-6428a856-b23c-4e69-8773-aa9c6fdf1272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135932586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1135932586
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3096782149
Short name T386
Test name
Test status
Simulation time 1547204131 ps
CPU time 23.27 seconds
Started Jul 30 07:36:18 PM PDT 24
Finished Jul 30 07:36:42 PM PDT 24
Peak memory 211004 kb
Host smart-b5dfc443-5ef1-4a56-ba9f-80de40e8abf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096782149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3096782149
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.45153471
Short name T664
Test name
Test status
Simulation time 65846050 ps
CPU time 0.76 seconds
Started Jul 30 07:36:23 PM PDT 24
Finished Jul 30 07:36:24 PM PDT 24
Peak memory 205940 kb
Host smart-4b8ea586-c473-41c0-8434-a84b41de5169
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45153471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.45153471
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1773415605
Short name T398
Test name
Test status
Simulation time 116831014 ps
CPU time 4.03 seconds
Started Jul 30 07:36:24 PM PDT 24
Finished Jul 30 07:36:28 PM PDT 24
Peak memory 214312 kb
Host smart-9a941254-8a1b-4035-b8a5-f5c6f1267341
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1773415605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1773415605
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.4056918914
Short name T28
Test name
Test status
Simulation time 26244609 ps
CPU time 1.66 seconds
Started Jul 30 07:36:24 PM PDT 24
Finished Jul 30 07:36:25 PM PDT 24
Peak memory 208172 kb
Host smart-d89c1656-b020-4df8-8549-3da9ed0ee6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056918914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.4056918914
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1454337642
Short name T257
Test name
Test status
Simulation time 144201505 ps
CPU time 2.59 seconds
Started Jul 30 07:36:22 PM PDT 24
Finished Jul 30 07:36:25 PM PDT 24
Peak memory 207252 kb
Host smart-3ff2de8f-08cd-4b6c-9db1-d56959bdf30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454337642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1454337642
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3501410754
Short name T24
Test name
Test status
Simulation time 120969015 ps
CPU time 4.04 seconds
Started Jul 30 07:36:25 PM PDT 24
Finished Jul 30 07:36:29 PM PDT 24
Peak memory 214312 kb
Host smart-2c9bae5a-3b50-47a2-b8e9-574e6b2e6c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501410754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3501410754
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2192577402
Short name T835
Test name
Test status
Simulation time 54423615 ps
CPU time 2.72 seconds
Started Jul 30 07:36:22 PM PDT 24
Finished Jul 30 07:36:25 PM PDT 24
Peak memory 214344 kb
Host smart-555b7057-84e4-425b-8adf-9fd6e00ffb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192577402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2192577402
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1790287482
Short name T456
Test name
Test status
Simulation time 115407162 ps
CPU time 5.41 seconds
Started Jul 30 07:36:23 PM PDT 24
Finished Jul 30 07:36:29 PM PDT 24
Peak memory 208656 kb
Host smart-5edaff44-08ac-4942-a07d-3f48920099e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790287482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1790287482
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2655239742
Short name T908
Test name
Test status
Simulation time 907218524 ps
CPU time 5.63 seconds
Started Jul 30 07:36:20 PM PDT 24
Finished Jul 30 07:36:26 PM PDT 24
Peak memory 208428 kb
Host smart-0135b5d4-c271-41d9-8267-4423cade22f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655239742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2655239742
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1022554842
Short name T280
Test name
Test status
Simulation time 8476536565 ps
CPU time 14.93 seconds
Started Jul 30 07:36:21 PM PDT 24
Finished Jul 30 07:36:36 PM PDT 24
Peak memory 208168 kb
Host smart-2b67acd6-5f61-4807-b4ba-60ac354bb451
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022554842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1022554842
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3119378264
Short name T580
Test name
Test status
Simulation time 729847438 ps
CPU time 5.72 seconds
Started Jul 30 07:36:23 PM PDT 24
Finished Jul 30 07:36:29 PM PDT 24
Peak memory 208048 kb
Host smart-f466963f-fce5-40d7-aeea-fe1275a00675
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119378264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3119378264
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3243751764
Short name T470
Test name
Test status
Simulation time 85310259 ps
CPU time 3.83 seconds
Started Jul 30 07:36:21 PM PDT 24
Finished Jul 30 07:36:25 PM PDT 24
Peak memory 208720 kb
Host smart-c72b6cbd-1c0d-4e7e-be19-9e0e0210bb9b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243751764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3243751764
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.3186509721
Short name T581
Test name
Test status
Simulation time 96598849 ps
CPU time 4.22 seconds
Started Jul 30 07:36:24 PM PDT 24
Finished Jul 30 07:36:28 PM PDT 24
Peak memory 209104 kb
Host smart-0b1fca70-4ca1-412a-b5ee-c9a36773c817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186509721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3186509721
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1906598867
Short name T441
Test name
Test status
Simulation time 693688824 ps
CPU time 6.84 seconds
Started Jul 30 07:36:20 PM PDT 24
Finished Jul 30 07:36:27 PM PDT 24
Peak memory 208320 kb
Host smart-0ae7bf2e-7c28-451e-a52e-08055408eb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906598867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1906598867
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1337176417
Short name T186
Test name
Test status
Simulation time 524043626 ps
CPU time 18.33 seconds
Started Jul 30 07:36:24 PM PDT 24
Finished Jul 30 07:36:43 PM PDT 24
Peak memory 220148 kb
Host smart-6619e168-5a19-4ced-b8d7-4eed5baee731
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337176417 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1337176417
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2820976404
Short name T275
Test name
Test status
Simulation time 200961433 ps
CPU time 5.67 seconds
Started Jul 30 07:36:23 PM PDT 24
Finished Jul 30 07:36:29 PM PDT 24
Peak memory 209920 kb
Host smart-0bae6a23-5791-4018-a60f-5406a8a9fc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820976404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2820976404
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.261673309
Short name T36
Test name
Test status
Simulation time 293749038 ps
CPU time 2.97 seconds
Started Jul 30 07:36:24 PM PDT 24
Finished Jul 30 07:36:27 PM PDT 24
Peak memory 210128 kb
Host smart-d48270b1-36df-4306-a0e1-345d7873a123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261673309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.261673309
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.1633965035
Short name T484
Test name
Test status
Simulation time 17346127 ps
CPU time 0.69 seconds
Started Jul 30 07:32:41 PM PDT 24
Finished Jul 30 07:32:42 PM PDT 24
Peak memory 205912 kb
Host smart-7c6ceab9-9ec1-46fd-bc6e-5a75aedb3b0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633965035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.1633965035
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1057109286
Short name T401
Test name
Test status
Simulation time 250877100 ps
CPU time 11.92 seconds
Started Jul 30 07:32:35 PM PDT 24
Finished Jul 30 07:32:47 PM PDT 24
Peak memory 215316 kb
Host smart-8cf5ef72-22a2-48fc-b630-b8fd0ee84491
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1057109286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1057109286
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1228919572
Short name T30
Test name
Test status
Simulation time 61937335 ps
CPU time 3.27 seconds
Started Jul 30 07:32:38 PM PDT 24
Finished Jul 30 07:32:42 PM PDT 24
Peak memory 209568 kb
Host smart-2d11ffda-dd46-42cf-b0ec-dbffa3185502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228919572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1228919572
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1891866046
Short name T274
Test name
Test status
Simulation time 1414573253 ps
CPU time 14.86 seconds
Started Jul 30 07:32:37 PM PDT 24
Finished Jul 30 07:32:52 PM PDT 24
Peak memory 208956 kb
Host smart-06199a5c-4010-4e78-a6d8-ea73a38a9a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891866046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1891866046
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3316157617
Short name T768
Test name
Test status
Simulation time 114870260 ps
CPU time 4.88 seconds
Started Jul 30 07:32:41 PM PDT 24
Finished Jul 30 07:32:46 PM PDT 24
Peak memory 214296 kb
Host smart-78de28c2-efa2-440f-b7f5-c89163ebe760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316157617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3316157617
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2208145374
Short name T317
Test name
Test status
Simulation time 53807437 ps
CPU time 2.34 seconds
Started Jul 30 07:32:40 PM PDT 24
Finished Jul 30 07:32:43 PM PDT 24
Peak memory 214220 kb
Host smart-c4799175-f43d-49c1-aacb-77e3f2134102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208145374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2208145374
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1807159660
Short name T217
Test name
Test status
Simulation time 120161633 ps
CPU time 5.41 seconds
Started Jul 30 07:32:40 PM PDT 24
Finished Jul 30 07:32:46 PM PDT 24
Peak memory 209740 kb
Host smart-b0d883bc-6f41-4804-a32f-1c68b0e3212e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807159660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1807159660
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3088865590
Short name T788
Test name
Test status
Simulation time 749109445 ps
CPU time 10.18 seconds
Started Jul 30 07:32:33 PM PDT 24
Finished Jul 30 07:32:44 PM PDT 24
Peak memory 209252 kb
Host smart-8257462d-0af0-4115-89fc-86e9bfad55a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088865590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3088865590
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1718250945
Short name T808
Test name
Test status
Simulation time 382718588 ps
CPU time 3.94 seconds
Started Jul 30 07:32:32 PM PDT 24
Finished Jul 30 07:32:36 PM PDT 24
Peak memory 209008 kb
Host smart-5387e264-a50a-4cfe-a1a1-5a09b62bab3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718250945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1718250945
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3670165954
Short name T778
Test name
Test status
Simulation time 224023976 ps
CPU time 3 seconds
Started Jul 30 07:32:36 PM PDT 24
Finished Jul 30 07:32:39 PM PDT 24
Peak memory 207028 kb
Host smart-278a7f5c-844e-4b44-8e2b-1a95dfb55ccf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670165954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3670165954
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.550435920
Short name T796
Test name
Test status
Simulation time 743327368 ps
CPU time 5.41 seconds
Started Jul 30 07:32:31 PM PDT 24
Finished Jul 30 07:32:36 PM PDT 24
Peak memory 207904 kb
Host smart-aec5287e-25ba-4184-9f4b-56f0b7f53ebb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550435920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.550435920
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.4066914946
Short name T457
Test name
Test status
Simulation time 249547066 ps
CPU time 3.44 seconds
Started Jul 30 07:32:35 PM PDT 24
Finished Jul 30 07:32:38 PM PDT 24
Peak memory 207024 kb
Host smart-b6364237-f455-48ac-9177-6e797ccf2731
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066914946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.4066914946
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1489514532
Short name T687
Test name
Test status
Simulation time 65205669 ps
CPU time 2.64 seconds
Started Jul 30 07:32:39 PM PDT 24
Finished Jul 30 07:32:42 PM PDT 24
Peak memory 215936 kb
Host smart-a4cf79da-e95f-4280-ad69-a987c642f0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489514532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1489514532
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3313177001
Short name T440
Test name
Test status
Simulation time 1328979002 ps
CPU time 20.92 seconds
Started Jul 30 07:32:32 PM PDT 24
Finished Jul 30 07:32:53 PM PDT 24
Peak memory 208584 kb
Host smart-0c02a518-e468-4d2e-a62b-dacbe53eb1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313177001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3313177001
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3325984247
Short name T801
Test name
Test status
Simulation time 420301974 ps
CPU time 4.44 seconds
Started Jul 30 07:32:40 PM PDT 24
Finished Jul 30 07:32:45 PM PDT 24
Peak memory 214268 kb
Host smart-3e0f31a8-ee8d-41a6-9cf4-9f9cea850433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325984247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3325984247
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2677525247
Short name T196
Test name
Test status
Simulation time 96938748 ps
CPU time 3.7 seconds
Started Jul 30 07:32:39 PM PDT 24
Finished Jul 30 07:32:43 PM PDT 24
Peak memory 210080 kb
Host smart-6484149c-7012-4797-91d6-5c507138b43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677525247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2677525247
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1049469032
Short name T527
Test name
Test status
Simulation time 27304482 ps
CPU time 0.9 seconds
Started Jul 30 07:32:46 PM PDT 24
Finished Jul 30 07:32:47 PM PDT 24
Peak memory 205996 kb
Host smart-08cca10a-1e7f-478d-ba3c-5df7084e556a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049469032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1049469032
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1288491283
Short name T403
Test name
Test status
Simulation time 138834749 ps
CPU time 2.86 seconds
Started Jul 30 07:32:46 PM PDT 24
Finished Jul 30 07:32:49 PM PDT 24
Peak memory 214344 kb
Host smart-c606e65b-42fa-45db-86ca-bb75b4ad104b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1288491283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1288491283
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1461440502
Short name T668
Test name
Test status
Simulation time 259982280 ps
CPU time 4.09 seconds
Started Jul 30 07:32:42 PM PDT 24
Finished Jul 30 07:32:47 PM PDT 24
Peak memory 218224 kb
Host smart-661e6c78-8704-4b86-b72b-5397cf771670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461440502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1461440502
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2225154203
Short name T359
Test name
Test status
Simulation time 373638485 ps
CPU time 3.31 seconds
Started Jul 30 07:32:42 PM PDT 24
Finished Jul 30 07:32:45 PM PDT 24
Peak memory 214276 kb
Host smart-831e7b9c-b39c-4cb3-a472-b36bc6970006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225154203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2225154203
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2064914662
Short name T608
Test name
Test status
Simulation time 156824860 ps
CPU time 2.24 seconds
Started Jul 30 07:32:43 PM PDT 24
Finished Jul 30 07:32:45 PM PDT 24
Peak memory 211596 kb
Host smart-e5123669-ac5e-4855-b1c0-6d27ac071632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064914662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2064914662
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2751484992
Short name T814
Test name
Test status
Simulation time 40781783 ps
CPU time 2.48 seconds
Started Jul 30 07:32:44 PM PDT 24
Finished Jul 30 07:32:47 PM PDT 24
Peak memory 209236 kb
Host smart-270ddec6-4bc1-4f0c-9148-04623094c72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751484992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2751484992
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3539298291
Short name T492
Test name
Test status
Simulation time 596396047 ps
CPU time 11.37 seconds
Started Jul 30 07:32:42 PM PDT 24
Finished Jul 30 07:32:54 PM PDT 24
Peak memory 207584 kb
Host smart-0d7de48c-64d0-4939-8f20-6559df477f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539298291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3539298291
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2528614532
Short name T601
Test name
Test status
Simulation time 86439533 ps
CPU time 3.25 seconds
Started Jul 30 07:32:42 PM PDT 24
Finished Jul 30 07:32:46 PM PDT 24
Peak memory 208476 kb
Host smart-2e15fd56-8a4f-4d0c-9dcc-0829268169b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528614532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2528614532
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3463990044
Short name T501
Test name
Test status
Simulation time 53202342 ps
CPU time 2.86 seconds
Started Jul 30 07:32:44 PM PDT 24
Finished Jul 30 07:32:47 PM PDT 24
Peak memory 207048 kb
Host smart-f4cf379d-7683-4f4a-a7f2-123efdb6938b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463990044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3463990044
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3908539429
Short name T485
Test name
Test status
Simulation time 535951835 ps
CPU time 6.89 seconds
Started Jul 30 07:32:42 PM PDT 24
Finished Jul 30 07:32:49 PM PDT 24
Peak memory 208848 kb
Host smart-12bfbc64-7b97-4f1b-bd6e-da2f61ffe04a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908539429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3908539429
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2098932487
Short name T537
Test name
Test status
Simulation time 1077147842 ps
CPU time 25.54 seconds
Started Jul 30 07:32:44 PM PDT 24
Finished Jul 30 07:33:10 PM PDT 24
Peak memory 208016 kb
Host smart-c0ebc9f2-68c4-4ab6-93c3-f0b1c7a929d6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098932487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2098932487
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1694325834
Short name T752
Test name
Test status
Simulation time 61243109 ps
CPU time 2.82 seconds
Started Jul 30 07:32:46 PM PDT 24
Finished Jul 30 07:32:49 PM PDT 24
Peak memory 208880 kb
Host smart-d0bbf805-1a08-4d95-8c45-92f744327d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694325834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1694325834
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3093267013
Short name T584
Test name
Test status
Simulation time 650298934 ps
CPU time 6.32 seconds
Started Jul 30 07:32:43 PM PDT 24
Finished Jul 30 07:32:50 PM PDT 24
Peak memory 206920 kb
Host smart-fcceab55-f061-49ed-a905-9f894922d154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093267013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3093267013
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2980206410
Short name T224
Test name
Test status
Simulation time 497950581 ps
CPU time 12.61 seconds
Started Jul 30 07:32:48 PM PDT 24
Finished Jul 30 07:33:01 PM PDT 24
Peak memory 220184 kb
Host smart-a750b2c6-62ee-4505-b57e-4df255f345a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980206410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2980206410
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3549047652
Short name T660
Test name
Test status
Simulation time 283291617 ps
CPU time 6.5 seconds
Started Jul 30 07:32:43 PM PDT 24
Finished Jul 30 07:32:50 PM PDT 24
Peak memory 214380 kb
Host smart-776577a5-1765-4647-98dc-0aabb2cb47d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549047652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3549047652
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.4084924118
Short name T854
Test name
Test status
Simulation time 59673692 ps
CPU time 1.71 seconds
Started Jul 30 07:32:46 PM PDT 24
Finished Jul 30 07:32:48 PM PDT 24
Peak memory 209872 kb
Host smart-820283ea-ca56-4a5a-96d3-bac56cf3d3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084924118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.4084924118
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2310177348
Short name T739
Test name
Test status
Simulation time 113153751 ps
CPU time 0.87 seconds
Started Jul 30 07:32:50 PM PDT 24
Finished Jul 30 07:32:51 PM PDT 24
Peak memory 206024 kb
Host smart-4eeb0782-1be8-4715-8a99-299902f60b78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310177348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2310177348
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3389192833
Short name T536
Test name
Test status
Simulation time 55237805 ps
CPU time 2.57 seconds
Started Jul 30 07:32:46 PM PDT 24
Finished Jul 30 07:32:49 PM PDT 24
Peak memory 210444 kb
Host smart-930bdb03-ab1f-486e-8d6d-bd7e25677cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389192833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3389192833
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3716618006
Short name T259
Test name
Test status
Simulation time 186233692 ps
CPU time 2.13 seconds
Started Jul 30 07:32:50 PM PDT 24
Finished Jul 30 07:32:52 PM PDT 24
Peak memory 214352 kb
Host smart-4304dece-b7d8-4893-821e-d63d180776f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716618006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3716618006
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.504179582
Short name T258
Test name
Test status
Simulation time 269355875 ps
CPU time 3.48 seconds
Started Jul 30 07:32:50 PM PDT 24
Finished Jul 30 07:32:53 PM PDT 24
Peak memory 214252 kb
Host smart-20a7c294-b684-4ca8-b708-48f49355b1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504179582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.504179582
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.736512795
Short name T704
Test name
Test status
Simulation time 292563238 ps
CPU time 4.56 seconds
Started Jul 30 07:32:51 PM PDT 24
Finished Jul 30 07:32:56 PM PDT 24
Peak memory 214320 kb
Host smart-5caf15d8-a332-44a4-aff2-bbceec0df2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736512795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.736512795
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1329851902
Short name T548
Test name
Test status
Simulation time 253573349 ps
CPU time 3.38 seconds
Started Jul 30 07:32:47 PM PDT 24
Finished Jul 30 07:32:50 PM PDT 24
Peak memory 208824 kb
Host smart-6806a855-0d8a-48db-827b-f4baf34ee1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329851902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1329851902
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.606050888
Short name T459
Test name
Test status
Simulation time 227026239 ps
CPU time 3.64 seconds
Started Jul 30 07:32:46 PM PDT 24
Finished Jul 30 07:32:50 PM PDT 24
Peak memory 206844 kb
Host smart-12f76ba8-8346-4dbb-82b8-d49e1312b76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606050888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.606050888
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.192364482
Short name T642
Test name
Test status
Simulation time 4488698843 ps
CPU time 20.93 seconds
Started Jul 30 07:32:47 PM PDT 24
Finished Jul 30 07:33:08 PM PDT 24
Peak memory 208012 kb
Host smart-66708e6a-53ec-48c3-8b64-95a442e0f246
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192364482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.192364482
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1897152124
Short name T323
Test name
Test status
Simulation time 88533818 ps
CPU time 3.16 seconds
Started Jul 30 07:32:47 PM PDT 24
Finished Jul 30 07:32:50 PM PDT 24
Peak memory 208392 kb
Host smart-bc0a3e67-d6ee-450e-80ec-d230e68fb96c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897152124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1897152124
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.484023006
Short name T842
Test name
Test status
Simulation time 590189338 ps
CPU time 18.54 seconds
Started Jul 30 07:32:46 PM PDT 24
Finished Jul 30 07:33:04 PM PDT 24
Peak memory 209008 kb
Host smart-6c985e40-909d-48f8-9d1e-3c5a42c6571d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484023006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.484023006
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.2944632905
Short name T528
Test name
Test status
Simulation time 147317015 ps
CPU time 3.33 seconds
Started Jul 30 07:32:50 PM PDT 24
Finished Jul 30 07:32:54 PM PDT 24
Peak memory 208956 kb
Host smart-5e35dfc4-baf2-440a-bd76-e3fcc36d2245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944632905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.2944632905
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3939515933
Short name T839
Test name
Test status
Simulation time 37073409 ps
CPU time 2.24 seconds
Started Jul 30 07:32:49 PM PDT 24
Finished Jul 30 07:32:51 PM PDT 24
Peak memory 208496 kb
Host smart-4a000eab-0ce5-4f1a-9f5a-4b9125626b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939515933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3939515933
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2387262290
Short name T832
Test name
Test status
Simulation time 1864560267 ps
CPU time 49.09 seconds
Started Jul 30 07:32:51 PM PDT 24
Finished Jul 30 07:33:40 PM PDT 24
Peak memory 222468 kb
Host smart-82297053-c0cc-4ada-bc74-aa432641ebe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387262290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2387262290
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.248696090
Short name T372
Test name
Test status
Simulation time 1240007102 ps
CPU time 19.92 seconds
Started Jul 30 07:32:51 PM PDT 24
Finished Jul 30 07:33:11 PM PDT 24
Peak memory 222428 kb
Host smart-73ec75dc-777d-4a14-9acb-b159c3c43901
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248696090 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.248696090
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3243584308
Short name T305
Test name
Test status
Simulation time 246604504 ps
CPU time 6.47 seconds
Started Jul 30 07:32:52 PM PDT 24
Finished Jul 30 07:32:58 PM PDT 24
Peak memory 218452 kb
Host smart-d2f5510d-fb7a-4767-8a86-221f8c6ae4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243584308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3243584308
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1191890114
Short name T715
Test name
Test status
Simulation time 63414297 ps
CPU time 2.13 seconds
Started Jul 30 07:32:50 PM PDT 24
Finished Jul 30 07:32:52 PM PDT 24
Peak memory 210000 kb
Host smart-06fc78ad-dcf5-4c3a-ba0f-15ad8c98b0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191890114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1191890114
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.848170198
Short name T626
Test name
Test status
Simulation time 11911925 ps
CPU time 0.87 seconds
Started Jul 30 07:32:57 PM PDT 24
Finished Jul 30 07:32:58 PM PDT 24
Peak memory 205936 kb
Host smart-04246253-12ba-4075-8579-c977d88d5fdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848170198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.848170198
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2104441839
Short name T402
Test name
Test status
Simulation time 6914889473 ps
CPU time 96.66 seconds
Started Jul 30 07:32:55 PM PDT 24
Finished Jul 30 07:34:32 PM PDT 24
Peak memory 215292 kb
Host smart-c22e61ad-2572-4435-a857-d79c77f97d13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2104441839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2104441839
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2245419091
Short name T333
Test name
Test status
Simulation time 208539988 ps
CPU time 3.25 seconds
Started Jul 30 07:32:55 PM PDT 24
Finished Jul 30 07:32:58 PM PDT 24
Peak memory 207072 kb
Host smart-0f15fb7b-3c2a-4c31-b56f-d18aa7ded5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245419091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2245419091
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2203438136
Short name T627
Test name
Test status
Simulation time 315992354 ps
CPU time 3.91 seconds
Started Jul 30 07:32:54 PM PDT 24
Finished Jul 30 07:32:58 PM PDT 24
Peak memory 214296 kb
Host smart-3a30bc4b-4ceb-41d0-9797-4b2a07be0485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203438136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2203438136
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.1558291664
Short name T35
Test name
Test status
Simulation time 34218077 ps
CPU time 1.98 seconds
Started Jul 30 07:32:54 PM PDT 24
Finished Jul 30 07:32:56 PM PDT 24
Peak memory 214256 kb
Host smart-3f51f648-1f89-4df8-b98a-15ccbe049a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558291664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1558291664
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.770651487
Short name T679
Test name
Test status
Simulation time 122442396 ps
CPU time 2.77 seconds
Started Jul 30 07:32:55 PM PDT 24
Finished Jul 30 07:32:57 PM PDT 24
Peak memory 214356 kb
Host smart-39d32ea4-d4e7-4986-8527-eb827f94e047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770651487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.770651487
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2833729880
Short name T900
Test name
Test status
Simulation time 198435629 ps
CPU time 3.33 seconds
Started Jul 30 07:32:55 PM PDT 24
Finished Jul 30 07:32:59 PM PDT 24
Peak memory 209968 kb
Host smart-7fd76df4-606c-4599-8135-9f907d79cfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833729880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2833729880
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3164118201
Short name T714
Test name
Test status
Simulation time 226384184 ps
CPU time 2.98 seconds
Started Jul 30 07:32:54 PM PDT 24
Finished Jul 30 07:32:57 PM PDT 24
Peak memory 208760 kb
Host smart-ef80f3d8-9392-45c6-87ff-37dc6ef01800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164118201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3164118201
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.156583296
Short name T247
Test name
Test status
Simulation time 159733485 ps
CPU time 5.07 seconds
Started Jul 30 07:32:55 PM PDT 24
Finished Jul 30 07:33:00 PM PDT 24
Peak memory 208028 kb
Host smart-f03c253e-e89d-4b7a-876e-fe6ecd34c0bd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156583296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.156583296
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1272615292
Short name T852
Test name
Test status
Simulation time 1274132104 ps
CPU time 22.09 seconds
Started Jul 30 07:32:54 PM PDT 24
Finished Jul 30 07:33:16 PM PDT 24
Peak memory 208920 kb
Host smart-fba4cc54-4697-4d61-908f-5e9464d048d2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272615292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1272615292
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2535646067
Short name T509
Test name
Test status
Simulation time 702734697 ps
CPU time 21.85 seconds
Started Jul 30 07:32:54 PM PDT 24
Finished Jul 30 07:33:15 PM PDT 24
Peak memory 208760 kb
Host smart-a21fcd7e-9182-421d-82be-fa8fbeef9f28
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535646067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2535646067
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.4243911046
Short name T277
Test name
Test status
Simulation time 297487538 ps
CPU time 3.39 seconds
Started Jul 30 07:32:53 PM PDT 24
Finished Jul 30 07:32:57 PM PDT 24
Peak memory 208796 kb
Host smart-d7540208-850f-4c5d-a755-6181a78f04cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243911046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.4243911046
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3713432878
Short name T483
Test name
Test status
Simulation time 108826842 ps
CPU time 3.32 seconds
Started Jul 30 07:32:53 PM PDT 24
Finished Jul 30 07:32:56 PM PDT 24
Peak memory 206788 kb
Host smart-41508db5-9030-4479-84e6-4f98292b7c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713432878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3713432878
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.379838006
Short name T807
Test name
Test status
Simulation time 1176899194 ps
CPU time 21.43 seconds
Started Jul 30 07:32:57 PM PDT 24
Finished Jul 30 07:33:19 PM PDT 24
Peak memory 216368 kb
Host smart-b8c0680f-ce04-4a81-b817-0be750fff6c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379838006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.379838006
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.1486004859
Short name T133
Test name
Test status
Simulation time 1567549018 ps
CPU time 26.14 seconds
Started Jul 30 07:32:58 PM PDT 24
Finished Jul 30 07:33:24 PM PDT 24
Peak memory 222432 kb
Host smart-c4f50a8c-1829-4707-8fd5-41c64d179b29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486004859 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.1486004859
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.861023390
Short name T455
Test name
Test status
Simulation time 851008506 ps
CPU time 6.25 seconds
Started Jul 30 07:32:55 PM PDT 24
Finished Jul 30 07:33:01 PM PDT 24
Peak memory 218400 kb
Host smart-18320e4d-d362-47f6-8b16-d36d3902d18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861023390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.861023390
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.524369717
Short name T889
Test name
Test status
Simulation time 67355650 ps
CPU time 1.76 seconds
Started Jul 30 07:32:59 PM PDT 24
Finished Jul 30 07:33:00 PM PDT 24
Peak memory 208664 kb
Host smart-35137d24-ce74-4427-b98f-b3ca87ffd146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524369717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.524369717
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1667095501
Short name T899
Test name
Test status
Simulation time 53153023 ps
CPU time 0.79 seconds
Started Jul 30 07:33:09 PM PDT 24
Finished Jul 30 07:33:10 PM PDT 24
Peak memory 205856 kb
Host smart-9bd2a032-3838-4d17-8543-43756bc3a915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667095501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1667095501
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.2858105513
Short name T310
Test name
Test status
Simulation time 58439396 ps
CPU time 3.83 seconds
Started Jul 30 07:33:04 PM PDT 24
Finished Jul 30 07:33:08 PM PDT 24
Peak memory 214820 kb
Host smart-8395082d-cb95-4643-a24a-02d411d492a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2858105513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2858105513
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2479767920
Short name T586
Test name
Test status
Simulation time 182606105 ps
CPU time 4.19 seconds
Started Jul 30 07:33:00 PM PDT 24
Finished Jul 30 07:33:05 PM PDT 24
Peak memory 209864 kb
Host smart-0b08f188-4a0d-4a00-805f-385a642fdc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479767920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2479767920
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2110203327
Short name T759
Test name
Test status
Simulation time 163245210 ps
CPU time 5.9 seconds
Started Jul 30 07:33:02 PM PDT 24
Finished Jul 30 07:33:08 PM PDT 24
Peak memory 222440 kb
Host smart-9f5a4b1c-4102-4302-bc9c-338a164593a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110203327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2110203327
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1468879060
Short name T319
Test name
Test status
Simulation time 143631992 ps
CPU time 2.64 seconds
Started Jul 30 07:33:03 PM PDT 24
Finished Jul 30 07:33:05 PM PDT 24
Peak memory 214244 kb
Host smart-9f705ffc-9529-4a0c-97ec-ac92236613d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468879060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1468879060
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1526386897
Short name T545
Test name
Test status
Simulation time 144302680 ps
CPU time 4 seconds
Started Jul 30 07:33:01 PM PDT 24
Finished Jul 30 07:33:05 PM PDT 24
Peak memory 220088 kb
Host smart-685809a1-82b4-42e9-8e04-932fd2c3f212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526386897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1526386897
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.992829108
Short name T892
Test name
Test status
Simulation time 1132757848 ps
CPU time 4.98 seconds
Started Jul 30 07:32:57 PM PDT 24
Finished Jul 30 07:33:02 PM PDT 24
Peak memory 209384 kb
Host smart-55abf47a-a80b-48bc-acc5-fa3accac9f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992829108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.992829108
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1033912831
Short name T749
Test name
Test status
Simulation time 73761038 ps
CPU time 3.14 seconds
Started Jul 30 07:32:57 PM PDT 24
Finished Jul 30 07:33:00 PM PDT 24
Peak memory 208048 kb
Host smart-82e23d46-0472-4672-9a4d-b6731888eb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033912831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1033912831
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3361215357
Short name T757
Test name
Test status
Simulation time 212165824 ps
CPU time 3.54 seconds
Started Jul 30 07:32:58 PM PDT 24
Finished Jul 30 07:33:01 PM PDT 24
Peak memory 208796 kb
Host smart-f5b05622-4e15-4d8c-bb5d-9b1fb0d43b46
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361215357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3361215357
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1335475252
Short name T139
Test name
Test status
Simulation time 122666103 ps
CPU time 2.78 seconds
Started Jul 30 07:33:02 PM PDT 24
Finished Jul 30 07:33:05 PM PDT 24
Peak memory 206960 kb
Host smart-54206b5d-26c1-4e8e-b0a0-2a0d907ff9af
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335475252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1335475252
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3451071005
Short name T840
Test name
Test status
Simulation time 6451702442 ps
CPU time 51.84 seconds
Started Jul 30 07:33:00 PM PDT 24
Finished Jul 30 07:33:52 PM PDT 24
Peak memory 208528 kb
Host smart-4bbd3de8-4458-4227-82d5-cfbe411e1222
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451071005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3451071005
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3578932097
Short name T132
Test name
Test status
Simulation time 40359568 ps
CPU time 2.15 seconds
Started Jul 30 07:33:06 PM PDT 24
Finished Jul 30 07:33:08 PM PDT 24
Peak memory 218256 kb
Host smart-6d386e02-0dec-423f-bab5-81bb47f56885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578932097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3578932097
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2485025433
Short name T781
Test name
Test status
Simulation time 275246548 ps
CPU time 3.15 seconds
Started Jul 30 07:32:58 PM PDT 24
Finished Jul 30 07:33:01 PM PDT 24
Peak memory 208740 kb
Host smart-cde431bc-9a12-4332-8937-d9adc36e261c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485025433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2485025433
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.3722619750
Short name T253
Test name
Test status
Simulation time 5667228820 ps
CPU time 180.41 seconds
Started Jul 30 07:33:04 PM PDT 24
Finished Jul 30 07:36:05 PM PDT 24
Peak memory 222536 kb
Host smart-32412d62-ee9d-4cd1-ba2f-1ef22f96b35a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722619750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3722619750
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.3982665132
Short name T110
Test name
Test status
Simulation time 218874721 ps
CPU time 13.29 seconds
Started Jul 30 07:33:08 PM PDT 24
Finished Jul 30 07:33:22 PM PDT 24
Peak memory 222484 kb
Host smart-f6a592f7-deed-444b-82e4-ad302e0f86dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982665132 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.3982665132
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1424507490
Short name T541
Test name
Test status
Simulation time 260505655 ps
CPU time 6.26 seconds
Started Jul 30 07:33:01 PM PDT 24
Finished Jul 30 07:33:07 PM PDT 24
Peak memory 214296 kb
Host smart-232fde29-c2be-477d-9f11-e56121fabc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424507490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1424507490
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2062833122
Short name T559
Test name
Test status
Simulation time 87325257 ps
CPU time 2.01 seconds
Started Jul 30 07:33:05 PM PDT 24
Finished Jul 30 07:33:08 PM PDT 24
Peak memory 210532 kb
Host smart-475c4b97-4cc0-4b59-8cd4-519845a8404d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062833122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2062833122
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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