Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
74.60	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	15	34	69.39

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	14	21	60.00	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	36	1			T45	1		T26	1		T27	1
auto[OpGenId]	14	1			T57	1		T60	1		T59	1
auto[OpGenSwOut]	19	1			T25	2		T36	1		T53	1
auto[OpGenHwOut]	21	1			T5	1		T6	1		T7	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1667	1			T25	4		T8	90		T106	3
auto[StInit]	80	1			T45	1		T26	1		T53	1
auto[StCreatorRootKey]	62	1			T1	1		T36	1		T57	1
auto[StOwnerIntKey]	46	1			T48	1		T4	1		T109	1
auto[StOwnerKey]	38	1			T25	2		T55	1		T43	1
auto[StDisabled]	433	1			T3	1		T15	1		T25	11
auto[StInvalid]	49	1			T50	1		T54	1		T208	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3375

1

T1

2

T2

1

T3

2

auto[1]

90

1

T45

1

T25

2

T26

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1661	1			T25	4		T8	90		T106	3
auto[StReset]	auto[1]	6	1			T52	1		T19	1		T209	1
auto[StInit]	auto[0]	40	1			T55	4		T37	1		T109	1
auto[StInit]	auto[1]	40	1			T45	1		T26	1		T53	1
auto[StCreatorRootKey]	auto[0]	45	1			T1	1		T39	1		T109	1
auto[StCreatorRootKey]	auto[1]	17	1			T36	1		T57	1		T59	1
auto[StOwnerIntKey]	auto[0]	34	1			T48	1		T109	1		T62	1
auto[StOwnerIntKey]	auto[1]	12	1			T4	1		T60	1		T148	1
auto[StOwnerKey]	auto[0]	30	1			T55	1		T43	1		T65	1
auto[StOwnerKey]	auto[1]	8	1			T25	2		T5	1		T186	1
auto[StDisabled]	auto[0]	426	1			T3	1		T15	1		T25	11
auto[StDisabled]	auto[1]	7	1			T210	1		T211	3		T212	1
auto[StInvalid]	auto[0]	49	1			T50	1		T54	1		T208	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	14	21	60.00	14

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId]]	0	1	1
[auto[StReset]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[StDisabled]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	4	1			T52	1		T19	1		T209	1
auto[StReset]	auto[OpGenSwOut]	2	1			T213	1		T214	1		-	-
auto[StInit]	auto[OpAdvance]	17	1			T45	1		T26	1		T27	1
auto[StInit]	auto[OpGenId]	5	1			T59	1		T147	1		T215	2
auto[StInit]	auto[OpGenSwOut]	8	1			T53	1		T163	1		T216	1
auto[StInit]	auto[OpGenHwOut]	10	1			T6	1		T7	1		T42	1
auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T124	1		T217	1		T218	1
auto[StCreatorRootKey]	auto[OpGenId]	3	1			T57	1		T219	1		T184	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	2	1			T36	1		T220	1		-	-
auto[StCreatorRootKey]	auto[OpGenHwOut]	6	1			T59	1		T221	1		T222	1
auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T223	1		T224	1		T225	1
auto[StOwnerIntKey]	auto[OpGenId]	2	1			T60	1		T215	1		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T4	1		T226	1		T227	1
auto[StOwnerIntKey]	auto[OpGenHwOut]	3	1			T148	1		T47	1		T228	1
auto[StOwnerKey]	auto[OpAdvance]	3	1			T186	1		T229	1		T230	1
auto[StOwnerKey]	auto[OpGenId]	1	1			T231	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T25	2		-	-		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	2	1			T5	1		T150	1		-	-
auto[StDisabled]	auto[OpAdvance]	2	1			T210	1		T211	1		-	-
auto[StDisabled]	auto[OpGenId]	3	1			T212	1		T232	1		T233	1
auto[StDisabled]	auto[OpGenSwOut]	2	1			T211	2		-	-		-	-