Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	73	257	77.88

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	54	226	80.71	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4672

1

T2

1

T3

4

T11

6

auto[1]

585

1

T2

3

T15

1

T16

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4672

1

T2

1

T3

4

T11

6

auto[1]

585

1

T2

3

T15

1

T16

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4614

1

T2

4

T3

1

T11

6

auto[1]

643

1

T3

3

T14

5

T25

4

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4614

1

T2

4

T3

1

T11

6

auto[1]

643

1

T3

3

T14

5

T25

4

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	405	1			T2	2		T11	2		T12	2
auto[OpGenId]	1130	1			T3	1		T11	1		T17	2
auto[OpGenSwOut]	1152	1			T3	2		T11	1		T12	7
auto[OpGenHwOut]	2521	1			T2	2		T3	1		T11	2
auto[OpDisable]	49	1			T25	1		T48	1		T49	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	405	1			T2	2		T11	2		T12	2
auto[OpGenId]	1130	1			T3	1		T11	1		T17	2
auto[OpGenSwOut]	1152	1			T3	2		T11	1		T12	7
auto[OpGenHwOut]	2521	1			T2	2		T3	1		T11	2
auto[OpDisable]	49	1			T25	1		T48	1		T49	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4732

1

T2

4

T3

4

T11

6

auto[1]

525

1

T12

4

T16

1

T25

5

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4732

1

T2

4

T3

4

T11

6

auto[1]

525

1

T12

4

T16

1

T25

5

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4942

1

T2

4

T3

4

T11

5

auto[1]

315

1

T11

1

T12

8

T108

3

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1809	1			T2	3		T3	1		T11	4
auto[1]	683	1			T2	1		T3	1		T12	5
auto[2]	662	1			T12	4		T25	6		T48	4
auto[3]	731	1			T3	1		T12	1		T14	2
auto[4]	318	1			T3	1		T14	1		T35	1
auto[5]	343	1			T11	1		T35	2		T25	1
auto[6]	348	1			T14	1		T35	2		T25	5
auto[7]	363	1			T11	1		T12	3		T17	2

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1372	1			T3	1		T11	2		T12	3
clear_one[1]	683	1			T2	1		T3	1		T12	5
clear_one[2]	662	1			T12	4		T25	6		T48	4
clear_one[3]	731	1			T3	1		T12	1		T14	2
clear_none	1809	1			T2	3		T3	1		T11	4

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	899	1			T11	2		T12	2		T35	3
auto[StInit]	655	1			T11	1		T14	1		T15	1
auto[StCreatorRootKey]	580	1			T12	3		T14	1		T17	1
auto[StOwnerIntKey]	535	1			T2	1		T12	1		T14	1
auto[StOwnerKey]	502	1			T2	1		T12	3		T14	1
auto[StDisabled]	1818	1			T2	2		T3	4		T11	3
auto[StInvalid]	268	1			T38	4		T50	4		T54	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	899	1			T11	2		T12	2		T35	3
auto[StInit]	655	1			T11	1		T14	1		T15	1
auto[StCreatorRootKey]	580	1			T12	3		T14	1		T17	1
auto[StOwnerIntKey]	535	1			T2	1		T12	1		T14	1
auto[StOwnerKey]	502	1			T2	1		T12	3		T14	1
auto[StDisabled]	1818	1			T2	2		T3	4		T11	3
auto[StInvalid]	268	1			T38	4		T50	4		T54	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[2]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[3] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	5
[auto[3] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	5
[auto[3] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	20
[auto[3] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	5

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	2	1			T137	1		T234	1		-	-
auto[0]	auto[StReset]	auto[OpGenId]	156	1			T25	2		T49	1		T72	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	140	1			T12	1		T25	3		T48	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	240	1			T11	2		T35	1		T25	2
auto[0]	auto[StInit]	auto[OpAdvance]	35	1			T15	1		T23	2		T55	1
auto[0]	auto[StInit]	auto[OpGenId]	88	1			T11	1		T17	1		T45	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	89	1			T25	1		T36	1		T108	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	204	1			T14	1		T25	1		T85	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	27	1			T25	1		T132	1		T200	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	53	1			T25	1		T106	2		T55	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	54	1			T201	1		T18	1		T68	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	81	1			T48	1		T126	1		T235	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	12	1			T2	1		T61	1		T236	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	27	1			T83	1		T139	2		T237	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	32	1			T67	1		T139	1		T234	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	50	1			T25	1		T85	1		T55	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T136	1		T238	1		T239	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	19	1			T61	1		T236	1		T240	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	25	1			T16	1		T109	1		T68	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	47	1			T2	1		T15	1		T200	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	31	1			T25	2		T138	3		T68	1
auto[0]	auto[StDisabled]	auto[OpGenId]	63	1			T25	2		T106	1		T241	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	77	1			T3	1		T11	1		T136	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	158	1			T2	1		T14	1		T85	1
auto[0]	auto[StDisabled]	auto[OpDisable]	17	1			T25	1		T48	1		T49	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	13	1			T38	1		T54	1		T87	1
auto[0]	auto[StInvalid]	auto[OpGenId]	24	1			T50	2		T51	1		T242	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	24	1			T243	2		T87	2		T244	2
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	17	1			T245	1		T246	2		T247	1
auto[1]	auto[StReset]	auto[OpGenId]	22	1			T55	2		T248	1		T249	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	15	1			T129	1		T61	1		T46	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	40	1			T12	1		T131	3		T46	1
auto[1]	auto[StInit]	auto[OpAdvance]	4	1			T250	1		T251	1		T230	1
auto[1]	auto[StInit]	auto[OpGenId]	6	1			T25	1		T22	1		T91	2
auto[1]	auto[StInit]	auto[OpGenSwOut]	11	1			T106	1		T68	1		T252	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	29	1			T35	1		T22	1		T23	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T17	1		T25	1		T58	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T241	1		T120	1		T59	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T25	1		T48	1		T98	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	38	1			T14	1		T207	1		T206	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	13	1			T12	1		T55	1		T239	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	20	1			T241	1		T138	1		T121	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T136	1		T132	1		T201	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	41	1			T136	1		T130	1		T253	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T254	1		T255	1		T256	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	11	1			T257	1		T258	1		T228	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T259	1		T68	1		T260	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	48	1			T12	3		T35	1		T85	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	24	1			T2	1		T95	1		T68	1
auto[1]	auto[StDisabled]	auto[OpGenId]	50	1			T108	1		T106	1		T109	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	48	1			T3	1		T25	1		T48	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	163	1			T14	1		T106	1		T129	1
auto[1]	auto[StDisabled]	auto[OpDisable]	7	1			T261	1		T46	1		T262	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	5	1			T263	1		T264	1		T265	1
auto[1]	auto[StInvalid]	auto[OpGenId]	11	1			T208	1		T247	1		T266	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T245	1		T266	1		T267	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T50	1		T54	1		T243	1
auto[2]	auto[StReset]	auto[OpAdvance]	3	1			T254	1		T268	1		T269	1
auto[2]	auto[StReset]	auto[OpGenId]	11	1			T48	1		T46	1		T74	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	13	1			T129	1		T208	1		T68	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	41	1			T131	1		T270	1		T208	1
auto[2]	auto[StInit]	auto[OpAdvance]	3	1			T271	1		T272	1		T273	1
auto[2]	auto[StInit]	auto[OpGenId]	12	1			T48	1		T23	1		T68	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	11	1			T24	1		T61	1		T254	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	17	1			T274	1		T66	1		T275	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T276	1		T277	2		T273	2
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T278	1		T138	1		T59	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T25	1		T55	1		T138	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	24	1			T25	1		T278	3		T279	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T69	1		T280	1		T281	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T48	1		T106	1		T68	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T25	1		T277	1		T226	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	42	1			T282	1		T206	1		T68	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T106	1		T283	1		T284	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	23	1			T285	1		T59	1		T286	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	23	1			T25	1		T130	1		T68	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	42	1			T235	1		T66	1		T270	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	17	1			T25	1		T130	1		T101	1
auto[2]	auto[StDisabled]	auto[OpGenId]	49	1			T106	1		T55	1		T278	3
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	56	1			T12	3		T25	1		T48	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	152	1			T12	1		T130	1		T131	1
auto[2]	auto[StDisabled]	auto[OpDisable]	8	1			T56	1		T128	1		T59	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	7	1			T287	1		T90	1		T288	2
auto[2]	auto[StInvalid]	auto[OpGenId]	14	1			T51	1		T244	2		T289	2
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T38	1		T287	1		T90	2
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T290	2		T266	1		T288	1
auto[3]	auto[StReset]	auto[OpGenId]	15	1			T47	1		T89	1		T291	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	18	1			T25	1		T55	1		T95	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	41	1			T84	1		T199	1		T198	1
auto[3]	auto[StInit]	auto[OpAdvance]	7	1			T23	1		T199	1		T277	1
auto[3]	auto[StInit]	auto[OpGenId]	9	1			T292	1		T293	1		T229	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	10	1			T55	1		T252	1		T294	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	22	1			T189	1		T239	1		T217	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T190	1		T295	1		T228	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T277	2		T296	1		T102	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T128	1		T199	1		T277	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	36	1			T85	1		T253	1		T95	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T61	1		T297	1		T298	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	22	1			T278	2		T46	1		T59	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	21	1			T202	1		T68	1		T240	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	45	1			T14	1		T131	1		T274	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T236	2		T297	2		T296	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	17	1			T299	1		T59	1		T34	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T67	1		T299	1		T297	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	51	1			T14	1		T25	2		T106	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	27	1			T12	1		T55	1		T126	1
auto[3]	auto[StDisabled]	auto[OpGenId]	68	1			T3	1		T17	1		T106	2
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	69	1			T48	1		T83	1		T55	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	152	1			T35	3		T83	1		T55	1
auto[3]	auto[StDisabled]	auto[OpDisable]	6	1			T68	1		T300	1		T74	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	3	1			T51	1		T301	1		T302	1
auto[3]	auto[StInvalid]	auto[OpGenId]	12	1			T208	1		T86	1		T242	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T54	1		T243	1		T87	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T54	1		T303	1		T289	1
auto[4]	auto[StReset]	auto[OpGenId]	6	1			T292	1		T88	1		T304	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	4	1			T61	1		T305	1		T306	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	15	1			T35	1		T84	1		T124	1
auto[4]	auto[StInit]	auto[OpAdvance]	3	1			T307	1		T228	1		T281	1
auto[4]	auto[StInit]	auto[OpGenId]	4	1			T297	1		T308	1		T309	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	9	1			T130	2		T46	1		T310	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	16	1			T22	1		T130	1		T92	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T137	1		T256	1		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T202	1		T74	1		T311	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T136	1		T299	1		T312	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	25	1			T84	1		T274	1		T313	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T106	1		T297	1		T314	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T126	1		T315	1		T316	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T25	1		T317	1		T65	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	8	1			T318	1		T319	1		T320	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T234	1		T283	1		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	5	1			T55	1		T321	1		T322	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T25	1		T205	1		T46	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T25	1		T323	1		T324	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	9	1			T55	1		T325	1		T296	1
auto[4]	auto[StDisabled]	auto[OpGenId]	27	1			T25	1		T299	1		T59	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	23	1			T25	3		T48	1		T137	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	76	1			T3	1		T14	1		T85	1
auto[4]	auto[StDisabled]	auto[OpDisable]	3	1			T252	1		T326	1		T327	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	4	1			T86	1		T246	1		T328	1
auto[4]	auto[StInvalid]	auto[OpGenId]	2	1			T38	1		T329	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T287	1		T330	1		T290	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T289	1		T247	1		T331	1
auto[5]	auto[StReset]	auto[OpGenId]	7	1			T25	1		T276	1		T268	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	11	1			T120	1		T61	1		T332	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	16	1			T35	1		T333	1		T334	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T254	1		T335	1		-	-
auto[5]	auto[StInit]	auto[OpGenId]	6	1			T103	1		T124	1		T239	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	7	1			T336	1		T337	1		T88	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	6	1			T338	1		T339	1		T340	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T5	1		T341	1		T229	2
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T342	1		T343	1		T283	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T254	1		T344	1		T345	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	28	1			T35	1		T68	1		T318	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T308	1		T346	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T68	1		T347	1		T348	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T254	1		T74	1		T239	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T84	1		T270	1		T68	2
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T137	1		T232	1		T349	3
auto[5]	auto[StOwnerKey]	auto[OpGenId]	5	1			T201	1		T350	1		T252	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T254	1		T226	1		T306	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	15	1			T84	1		T131	1		T351	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	18	1			T11	1		T278	1		T68	1
auto[5]	auto[StDisabled]	auto[OpGenId]	26	1			T106	1		T129	1		T120	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	27	1			T55	1		T68	1		T352	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	71	1			T85	1		T84	1		T131	1
auto[5]	auto[StDisabled]	auto[OpDisable]	3	1			T353	1		T354	1		T355	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	2	1			T356	1		T357	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	4	1			T242	1		T358	1		T359	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T89	1		T356	1		T360	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T287	1		T356	1		T361	1
auto[6]	auto[StReset]	auto[OpGenId]	15	1			T48	1		T22	1		T120	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	11	1			T25	1		T38	1		T61	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	23	1			T22	1		T259	1		T252	1
auto[6]	auto[StInit]	auto[OpAdvance]	3	1			T25	1		T212	1		T362	1
auto[6]	auto[StInit]	auto[OpGenId]	4	1			T72	1		T129	1		T363	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	2	1			T128	1		T364	1		-	-
auto[6]	auto[StInit]	auto[OpGenHwOut]	11	1			T25	1		T270	1		T333	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T365	1		T366	1		T367	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T106	1		T68	1		T337	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T68	2		T368	1		T104	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	26	1			T131	1		T369	1		T351	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T299	2		T239	1		T370	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T249	1		T371	1		T372	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T299	1		T74	1		T337	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	17	1			T35	1		T235	1		T207	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T272	1		T373	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	12	1			T374	1		T239	1		T375	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T83	1		T61	1		T376	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T63	1		T337	1		T377	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	8	1			T25	1		T315	1		T378	1
auto[6]	auto[StDisabled]	auto[OpGenId]	30	1			T136	2		T106	1		T199	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	23	1			T25	1		T48	1		T106	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	68	1			T14	1		T35	1		T85	1
auto[6]	auto[StDisabled]	auto[OpDisable]	2	1			T74	2		-	-		-	-
auto[6]	auto[StInvalid]	auto[OpAdvance]	3	1			T330	1		T379	1		T380	1
auto[6]	auto[StInvalid]	auto[OpGenId]	8	1			T243	1		T89	1		T381	3
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T86	1		T382	1		T383	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T384	1		T379	1		-	-
auto[7]	auto[StReset]	auto[OpGenId]	11	1			T75	1		T342	1		T211	2
auto[7]	auto[StReset]	auto[OpGenSwOut]	5	1			T25	1		T120	1		T264	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	18	1			T25	1		T86	1		T334	1
auto[7]	auto[StInit]	auto[OpAdvance]	3	1			T108	1		T212	1		T385	1
auto[7]	auto[StInit]	auto[OpGenId]	4	1			T22	1		T61	1		T386	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	6	1			T68	1		T91	1		T307	2
auto[7]	auto[StInit]	auto[OpGenHwOut]	12	1			T22	1		T84	1		T387	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T67	1		T198	1		T252	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T25	1		T305	3		T224	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T12	3		T48	1		T83	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T282	1		T388	1		T299	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T108	1		T139	1		T378	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T389	1		T226	1		T390	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T17	1		T106	1		T61	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T108	1		T63	1		T334	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T106	1		T234	1		T391	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	2	1			T217	1		T392	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T139	2		T393	1		T74	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T139	1		T313	1		T315	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	10	1			T11	1		T25	1		T74	1
auto[7]	auto[StDisabled]	auto[OpGenId]	31	1			T108	1		T137	1		T59	2
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	35	1			T83	1		T106	1		T199	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	83	1			T17	1		T109	1		T282	2
auto[7]	auto[StDisabled]	auto[OpDisable]	3	1			T68	1		T348	1		T394	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	3	1			T50	1		T208	1		T395	1
auto[7]	auto[StInvalid]	auto[OpGenId]	10	1			T38	1		T51	1		T86	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T303	1		T87	1		T244	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T289	1		T247	1		T382	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1372

1

T3

1

T11

2

T12

3

clear_one[1]

auto[0]

auto[0]

auto[0]

373

1

T2

1

T12

4

T17

1

clear_one[1]

auto[0]

auto[0]

auto[1]

125

1

T12

1

T85

1

T131

1

clear_one[1]

auto[0]

auto[1]

auto[0]

139

1

T3

1

T14

2

T25

1

clear_one[1]

auto[0]

auto[1]

auto[1]

46

1

T129

1

T201

1

T317

1

clear_one[2]

auto[0]

auto[0]

auto[0]

391

1

T12

1

T25

3

T48

3

clear_one[2]

auto[0]

auto[0]

auto[1]

118

1

T12

3

T25

1

T48

1

clear_one[2]

auto[1]

auto[0]

auto[0]

125

1

T130

3

T235

1

T198

1

clear_one[2]

auto[1]

auto[0]

auto[1]

28

1

T25

2

T146

1

T285

1

clear_one[3]

auto[0]

auto[0]

auto[0]

398

1

T12

1

T17

1

T25

2

clear_one[3]

auto[0]

auto[1]

auto[0]

139

1

T3

1

T14

2

T25

1

clear_one[3]

auto[1]

auto[0]

auto[0]

129

1

T35

3

T83

1

T106

1

clear_one[3]

auto[1]

auto[1]

auto[0]

65

1

T55

1

T126

1

T132

1

clear_none

auto[0]

auto[0]

auto[0]

1271

1

T11

4

T12

1

T14

1

clear_none

auto[0]

auto[0]

auto[1]

122

1

T25

2

T85

2

T48

1

clear_none

auto[0]

auto[1]

auto[0]

141

1

T3

1

T14

1

T25

1

clear_none

auto[0]

auto[1]

auto[1]

37

1

T55

1

T129

1

T68

1

clear_none

auto[1]

auto[0]

auto[0]

129

1

T2

3

T15

1

T84

2

clear_none

auto[1]

auto[0]

auto[1]

33

1

T16

1

T278

3

T139

1

clear_none

auto[1]

auto[1]

auto[0]

60

1

T25

1

T205

1

T61

1

clear_none

auto[1]

auto[1]

auto[1]

16

1

T106

1

T59

1

T277

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1293	1			T3	1		T11	1		T12	1
clear_all	auto[1]	79	1			T11	1		T12	2		T108	2
clear_one[1]	auto[0]	645	1			T2	1		T3	1		T12	2
clear_one[1]	auto[1]	38	1			T12	3		T108	1		T136	1
clear_one[2]	auto[0]	616	1			T12	1		T25	6		T48	4
clear_one[2]	auto[1]	46	1			T12	3		T278	5		T138	1
clear_one[3]	auto[0]	661	1			T3	1		T12	1		T14	2
clear_one[3]	auto[1]	70	1			T278	3		T138	6		T139	7
clear_none	auto[0]	1727	1			T2	3		T3	1		T11	4
clear_none	auto[1]	82	1			T136	3		T137	1		T278	2