Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10800

1

T1

9

T2

9

T3

18

auto[Attestation]

7527

1

T1

2

T2

8

T3

9

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2631	1			T2	2		T3	3		T11	2
auto[Aes]	3270	1			T1	2		T2	8		T3	3
auto[Kmac]	3302	1			T1	3		T2	3		T3	6
auto[Otbn]	3374	1			T1	3		T3	5		T11	3

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7584	1			T1	2		T2	8		T3	16
auto[OpGenId]	5750	1			T1	3		T2	4		T3	10
auto[OpGenSwOut]	5741	1			T1	5		T2	7		T3	13
auto[OpGenHwOut]	6836	1			T1	3		T2	6		T3	4
auto[OpDisable]	122	1			T25	2		T48	1		T49	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10532

1

T1

6

T2

7

T3

16

auto[OpDoneFail]

15501

1

T1

7

T2

18

T3

27

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6037	1			T1	4		T2	1		T3	13
auto[StInit]	3827	1			T1	5		T2	1		T3	4
auto[StCreatorRootKey]	3160	1			T1	4		T2	3		T3	4
auto[StOwnerIntKey]	2722	1			T2	1		T3	4		T11	4
auto[StOwnerKey]	2506	1			T2	3		T3	4		T11	2
auto[StDisabled]	7781	1			T2	16		T3	14		T11	10

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	313	1			T3	1		T11	1		T12	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	84	1			T25	3		T23	1		T106	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	76	1			T25	1		T128	1		T61	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	74	1			T25	2		T48	1		T136	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	64	1			T25	2		T130	1		T63	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	202	1			T3	1		T12	2		T25	6
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	289	1			T1	1		T3	2		T11	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	86	1			T25	2		T23	1		T196	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	88	1			T2	1		T48	2		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	60	1			T11	1		T15	1		T25	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	73	1			T15	1		T106	1		T126	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	215	1			T2	1		T3	1		T11	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	308	1			T3	2		T11	1		T12	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	89	1			T1	2		T11	1		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	83	1			T11	1		T25	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	78	1			T17	1		T25	2		T108	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	53	1			T17	1		T25	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	203	1			T2	3		T11	2		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	343	1			T3	3		T12	1		T25	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	96	1			T1	1		T25	2		T108	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	84	1			T25	1		T108	1		T136	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	80	1			T11	1		T25	2		T67	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	64	1			T3	1		T25	1		T106	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	205	1			T25	3		T48	1		T83	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	68	1			T25	2		T55	1		T109	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	81	1			T16	1		T45	1		T25	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	89	1			T25	3		T106	1		T197	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	74	1			T25	2		T106	1		T55	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	63	1			T25	2		T48	1		T106	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	221	1			T3	1		T12	1		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	61	1			T55	1		T120	3		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	101	1			T11	1		T25	2		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	87	1			T1	1		T12	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	61	1			T15	1		T17	1		T55	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	72	1			T2	1		T15	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	207	1			T2	1		T25	9		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	46	1			T25	4		T120	1		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	126	1			T26	1		T36	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	77	1			T25	1		T48	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	68	1			T25	1		T109	1		T198	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	66	1			T11	1		T67	1		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	227	1			T12	1		T25	2		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	66	1			T25	3		T55	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	116	1			T106	1		T55	1		T126	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	88	1			T12	1		T25	2		T55	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	61	1			T200	1		T201	1		T202	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	68	1			T55	1		T126	1		T203	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	237	1			T3	1		T25	5		T48	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	286	1			T11	1		T12	1		T25	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	90	1			T25	2		T22	2		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	55	1			T95	1		T5	1		T61	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	47	1			T15	1		T25	1		T55	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	61	1			T25	1		T55	4		T61	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	176	1			T2	1		T17	1		T25	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	417	1			T11	1		T12	1		T35	10
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	124	1			T35	1		T25	1		T22	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	101	1			T204	1		T205	1		T206	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	107	1			T16	1		T25	2		T108	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	91	1			T2	1		T16	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	293	1			T2	1		T35	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	429	1			T1	1		T11	4		T12	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	125	1			T25	3		T49	1		T22	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	120	1			T25	2		T106	1		T128	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	97	1			T14	1		T25	1		T106	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	79	1			T3	1		T25	2		T207	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	268	1			T11	2		T14	2		T25	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	459	1			T11	2		T25	3		T48	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	123	1			T1	1		T85	1		T22	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	105	1			T1	1		T16	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	95	1			T25	1		T48	1		T131	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	88	1			T16	2		T17	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	279	1			T17	1		T25	3		T85	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	44	1			T25	2		T55	1		T120	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	105	1			T49	1		T56	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	67	1			T25	2		T36	1		T126	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	58	1			T16	1		T25	1		T106	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	54	1			T132	1		T200	1		T138	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	179	1			T2	1		T25	4		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	44	1			T25	2		T55	1		T120	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	118	1			T17	1		T25	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	110	1			T2	1		T35	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	101	1			T35	1		T25	2		T136	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	99	1			T15	1		T25	1		T55	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	265	1			T2	1		T35	3		T25	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	36	1			T25	2		T55	1		T120	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	136	1			T14	1		T25	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	121	1			T3	1		T14	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	83	1			T3	1		T17	1		T106	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	101	1			T14	1		T25	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	283	1			T3	1		T14	2		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	39	1			T25	1		T120	1		T61	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	127	1			T25	1		T48	1		T108	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	113	1			T85	1		T55	1		T63	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	96	1			T85	1		T48	2		T55	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	95	1			T12	1		T16	2		T85	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	247	1			T12	1		T25	1		T85	3

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	198	1			T25	4		T48	1		T136	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	615	1			T3	2		T11	1		T12	5
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	201	1			T11	1		T15	2		T25	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	610	1			T1	1		T2	2		T3	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	205	1			T11	1		T17	2		T25	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	609	1			T1	2		T2	3		T3	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	214	1			T3	1		T11	1		T25	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	658	1			T1	1		T3	3		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	206	1			T25	7		T106	4		T55	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	390	1			T3	1		T12	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	199	1			T1	1		T2	1		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	390	1			T2	1		T11	1		T25	11
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	189	1			T11	1		T25	2		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	421	1			T12	1		T25	6		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	198	1			T12	1		T25	2		T55	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	438	1			T3	1		T25	8		T48	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	144	1			T15	1		T25	2		T55	5
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	571	1			T2	1		T11	1		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	280	1			T16	2		T35	1		T25	4
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	853	1			T2	2		T11	1		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	280	1			T3	1		T14	1		T25	4
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	838	1			T1	1		T11	6		T12	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	274	1			T1	1		T16	3		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	875	1			T1	1		T11	2		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	165	1			T16	1		T25	3		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	342	1			T2	1		T25	6		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	293	1			T2	1		T15	1		T35	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	444	1			T2	1		T17	1		T35	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	290	1			T3	2		T14	2		T25	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	470	1			T3	1		T14	3		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	282	1			T12	1		T16	2		T85	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	435	1			T12	1		T25	3		T85	3