Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31931

1

T1

15

T2

30

T3

49

auto[1]

366

1

T11

2

T12

7

T108

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31940	1			T1	15		T2	30		T3	49
auto[134217728:268435455]	13	1			T108	1		T132	1		T138	1
auto[268435456:402653183]	11	1			T139	1		T190	1		T404	1
auto[402653184:536870911]	6	1			T139	1		T391	1		T268	1
auto[536870912:671088639]	18	1			T12	2		T138	1		T254	3
auto[671088640:805306367]	15	1			T12	2		T130	1		T278	1
auto[805306368:939524095]	11	1			T108	1		T139	1		T277	1
auto[939524096:1073741823]	14	1			T236	1		T254	1		T297	1
auto[1073741824:1207959551]	12	1			T12	1		T139	1		T277	1
auto[1207959552:1342177279]	12	1			T236	1		T190	1		T284	1
auto[1342177280:1476395007]	15	1			T278	1		T139	1		T234	1
auto[1476395008:1610612735]	11	1			T278	2		T254	1		T391	1
auto[1610612736:1744830463]	4	1			T403	1		T370	1		T417	1
auto[1744830464:1879048191]	19	1			T136	1		T278	1		T138	1
auto[1879048192:2013265919]	11	1			T138	1		T139	2		T315	1
auto[2013265920:2147483647]	10	1			T11	1		T278	1		T254	2
auto[2147483648:2281701375]	13	1			T278	1		T139	1		T236	1
auto[2281701376:2415919103]	10	1			T278	1		T234	1		T277	1
auto[2415919104:2550136831]	12	1			T108	1		T132	1		T138	1
auto[2550136832:2684354559]	8	1			T136	1		T297	1		T391	1
auto[2684354560:2818572287]	14	1			T11	1		T132	1		T139	1
auto[2818572288:2952790015]	17	1			T108	1		T136	1		T139	2
auto[2952790016:3087007743]	10	1			T254	1		T277	1		T404	1
auto[3087007744:3221225471]	11	1			T12	1		T278	2		T254	1
auto[3221225472:3355443199]	11	1			T278	1		T139	1		T190	1
auto[3355443200:3489660927]	6	1			T130	1		T278	1		T139	1
auto[3489660928:3623878655]	16	1			T136	1		T278	2		T234	1
auto[3623878656:3758096383]	10	1			T12	1		T138	1		T234	1
auto[3758096384:3892314111]	11	1			T138	1		T391	1		T418	2
auto[3892314112:4026531839]	7	1			T130	1		T138	1		T234	1
auto[4026531840:4160749567]	15	1			T139	1		T254	1		T277	1
auto[4160749568:4294967295]	4	1			T254	1		T391	1		T418	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31931	1			T1	15		T2	30		T3	49
auto[0:134217727]	auto[1]	9	1			T136	1		T278	1		T277	1
auto[134217728:268435455]	auto[1]	13	1			T108	1		T132	1		T138	1
auto[268435456:402653183]	auto[1]	11	1			T139	1		T190	1		T404	1
auto[402653184:536870911]	auto[1]	6	1			T139	1		T391	1		T268	1
auto[536870912:671088639]	auto[1]	18	1			T12	2		T138	1		T254	3
auto[671088640:805306367]	auto[1]	15	1			T12	2		T130	1		T278	1
auto[805306368:939524095]	auto[1]	11	1			T108	1		T139	1		T277	1
auto[939524096:1073741823]	auto[1]	14	1			T236	1		T254	1		T297	1
auto[1073741824:1207959551]	auto[1]	12	1			T12	1		T139	1		T277	1
auto[1207959552:1342177279]	auto[1]	12	1			T236	1		T190	1		T284	1
auto[1342177280:1476395007]	auto[1]	15	1			T278	1		T139	1		T234	1
auto[1476395008:1610612735]	auto[1]	11	1			T278	2		T254	1		T391	1
auto[1610612736:1744830463]	auto[1]	4	1			T403	1		T370	1		T417	1
auto[1744830464:1879048191]	auto[1]	19	1			T136	1		T278	1		T138	1
auto[1879048192:2013265919]	auto[1]	11	1			T138	1		T139	2		T315	1
auto[2013265920:2147483647]	auto[1]	10	1			T11	1		T278	1		T254	2
auto[2147483648:2281701375]	auto[1]	13	1			T278	1		T139	1		T236	1
auto[2281701376:2415919103]	auto[1]	10	1			T278	1		T234	1		T277	1
auto[2415919104:2550136831]	auto[1]	12	1			T108	1		T132	1		T138	1
auto[2550136832:2684354559]	auto[1]	8	1			T136	1		T297	1		T391	1
auto[2684354560:2818572287]	auto[1]	14	1			T11	1		T132	1		T139	1
auto[2818572288:2952790015]	auto[1]	17	1			T108	1		T136	1		T139	2
auto[2952790016:3087007743]	auto[1]	10	1			T254	1		T277	1		T404	1
auto[3087007744:3221225471]	auto[1]	11	1			T12	1		T278	2		T254	1
auto[3221225472:3355443199]	auto[1]	11	1			T278	1		T139	1		T190	1
auto[3355443200:3489660927]	auto[1]	6	1			T130	1		T278	1		T139	1
auto[3489660928:3623878655]	auto[1]	16	1			T136	1		T278	2		T234	1
auto[3623878656:3758096383]	auto[1]	10	1			T12	1		T138	1		T234	1
auto[3758096384:3892314111]	auto[1]	11	1			T138	1		T391	1		T418	2
auto[3892314112:4026531839]	auto[1]	7	1			T130	1		T138	1		T234	1
auto[4026531840:4160749567]	auto[1]	15	1			T139	1		T254	1		T277	1
auto[4160749568:4294967295]	auto[1]	4	1			T254	1		T391	1		T418	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1568

1

T2

3

T11

3

T12

3

auto[1]

1716

1

T2

3

T11

4

T12

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	96	1			T25	2		T48	1		T108	1
auto[134217728:268435455]	114	1			T2	1		T25	5		T4	1
auto[268435456:402653183]	124	1			T2	1		T15	1		T25	2
auto[402653184:536870911]	102	1			T12	1		T25	3		T48	1
auto[536870912:671088639]	105	1			T17	1		T45	1		T53	1
auto[671088640:805306367]	114	1			T25	2		T22	1		T106	1
auto[805306368:939524095]	104	1			T15	1		T16	1		T25	4
auto[939524096:1073741823]	93	1			T15	1		T25	1		T48	1
auto[1073741824:1207959551]	114	1			T2	1		T11	2		T25	1
auto[1207959552:1342177279]	86	1			T12	1		T25	4		T48	1
auto[1342177280:1476395007]	104	1			T2	1		T12	2		T25	4
auto[1476395008:1610612735]	87	1			T25	1		T136	1		T22	2
auto[1610612736:1744830463]	89	1			T11	2		T15	1		T48	2
auto[1744830464:1879048191]	110	1			T45	1		T106	1		T55	2
auto[1879048192:2013265919]	95	1			T25	1		T48	1		T106	1
auto[2013265920:2147483647]	120	1			T25	3		T48	1		T53	1
auto[2147483648:2281701375]	108	1			T25	2		T136	1		T106	1
auto[2281701376:2415919103]	96	1			T2	1		T25	3		T48	1
auto[2415919104:2550136831]	97	1			T55	1		T126	1		T129	1
auto[2550136832:2684354559]	97	1			T2	1		T17	1		T25	1
auto[2684354560:2818572287]	114	1			T15	1		T25	2		T48	1
auto[2818572288:2952790015]	106	1			T25	5		T48	2		T22	1
auto[2952790016:3087007743]	103	1			T45	1		T25	2		T22	1
auto[3087007744:3221225471]	103	1			T12	1		T16	1		T25	1
auto[3221225472:3355443199]	93	1			T12	1		T25	2		T108	1
auto[3355443200:3489660927]	112	1			T11	1		T15	1		T25	1
auto[3489660928:3623878655]	107	1			T45	2		T25	3		T136	1
auto[3623878656:3758096383]	109	1			T11	1		T25	3		T48	1
auto[3758096384:3892314111]	94	1			T55	1		T128	1		T60	1
auto[3892314112:4026531839]	101	1			T25	1		T48	1		T108	1
auto[4026531840:4160749567]	100	1			T11	1		T25	2		T48	2
auto[4160749568:4294967295]	87	1			T25	1		T48	2		T55	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	36	1			T48	1		T108	1		T38	1
auto[0:134217727]	auto[1]	60	1			T25	2		T23	1		T106	1
auto[134217728:268435455]	auto[0]	66	1			T25	4		T106	1		T55	2
auto[134217728:268435455]	auto[1]	48	1			T2	1		T25	1		T4	1
auto[268435456:402653183]	auto[0]	64	1			T2	1		T25	1		T22	1
auto[268435456:402653183]	auto[1]	60	1			T15	1		T25	1		T55	2
auto[402653184:536870911]	auto[0]	45	1			T25	2		T48	1		T129	1
auto[402653184:536870911]	auto[1]	57	1			T12	1		T25	1		T106	1
auto[536870912:671088639]	auto[0]	43	1			T17	1		T53	1		T106	2
auto[536870912:671088639]	auto[1]	62	1			T45	1		T55	1		T138	1
auto[671088640:805306367]	auto[0]	51	1			T25	1		T22	1		T55	1
auto[671088640:805306367]	auto[1]	63	1			T25	1		T106	1		T55	1
auto[805306368:939524095]	auto[0]	50	1			T25	3		T128	1		T130	1
auto[805306368:939524095]	auto[1]	54	1			T15	1		T16	1		T25	1
auto[939524096:1073741823]	auto[0]	44	1			T25	1		T126	1		T405	1
auto[939524096:1073741823]	auto[1]	49	1			T15	1		T48	1		T72	1
auto[1073741824:1207959551]	auto[0]	52	1			T11	1		T48	1		T55	3
auto[1073741824:1207959551]	auto[1]	62	1			T2	1		T11	1		T25	1
auto[1207959552:1342177279]	auto[0]	48	1			T12	1		T25	3		T130	1
auto[1207959552:1342177279]	auto[1]	38	1			T25	1		T48	1		T55	1
auto[1342177280:1476395007]	auto[0]	39	1			T2	1		T25	3		T36	1
auto[1342177280:1476395007]	auto[1]	65	1			T12	2		T25	1		T200	1
auto[1476395008:1610612735]	auto[0]	33	1			T22	2		T198	1		T120	1
auto[1476395008:1610612735]	auto[1]	54	1			T25	1		T136	1		T205	1
auto[1610612736:1744830463]	auto[0]	46	1			T15	1		T48	2		T106	2
auto[1610612736:1744830463]	auto[1]	43	1			T11	2		T55	1		T5	1
auto[1744830464:1879048191]	auto[0]	65	1			T45	1		T55	1		T57	1
auto[1744830464:1879048191]	auto[1]	45	1			T106	1		T55	1		T199	1
auto[1879048192:2013265919]	auto[0]	49	1			T25	1		T48	1		T57	1
auto[1879048192:2013265919]	auto[1]	46	1			T106	1		T55	1		T128	1
auto[2013265920:2147483647]	auto[0]	65	1			T25	1		T48	1		T53	1
auto[2013265920:2147483647]	auto[1]	55	1			T25	2		T108	1		T261	1
auto[2147483648:2281701375]	auto[0]	50	1			T25	1		T136	1		T55	1
auto[2147483648:2281701375]	auto[1]	58	1			T25	1		T106	1		T55	1
auto[2281701376:2415919103]	auto[0]	53	1			T25	1		T50	2		T61	1
auto[2281701376:2415919103]	auto[1]	43	1			T2	1		T25	2		T48	1
auto[2415919104:2550136831]	auto[0]	44	1			T55	1		T38	1		T199	1
auto[2415919104:2550136831]	auto[1]	53	1			T126	1		T129	1		T197	1
auto[2550136832:2684354559]	auto[0]	44	1			T2	1		T17	1		T25	1
auto[2550136832:2684354559]	auto[1]	53	1			T36	1		T108	1		T106	1
auto[2684354560:2818572287]	auto[0]	49	1			T55	1		T129	1		T204	1
auto[2684354560:2818572287]	auto[1]	65	1			T15	1		T25	2		T48	1
auto[2818572288:2952790015]	auto[0]	50	1			T25	2		T22	1		T106	1
auto[2818572288:2952790015]	auto[1]	56	1			T25	3		T48	2		T60	1
auto[2952790016:3087007743]	auto[0]	54	1			T22	1		T61	1		T419	1
auto[2952790016:3087007743]	auto[1]	49	1			T45	1		T25	2		T132	1
auto[3087007744:3221225471]	auto[0]	48	1			T12	1		T25	1		T106	1
auto[3087007744:3221225471]	auto[1]	55	1			T16	1		T106	1		T55	1
auto[3221225472:3355443199]	auto[0]	53	1			T12	1		T25	1		T108	1
auto[3221225472:3355443199]	auto[1]	40	1			T25	1		T136	1		T67	1
auto[3355443200:3489660927]	auto[0]	48	1			T11	1		T15	1		T53	1
auto[3355443200:3489660927]	auto[1]	64	1			T25	1		T106	1		T55	2
auto[3489660928:3623878655]	auto[0]	55	1			T45	1		T25	2		T136	1
auto[3489660928:3623878655]	auto[1]	52	1			T45	1		T25	1		T405	1
auto[3623878656:3758096383]	auto[0]	46	1			T25	1		T48	1		T199	1
auto[3623878656:3758096383]	auto[1]	63	1			T11	1		T25	2		T55	2
auto[3758096384:3892314111]	auto[0]	44	1			T128	1		T61	1		T68	1
auto[3758096384:3892314111]	auto[1]	50	1			T55	1		T60	1		T61	1
auto[3892314112:4026531839]	auto[0]	52	1			T25	1		T48	1		T22	1
auto[3892314112:4026531839]	auto[1]	49	1			T108	1		T106	1		T197	1
auto[4026531840:4160749567]	auto[0]	49	1			T11	1		T25	1		T48	1
auto[4026531840:4160749567]	auto[1]	51	1			T25	1		T48	1		T55	1
auto[4160749568:4294967295]	auto[0]	33	1			T48	1		T55	1		T129	1
auto[4160749568:4294967295]	auto[1]	54	1			T25	1		T48	1		T61	3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1549

1

T2

3

T11

1

T12

4

auto[1]

1737

1

T2

3

T11

6

T12

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T25	3		T106	1		T55	2
auto[134217728:268435455]	82	1			T25	3		T106	2		T129	2
auto[268435456:402653183]	111	1			T2	1		T25	3		T55	1
auto[402653184:536870911]	89	1			T12	1		T25	2		T106	1
auto[536870912:671088639]	97	1			T15	1		T25	2		T55	1
auto[671088640:805306367]	103	1			T25	1		T53	1		T55	2
auto[805306368:939524095]	92	1			T2	1		T22	1		T106	1
auto[939524096:1073741823]	108	1			T25	5		T48	1		T55	1
auto[1073741824:1207959551]	116	1			T25	1		T48	1		T53	1
auto[1207959552:1342177279]	114	1			T15	1		T25	2		T48	3
auto[1342177280:1476395007]	96	1			T2	1		T15	1		T25	1
auto[1476395008:1610612735]	98	1			T2	1		T45	1		T25	1
auto[1610612736:1744830463]	106	1			T12	1		T25	3		T106	1
auto[1744830464:1879048191]	99	1			T25	1		T53	1		T4	1
auto[1879048192:2013265919]	102	1			T25	3		T106	2		T55	1
auto[2013265920:2147483647]	104	1			T12	1		T45	1		T25	5
auto[2147483648:2281701375]	107	1			T11	1		T16	1		T25	3
auto[2281701376:2415919103]	101	1			T15	1		T25	1		T136	1
auto[2415919104:2550136831]	110	1			T11	2		T45	1		T25	1
auto[2550136832:2684354559]	109	1			T15	1		T25	1		T48	1
auto[2684354560:2818572287]	108	1			T11	1		T25	2		T48	2
auto[2818572288:2952790015]	109	1			T17	1		T45	1		T25	2
auto[2952790016:3087007743]	104	1			T45	1		T25	3		T48	1
auto[3087007744:3221225471]	108	1			T15	1		T25	1		T48	1
auto[3221225472:3355443199]	90	1			T2	1		T25	1		T36	1
auto[3355443200:3489660927]	101	1			T12	1		T25	1		T108	1
auto[3489660928:3623878655]	100	1			T12	1		T16	1		T25	3
auto[3623878656:3758096383]	93	1			T25	2		T48	1		T136	1
auto[3758096384:3892314111]	97	1			T11	2		T25	3		T48	1
auto[3892314112:4026531839]	110	1			T2	1		T25	1		T48	1
auto[4026531840:4160749567]	116	1			T11	1		T17	1		T25	1
auto[4160749568:4294967295]	103	1			T12	1		T55	1		T67	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	46	1			T55	1		T109	1		T198	1
auto[0:134217727]	auto[1]	57	1			T25	3		T106	1		T55	1
auto[134217728:268435455]	auto[0]	40	1			T25	2		T106	1		T129	2
auto[134217728:268435455]	auto[1]	42	1			T25	1		T106	1		T5	1
auto[268435456:402653183]	auto[0]	56	1			T2	1		T25	2		T55	1
auto[268435456:402653183]	auto[1]	55	1			T25	1		T199	1		T205	1
auto[402653184:536870911]	auto[0]	49	1			T12	1		T25	2		T129	1
auto[402653184:536870911]	auto[1]	40	1			T106	1		T261	1		T121	1
auto[536870912:671088639]	auto[0]	47	1			T15	1		T25	2		T55	1
auto[536870912:671088639]	auto[1]	50	1			T5	1		T61	2		T138	1
auto[671088640:805306367]	auto[0]	55	1			T53	1		T67	1		T128	1
auto[671088640:805306367]	auto[1]	48	1			T25	1		T55	2		T54	1
auto[805306368:939524095]	auto[0]	52	1			T22	1		T106	1		T205	1
auto[805306368:939524095]	auto[1]	40	1			T2	1		T55	1		T63	1
auto[939524096:1073741823]	auto[0]	47	1			T25	3		T128	1		T54	1
auto[939524096:1073741823]	auto[1]	61	1			T25	2		T48	1		T55	1
auto[1073741824:1207959551]	auto[0]	57	1			T22	1		T55	1		T67	1
auto[1073741824:1207959551]	auto[1]	59	1			T25	1		T48	1		T53	1
auto[1207959552:1342177279]	auto[0]	48	1			T15	1		T55	1		T126	1
auto[1207959552:1342177279]	auto[1]	66	1			T25	2		T48	3		T55	1
auto[1342177280:1476395007]	auto[0]	48	1			T2	1		T25	1		T136	1
auto[1342177280:1476395007]	auto[1]	48	1			T15	1		T108	1		T55	1
auto[1476395008:1610612735]	auto[0]	38	1			T25	1		T48	2		T130	1
auto[1476395008:1610612735]	auto[1]	60	1			T2	1		T45	1		T106	1
auto[1610612736:1744830463]	auto[0]	59	1			T12	1		T25	2		T129	1
auto[1610612736:1744830463]	auto[1]	47	1			T25	1		T106	1		T128	1
auto[1744830464:1879048191]	auto[0]	47	1			T25	1		T53	1		T106	1
auto[1744830464:1879048191]	auto[1]	52	1			T4	1		T67	1		T128	1
auto[1879048192:2013265919]	auto[0]	48	1			T25	2		T106	1		T55	1
auto[1879048192:2013265919]	auto[1]	54	1			T25	1		T106	1		T200	1
auto[2013265920:2147483647]	auto[0]	57	1			T12	1		T25	3		T48	1
auto[2013265920:2147483647]	auto[1]	47	1			T45	1		T25	2		T55	2
auto[2147483648:2281701375]	auto[0]	51	1			T25	1		T106	1		T95	1
auto[2147483648:2281701375]	auto[1]	56	1			T11	1		T16	1		T25	2
auto[2281701376:2415919103]	auto[0]	47	1			T25	1		T22	1		T106	1
auto[2281701376:2415919103]	auto[1]	54	1			T15	1		T136	1		T278	1
auto[2415919104:2550136831]	auto[0]	46	1			T45	1		T25	1		T55	1
auto[2415919104:2550136831]	auto[1]	64	1			T11	2		T108	1		T106	1
auto[2550136832:2684354559]	auto[0]	55	1			T25	1		T48	1		T22	2
auto[2550136832:2684354559]	auto[1]	54	1			T15	1		T128	1		T129	1
auto[2684354560:2818572287]	auto[0]	46	1			T11	1		T106	1		T66	1
auto[2684354560:2818572287]	auto[1]	62	1			T25	2		T48	2		T55	2
auto[2818572288:2952790015]	auto[0]	54	1			T25	2		T48	1		T55	1
auto[2818572288:2952790015]	auto[1]	55	1			T17	1		T45	1		T106	1
auto[2952790016:3087007743]	auto[0]	49	1			T45	1		T25	1		T48	1
auto[2952790016:3087007743]	auto[1]	55	1			T25	2		T55	1		T63	1
auto[3087007744:3221225471]	auto[0]	52	1			T25	1		T22	1		T55	1
auto[3087007744:3221225471]	auto[1]	56	1			T15	1		T48	1		T106	1
auto[3221225472:3355443199]	auto[0]	38	1			T25	1		T36	1		T23	1
auto[3221225472:3355443199]	auto[1]	52	1			T2	1		T200	1		T199	1
auto[3355443200:3489660927]	auto[0]	45	1			T108	1		T57	1		T38	1
auto[3355443200:3489660927]	auto[1]	56	1			T12	1		T25	1		T106	1
auto[3489660928:3623878655]	auto[0]	42	1			T25	1		T48	2		T22	1
auto[3489660928:3623878655]	auto[1]	58	1			T12	1		T16	1		T25	2
auto[3623878656:3758096383]	auto[0]	43	1			T25	1		T48	1		T55	1
auto[3623878656:3758096383]	auto[1]	50	1			T25	1		T136	1		T197	1
auto[3758096384:3892314111]	auto[0]	48	1			T25	2		T136	1		T22	2
auto[3758096384:3892314111]	auto[1]	49	1			T11	2		T25	1		T48	1
auto[3892314112:4026531839]	auto[0]	40	1			T2	1		T25	1		T38	1
auto[3892314112:4026531839]	auto[1]	70	1			T48	1		T53	1		T55	1
auto[4026531840:4160749567]	auto[0]	50	1			T17	1		T25	1		T36	1
auto[4026531840:4160749567]	auto[1]	66	1			T11	1		T200	1		T95	1
auto[4160749568:4294967295]	auto[0]	49	1			T12	1		T197	1		T38	1
auto[4160749568:4294967295]	auto[1]	54	1			T55	1		T67	1		T61	3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1536

1

T2

4

T11

2

T12

3

auto[1]

1747

1

T2

2

T11

5

T12

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	107	1			T25	1		T106	1		T55	1
auto[134217728:268435455]	100	1			T2	1		T11	1		T15	1
auto[268435456:402653183]	103	1			T25	4		T108	1		T106	1
auto[402653184:536870911]	105	1			T11	1		T25	1		T36	1
auto[536870912:671088639]	109	1			T2	1		T15	1		T17	1
auto[671088640:805306367]	96	1			T12	2		T25	2		T48	1
auto[805306368:939524095]	106	1			T16	1		T25	2		T48	1
auto[939524096:1073741823]	108	1			T12	1		T15	1		T25	3
auto[1073741824:1207959551]	99	1			T15	1		T25	1		T106	1
auto[1207959552:1342177279]	88	1			T12	1		T25	1		T48	2
auto[1342177280:1476395007]	100	1			T16	1		T17	1		T45	1
auto[1476395008:1610612735]	102	1			T25	3		T22	1		T55	1
auto[1610612736:1744830463]	119	1			T11	1		T108	1		T72	1
auto[1744830464:1879048191]	115	1			T25	2		T48	2		T136	1
auto[1879048192:2013265919]	103	1			T45	1		T25	1		T48	1
auto[2013265920:2147483647]	102	1			T48	1		T55	3		T126	1
auto[2147483648:2281701375]	92	1			T25	3		T48	1		T106	1
auto[2281701376:2415919103]	104	1			T25	1		T48	2		T130	1
auto[2415919104:2550136831]	105	1			T25	1		T22	1		T128	1
auto[2550136832:2684354559]	79	1			T12	1		T25	1		T67	1
auto[2684354560:2818572287]	92	1			T25	1		T22	1		T106	1
auto[2818572288:2952790015]	79	1			T2	1		T12	1		T45	1
auto[2952790016:3087007743]	94	1			T11	1		T25	2		T48	1
auto[3087007744:3221225471]	104	1			T2	1		T11	1		T25	3
auto[3221225472:3355443199]	118	1			T15	1		T25	5		T48	1
auto[3355443200:3489660927]	109	1			T2	1		T25	3		T48	1
auto[3489660928:3623878655]	118	1			T15	1		T45	1		T25	4
auto[3623878656:3758096383]	110	1			T45	1		T25	5		T36	1
auto[3758096384:3892314111]	97	1			T2	1		T25	1		T48	3
auto[3892314112:4026531839]	98	1			T25	1		T106	1		T199	1
auto[4026531840:4160749567]	111	1			T11	1		T25	3		T23	1
auto[4160749568:4294967295]	111	1			T11	1		T55	2		T128	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	51	1			T25	1		T106	1		T55	1
auto[0:134217727]	auto[1]	56	1			T198	1		T61	1		T68	1
auto[134217728:268435455]	auto[0]	49	1			T2	1		T25	1		T108	1
auto[134217728:268435455]	auto[1]	51	1			T11	1		T15	1		T25	1
auto[268435456:402653183]	auto[0]	49	1			T25	2		T55	2		T128	1
auto[268435456:402653183]	auto[1]	54	1			T25	2		T108	1		T106	1
auto[402653184:536870911]	auto[0]	53	1			T25	1		T36	1		T53	1
auto[402653184:536870911]	auto[1]	52	1			T11	1		T106	1		T130	1
auto[536870912:671088639]	auto[0]	54	1			T2	1		T17	1		T25	3
auto[536870912:671088639]	auto[1]	55	1			T15	1		T25	1		T106	1
auto[671088640:805306367]	auto[0]	49	1			T12	1		T25	1		T48	1
auto[671088640:805306367]	auto[1]	47	1			T12	1		T25	1		T55	1
auto[805306368:939524095]	auto[0]	40	1			T25	1		T48	1		T22	1
auto[805306368:939524095]	auto[1]	66	1			T16	1		T25	1		T53	1
auto[939524096:1073741823]	auto[0]	43	1			T12	1		T25	2		T106	1
auto[939524096:1073741823]	auto[1]	65	1			T15	1		T25	1		T48	1
auto[1073741824:1207959551]	auto[0]	46	1			T55	2		T129	1		T38	1
auto[1073741824:1207959551]	auto[1]	53	1			T15	1		T25	1		T106	1
auto[1207959552:1342177279]	auto[0]	49	1			T12	1		T25	1		T48	1
auto[1207959552:1342177279]	auto[1]	39	1			T48	1		T57	1		T236	1
auto[1342177280:1476395007]	auto[0]	50	1			T45	1		T53	1		T106	1
auto[1342177280:1476395007]	auto[1]	50	1			T16	1		T17	1		T25	1
auto[1476395008:1610612735]	auto[0]	44	1			T25	2		T22	1		T407	1
auto[1476395008:1610612735]	auto[1]	58	1			T25	1		T55	1		T61	1
auto[1610612736:1744830463]	auto[0]	57	1			T11	1		T108	1		T198	1
auto[1610612736:1744830463]	auto[1]	62	1			T72	1		T199	1		T61	1
auto[1744830464:1879048191]	auto[0]	65	1			T25	1		T48	2		T106	2
auto[1744830464:1879048191]	auto[1]	50	1			T25	1		T136	1		T106	1
auto[1879048192:2013265919]	auto[0]	49	1			T48	1		T53	1		T106	1
auto[1879048192:2013265919]	auto[1]	54	1			T45	1		T25	1		T136	1
auto[2013265920:2147483647]	auto[0]	40	1			T55	1		T130	2		T38	1
auto[2013265920:2147483647]	auto[1]	62	1			T48	1		T55	2		T126	1
auto[2147483648:2281701375]	auto[0]	45	1			T25	2		T48	1		T130	1
auto[2147483648:2281701375]	auto[1]	47	1			T25	1		T106	1		T55	2
auto[2281701376:2415919103]	auto[0]	54	1			T48	2		T130	1		T405	1
auto[2281701376:2415919103]	auto[1]	50	1			T25	1		T57	1		T63	1
auto[2415919104:2550136831]	auto[0]	44	1			T25	1		T61	3		T68	1
auto[2415919104:2550136831]	auto[1]	61	1			T22	1		T128	1		T24	1
auto[2550136832:2684354559]	auto[0]	31	1			T25	1		T38	1		T205	1
auto[2550136832:2684354559]	auto[1]	48	1			T12	1		T67	1		T254	1
auto[2684354560:2818572287]	auto[0]	47	1			T22	1		T405	1		T61	1
auto[2684354560:2818572287]	auto[1]	45	1			T25	1		T106	1		T55	1
auto[2818572288:2952790015]	auto[0]	36	1			T45	1		T136	1		T129	2
auto[2818572288:2952790015]	auto[1]	43	1			T2	1		T12	1		T130	1
auto[2952790016:3087007743]	auto[0]	41	1			T11	1		T25	2		T55	1
auto[2952790016:3087007743]	auto[1]	53	1			T48	1		T54	1		T61	1
auto[3087007744:3221225471]	auto[0]	42	1			T2	1		T25	1		T48	1
auto[3087007744:3221225471]	auto[1]	62	1			T11	1		T25	2		T205	1
auto[3221225472:3355443199]	auto[0]	62	1			T25	2		T48	1		T108	1
auto[3221225472:3355443199]	auto[1]	56	1			T15	1		T25	3		T106	1
auto[3355443200:3489660927]	auto[0]	45	1			T25	1		T106	1		T199	1
auto[3355443200:3489660927]	auto[1]	64	1			T2	1		T25	2		T48	1
auto[3489660928:3623878655]	auto[0]	52	1			T15	1		T45	1		T25	2
auto[3489660928:3623878655]	auto[1]	66	1			T25	2		T95	1		T60	1
auto[3623878656:3758096383]	auto[0]	42	1			T25	3		T55	1		T38	1
auto[3623878656:3758096383]	auto[1]	68	1			T45	1		T25	2		T36	1
auto[3758096384:3892314111]	auto[0]	48	1			T2	1		T129	1		T197	1
auto[3758096384:3892314111]	auto[1]	49	1			T25	1		T48	3		T108	1
auto[3892314112:4026531839]	auto[0]	58	1			T106	1		T199	1		T198	1
auto[3892314112:4026531839]	auto[1]	40	1			T25	1		T315	1		T123	1
auto[4026531840:4160749567]	auto[0]	50	1			T25	2		T23	1		T55	1
auto[4026531840:4160749567]	auto[1]	61	1			T11	1		T25	1		T109	1
auto[4160749568:4294967295]	auto[0]	51	1			T55	1		T109	1		T6	1
auto[4160749568:4294967295]	auto[1]	60	1			T11	1		T55	1		T128	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1529

1

T2

4

T11

2

T12

2

auto[1]

1755

1

T2

2

T11

5

T12

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	106	1			T25	2		T23	1		T55	2
auto[134217728:268435455]	93	1			T48	1		T136	1		T106	1
auto[268435456:402653183]	91	1			T17	1		T25	1		T48	1
auto[402653184:536870911]	99	1			T25	3		T48	1		T106	1
auto[536870912:671088639]	103	1			T45	1		T25	5		T137	1
auto[671088640:805306367]	99	1			T25	2		T48	1		T108	1
auto[805306368:939524095]	96	1			T2	1		T25	1		T60	1
auto[939524096:1073741823]	114	1			T2	1		T15	1		T25	1
auto[1073741824:1207959551]	104	1			T12	1		T25	1		T48	1
auto[1207959552:1342177279]	90	1			T16	1		T108	1		T22	1
auto[1342177280:1476395007]	82	1			T12	1		T25	4		T4	1
auto[1476395008:1610612735]	96	1			T2	1		T45	1		T36	1
auto[1610612736:1744830463]	105	1			T12	1		T25	3		T48	1
auto[1744830464:1879048191]	101	1			T15	1		T45	1		T25	3
auto[1879048192:2013265919]	109	1			T11	1		T25	1		T106	1
auto[2013265920:2147483647]	108	1			T25	2		T55	1		T67	1
auto[2147483648:2281701375]	113	1			T2	1		T17	1		T25	1
auto[2281701376:2415919103]	100	1			T12	1		T25	3		T55	2
auto[2415919104:2550136831]	86	1			T11	1		T25	2		T55	1
auto[2550136832:2684354559]	125	1			T11	2		T15	1		T25	3
auto[2684354560:2818572287]	94	1			T11	1		T15	1		T16	1
auto[2818572288:2952790015]	119	1			T12	1		T25	1		T48	4
auto[2952790016:3087007743]	97	1			T25	2		T36	1		T48	1
auto[3087007744:3221225471]	116	1			T45	1		T106	1		T55	5
auto[3221225472:3355443199]	114	1			T2	1		T25	3		T106	1
auto[3355443200:3489660927]	99	1			T11	1		T25	4		T106	1
auto[3489660928:3623878655]	102	1			T25	2		T55	2		T126	1
auto[3623878656:3758096383]	116	1			T11	1		T15	2		T25	1
auto[3758096384:3892314111]	102	1			T25	1		T48	1		T136	1
auto[3892314112:4026531839]	102	1			T2	1		T25	3		T108	1
auto[4026531840:4160749567]	111	1			T12	1		T45	1		T25	2
auto[4160749568:4294967295]	92	1			T25	4		T108	1		T106	2