Unified Coverage Report :: Group Instance : salt_4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2896

1

T2

6

T11

7

T12

6

auto[1]

309

1

T11

3

T12

3

T108

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T2	1		T25	2		T106	1
auto[134217728:268435455]	102	1			T25	2		T55	1		T132	1
auto[268435456:402653183]	92	1			T11	2		T17	1		T25	1
auto[402653184:536870911]	104	1			T25	2		T4	1		T106	1
auto[536870912:671088639]	75	1			T25	1		T136	2		T22	1
auto[671088640:805306367]	109	1			T2	1		T11	1		T12	1
auto[805306368:939524095]	111	1			T16	1		T25	1		T108	1
auto[939524096:1073741823]	86	1			T16	1		T25	2		T48	2
auto[1073741824:1207959551]	97	1			T11	1		T17	1		T48	1
auto[1207959552:1342177279]	91	1			T25	1		T106	2		T55	1
auto[1342177280:1476395007]	98	1			T11	2		T12	1		T25	1
auto[1476395008:1610612735]	93	1			T25	2		T23	1		T137	1
auto[1610612736:1744830463]	85	1			T25	2		T106	3		T55	2
auto[1744830464:1879048191]	102	1			T25	2		T108	1		T22	1
auto[1879048192:2013265919]	102	1			T25	2		T55	1		T128	1
auto[2013265920:2147483647]	100	1			T2	1		T25	3		T48	2
auto[2147483648:2281701375]	97	1			T12	1		T25	1		T48	2
auto[2281701376:2415919103]	119	1			T11	1		T48	1		T53	1
auto[2415919104:2550136831]	96	1			T12	1		T25	3		T48	1
auto[2550136832:2684354559]	83	1			T2	2		T12	1		T15	1
auto[2684354560:2818572287]	129	1			T12	1		T25	2		T106	2
auto[2818572288:2952790015]	100	1			T25	3		T48	2		T22	1
auto[2952790016:3087007743]	100	1			T25	3		T106	2		T63	1
auto[3087007744:3221225471]	105	1			T25	3		T48	1		T136	1
auto[3221225472:3355443199]	101	1			T15	1		T25	2		T72	1
auto[3355443200:3489660927]	103	1			T25	3		T48	1		T53	1
auto[3489660928:3623878655]	112	1			T15	1		T25	2		T48	1
auto[3623878656:3758096383]	101	1			T25	2		T48	2		T22	1
auto[3758096384:3892314111]	105	1			T12	2		T128	1		T129	1
auto[3892314112:4026531839]	107	1			T11	1		T25	3		T22	1
auto[4026531840:4160749567]	92	1			T2	1		T11	1		T48	1
auto[4160749568:4294967295]	99	1			T11	1		T12	1		T25	3

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	96	1			T2	1		T25	2		T106	1
auto[0:134217727]	auto[1]	13	1			T138	1		T297	1		T418	2
auto[134217728:268435455]	auto[0]	91	1			T25	2		T55	1		T132	1
auto[134217728:268435455]	auto[1]	11	1			T138	1		T139	1		T277	1
auto[268435456:402653183]	auto[0]	83	1			T11	2		T17	1		T25	1
auto[268435456:402653183]	auto[1]	9	1			T138	1		T139	1		T315	1
auto[402653184:536870911]	auto[0]	95	1			T25	2		T4	1		T106	1
auto[402653184:536870911]	auto[1]	9	1			T236	1		T254	1		T297	1
auto[536870912:671088639]	auto[0]	65	1			T25	1		T22	1		T55	1
auto[536870912:671088639]	auto[1]	10	1			T136	2		T254	1		T234	1
auto[671088640:805306367]	auto[0]	99	1			T2	1		T11	1		T12	1
auto[671088640:805306367]	auto[1]	10	1			T136	1		T138	2		T234	2
auto[805306368:939524095]	auto[0]	100	1			T16	1		T25	1		T55	2
auto[805306368:939524095]	auto[1]	11	1			T108	1		T278	1		T139	1
auto[939524096:1073741823]	auto[0]	77	1			T16	1		T25	2		T48	2
auto[939524096:1073741823]	auto[1]	9	1			T137	1		T254	1		T190	1
auto[1073741824:1207959551]	auto[0]	86	1			T17	1		T48	1		T109	1
auto[1073741824:1207959551]	auto[1]	11	1			T11	1		T130	1		T278	1
auto[1207959552:1342177279]	auto[0]	85	1			T25	1		T106	2		T55	1
auto[1207959552:1342177279]	auto[1]	6	1			T417	2		T314	1		T423	1
auto[1342177280:1476395007]	auto[0]	85	1			T11	1		T12	1		T25	1
auto[1342177280:1476395007]	auto[1]	13	1			T11	1		T138	1		T139	2
auto[1476395008:1610612735]	auto[0]	85	1			T25	2		T23	1		T137	1
auto[1476395008:1610612735]	auto[1]	8	1			T236	1		T254	1		T284	1
auto[1610612736:1744830463]	auto[0]	76	1			T25	2		T106	3		T55	2
auto[1610612736:1744830463]	auto[1]	9	1			T254	1		T234	1		T277	1
auto[1744830464:1879048191]	auto[0]	93	1			T25	2		T22	1		T55	1
auto[1744830464:1879048191]	auto[1]	9	1			T108	1		T278	1		T297	1
auto[1879048192:2013265919]	auto[0]	89	1			T25	2		T55	1		T128	1
auto[1879048192:2013265919]	auto[1]	13	1			T278	1		T139	1		T236	1
auto[2013265920:2147483647]	auto[0]	87	1			T2	1		T25	3		T48	2
auto[2013265920:2147483647]	auto[1]	13	1			T132	1		T137	1		T139	1
auto[2147483648:2281701375]	auto[0]	86	1			T12	1		T25	1		T48	2
auto[2147483648:2281701375]	auto[1]	11	1			T139	1		T236	1		T254	1
auto[2281701376:2415919103]	auto[0]	110	1			T11	1		T48	1		T53	1
auto[2281701376:2415919103]	auto[1]	9	1			T132	1		T139	1		T254	1
auto[2415919104:2550136831]	auto[0]	84	1			T25	3		T48	1		T136	1
auto[2415919104:2550136831]	auto[1]	12	1			T12	1		T278	1		T139	1
auto[2550136832:2684354559]	auto[0]	77	1			T2	2		T12	1		T15	1
auto[2550136832:2684354559]	auto[1]	6	1			T404	1		T418	1		T305	1
auto[2684354560:2818572287]	auto[0]	112	1			T25	2		T106	2		T55	1
auto[2684354560:2818572287]	auto[1]	17	1			T12	1		T139	1		T236	2
auto[2818572288:2952790015]	auto[0]	92	1			T25	3		T48	2		T22	1
auto[2818572288:2952790015]	auto[1]	8	1			T130	1		T139	2		T190	1
auto[2952790016:3087007743]	auto[0]	90	1			T25	3		T106	2		T63	1
auto[2952790016:3087007743]	auto[1]	10	1			T139	1		T236	1		T277	1
auto[3087007744:3221225471]	auto[0]	95	1			T25	3		T48	1		T136	1
auto[3087007744:3221225471]	auto[1]	10	1			T236	1		T254	1		T297	1
auto[3221225472:3355443199]	auto[0]	97	1			T15	1		T25	2		T72	1
auto[3221225472:3355443199]	auto[1]	4	1			T278	1		T139	1		T418	1
auto[3355443200:3489660927]	auto[0]	97	1			T25	3		T48	1		T53	1
auto[3355443200:3489660927]	auto[1]	6	1			T403	1		T423	1		T420	1
auto[3489660928:3623878655]	auto[0]	100	1			T15	1		T25	2		T48	1
auto[3489660928:3623878655]	auto[1]	12	1			T132	1		T278	1		T139	1
auto[3623878656:3758096383]	auto[0]	95	1			T25	2		T48	2		T22	1
auto[3623878656:3758096383]	auto[1]	6	1			T234	1		T404	1		T418	1
auto[3758096384:3892314111]	auto[0]	97	1			T12	1		T128	1		T129	1
auto[3758096384:3892314111]	auto[1]	8	1			T12	1		T236	1		T254	1
auto[3892314112:4026531839]	auto[0]	100	1			T25	3		T22	1		T55	1
auto[3892314112:4026531839]	auto[1]	7	1			T11	1		T138	1		T139	1
auto[4026531840:4160749567]	auto[0]	79	1			T2	1		T11	1		T48	1
auto[4026531840:4160749567]	auto[1]	13	1			T108	1		T278	1		T234	2
auto[4160749568:4294967295]	auto[0]	93	1			T11	1		T12	1		T25	3
auto[4160749568:4294967295]	auto[1]	6	1			T139	1		T254	1		T277	1