Unified Coverage Report :: Group Instance : salt_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2897

1

T2

6

T11

7

T12

6

auto[1]

318

1

T11

1

T108

8

T136

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T2	1		T11	1		T25	4
auto[134217728:268435455]	85	1			T25	1		T4	1		T106	1
auto[268435456:402653183]	95	1			T25	1		T36	1		T55	1
auto[402653184:536870911]	102	1			T11	1		T12	2		T15	1
auto[536870912:671088639]	98	1			T11	1		T25	1		T22	1
auto[671088640:805306367]	107	1			T2	1		T25	4		T48	2
auto[805306368:939524095]	91	1			T12	1		T25	1		T48	4
auto[939524096:1073741823]	95	1			T17	1		T25	3		T136	1
auto[1073741824:1207959551]	104	1			T2	1		T11	1		T25	3
auto[1207959552:1342177279]	116	1			T25	2		T108	1		T136	1
auto[1342177280:1476395007]	95	1			T25	1		T48	1		T106	1
auto[1476395008:1610612735]	100	1			T25	1		T106	2		T55	1
auto[1610612736:1744830463]	103	1			T2	1		T25	1		T108	2
auto[1744830464:1879048191]	101	1			T25	3		T48	1		T53	1
auto[1879048192:2013265919]	93	1			T12	1		T25	2		T48	1
auto[2013265920:2147483647]	93	1			T25	3		T55	1		T129	2
auto[2147483648:2281701375]	95	1			T25	3		T22	1		T55	1
auto[2281701376:2415919103]	94	1			T2	1		T25	1		T136	1
auto[2415919104:2550136831]	102	1			T25	4		T48	1		T106	1
auto[2550136832:2684354559]	115	1			T16	1		T25	3		T48	1
auto[2684354560:2818572287]	107	1			T15	1		T136	2		T55	2
auto[2818572288:2952790015]	107	1			T12	1		T16	1		T25	2
auto[2952790016:3087007743]	84	1			T11	1		T25	4		T126	1
auto[3087007744:3221225471]	108	1			T108	2		T106	2		T55	2
auto[3221225472:3355443199]	103	1			T17	1		T25	1		T108	1
auto[3355443200:3489660927]	104	1			T2	1		T25	2		T48	1
auto[3489660928:3623878655]	92	1			T15	1		T106	1		T55	1
auto[3623878656:3758096383]	118	1			T12	1		T55	1		T130	1
auto[3758096384:3892314111]	107	1			T11	2		T25	1		T48	1
auto[3892314112:4026531839]	114	1			T11	1		T25	1		T48	1
auto[4026531840:4160749567]	96	1			T25	1		T23	1		T106	1
auto[4160749568:4294967295]	88	1			T25	3		T48	1		T106	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	91	1			T2	1		T25	4		T55	1
auto[0:134217727]	auto[1]	12	1			T11	1		T108	1		T130	1
auto[134217728:268435455]	auto[0]	78	1			T25	1		T4	1		T106	1
auto[134217728:268435455]	auto[1]	7	1			T278	1		T234	1		T404	1
auto[268435456:402653183]	auto[0]	77	1			T25	1		T36	1		T55	1
auto[268435456:402653183]	auto[1]	18	1			T130	1		T278	1		T234	1
auto[402653184:536870911]	auto[0]	91	1			T11	1		T12	2		T15	1
auto[402653184:536870911]	auto[1]	11	1			T139	1		T236	1		T404	1
auto[536870912:671088639]	auto[0]	90	1			T11	1		T25	1		T22	1
auto[536870912:671088639]	auto[1]	8	1			T139	1		T234	1		T190	1
auto[671088640:805306367]	auto[0]	98	1			T2	1		T25	4		T48	2
auto[671088640:805306367]	auto[1]	9	1			T278	1		T254	1		T391	1
auto[805306368:939524095]	auto[0]	78	1			T12	1		T25	1		T48	4
auto[805306368:939524095]	auto[1]	13	1			T136	1		T278	2		T297	1
auto[939524096:1073741823]	auto[0]	86	1			T17	1		T25	3		T137	1
auto[939524096:1073741823]	auto[1]	9	1			T136	1		T278	1		T315	1
auto[1073741824:1207959551]	auto[0]	94	1			T2	1		T11	1		T25	3
auto[1073741824:1207959551]	auto[1]	10	1			T139	1		T190	1		T418	1
auto[1207959552:1342177279]	auto[0]	106	1			T25	2		T108	1		T129	1
auto[1207959552:1342177279]	auto[1]	10	1			T136	1		T278	1		T139	1
auto[1342177280:1476395007]	auto[0]	89	1			T25	1		T48	1		T106	1
auto[1342177280:1476395007]	auto[1]	6	1			T139	1		T254	2		T277	1
auto[1476395008:1610612735]	auto[0]	90	1			T25	1		T106	2		T55	1
auto[1476395008:1610612735]	auto[1]	10	1			T190	1		T277	1		T418	1
auto[1610612736:1744830463]	auto[0]	92	1			T2	1		T25	1		T108	1
auto[1610612736:1744830463]	auto[1]	11	1			T108	1		T136	1		T278	1
auto[1744830464:1879048191]	auto[0]	92	1			T25	3		T48	1		T53	1
auto[1744830464:1879048191]	auto[1]	9	1			T139	1		T254	1		T190	1
auto[1879048192:2013265919]	auto[0]	90	1			T12	1		T25	2		T48	1
auto[1879048192:2013265919]	auto[1]	3	1			T108	1		T132	1		T277	1
auto[2013265920:2147483647]	auto[0]	87	1			T25	3		T55	1		T129	2
auto[2013265920:2147483647]	auto[1]	6	1			T278	1		T190	1		T418	2
auto[2147483648:2281701375]	auto[0]	79	1			T25	3		T22	1		T55	1
auto[2147483648:2281701375]	auto[1]	16	1			T132	1		T236	3		T254	1
auto[2281701376:2415919103]	auto[0]	84	1			T2	1		T25	1		T136	1
auto[2281701376:2415919103]	auto[1]	10	1			T139	1		T236	1		T277	1
auto[2415919104:2550136831]	auto[0]	88	1			T25	4		T48	1		T106	1
auto[2415919104:2550136831]	auto[1]	14	1			T130	1		T138	2		T139	1
auto[2550136832:2684354559]	auto[0]	105	1			T16	1		T25	3		T48	1
auto[2550136832:2684354559]	auto[1]	10	1			T139	1		T234	1		T277	1
auto[2684354560:2818572287]	auto[0]	88	1			T15	1		T136	1		T55	2
auto[2684354560:2818572287]	auto[1]	19	1			T136	1		T130	2		T278	1
auto[2818572288:2952790015]	auto[0]	98	1			T12	1		T16	1		T25	2
auto[2818572288:2952790015]	auto[1]	9	1			T108	1		T254	1		T268	1
auto[2952790016:3087007743]	auto[0]	76	1			T11	1		T25	4		T126	1
auto[2952790016:3087007743]	auto[1]	8	1			T130	1		T236	1		T391	2
auto[3087007744:3221225471]	auto[0]	98	1			T106	2		T55	2		T38	1
auto[3087007744:3221225471]	auto[1]	10	1			T108	2		T139	1		T234	1
auto[3221225472:3355443199]	auto[0]	95	1			T17	1		T25	1		T108	1
auto[3221225472:3355443199]	auto[1]	8	1			T130	1		T403	1		T421	2
auto[3355443200:3489660927]	auto[0]	100	1			T2	1		T25	2		T48	1
auto[3355443200:3489660927]	auto[1]	4	1			T277	1		T305	1		T269	1
auto[3489660928:3623878655]	auto[0]	88	1			T15	1		T106	1		T55	1
auto[3489660928:3623878655]	auto[1]	4	1			T271	1		T273	1		T425	1
auto[3623878656:3758096383]	auto[0]	107	1			T12	1		T55	1		T130	1
auto[3623878656:3758096383]	auto[1]	11	1			T278	1		T138	1		T236	1
auto[3758096384:3892314111]	auto[0]	91	1			T11	2		T25	1		T48	1
auto[3758096384:3892314111]	auto[1]	16	1			T108	1		T278	1		T138	1
auto[3892314112:4026531839]	auto[0]	101	1			T11	1		T25	1		T48	1
auto[3892314112:4026531839]	auto[1]	13	1			T108	1		T136	1		T139	1
auto[4026531840:4160749567]	auto[0]	87	1			T25	1		T23	1		T106	1
auto[4026531840:4160749567]	auto[1]	9	1			T132	1		T278	1		T236	1
auto[4160749568:4294967295]	auto[0]	83	1			T25	3		T48	1		T106	1
auto[4160749568:4294967295]	auto[1]	5	1			T138	1		T236	1		T234	1