Unified Coverage Report :: Group Instance : attest_sw_binding_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1549

1

T2

4

T11

2

T12

5

auto[1]

1735

1

T2

2

T11

5

T12

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T25	1		T53	1		T55	2
auto[134217728:268435455]	92	1			T25	5		T48	1		T106	1
auto[268435456:402653183]	114	1			T2	1		T25	1		T48	1
auto[402653184:536870911]	95	1			T11	1		T22	1		T106	1
auto[536870912:671088639]	102	1			T2	1		T108	1		T106	1
auto[671088640:805306367]	88	1			T25	1		T48	1		T22	1
auto[805306368:939524095]	94	1			T45	1		T25	2		T106	1
auto[939524096:1073741823]	98	1			T25	5		T55	1		T129	1
auto[1073741824:1207959551]	79	1			T2	1		T12	1		T63	1
auto[1207959552:1342177279]	111	1			T15	1		T25	2		T55	1
auto[1342177280:1476395007]	89	1			T2	1		T48	2		T136	1
auto[1476395008:1610612735]	111	1			T15	1		T25	1		T22	1
auto[1610612736:1744830463]	135	1			T11	1		T45	1		T25	3
auto[1744830464:1879048191]	95	1			T25	5		T48	1		T106	1
auto[1879048192:2013265919]	97	1			T12	1		T15	1		T45	1
auto[2013265920:2147483647]	106	1			T25	2		T48	1		T108	2
auto[2147483648:2281701375]	113	1			T2	1		T11	1		T45	1
auto[2281701376:2415919103]	117	1			T15	1		T45	1		T25	2
auto[2415919104:2550136831]	104	1			T25	2		T136	1		T106	1
auto[2550136832:2684354559]	112	1			T15	1		T48	1		T106	2
auto[2684354560:2818572287]	92	1			T11	1		T17	1		T25	1
auto[2818572288:2952790015]	111	1			T12	1		T16	1		T25	4
auto[2952790016:3087007743]	114	1			T25	3		T36	1		T72	1
auto[3087007744:3221225471]	123	1			T11	2		T16	1		T48	1
auto[3221225472:3355443199]	92	1			T12	1		T55	3		T126	1
auto[3355443200:3489660927]	103	1			T25	2		T106	1		T205	1
auto[3489660928:3623878655]	113	1			T11	1		T12	1		T15	1
auto[3623878656:3758096383]	112	1			T25	3		T22	1		T55	3
auto[3758096384:3892314111]	89	1			T2	1		T25	4		T108	1
auto[3892314112:4026531839]	103	1			T25	1		T48	1		T55	1
auto[4026531840:4160749567]	91	1			T25	2		T48	3		T67	1
auto[4160749568:4294967295]	89	1			T12	1		T17	1		T25	4

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	49	1			T53	1		T128	1		T199	1
auto[0:134217727]	auto[1]	51	1			T25	1		T55	2		T405	1
auto[134217728:268435455]	auto[0]	41	1			T25	3		T55	1		T129	1
auto[134217728:268435455]	auto[1]	51	1			T25	2		T48	1		T106	1
auto[268435456:402653183]	auto[0]	50	1			T48	1		T22	1		T23	1
auto[268435456:402653183]	auto[1]	64	1			T2	1		T25	1		T55	2
auto[402653184:536870911]	auto[0]	42	1			T22	1		T106	1		T130	1
auto[402653184:536870911]	auto[1]	53	1			T11	1		T126	1		T205	1
auto[536870912:671088639]	auto[0]	47	1			T2	1		T55	2		T51	1
auto[536870912:671088639]	auto[1]	55	1			T108	1		T106	1		T61	1
auto[671088640:805306367]	auto[0]	39	1			T25	1		T48	1		T22	1
auto[671088640:805306367]	auto[1]	49	1			T55	1		T67	1		T205	1
auto[805306368:939524095]	auto[0]	54	1			T45	1		T25	1		T106	1
auto[805306368:939524095]	auto[1]	40	1			T25	1		T261	1		T120	1
auto[939524096:1073741823]	auto[0]	44	1			T25	1		T55	1		T129	1
auto[939524096:1073741823]	auto[1]	54	1			T25	4		T58	1		T121	1
auto[1073741824:1207959551]	auto[0]	39	1			T2	1		T12	1		T50	1
auto[1073741824:1207959551]	auto[1]	40	1			T63	1		T321	1		T138	1
auto[1207959552:1342177279]	auto[0]	57	1			T25	2		T55	1		T38	1
auto[1207959552:1342177279]	auto[1]	54	1			T15	1		T67	1		T63	1
auto[1342177280:1476395007]	auto[0]	44	1			T2	1		T128	1		T38	1
auto[1342177280:1476395007]	auto[1]	45	1			T48	2		T136	1		T55	2
auto[1476395008:1610612735]	auto[0]	48	1			T22	1		T322	1		T254	1
auto[1476395008:1610612735]	auto[1]	63	1			T15	1		T25	1		T50	1
auto[1610612736:1744830463]	auto[0]	68	1			T11	1		T45	1		T25	2
auto[1610612736:1744830463]	auto[1]	67	1			T25	1		T106	2		T132	1
auto[1744830464:1879048191]	auto[0]	45	1			T25	2		T48	1		T106	1
auto[1744830464:1879048191]	auto[1]	50	1			T25	3		T54	1		T121	1
auto[1879048192:2013265919]	auto[0]	46	1			T12	1		T15	1		T45	1
auto[1879048192:2013265919]	auto[1]	51	1			T109	1		T60	1		T252	1
auto[2013265920:2147483647]	auto[0]	55	1			T25	1		T108	2		T38	1
auto[2013265920:2147483647]	auto[1]	51	1			T25	1		T48	1		T57	1
auto[2147483648:2281701375]	auto[0]	48	1			T2	1		T25	1		T48	1
auto[2147483648:2281701375]	auto[1]	65	1			T11	1		T45	1		T25	2
auto[2281701376:2415919103]	auto[0]	51	1			T106	2		T129	1		T204	1
auto[2281701376:2415919103]	auto[1]	66	1			T15	1		T45	1		T25	2
auto[2415919104:2550136831]	auto[0]	49	1			T25	1		T55	1		T129	1
auto[2415919104:2550136831]	auto[1]	55	1			T25	1		T136	1		T106	1
auto[2550136832:2684354559]	auto[0]	47	1			T5	1		T61	1		T68	1
auto[2550136832:2684354559]	auto[1]	65	1			T15	1		T48	1		T106	2
auto[2684354560:2818572287]	auto[0]	45	1			T17	1		T25	1		T48	1
auto[2684354560:2818572287]	auto[1]	47	1			T11	1		T129	2		T261	1
auto[2818572288:2952790015]	auto[0]	53	1			T12	1		T25	3		T22	1
auto[2818572288:2952790015]	auto[1]	58	1			T16	1		T25	1		T106	1
auto[2952790016:3087007743]	auto[0]	54	1			T25	2		T36	1		T55	1
auto[2952790016:3087007743]	auto[1]	60	1			T25	1		T72	1		T4	1
auto[3087007744:3221225471]	auto[0]	55	1			T11	1		T57	1		T205	1
auto[3087007744:3221225471]	auto[1]	68	1			T11	1		T16	1		T48	1
auto[3221225472:3355443199]	auto[0]	50	1			T12	1		T55	2		T126	1
auto[3221225472:3355443199]	auto[1]	42	1			T55	1		T57	1		T201	1
auto[3355443200:3489660927]	auto[0]	42	1			T25	1		T106	1		T61	2
auto[3355443200:3489660927]	auto[1]	61	1			T25	1		T205	1		T58	1
auto[3489660928:3623878655]	auto[0]	49	1			T25	1		T48	1		T38	1
auto[3489660928:3623878655]	auto[1]	64	1			T11	1		T12	1		T15	1
auto[3623878656:3758096383]	auto[0]	46	1			T25	1		T22	1		T55	1
auto[3623878656:3758096383]	auto[1]	66	1			T25	2		T55	2		T24	1
auto[3758096384:3892314111]	auto[0]	48	1			T25	1		T108	1		T55	4
auto[3758096384:3892314111]	auto[1]	41	1			T2	1		T25	3		T55	1
auto[3892314112:4026531839]	auto[0]	57	1			T25	1		T48	1		T130	1
auto[3892314112:4026531839]	auto[1]	46	1			T55	1		T5	1		T58	1
auto[4026531840:4160749567]	auto[0]	43	1			T25	2		T48	1		T67	1
auto[4026531840:4160749567]	auto[1]	48	1			T48	2		T66	1		T139	1
auto[4160749568:4294967295]	auto[0]	44	1			T12	1		T17	1		T25	2
auto[4160749568:4294967295]	auto[1]	45	1			T25	2		T48	1		T106	2