Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6847

1

T2

19

T11

14

T12

11

auto[1]

300

1

T11

2

T12

5

T108

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2876	1			T2	6		T11	7		T12	5
auto[134217728:268435455]	172	1			T16	1		T25	1		T106	2
auto[268435456:402653183]	159	1			T12	1		T25	5		T48	2
auto[402653184:536870911]	138	1			T12	1		T16	1		T17	1
auto[536870912:671088639]	142	1			T15	1		T25	1		T106	2
auto[671088640:805306367]	150	1			T2	1		T17	2		T25	1
auto[805306368:939524095]	132	1			T2	2		T12	1		T25	2
auto[939524096:1073741823]	159	1			T2	1		T25	1		T48	1
auto[1073741824:1207959551]	135	1			T11	1		T12	1		T25	2
auto[1207959552:1342177279]	149	1			T11	2		T53	1		T108	1
auto[1342177280:1476395007]	121	1			T12	1		T17	1		T25	4
auto[1476395008:1610612735]	137	1			T12	1		T25	3		T55	2
auto[1610612736:1744830463]	137	1			T2	2		T15	1		T25	1
auto[1744830464:1879048191]	145	1			T25	6		T48	1		T22	1
auto[1879048192:2013265919]	142	1			T15	2		T25	2		T55	1
auto[2013265920:2147483647]	154	1			T25	2		T48	3		T108	1
auto[2147483648:2281701375]	118	1			T25	2		T130	1		T199	1
auto[2281701376:2415919103]	127	1			T2	1		T11	2		T12	1
auto[2415919104:2550136831]	117	1			T17	1		T55	2		T129	1
auto[2550136832:2684354559]	133	1			T2	1		T11	1		T25	3
auto[2684354560:2818572287]	130	1			T2	1		T25	1		T48	1
auto[2818572288:2952790015]	124	1			T2	1		T25	3		T136	1
auto[2952790016:3087007743]	127	1			T11	1		T136	1		T22	1
auto[3087007744:3221225471]	122	1			T11	1		T25	2		T22	2
auto[3221225472:3355443199]	147	1			T12	1		T16	1		T25	2
auto[3355443200:3489660927]	142	1			T2	1		T11	1		T12	2
auto[3489660928:3623878655]	131	1			T2	1		T17	1		T25	3
auto[3623878656:3758096383]	135	1			T25	1		T108	1		T22	1
auto[3758096384:3892314111]	153	1			T12	1		T25	4		T48	2
auto[3892314112:4026531839]	115	1			T25	3		T136	2		T22	2
auto[4026531840:4160749567]	127	1			T2	1		T17	1		T25	2
auto[4160749568:4294967295]	151	1			T17	1		T25	1		T48	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2865	1			T2	6		T11	7		T12	5
auto[0:134217727]	auto[1]	11	1			T108	1		T278	1		T139	1
auto[134217728:268435455]	auto[0]	163	1			T16	1		T25	1		T106	2
auto[134217728:268435455]	auto[1]	9	1			T130	1		T236	1		T297	1
auto[268435456:402653183]	auto[0]	150	1			T25	5		T48	2		T106	2
auto[268435456:402653183]	auto[1]	9	1			T12	1		T136	1		T139	2
auto[402653184:536870911]	auto[0]	129	1			T12	1		T16	1		T17	1
auto[402653184:536870911]	auto[1]	9	1			T136	1		T139	1		T236	1
auto[536870912:671088639]	auto[0]	136	1			T15	1		T25	1		T106	2
auto[536870912:671088639]	auto[1]	6	1			T139	1		T236	2		T272	1
auto[671088640:805306367]	auto[0]	141	1			T2	1		T17	2		T25	1
auto[671088640:805306367]	auto[1]	9	1			T138	1		T139	1		T418	1
auto[805306368:939524095]	auto[0]	128	1			T2	2		T12	1		T25	2
auto[805306368:939524095]	auto[1]	4	1			T278	1		T268	1		T420	1
auto[939524096:1073741823]	auto[0]	147	1			T2	1		T25	1		T48	1
auto[939524096:1073741823]	auto[1]	12	1			T278	1		T139	1		T234	1
auto[1073741824:1207959551]	auto[0]	124	1			T11	1		T25	2		T4	1
auto[1073741824:1207959551]	auto[1]	11	1			T12	1		T138	2		T404	1
auto[1207959552:1342177279]	auto[0]	140	1			T11	1		T53	1		T108	1
auto[1207959552:1342177279]	auto[1]	9	1			T11	1		T139	2		T236	2
auto[1342177280:1476395007]	auto[0]	109	1			T12	1		T17	1		T25	4
auto[1342177280:1476395007]	auto[1]	12	1			T278	1		T138	1		T139	1
auto[1476395008:1610612735]	auto[0]	124	1			T25	3		T55	2		T128	1
auto[1476395008:1610612735]	auto[1]	13	1			T12	1		T139	2		T254	1
auto[1610612736:1744830463]	auto[0]	126	1			T2	2		T15	1		T25	1
auto[1610612736:1744830463]	auto[1]	11	1			T278	1		T139	1		T234	1
auto[1744830464:1879048191]	auto[0]	134	1			T25	6		T48	1		T22	1
auto[1744830464:1879048191]	auto[1]	11	1			T139	1		T254	2		T404	1
auto[1879048192:2013265919]	auto[0]	132	1			T15	2		T25	2		T55	1
auto[1879048192:2013265919]	auto[1]	10	1			T278	1		T138	1		T139	1
auto[2013265920:2147483647]	auto[0]	140	1			T25	2		T48	3		T108	1
auto[2013265920:2147483647]	auto[1]	14	1			T136	1		T137	1		T139	1
auto[2147483648:2281701375]	auto[0]	108	1			T25	2		T199	1		T95	1
auto[2147483648:2281701375]	auto[1]	10	1			T130	1		T139	2		T234	1
auto[2281701376:2415919103]	auto[0]	120	1			T2	1		T11	1		T12	1
auto[2281701376:2415919103]	auto[1]	7	1			T11	1		T136	2		T254	1
auto[2415919104:2550136831]	auto[0]	113	1			T17	1		T55	2		T129	1
auto[2415919104:2550136831]	auto[1]	4	1			T278	1		T268	1		T421	1
auto[2550136832:2684354559]	auto[0]	126	1			T2	1		T11	1		T25	3
auto[2550136832:2684354559]	auto[1]	7	1			T139	1		T277	1		T391	1
auto[2684354560:2818572287]	auto[0]	118	1			T2	1		T25	1		T48	1
auto[2684354560:2818572287]	auto[1]	12	1			T136	1		T130	1		T137	1
auto[2818572288:2952790015]	auto[0]	117	1			T2	1		T25	3		T136	1
auto[2818572288:2952790015]	auto[1]	7	1			T278	1		T315	1		T297	1
auto[2952790016:3087007743]	auto[0]	117	1			T11	1		T136	1		T22	1
auto[2952790016:3087007743]	auto[1]	10	1			T278	2		T403	1		T391	1
auto[3087007744:3221225471]	auto[0]	109	1			T11	1		T25	2		T22	2
auto[3087007744:3221225471]	auto[1]	13	1			T138	1		T139	1		T254	2
auto[3221225472:3355443199]	auto[0]	137	1			T16	1		T25	2		T48	1
auto[3221225472:3355443199]	auto[1]	10	1			T12	1		T136	1		T130	1
auto[3355443200:3489660927]	auto[0]	131	1			T2	1		T11	1		T12	1
auto[3355443200:3489660927]	auto[1]	11	1			T12	1		T108	1		T130	1
auto[3489660928:3623878655]	auto[0]	126	1			T2	1		T17	1		T25	3
auto[3489660928:3623878655]	auto[1]	5	1			T278	1		T234	2		T272	1
auto[3623878656:3758096383]	auto[0]	124	1			T25	1		T108	1		T22	1
auto[3623878656:3758096383]	auto[1]	11	1			T138	1		T284	1		T417	2
auto[3758096384:3892314111]	auto[0]	145	1			T12	1		T25	4		T48	2
auto[3758096384:3892314111]	auto[1]	8	1			T278	1		T403	1		T391	1
auto[3892314112:4026531839]	auto[0]	110	1			T25	3		T136	2		T22	2
auto[3892314112:4026531839]	auto[1]	5	1			T137	1		T268	1		T272	1
auto[4026531840:4160749567]	auto[0]	123	1			T2	1		T17	1		T25	2
auto[4026531840:4160749567]	auto[1]	4	1			T138	1		T284	1		T269	1
auto[4160749568:4294967295]	auto[0]	135	1			T17	1		T25	1		T48	1
auto[4160749568:4294967295]	auto[1]	16	1			T278	1		T138	1		T139	1