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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4414 1 T2 12 T11 12 T12 12
auto[1] 2155 1 T11 2 T15 6 T16 4


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 188 1 T45 2 T25 8 T48 2
auto[134217728:268435455] 216 1 T15 2 T72 2 T22 2
auto[268435456:402653183] 230 1 T25 10 T48 2 T136 2
auto[402653184:536870911] 160 1 T12 2 T25 2 T48 2
auto[536870912:671088639] 186 1 T11 2 T25 2 T23 2
auto[671088640:805306367] 172 1 T15 2 T25 2 T48 4
auto[805306368:939524095] 230 1 T25 2 T55 2 T129 2
auto[939524096:1073741823] 192 1 T25 2 T106 2 T55 8
auto[1073741824:1207959551] 192 1 T11 2 T25 6 T53 2
auto[1207959552:1342177279] 244 1 T25 2 T48 2 T4 2
auto[1342177280:1476395007] 196 1 T25 4 T53 2 T55 4
auto[1476395008:1610612735] 155 1 T2 2 T16 2 T22 4
auto[1610612736:1744830463] 212 1 T25 4 T22 4 T106 4
auto[1744830464:1879048191] 220 1 T25 4 T36 4 T136 2
auto[1879048192:2013265919] 244 1 T45 4 T25 10 T48 4
auto[2013265920:2147483647] 206 1 T12 2 T25 6 T108 2
auto[2147483648:2281701375] 208 1 T2 2 T25 8 T199 2
auto[2281701376:2415919103] 212 1 T11 2 T55 4 T57 2
auto[2415919104:2550136831] 182 1 T2 2 T25 4 T48 2
auto[2550136832:2684354559] 206 1 T25 6 T48 2 T53 2
auto[2684354560:2818572287] 182 1 T12 2 T25 4 T53 2
auto[2818572288:2952790015] 212 1 T11 2 T12 2 T15 4
auto[2952790016:3087007743] 218 1 T25 4 T106 2 T55 2
auto[3087007744:3221225471] 196 1 T17 2 T108 2 T106 2
auto[3221225472:3355443199] 206 1 T45 2 T25 4 T48 6
auto[3355443200:3489660927] 200 1 T45 2 T25 2 T22 2
auto[3489660928:3623878655] 234 1 T11 4 T12 2 T25 12
auto[3623878656:3758096383] 208 1 T2 2 T15 4 T25 2
auto[3758096384:3892314111] 174 1 T25 2 T48 2 T106 2
auto[3892314112:4026531839] 218 1 T25 2 T106 6 T126 2
auto[4026531840:4160749567] 236 1 T2 2 T11 2 T16 2
auto[4160749568:4294967295] 234 1 T2 2 T12 2 T25 2


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 120 1 T45 2 T25 4 T48 2
auto[0:134217727] auto[1] 68 1 T25 4 T38 2 T204 2
auto[134217728:268435455] auto[0] 140 1 T72 2 T129 2 T200 2
auto[134217728:268435455] auto[1] 76 1 T15 2 T22 2 T55 2
auto[268435456:402653183] auto[0] 136 1 T25 8 T48 2 T136 2
auto[268435456:402653183] auto[1] 94 1 T25 2 T106 2 T129 2
auto[402653184:536870911] auto[0] 102 1 T12 2 T25 2 T48 2
auto[402653184:536870911] auto[1] 58 1 T55 2 T5 2 T419 2
auto[536870912:671088639] auto[0] 132 1 T11 2 T25 2 T128 2
auto[536870912:671088639] auto[1] 54 1 T23 2 T261 2 T299 2
auto[671088640:805306367] auto[0] 108 1 T15 2 T25 2 T48 4
auto[671088640:805306367] auto[1] 64 1 T108 2 T55 4 T61 2
auto[805306368:939524095] auto[0] 166 1 T25 2 T55 2 T129 2
auto[805306368:939524095] auto[1] 64 1 T405 2 T202 2 T66 2
auto[939524096:1073741823] auto[0] 128 1 T25 2 T106 2 T55 2
auto[939524096:1073741823] auto[1] 64 1 T55 6 T204 2 T86 2
auto[1073741824:1207959551] auto[0] 136 1 T11 2 T25 6 T53 2
auto[1073741824:1207959551] auto[1] 56 1 T55 2 T61 4 T208 2
auto[1207959552:1342177279] auto[0] 140 1 T25 2 T48 2 T55 2
auto[1207959552:1342177279] auto[1] 104 1 T4 2 T95 2 T68 2
auto[1342177280:1476395007] auto[0] 120 1 T25 4 T53 2 T55 2
auto[1342177280:1476395007] auto[1] 76 1 T55 2 T129 2 T38 2
auto[1476395008:1610612735] auto[0] 120 1 T2 2 T22 2 T130 6
auto[1476395008:1610612735] auto[1] 35 1 T16 2 T22 2 T109 2
auto[1610612736:1744830463] auto[0] 138 1 T25 4 T22 4 T106 2
auto[1610612736:1744830463] auto[1] 74 1 T106 2 T55 4 T61 2
auto[1744830464:1879048191] auto[0] 154 1 T25 4 T136 2 T55 2
auto[1744830464:1879048191] auto[1] 66 1 T36 4 T68 2 T139 2
auto[1879048192:2013265919] auto[0] 158 1 T45 4 T25 10 T48 4
auto[1879048192:2013265919] auto[1] 86 1 T55 2 T92 2 T58 2
auto[2013265920:2147483647] auto[0] 132 1 T12 2 T25 4 T108 2
auto[2013265920:2147483647] auto[1] 74 1 T25 2 T106 2 T57 2
auto[2147483648:2281701375] auto[0] 130 1 T2 2 T25 6 T109 2
auto[2147483648:2281701375] auto[1] 78 1 T25 2 T199 2 T61 4
auto[2281701376:2415919103] auto[0] 136 1 T11 2 T55 4 T57 2
auto[2281701376:2415919103] auto[1] 76 1 T419 2 T121 2 T59 2
auto[2415919104:2550136831] auto[0] 132 1 T2 2 T25 4 T48 2
auto[2415919104:2550136831] auto[1] 50 1 T55 2 T6 2 T419 2
auto[2550136832:2684354559] auto[0] 156 1 T25 2 T48 2 T53 2
auto[2550136832:2684354559] auto[1] 50 1 T25 4 T55 2 T321 2
auto[2684354560:2818572287] auto[0] 124 1 T12 2 T25 4 T106 2
auto[2684354560:2818572287] auto[1] 58 1 T53 2 T204 2 T5 2
auto[2818572288:2952790015] auto[0] 154 1 T12 2 T15 2 T25 4
auto[2818572288:2952790015] auto[1] 58 1 T11 2 T15 2 T128 2
auto[2952790016:3087007743] auto[0] 126 1 T25 4 T55 2 T322 2
auto[2952790016:3087007743] auto[1] 92 1 T106 2 T129 2 T198 2
auto[3087007744:3221225471] auto[0] 140 1 T108 2 T106 2 T55 2
auto[3087007744:3221225471] auto[1] 56 1 T17 2 T126 2 T109 2
auto[3221225472:3355443199] auto[0] 140 1 T25 4 T48 6 T136 2
auto[3221225472:3355443199] auto[1] 66 1 T45 2 T61 6 T68 2
auto[3355443200:3489660927] auto[0] 148 1 T25 2 T22 2 T106 2
auto[3355443200:3489660927] auto[1] 52 1 T45 2 T126 2 T205 2
auto[3489660928:3623878655] auto[0] 164 1 T11 4 T12 2 T25 12
auto[3489660928:3623878655] auto[1] 70 1 T106 2 T121 2 T252 2
auto[3623878656:3758096383] auto[0] 134 1 T2 2 T15 2 T25 2
auto[3623878656:3758096383] auto[1] 74 1 T15 2 T128 2 T261 2
auto[3758096384:3892314111] auto[0] 114 1 T25 2 T48 2 T55 2
auto[3758096384:3892314111] auto[1] 60 1 T106 2 T132 2 T204 2
auto[3892314112:4026531839] auto[0] 148 1 T25 2 T106 4 T126 2
auto[3892314112:4026531839] auto[1] 70 1 T106 2 T129 2 T60 2
auto[4026531840:4160749567] auto[0] 182 1 T2 2 T11 2 T25 4
auto[4026531840:4160749567] auto[1] 54 1 T16 2 T17 2 T55 2
auto[4160749568:4294967295] auto[0] 156 1 T2 2 T12 2 T25 2
auto[4160749568:4294967295] auto[1] 78 1 T106 2 T55 2 T63 2

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