Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.75 99.04 98.11 98.44 100.00 99.02 98.41 91.24


Total test records in report: 1090
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T1008 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1894645179 Jul 31 07:17:17 PM PDT 24 Jul 31 07:17:20 PM PDT 24 45109173 ps
T1009 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3814249901 Jul 31 07:17:25 PM PDT 24 Jul 31 07:17:26 PM PDT 24 31111367 ps
T169 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.837246185 Jul 31 07:17:24 PM PDT 24 Jul 31 07:17:29 PM PDT 24 106138233 ps
T1010 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3727074004 Jul 31 07:16:49 PM PDT 24 Jul 31 07:17:02 PM PDT 24 953270171 ps
T1011 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1057564581 Jul 31 07:17:18 PM PDT 24 Jul 31 07:17:20 PM PDT 24 117539759 ps
T1012 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.662552178 Jul 31 07:17:16 PM PDT 24 Jul 31 07:17:18 PM PDT 24 115127978 ps
T1013 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3967854425 Jul 31 07:17:29 PM PDT 24 Jul 31 07:17:31 PM PDT 24 92961645 ps
T1014 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3732857050 Jul 31 07:17:27 PM PDT 24 Jul 31 07:17:28 PM PDT 24 6749102 ps
T159 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2267094294 Jul 31 07:17:11 PM PDT 24 Jul 31 07:17:16 PM PDT 24 243177952 ps
T1015 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2806151706 Jul 31 07:17:17 PM PDT 24 Jul 31 07:17:24 PM PDT 24 503285609 ps
T1016 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.562550759 Jul 31 07:16:49 PM PDT 24 Jul 31 07:16:52 PM PDT 24 169739157 ps
T1017 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3292443515 Jul 31 07:17:18 PM PDT 24 Jul 31 07:17:21 PM PDT 24 249940741 ps
T1018 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.109692559 Jul 31 07:16:50 PM PDT 24 Jul 31 07:16:52 PM PDT 24 44043502 ps
T168 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1299765144 Jul 31 07:16:52 PM PDT 24 Jul 31 07:16:55 PM PDT 24 517052436 ps
T1019 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3559215345 Jul 31 07:16:56 PM PDT 24 Jul 31 07:17:01 PM PDT 24 195637618 ps
T1020 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3905127308 Jul 31 07:17:25 PM PDT 24 Jul 31 07:17:26 PM PDT 24 106851363 ps
T1021 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.532715985 Jul 31 07:16:50 PM PDT 24 Jul 31 07:16:51 PM PDT 24 21381738 ps
T1022 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2775856927 Jul 31 07:17:19 PM PDT 24 Jul 31 07:17:20 PM PDT 24 16583126 ps
T1023 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2111845838 Jul 31 07:17:04 PM PDT 24 Jul 31 07:17:10 PM PDT 24 251944282 ps
T1024 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.52138648 Jul 31 07:17:24 PM PDT 24 Jul 31 07:17:26 PM PDT 24 56711992 ps
T1025 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1159986522 Jul 31 07:17:24 PM PDT 24 Jul 31 07:17:25 PM PDT 24 39942120 ps
T1026 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2477040558 Jul 31 07:17:24 PM PDT 24 Jul 31 07:17:26 PM PDT 24 69438473 ps
T1027 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3665379827 Jul 31 07:17:05 PM PDT 24 Jul 31 07:17:07 PM PDT 24 128137447 ps
T1028 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.76568790 Jul 31 07:17:17 PM PDT 24 Jul 31 07:17:22 PM PDT 24 151267019 ps
T1029 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.94353736 Jul 31 07:17:18 PM PDT 24 Jul 31 07:17:19 PM PDT 24 27461280 ps
T1030 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3034279635 Jul 31 07:17:16 PM PDT 24 Jul 31 07:17:18 PM PDT 24 42222673 ps
T1031 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3186201359 Jul 31 07:16:45 PM PDT 24 Jul 31 07:16:50 PM PDT 24 311391416 ps
T1032 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1875730674 Jul 31 07:17:33 PM PDT 24 Jul 31 07:17:34 PM PDT 24 10629142 ps
T1033 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1037145652 Jul 31 07:16:44 PM PDT 24 Jul 31 07:16:54 PM PDT 24 220439899 ps
T1034 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3904578320 Jul 31 07:17:05 PM PDT 24 Jul 31 07:17:07 PM PDT 24 22141950 ps
T1035 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1687547730 Jul 31 07:16:53 PM PDT 24 Jul 31 07:16:55 PM PDT 24 51347727 ps
T1036 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.643450421 Jul 31 07:17:18 PM PDT 24 Jul 31 07:17:19 PM PDT 24 22485495 ps
T1037 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3751332499 Jul 31 07:16:52 PM PDT 24 Jul 31 07:16:54 PM PDT 24 193884387 ps
T1038 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3760779845 Jul 31 07:17:27 PM PDT 24 Jul 31 07:17:28 PM PDT 24 26649612 ps
T1039 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2474707744 Jul 31 07:17:06 PM PDT 24 Jul 31 07:17:08 PM PDT 24 870851456 ps
T1040 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1768054459 Jul 31 07:17:19 PM PDT 24 Jul 31 07:17:20 PM PDT 24 124632539 ps
T1041 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2163061160 Jul 31 07:16:57 PM PDT 24 Jul 31 07:16:59 PM PDT 24 124349960 ps
T1042 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2401433960 Jul 31 07:16:47 PM PDT 24 Jul 31 07:16:56 PM PDT 24 326877370 ps
T1043 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3796674196 Jul 31 07:16:45 PM PDT 24 Jul 31 07:16:46 PM PDT 24 105308361 ps
T1044 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.916192999 Jul 31 07:17:18 PM PDT 24 Jul 31 07:17:19 PM PDT 24 114581380 ps
T164 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2161576409 Jul 31 07:16:52 PM PDT 24 Jul 31 07:16:59 PM PDT 24 151889889 ps
T1045 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1655509728 Jul 31 07:16:55 PM PDT 24 Jul 31 07:16:59 PM PDT 24 85483311 ps
T1046 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.753762005 Jul 31 07:17:18 PM PDT 24 Jul 31 07:17:21 PM PDT 24 328767092 ps
T162 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.77933548 Jul 31 07:16:55 PM PDT 24 Jul 31 07:16:58 PM PDT 24 101265864 ps
T1047 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3350825345 Jul 31 07:16:53 PM PDT 24 Jul 31 07:16:55 PM PDT 24 98744356 ps
T1048 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.997451937 Jul 31 07:16:45 PM PDT 24 Jul 31 07:16:46 PM PDT 24 17430451 ps
T1049 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3176021818 Jul 31 07:16:50 PM PDT 24 Jul 31 07:16:51 PM PDT 24 14952586 ps
T1050 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3514540271 Jul 31 07:17:18 PM PDT 24 Jul 31 07:17:18 PM PDT 24 18258088 ps
T1051 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1279667302 Jul 31 07:16:55 PM PDT 24 Jul 31 07:16:57 PM PDT 24 161387042 ps
T1052 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.654411399 Jul 31 07:16:55 PM PDT 24 Jul 31 07:16:56 PM PDT 24 50114910 ps
T1053 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3744204117 Jul 31 07:17:25 PM PDT 24 Jul 31 07:17:26 PM PDT 24 40643275 ps
T1054 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.4092109641 Jul 31 07:16:50 PM PDT 24 Jul 31 07:16:55 PM PDT 24 144397687 ps
T173 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2561761262 Jul 31 07:17:17 PM PDT 24 Jul 31 07:17:22 PM PDT 24 105604169 ps
T1055 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.633559275 Jul 31 07:16:43 PM PDT 24 Jul 31 07:16:44 PM PDT 24 12470236 ps
T1056 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2030821157 Jul 31 07:17:16 PM PDT 24 Jul 31 07:17:20 PM PDT 24 121167577 ps
T1057 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2241857644 Jul 31 07:16:51 PM PDT 24 Jul 31 07:16:53 PM PDT 24 20418883 ps
T1058 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.897615898 Jul 31 07:16:57 PM PDT 24 Jul 31 07:16:58 PM PDT 24 29868364 ps
T1059 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1059833549 Jul 31 07:17:18 PM PDT 24 Jul 31 07:17:19 PM PDT 24 32566449 ps
T1060 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.4087581295 Jul 31 07:17:29 PM PDT 24 Jul 31 07:17:31 PM PDT 24 54242011 ps
T1061 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2678986864 Jul 31 07:16:49 PM PDT 24 Jul 31 07:16:50 PM PDT 24 34840015 ps
T1062 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3806878374 Jul 31 07:17:17 PM PDT 24 Jul 31 07:17:18 PM PDT 24 109279127 ps
T1063 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1758889658 Jul 31 07:16:52 PM PDT 24 Jul 31 07:16:54 PM PDT 24 54065098 ps
T1064 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.161034288 Jul 31 07:17:29 PM PDT 24 Jul 31 07:17:30 PM PDT 24 11205679 ps
T1065 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.291084513 Jul 31 07:17:11 PM PDT 24 Jul 31 07:17:14 PM PDT 24 78950985 ps
T1066 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1803414821 Jul 31 07:16:51 PM PDT 24 Jul 31 07:16:58 PM PDT 24 492651604 ps
T1067 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.4164260053 Jul 31 07:17:34 PM PDT 24 Jul 31 07:17:35 PM PDT 24 34622408 ps
T1068 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3058954218 Jul 31 07:17:27 PM PDT 24 Jul 31 07:17:28 PM PDT 24 24294742 ps
T1069 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.4020193003 Jul 31 07:16:55 PM PDT 24 Jul 31 07:16:58 PM PDT 24 444350770 ps
T1070 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3530772985 Jul 31 07:17:04 PM PDT 24 Jul 31 07:17:06 PM PDT 24 112984319 ps
T1071 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2737888174 Jul 31 07:16:43 PM PDT 24 Jul 31 07:16:46 PM PDT 24 40117131 ps
T1072 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.368578065 Jul 31 07:16:52 PM PDT 24 Jul 31 07:16:54 PM PDT 24 130031610 ps
T1073 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1704353739 Jul 31 07:17:17 PM PDT 24 Jul 31 07:17:18 PM PDT 24 93708416 ps
T1074 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.952324731 Jul 31 07:17:34 PM PDT 24 Jul 31 07:17:35 PM PDT 24 30285058 ps
T1075 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3457159028 Jul 31 07:17:23 PM PDT 24 Jul 31 07:17:24 PM PDT 24 14318942 ps
T1076 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3701786248 Jul 31 07:16:54 PM PDT 24 Jul 31 07:17:00 PM PDT 24 214179397 ps
T1077 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2526611077 Jul 31 07:16:49 PM PDT 24 Jul 31 07:16:50 PM PDT 24 8480884 ps
T1078 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3820383949 Jul 31 07:16:45 PM PDT 24 Jul 31 07:16:47 PM PDT 24 45987576 ps
T1079 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.732796943 Jul 31 07:16:54 PM PDT 24 Jul 31 07:17:10 PM PDT 24 912375161 ps
T1080 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2723970696 Jul 31 07:16:55 PM PDT 24 Jul 31 07:16:56 PM PDT 24 10594123 ps
T1081 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3471370793 Jul 31 07:17:18 PM PDT 24 Jul 31 07:17:22 PM PDT 24 415828451 ps
T1082 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.898887324 Jul 31 07:17:25 PM PDT 24 Jul 31 07:17:25 PM PDT 24 27328154 ps
T1083 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3220178336 Jul 31 07:17:26 PM PDT 24 Jul 31 07:17:27 PM PDT 24 10485384 ps
T1084 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3278841875 Jul 31 07:16:51 PM PDT 24 Jul 31 07:16:52 PM PDT 24 111046492 ps
T1085 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3165823427 Jul 31 07:16:51 PM PDT 24 Jul 31 07:16:54 PM PDT 24 178347989 ps
T1086 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1903733625 Jul 31 07:16:54 PM PDT 24 Jul 31 07:16:56 PM PDT 24 232432222 ps
T165 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2664037309 Jul 31 07:17:17 PM PDT 24 Jul 31 07:17:22 PM PDT 24 181878390 ps
T1087 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2636275062 Jul 31 07:16:57 PM PDT 24 Jul 31 07:16:59 PM PDT 24 135855621 ps
T1088 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.53554329 Jul 31 07:17:26 PM PDT 24 Jul 31 07:17:27 PM PDT 24 10243995 ps
T1089 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1294746952 Jul 31 07:17:33 PM PDT 24 Jul 31 07:17:34 PM PDT 24 11672591 ps
T1090 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.4088078028 Jul 31 07:17:18 PM PDT 24 Jul 31 07:17:21 PM PDT 24 206179555 ps

Test location /workspace/coverage/default/35.keymgr_lc_disable.2749297593
Short name T15
Test name
Test status
Simulation time 90157945 ps
CPU time 4.11 seconds
Started Jul 31 05:38:21 PM PDT 24
Finished Jul 31 05:38:25 PM PDT 24
Peak memory 209876 kb
Host smart-8c20ebeb-905f-41bd-9538-d234ded9328c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749297593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2749297593
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3861503706
Short name T25
Test name
Test status
Simulation time 2744559537 ps
CPU time 54.49 seconds
Started Jul 31 05:37:55 PM PDT 24
Finished Jul 31 05:38:49 PM PDT 24
Peak memory 217840 kb
Host smart-11a315a8-e0c1-454a-8b37-37d2c52b7595
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861503706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3861503706
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.683161035
Short name T55
Test name
Test status
Simulation time 3103836124 ps
CPU time 20.13 seconds
Started Jul 31 05:38:04 PM PDT 24
Finished Jul 31 05:38:24 PM PDT 24
Peak memory 222604 kb
Host smart-5612fca7-6942-4dd7-8eb8-d106c2ebf6c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683161035 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.683161035
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.4056045345
Short name T8
Test name
Test status
Simulation time 896903087 ps
CPU time 5.45 seconds
Started Jul 31 05:36:16 PM PDT 24
Finished Jul 31 05:36:22 PM PDT 24
Peak memory 229132 kb
Host smart-d89b0cd5-e2f2-4613-8acb-f25c5768eab5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056045345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.4056045345
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.3987775878
Short name T123
Test name
Test status
Simulation time 494293702 ps
CPU time 17.5 seconds
Started Jul 31 05:38:40 PM PDT 24
Finished Jul 31 05:38:57 PM PDT 24
Peak memory 222488 kb
Host smart-2d9e3137-edb8-4a7a-b227-4507de550e15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987775878 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.3987775878
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1630577784
Short name T59
Test name
Test status
Simulation time 2829725393 ps
CPU time 40.62 seconds
Started Jul 31 05:36:57 PM PDT 24
Finished Jul 31 05:37:38 PM PDT 24
Peak memory 215436 kb
Host smart-932fdc16-7699-47f9-afee-3adc1340d5c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630577784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1630577784
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3976415091
Short name T61
Test name
Test status
Simulation time 7475002627 ps
CPU time 38.52 seconds
Started Jul 31 05:37:33 PM PDT 24
Finished Jul 31 05:38:12 PM PDT 24
Peak memory 222476 kb
Host smart-c9690b26-3998-48ef-97e4-fcfbac008027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976415091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3976415091
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.4180760699
Short name T139
Test name
Test status
Simulation time 286777436 ps
CPU time 14.95 seconds
Started Jul 31 05:36:46 PM PDT 24
Finished Jul 31 05:37:01 PM PDT 24
Peak memory 222448 kb
Host smart-8b3c003e-0fde-4060-8270-37da67bba362
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4180760699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.4180760699
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.4148030259
Short name T287
Test name
Test status
Simulation time 473679053 ps
CPU time 3.63 seconds
Started Jul 31 05:37:33 PM PDT 24
Finished Jul 31 05:37:37 PM PDT 24
Peak memory 214340 kb
Host smart-3a854e75-27ff-46ed-b2df-0e46c3225053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148030259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.4148030259
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1916283587
Short name T7
Test name
Test status
Simulation time 91956717 ps
CPU time 2.29 seconds
Started Jul 31 05:36:33 PM PDT 24
Finished Jul 31 05:36:35 PM PDT 24
Peak memory 217224 kb
Host smart-6c9cc79a-2e6d-43ba-afb9-2d05ecf0867b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916283587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1916283587
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3074900577
Short name T111
Test name
Test status
Simulation time 87528733 ps
CPU time 3.85 seconds
Started Jul 31 07:16:54 PM PDT 24
Finished Jul 31 07:16:57 PM PDT 24
Peak memory 214664 kb
Host smart-5785a231-af38-4bb1-8849-e16a9dc1adf6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074900577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3074900577
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.236647869
Short name T254
Test name
Test status
Simulation time 822724359 ps
CPU time 43.46 seconds
Started Jul 31 05:38:38 PM PDT 24
Finished Jul 31 05:39:22 PM PDT 24
Peak memory 215688 kb
Host smart-b2be0054-09f6-4907-8625-dfaebaeb5089
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=236647869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.236647869
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3054984195
Short name T68
Test name
Test status
Simulation time 1047091256 ps
CPU time 20.95 seconds
Started Jul 31 05:39:05 PM PDT 24
Finished Jul 31 05:39:26 PM PDT 24
Peak memory 217056 kb
Host smart-ff6e4a56-b2cc-472e-9f7d-4ef9cf6aba95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054984195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3054984195
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2730621305
Short name T12
Test name
Test status
Simulation time 103619944 ps
CPU time 5.16 seconds
Started Jul 31 05:38:54 PM PDT 24
Finished Jul 31 05:38:59 PM PDT 24
Peak memory 215352 kb
Host smart-7e8a1399-a8a0-4715-bb74-1bb1663c8221
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2730621305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2730621305
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2157084443
Short name T93
Test name
Test status
Simulation time 94184353 ps
CPU time 3.8 seconds
Started Jul 31 05:37:31 PM PDT 24
Finished Jul 31 05:37:35 PM PDT 24
Peak memory 210240 kb
Host smart-db020183-74d4-4c09-8ec3-16c9cc8ea3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157084443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2157084443
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3748043006
Short name T234
Test name
Test status
Simulation time 1059911895 ps
CPU time 26.64 seconds
Started Jul 31 05:37:03 PM PDT 24
Finished Jul 31 05:37:30 PM PDT 24
Peak memory 215100 kb
Host smart-8e31ec76-d928-400c-af08-4340e5eb39d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3748043006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3748043006
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.498132210
Short name T114
Test name
Test status
Simulation time 373186879 ps
CPU time 3.03 seconds
Started Jul 31 07:16:43 PM PDT 24
Finished Jul 31 07:16:47 PM PDT 24
Peak memory 214672 kb
Host smart-ce667d4e-7610-48fd-9493-179c106a9c48
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498132210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.498132210
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2945434520
Short name T106
Test name
Test status
Simulation time 1245672413 ps
CPU time 20.76 seconds
Started Jul 31 05:38:23 PM PDT 24
Finished Jul 31 05:38:44 PM PDT 24
Peak memory 222500 kb
Host smart-d7338eea-74e2-4749-bc43-2486071754e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945434520 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2945434520
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1147156344
Short name T391
Test name
Test status
Simulation time 1438466156 ps
CPU time 10.84 seconds
Started Jul 31 05:38:31 PM PDT 24
Finished Jul 31 05:38:42 PM PDT 24
Peak memory 214796 kb
Host smart-591a5086-5beb-45ff-96a2-29dfa963233e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1147156344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1147156344
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1589189263
Short name T1
Test name
Test status
Simulation time 79259909 ps
CPU time 2.61 seconds
Started Jul 31 05:36:40 PM PDT 24
Finished Jul 31 05:36:43 PM PDT 24
Peak memory 209784 kb
Host smart-fda63754-1b17-4422-8d19-6ef6adca69a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589189263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1589189263
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1903795721
Short name T19
Test name
Test status
Simulation time 93155144 ps
CPU time 4.52 seconds
Started Jul 31 05:36:12 PM PDT 24
Finished Jul 31 05:36:17 PM PDT 24
Peak memory 215636 kb
Host smart-4b3a9c56-3008-47d7-94b9-6029d50e2ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903795721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1903795721
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3955202261
Short name T220
Test name
Test status
Simulation time 356729304 ps
CPU time 3.53 seconds
Started Jul 31 05:38:53 PM PDT 24
Finished Jul 31 05:38:56 PM PDT 24
Peak memory 217160 kb
Host smart-eb2d9b56-d970-4fa0-9dcc-d5de9be7957a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955202261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3955202261
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3441249877
Short name T100
Test name
Test status
Simulation time 197684821 ps
CPU time 4.52 seconds
Started Jul 31 05:36:47 PM PDT 24
Finished Jul 31 05:36:52 PM PDT 24
Peak memory 214448 kb
Host smart-c07e448c-5cba-46f6-a41e-a58b4bb411f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441249877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3441249877
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3987150630
Short name T148
Test name
Test status
Simulation time 336624949 ps
CPU time 3.51 seconds
Started Jul 31 05:36:48 PM PDT 24
Finished Jul 31 05:36:52 PM PDT 24
Peak memory 222616 kb
Host smart-ea2c992c-90bd-4d42-bb40-2465975f6415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987150630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3987150630
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1668972094
Short name T425
Test name
Test status
Simulation time 503295399 ps
CPU time 12.58 seconds
Started Jul 31 05:37:19 PM PDT 24
Finished Jul 31 05:37:31 PM PDT 24
Peak memory 214268 kb
Host smart-1a7518f1-dc1d-4178-babf-9689bd71a08a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1668972094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1668972094
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2298498771
Short name T657
Test name
Test status
Simulation time 149058383 ps
CPU time 5.96 seconds
Started Jul 31 05:36:23 PM PDT 24
Finished Jul 31 05:36:29 PM PDT 24
Peak memory 214296 kb
Host smart-defd550b-03df-4ebb-8df7-cc44bcdd65cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298498771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2298498771
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3477667068
Short name T239
Test name
Test status
Simulation time 571689639 ps
CPU time 27.11 seconds
Started Jul 31 05:37:08 PM PDT 24
Finished Jul 31 05:37:35 PM PDT 24
Peak memory 222384 kb
Host smart-4827e6c8-3560-47fd-8e78-89441d71b023
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477667068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3477667068
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1416404460
Short name T272
Test name
Test status
Simulation time 2159562580 ps
CPU time 60.99 seconds
Started Jul 31 05:36:08 PM PDT 24
Finished Jul 31 05:37:09 PM PDT 24
Peak memory 216044 kb
Host smart-36866e78-923e-447a-9b7f-354412ff4103
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1416404460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1416404460
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.406684079
Short name T160
Test name
Test status
Simulation time 1017684780 ps
CPU time 9.35 seconds
Started Jul 31 07:17:18 PM PDT 24
Finished Jul 31 07:17:27 PM PDT 24
Peak memory 216736 kb
Host smart-8decc4c2-0801-4728-9291-3dedf02ccee1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406684079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err
.406684079
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.2535295449
Short name T121
Test name
Test status
Simulation time 1782879320 ps
CPU time 18.36 seconds
Started Jul 31 05:36:13 PM PDT 24
Finished Jul 31 05:36:32 PM PDT 24
Peak memory 222560 kb
Host smart-e33e2da9-6cba-49cd-98b8-0a2cd0278a68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535295449 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.2535295449
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.4201222878
Short name T278
Test name
Test status
Simulation time 2159865220 ps
CPU time 28.02 seconds
Started Jul 31 05:36:43 PM PDT 24
Finished Jul 31 05:37:11 PM PDT 24
Peak memory 214320 kb
Host smart-c126b859-735a-4e36-b24d-3c609876ba96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4201222878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.4201222878
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1652914262
Short name T153
Test name
Test status
Simulation time 100837080 ps
CPU time 5.58 seconds
Started Jul 31 07:16:54 PM PDT 24
Finished Jul 31 07:16:59 PM PDT 24
Peak memory 214392 kb
Host smart-6a56e129-7545-40b4-b104-87e2de812cdb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652914262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1652914262
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.4268725452
Short name T446
Test name
Test status
Simulation time 39652559 ps
CPU time 0.86 seconds
Started Jul 31 05:37:04 PM PDT 24
Finished Jul 31 05:37:05 PM PDT 24
Peak memory 205908 kb
Host smart-3780cb60-241f-4427-a843-7ef0191c4bc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268725452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.4268725452
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1040499719
Short name T22
Test name
Test status
Simulation time 2454473460 ps
CPU time 9.89 seconds
Started Jul 31 05:37:40 PM PDT 24
Finished Jul 31 05:37:50 PM PDT 24
Peak memory 220420 kb
Host smart-c9108b7c-e91c-4d7d-bd42-351a4b0cc849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040499719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1040499719
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.795699506
Short name T46
Test name
Test status
Simulation time 511319220 ps
CPU time 12.06 seconds
Started Jul 31 05:36:29 PM PDT 24
Finished Jul 31 05:36:42 PM PDT 24
Peak memory 215920 kb
Host smart-65bc279a-2bf9-4a0e-b058-b709598094b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795699506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.795699506
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.837246185
Short name T169
Test name
Test status
Simulation time 106138233 ps
CPU time 4.56 seconds
Started Jul 31 07:17:24 PM PDT 24
Finished Jul 31 07:17:29 PM PDT 24
Peak memory 214460 kb
Host smart-954425ce-3b30-4531-a06c-90d5b22d492f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837246185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err
.837246185
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2563293207
Short name T70
Test name
Test status
Simulation time 551979521 ps
CPU time 13.76 seconds
Started Jul 31 05:36:09 PM PDT 24
Finished Jul 31 05:36:23 PM PDT 24
Peak memory 222712 kb
Host smart-e3a0900a-e5d2-4a77-aa10-da6d66dde98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563293207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2563293207
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1855087536
Short name T296
Test name
Test status
Simulation time 476618532 ps
CPU time 13.2 seconds
Started Jul 31 05:37:50 PM PDT 24
Finished Jul 31 05:38:03 PM PDT 24
Peak memory 215416 kb
Host smart-0e00bd1b-21d0-4dd7-b9de-58e3e9f2d171
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855087536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1855087536
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1429597313
Short name T720
Test name
Test status
Simulation time 219460000 ps
CPU time 5.15 seconds
Started Jul 31 05:38:59 PM PDT 24
Finished Jul 31 05:39:04 PM PDT 24
Peak memory 214340 kb
Host smart-aa0201ee-9682-4a39-9655-d3ce844f2d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429597313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1429597313
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.4238878476
Short name T404
Test name
Test status
Simulation time 214567838 ps
CPU time 11.9 seconds
Started Jul 31 05:39:05 PM PDT 24
Finished Jul 31 05:39:17 PM PDT 24
Peak memory 222384 kb
Host smart-a172fbee-b5f1-462e-92bd-d11781409a35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4238878476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.4238878476
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2242518151
Short name T382
Test name
Test status
Simulation time 40919733 ps
CPU time 2.58 seconds
Started Jul 31 05:36:52 PM PDT 24
Finished Jul 31 05:36:55 PM PDT 24
Peak memory 214380 kb
Host smart-eedfc053-0725-429d-83b1-2ec1ef727721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242518151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2242518151
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.668850229
Short name T244
Test name
Test status
Simulation time 1083975325 ps
CPU time 2.83 seconds
Started Jul 31 05:37:11 PM PDT 24
Finished Jul 31 05:37:14 PM PDT 24
Peak memory 214356 kb
Host smart-142de86e-9cee-4068-ac29-3bee13eb8739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668850229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.668850229
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2664037309
Short name T165
Test name
Test status
Simulation time 181878390 ps
CPU time 4.56 seconds
Started Jul 31 07:17:17 PM PDT 24
Finished Jul 31 07:17:22 PM PDT 24
Peak memory 214416 kb
Host smart-d82a8ce1-68c8-447b-9311-c0aedcc83097
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664037309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2664037309
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3296029383
Short name T569
Test name
Test status
Simulation time 1647681494 ps
CPU time 4.68 seconds
Started Jul 31 05:38:59 PM PDT 24
Finished Jul 31 05:39:03 PM PDT 24
Peak memory 210392 kb
Host smart-09b37182-a2b5-49be-9a60-67cae1f35a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296029383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3296029383
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3457984166
Short name T119
Test name
Test status
Simulation time 1748244869 ps
CPU time 14.85 seconds
Started Jul 31 07:17:17 PM PDT 24
Finished Jul 31 07:17:32 PM PDT 24
Peak memory 220952 kb
Host smart-bdc58a09-0818-41a5-b71b-0b4c7a9e9276
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457984166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3457984166
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2398185357
Short name T146
Test name
Test status
Simulation time 78675126 ps
CPU time 5.42 seconds
Started Jul 31 05:37:14 PM PDT 24
Finished Jul 31 05:37:20 PM PDT 24
Peak memory 218780 kb
Host smart-8a9c5ca9-3e6b-4c2e-8a75-edfac7dc94dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398185357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2398185357
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1891334700
Short name T147
Test name
Test status
Simulation time 99413324 ps
CPU time 3.36 seconds
Started Jul 31 05:36:21 PM PDT 24
Finished Jul 31 05:36:24 PM PDT 24
Peak memory 216596 kb
Host smart-46872481-c739-4d1f-a86e-9e64fd14d3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891334700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1891334700
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3884245227
Short name T149
Test name
Test status
Simulation time 92670493 ps
CPU time 4.52 seconds
Started Jul 31 05:39:07 PM PDT 24
Finished Jul 31 05:39:11 PM PDT 24
Peak memory 218612 kb
Host smart-8ffce801-17fb-4b68-9014-b16a3030cf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884245227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3884245227
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.2695900905
Short name T5
Test name
Test status
Simulation time 311894117 ps
CPU time 9.14 seconds
Started Jul 31 05:37:27 PM PDT 24
Finished Jul 31 05:37:36 PM PDT 24
Peak memory 220028 kb
Host smart-74cf1b55-12d6-4479-9365-5b41ea9ea3ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695900905 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.2695900905
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.301593111
Short name T252
Test name
Test status
Simulation time 157312079 ps
CPU time 8.34 seconds
Started Jul 31 05:37:42 PM PDT 24
Finished Jul 31 05:37:50 PM PDT 24
Peak memory 222000 kb
Host smart-ce282756-35bf-467e-a61f-959cf0746bfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301593111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.301593111
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.690635929
Short name T281
Test name
Test status
Simulation time 286005723 ps
CPU time 4.88 seconds
Started Jul 31 05:38:19 PM PDT 24
Finished Jul 31 05:38:24 PM PDT 24
Peak memory 215484 kb
Host smart-8a4c9375-c911-4164-893d-d1d9232e2f6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=690635929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.690635929
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.1893846775
Short name T54
Test name
Test status
Simulation time 103552453 ps
CPU time 2.02 seconds
Started Jul 31 05:38:35 PM PDT 24
Finished Jul 31 05:38:37 PM PDT 24
Peak memory 214292 kb
Host smart-2f943695-8368-45e6-a305-bc5db3b84480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893846775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.1893846775
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.92553646
Short name T212
Test name
Test status
Simulation time 4255655454 ps
CPU time 39.09 seconds
Started Jul 31 05:39:07 PM PDT 24
Finished Jul 31 05:39:47 PM PDT 24
Peak memory 222448 kb
Host smart-0e8178aa-4fe8-45d3-918f-9526b59df288
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92553646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.92553646
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3170942513
Short name T726
Test name
Test status
Simulation time 412669627 ps
CPU time 10.97 seconds
Started Jul 31 05:39:02 PM PDT 24
Finished Jul 31 05:39:14 PM PDT 24
Peak memory 214668 kb
Host smart-90828280-1a83-40e3-8c6a-35b98d318033
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3170942513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3170942513
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3272842945
Short name T277
Test name
Test status
Simulation time 12251145102 ps
CPU time 33.12 seconds
Started Jul 31 05:36:30 PM PDT 24
Finished Jul 31 05:37:03 PM PDT 24
Peak memory 215164 kb
Host smart-9ca95147-d0c9-44a7-bef1-3941afa4f3f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3272842945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3272842945
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3826940276
Short name T10
Test name
Test status
Simulation time 1199810607 ps
CPU time 16.91 seconds
Started Jul 31 05:36:09 PM PDT 24
Finished Jul 31 05:36:26 PM PDT 24
Peak memory 238652 kb
Host smart-6db44f9f-19dc-4068-90b8-a9e68c590331
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826940276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3826940276
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3060567481
Short name T52
Test name
Test status
Simulation time 68545205 ps
CPU time 2.2 seconds
Started Jul 31 05:38:47 PM PDT 24
Finished Jul 31 05:38:50 PM PDT 24
Peak memory 214304 kb
Host smart-d283e204-a5c7-4bff-8a2f-0f677fb41c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060567481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3060567481
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3203766921
Short name T357
Test name
Test status
Simulation time 221561891 ps
CPU time 3.25 seconds
Started Jul 31 05:37:36 PM PDT 24
Finished Jul 31 05:37:40 PM PDT 24
Peak memory 222404 kb
Host smart-1f15e1aa-d50c-4b70-8588-49dc851f013a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203766921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3203766921
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1294095171
Short name T308
Test name
Test status
Simulation time 451319081 ps
CPU time 6.95 seconds
Started Jul 31 05:38:02 PM PDT 24
Finished Jul 31 05:38:09 PM PDT 24
Peak memory 214328 kb
Host smart-b007b021-4287-4bbe-b5ee-1ca05b1fdb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294095171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1294095171
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2884284036
Short name T229
Test name
Test status
Simulation time 2302048211 ps
CPU time 25.73 seconds
Started Jul 31 05:38:13 PM PDT 24
Finished Jul 31 05:38:39 PM PDT 24
Peak memory 222524 kb
Host smart-2d285d45-3a99-4372-89cb-ad6d417556ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884284036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2884284036
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3449093870
Short name T84
Test name
Test status
Simulation time 900026264 ps
CPU time 3.33 seconds
Started Jul 31 05:38:23 PM PDT 24
Finished Jul 31 05:38:26 PM PDT 24
Peak memory 208868 kb
Host smart-2164aee8-843b-4376-8966-17f9e1c26774
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449093870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3449093870
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.495246426
Short name T649
Test name
Test status
Simulation time 40604771692 ps
CPU time 213.81 seconds
Started Jul 31 05:38:51 PM PDT 24
Finished Jul 31 05:42:25 PM PDT 24
Peak memory 217232 kb
Host smart-56844d37-9d4f-4475-bba4-e3fc197e89f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495246426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.495246426
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1704870830
Short name T264
Test name
Test status
Simulation time 122007441 ps
CPU time 5.3 seconds
Started Jul 31 05:39:04 PM PDT 24
Finished Jul 31 05:39:09 PM PDT 24
Peak memory 214260 kb
Host smart-5ee36a9c-d113-4925-b193-731aa3a982f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704870830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1704870830
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2997332775
Short name T150
Test name
Test status
Simulation time 41144838 ps
CPU time 3.08 seconds
Started Jul 31 05:37:03 PM PDT 24
Finished Jul 31 05:37:06 PM PDT 24
Peak memory 222616 kb
Host smart-fdfee9db-3ef5-4d9e-b52a-6b5627438524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997332775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2997332775
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3422922819
Short name T152
Test name
Test status
Simulation time 624343676 ps
CPU time 3.5 seconds
Started Jul 31 05:37:40 PM PDT 24
Finished Jul 31 05:37:43 PM PDT 24
Peak memory 218196 kb
Host smart-fe5ada8a-cc79-404e-9c18-090910274fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422922819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3422922819
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.503747429
Short name T396
Test name
Test status
Simulation time 71983918 ps
CPU time 3.77 seconds
Started Jul 31 05:36:08 PM PDT 24
Finished Jul 31 05:36:12 PM PDT 24
Peak memory 222304 kb
Host smart-ceb4a486-791f-4faf-9fda-e3f0dbb432b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503747429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.503747429
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1575330105
Short name T334
Test name
Test status
Simulation time 163367511 ps
CPU time 5.47 seconds
Started Jul 31 05:36:47 PM PDT 24
Finished Jul 31 05:36:53 PM PDT 24
Peak memory 208648 kb
Host smart-02a7c9a8-66b3-47f6-89a6-36b9d515e371
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575330105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1575330105
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1819682705
Short name T205
Test name
Test status
Simulation time 190392025 ps
CPU time 4.82 seconds
Started Jul 31 05:36:57 PM PDT 24
Finished Jul 31 05:37:02 PM PDT 24
Peak memory 214316 kb
Host smart-427e838c-9536-4bcc-9519-9824baf766d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819682705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1819682705
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.1262475617
Short name T43
Test name
Test status
Simulation time 981186840 ps
CPU time 4.27 seconds
Started Jul 31 05:36:51 PM PDT 24
Finished Jul 31 05:36:55 PM PDT 24
Peak memory 210784 kb
Host smart-0e926724-d970-4023-afe4-fb6c1bd674d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262475617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1262475617
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2146238473
Short name T379
Test name
Test status
Simulation time 35361438 ps
CPU time 1.99 seconds
Started Jul 31 05:36:53 PM PDT 24
Finished Jul 31 05:36:56 PM PDT 24
Peak memory 214276 kb
Host smart-bf8f1323-a1d8-4b6e-8bfe-2e6b1c31b4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146238473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2146238473
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3895509672
Short name T370
Test name
Test status
Simulation time 230714180 ps
CPU time 3.13 seconds
Started Jul 31 05:37:08 PM PDT 24
Finished Jul 31 05:37:11 PM PDT 24
Peak memory 214344 kb
Host smart-a0f74ed7-7eb2-43a6-82ab-22aaa16566ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3895509672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3895509672
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.836003519
Short name T74
Test name
Test status
Simulation time 817941190 ps
CPU time 29.23 seconds
Started Jul 31 05:37:17 PM PDT 24
Finished Jul 31 05:37:46 PM PDT 24
Peak memory 215108 kb
Host smart-01ef8673-02c3-4beb-9a54-90b3f3872963
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836003519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.836003519
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.2639399300
Short name T256
Test name
Test status
Simulation time 43426836 ps
CPU time 3.01 seconds
Started Jul 31 05:37:15 PM PDT 24
Finished Jul 31 05:37:18 PM PDT 24
Peak memory 214312 kb
Host smart-d712ce1c-ddf5-41cf-a5c6-aa4de2b7e5bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2639399300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2639399300
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_random.1993013519
Short name T295
Test name
Test status
Simulation time 1038043604 ps
CPU time 23.64 seconds
Started Jul 31 05:37:19 PM PDT 24
Finished Jul 31 05:37:43 PM PDT 24
Peak memory 218384 kb
Host smart-d1d1bbb2-6637-45dc-a8c0-9b967d05b447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993013519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1993013519
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2088890382
Short name T792
Test name
Test status
Simulation time 362720568 ps
CPU time 1.95 seconds
Started Jul 31 05:37:41 PM PDT 24
Finished Jul 31 05:37:43 PM PDT 24
Peak memory 214172 kb
Host smart-0f82517b-2d79-493e-93b2-3b8fc8eb6f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088890382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2088890382
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.479715722
Short name T367
Test name
Test status
Simulation time 75091906 ps
CPU time 2.54 seconds
Started Jul 31 05:38:34 PM PDT 24
Finished Jul 31 05:38:37 PM PDT 24
Peak memory 209636 kb
Host smart-9baae84b-e65d-418d-bc27-b6d56f59c2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479715722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.479715722
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2483941094
Short name T211
Test name
Test status
Simulation time 380719670 ps
CPU time 19.95 seconds
Started Jul 31 05:38:49 PM PDT 24
Finished Jul 31 05:39:09 PM PDT 24
Peak memory 215032 kb
Host smart-29a5dce4-a3ff-4c30-b724-996b4bc41416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483941094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2483941094
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2700817094
Short name T51
Test name
Test status
Simulation time 283636387 ps
CPU time 2.51 seconds
Started Jul 31 05:39:02 PM PDT 24
Finished Jul 31 05:39:05 PM PDT 24
Peak memory 214300 kb
Host smart-22e73c7c-44a9-42f3-a8a4-2ad8ce8fed62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700817094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2700817094
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.205379796
Short name T166
Test name
Test status
Simulation time 311681215 ps
CPU time 5 seconds
Started Jul 31 07:16:57 PM PDT 24
Finished Jul 31 07:17:02 PM PDT 24
Peak memory 214384 kb
Host smart-cb55141c-4513-4b99-98a0-f35995aa2c81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205379796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.205379796
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1529636161
Short name T154
Test name
Test status
Simulation time 86932179 ps
CPU time 2.56 seconds
Started Jul 31 07:17:16 PM PDT 24
Finished Jul 31 07:17:18 PM PDT 24
Peak memory 214336 kb
Host smart-75053414-849d-45f9-ba12-7e989df98a84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529636161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1529636161
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3510268507
Short name T158
Test name
Test status
Simulation time 406382312 ps
CPU time 8.41 seconds
Started Jul 31 07:16:54 PM PDT 24
Finished Jul 31 07:17:02 PM PDT 24
Peak memory 214368 kb
Host smart-906eefea-80cd-4fb3-8d1a-354f8b97e30e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510268507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3510268507
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1299765144
Short name T168
Test name
Test status
Simulation time 517052436 ps
CPU time 3.7 seconds
Started Jul 31 07:16:52 PM PDT 24
Finished Jul 31 07:16:55 PM PDT 24
Peak memory 214356 kb
Host smart-954991cb-26f2-495a-ad61-606f2186c7ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299765144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1299765144
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1473517956
Short name T170
Test name
Test status
Simulation time 57973156 ps
CPU time 2.6 seconds
Started Jul 31 05:37:02 PM PDT 24
Finished Jul 31 05:37:05 PM PDT 24
Peak memory 210020 kb
Host smart-65bb04ed-83cb-451d-9b41-31b9d894ffa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473517956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1473517956
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.483415684
Short name T9
Test name
Test status
Simulation time 451712564 ps
CPU time 13.88 seconds
Started Jul 31 05:36:16 PM PDT 24
Finished Jul 31 05:36:30 PM PDT 24
Peak memory 229940 kb
Host smart-3c12ba04-7e5f-42c6-90a6-5eeec8dc9541
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483415684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.483415684
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1541195209
Short name T151
Test name
Test status
Simulation time 120689980 ps
CPU time 3.72 seconds
Started Jul 31 05:37:36 PM PDT 24
Finished Jul 31 05:37:40 PM PDT 24
Peak memory 217064 kb
Host smart-c7dbcc1d-d81e-45ae-9a18-39f426925ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541195209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1541195209
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2416611251
Short name T36
Test name
Test status
Simulation time 165397728 ps
CPU time 2.83 seconds
Started Jul 31 05:38:27 PM PDT 24
Finished Jul 31 05:38:30 PM PDT 24
Peak memory 217988 kb
Host smart-af632a98-f6f3-45ac-bb4b-9779c92cb682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416611251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2416611251
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3538518833
Short name T354
Test name
Test status
Simulation time 91046763 ps
CPU time 3.87 seconds
Started Jul 31 05:36:11 PM PDT 24
Finished Jul 31 05:36:15 PM PDT 24
Peak memory 214336 kb
Host smart-e9f092e7-ebc6-45a2-850b-856c00095cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538518833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3538518833
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1092137088
Short name T76
Test name
Test status
Simulation time 7376073169 ps
CPU time 49.31 seconds
Started Jul 31 05:36:07 PM PDT 24
Finished Jul 31 05:36:57 PM PDT 24
Peak memory 222600 kb
Host smart-effa398d-ffe2-48b4-9d56-d40f256652ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092137088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1092137088
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1016407834
Short name T72
Test name
Test status
Simulation time 306823854 ps
CPU time 1.73 seconds
Started Jul 31 05:36:06 PM PDT 24
Finished Jul 31 05:36:08 PM PDT 24
Peak memory 208024 kb
Host smart-f3f2112a-3556-4728-98f6-fa3e28424694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016407834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1016407834
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.2185108068
Short name T109
Test name
Test status
Simulation time 209528736 ps
CPU time 7.24 seconds
Started Jul 31 05:36:56 PM PDT 24
Finished Jul 31 05:37:04 PM PDT 24
Peak memory 222456 kb
Host smart-caf57dfb-044f-4b13-a367-df1cff7f7fd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185108068 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.2185108068
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.540845
Short name T284
Test name
Test status
Simulation time 112385997 ps
CPU time 6.12 seconds
Started Jul 31 05:37:01 PM PDT 24
Finished Jul 31 05:37:07 PM PDT 24
Peak memory 214372 kb
Host smart-0bc3e2f4-4e0f-448c-b660-a0f5f961ed0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=540845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.540845
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.737997182
Short name T327
Test name
Test status
Simulation time 4696607369 ps
CPU time 19.19 seconds
Started Jul 31 05:37:04 PM PDT 24
Finished Jul 31 05:37:23 PM PDT 24
Peak memory 216948 kb
Host smart-1331bc3f-5baa-405c-908c-38193287f46b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737997182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.737997182
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.219697904
Short name T242
Test name
Test status
Simulation time 76559590 ps
CPU time 2.84 seconds
Started Jul 31 05:37:06 PM PDT 24
Finished Jul 31 05:37:08 PM PDT 24
Peak memory 214304 kb
Host smart-983a2e12-56ab-4ba0-98f0-349a8b3fd487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219697904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.219697904
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.665527216
Short name T184
Test name
Test status
Simulation time 1382698705 ps
CPU time 10.22 seconds
Started Jul 31 05:37:00 PM PDT 24
Finished Jul 31 05:37:10 PM PDT 24
Peak memory 222556 kb
Host smart-6d2c9f08-dd58-40c4-a5e2-b7a520269938
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665527216 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.665527216
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3226876811
Short name T371
Test name
Test status
Simulation time 317649450 ps
CPU time 3.81 seconds
Started Jul 31 05:37:16 PM PDT 24
Finished Jul 31 05:37:20 PM PDT 24
Peak memory 210068 kb
Host smart-2900070f-7b92-4cfe-9b05-115622ade3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226876811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3226876811
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.1416566504
Short name T50
Test name
Test status
Simulation time 38738964 ps
CPU time 2.45 seconds
Started Jul 31 05:37:20 PM PDT 24
Finished Jul 31 05:37:23 PM PDT 24
Peak memory 214304 kb
Host smart-3a8ecaa0-8a82-4e99-b39a-050453403788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416566504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1416566504
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1576712405
Short name T349
Test name
Test status
Simulation time 285797177 ps
CPU time 7.55 seconds
Started Jul 31 05:36:15 PM PDT 24
Finished Jul 31 05:36:22 PM PDT 24
Peak memory 215292 kb
Host smart-c695bbd8-3c43-4d48-ae46-4c335a7db1ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1576712405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1576712405
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1507897502
Short name T364
Test name
Test status
Simulation time 480085976 ps
CPU time 11.56 seconds
Started Jul 31 05:36:14 PM PDT 24
Finished Jul 31 05:36:25 PM PDT 24
Peak memory 214308 kb
Host smart-6d84ec8c-860d-4d6a-9d4d-44b827780125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507897502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1507897502
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1595753847
Short name T650
Test name
Test status
Simulation time 136688428 ps
CPU time 3.22 seconds
Started Jul 31 05:36:14 PM PDT 24
Finished Jul 31 05:36:18 PM PDT 24
Peak memory 214324 kb
Host smart-e8813cc2-de0d-4788-aa05-29ecc5a387ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595753847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1595753847
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.355886042
Short name T329
Test name
Test status
Simulation time 296247246 ps
CPU time 4.7 seconds
Started Jul 31 05:36:14 PM PDT 24
Finished Jul 31 05:36:19 PM PDT 24
Peak memory 222424 kb
Host smart-c4c5d6b8-2846-49d5-a1d2-a42a227e182f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355886042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.355886042
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.926463564
Short name T215
Test name
Test status
Simulation time 24425872453 ps
CPU time 225.56 seconds
Started Jul 31 05:37:33 PM PDT 24
Finished Jul 31 05:41:18 PM PDT 24
Peak memory 219080 kb
Host smart-b84ea658-01bd-4c19-ac80-6846ace5e0f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926463564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.926463564
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1610029078
Short name T213
Test name
Test status
Simulation time 41715267 ps
CPU time 2.26 seconds
Started Jul 31 05:36:18 PM PDT 24
Finished Jul 31 05:36:20 PM PDT 24
Peak memory 214304 kb
Host smart-e6bd00dc-b96e-43a9-bec1-041b925da461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610029078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1610029078
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.1740993306
Short name T227
Test name
Test status
Simulation time 448582197 ps
CPU time 16.77 seconds
Started Jul 31 05:38:25 PM PDT 24
Finished Jul 31 05:38:42 PM PDT 24
Peak memory 222584 kb
Host smart-556cc5dd-be91-4a82-aedf-04a625bf9f75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740993306 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.1740993306
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.3197470060
Short name T231
Test name
Test status
Simulation time 634099767 ps
CPU time 10.49 seconds
Started Jul 31 05:38:36 PM PDT 24
Finished Jul 31 05:38:46 PM PDT 24
Peak memory 219888 kb
Host smart-23941854-add0-47b2-bff0-81c12ee7b921
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197470060 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.3197470060
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.1163714627
Short name T217
Test name
Test status
Simulation time 2185186805 ps
CPU time 23.51 seconds
Started Jul 31 05:38:40 PM PDT 24
Finished Jul 31 05:39:04 PM PDT 24
Peak memory 222492 kb
Host smart-efa68298-7bbd-4c3f-81ef-87293561940a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163714627 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.1163714627
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1833731595
Short name T958
Test name
Test status
Simulation time 795514231 ps
CPU time 8.08 seconds
Started Jul 31 07:16:49 PM PDT 24
Finished Jul 31 07:16:57 PM PDT 24
Peak memory 206252 kb
Host smart-78e78b7b-e1fe-4cf7-80fe-333309050c61
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833731595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
833731595
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1571327847
Short name T924
Test name
Test status
Simulation time 4314812080 ps
CPU time 8.73 seconds
Started Jul 31 07:16:45 PM PDT 24
Finished Jul 31 07:16:54 PM PDT 24
Peak memory 206160 kb
Host smart-0ce406e7-1339-482a-8c4f-a2ea58009f12
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571327847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
571327847
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3796674196
Short name T1043
Test name
Test status
Simulation time 105308361 ps
CPU time 1.39 seconds
Started Jul 31 07:16:45 PM PDT 24
Finished Jul 31 07:16:46 PM PDT 24
Peak memory 206036 kb
Host smart-bf6517a9-d476-4bcd-8cfb-6a24125bd992
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796674196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
796674196
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1018588352
Short name T956
Test name
Test status
Simulation time 17673961 ps
CPU time 1.26 seconds
Started Jul 31 07:16:43 PM PDT 24
Finished Jul 31 07:16:45 PM PDT 24
Peak memory 214516 kb
Host smart-31df1dd4-0c79-4d8a-bb3f-3cbd7758de0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018588352 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1018588352
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.436448785
Short name T1007
Test name
Test status
Simulation time 31314999 ps
CPU time 1.14 seconds
Started Jul 31 07:16:48 PM PDT 24
Finished Jul 31 07:16:49 PM PDT 24
Peak memory 206256 kb
Host smart-3fa3d028-0895-4996-a64e-0caa8fd90493
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436448785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.436448785
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.633559275
Short name T1055
Test name
Test status
Simulation time 12470236 ps
CPU time 0.85 seconds
Started Jul 31 07:16:43 PM PDT 24
Finished Jul 31 07:16:44 PM PDT 24
Peak memory 205884 kb
Host smart-b89abbde-7b6a-41f3-a4d6-545e77a9ca05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633559275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.633559275
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1018773648
Short name T936
Test name
Test status
Simulation time 100890289 ps
CPU time 1.81 seconds
Started Jul 31 07:16:52 PM PDT 24
Finished Jul 31 07:16:54 PM PDT 24
Peak memory 206116 kb
Host smart-a2828448-10eb-4841-82e9-4ba9dd609b70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018773648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1018773648
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3186201359
Short name T1031
Test name
Test status
Simulation time 311391416 ps
CPU time 4.4 seconds
Started Jul 31 07:16:45 PM PDT 24
Finished Jul 31 07:16:50 PM PDT 24
Peak memory 222776 kb
Host smart-1628cb60-ea34-4e56-80ce-9fa7cddcb779
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186201359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3186201359
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.403654043
Short name T957
Test name
Test status
Simulation time 252611085 ps
CPU time 2.05 seconds
Started Jul 31 07:16:50 PM PDT 24
Finished Jul 31 07:16:52 PM PDT 24
Peak memory 214456 kb
Host smart-822f75cc-aa18-42ea-9234-a89ef308e959
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403654043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.403654043
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1381798553
Short name T156
Test name
Test status
Simulation time 210628067 ps
CPU time 8.21 seconds
Started Jul 31 07:16:42 PM PDT 24
Finished Jul 31 07:16:50 PM PDT 24
Peak memory 214272 kb
Host smart-5a681826-8df4-4f55-9102-57683877f246
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381798553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.1381798553
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1295861397
Short name T976
Test name
Test status
Simulation time 3079968166 ps
CPU time 12.08 seconds
Started Jul 31 07:16:52 PM PDT 24
Finished Jul 31 07:17:04 PM PDT 24
Peak memory 206260 kb
Host smart-d1d3c83e-7be9-45df-9d18-99dd73ddf1d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295861397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
295861397
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1254145296
Short name T991
Test name
Test status
Simulation time 435847092 ps
CPU time 12.64 seconds
Started Jul 31 07:16:42 PM PDT 24
Finished Jul 31 07:16:54 PM PDT 24
Peak memory 206144 kb
Host smart-05a33a51-633a-45d4-bb17-5022772bce7d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254145296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1
254145296
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.59286452
Short name T996
Test name
Test status
Simulation time 47471361 ps
CPU time 1.01 seconds
Started Jul 31 07:16:43 PM PDT 24
Finished Jul 31 07:16:44 PM PDT 24
Peak memory 206172 kb
Host smart-920bd9b5-4f03-4a53-83de-7095ca3d9653
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59286452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.59286452
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.523505276
Short name T1006
Test name
Test status
Simulation time 33939430 ps
CPU time 1.17 seconds
Started Jul 31 07:16:43 PM PDT 24
Finished Jul 31 07:16:44 PM PDT 24
Peak memory 214372 kb
Host smart-8b74c23b-28af-42d5-980a-d89fb87b4e2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523505276 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.523505276
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3593290377
Short name T997
Test name
Test status
Simulation time 24893400 ps
CPU time 1.45 seconds
Started Jul 31 07:16:48 PM PDT 24
Finished Jul 31 07:16:50 PM PDT 24
Peak memory 206136 kb
Host smart-fd47b218-74eb-49ab-a29e-a93e9b6ed88c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593290377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3593290377
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2526611077
Short name T1077
Test name
Test status
Simulation time 8480884 ps
CPU time 0.8 seconds
Started Jul 31 07:16:49 PM PDT 24
Finished Jul 31 07:16:50 PM PDT 24
Peak memory 205944 kb
Host smart-a06cc5ca-26f0-4573-8503-73ac39c9a38d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526611077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2526611077
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2737888174
Short name T1071
Test name
Test status
Simulation time 40117131 ps
CPU time 2.42 seconds
Started Jul 31 07:16:43 PM PDT 24
Finished Jul 31 07:16:46 PM PDT 24
Peak memory 206068 kb
Host smart-fc36365c-927b-4955-a55b-f1ea61122309
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737888174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2737888174
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3165823427
Short name T1085
Test name
Test status
Simulation time 178347989 ps
CPU time 3.53 seconds
Started Jul 31 07:16:51 PM PDT 24
Finished Jul 31 07:16:54 PM PDT 24
Peak memory 214560 kb
Host smart-4a47f218-bfb5-4a1b-8d3e-13695c451d1c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165823427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3165823427
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2070774052
Short name T110
Test name
Test status
Simulation time 660787696 ps
CPU time 6.75 seconds
Started Jul 31 07:16:43 PM PDT 24
Finished Jul 31 07:16:50 PM PDT 24
Peak memory 214572 kb
Host smart-2b80e72c-7aed-4aad-a51d-47b76ae09d1c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070774052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2070774052
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.562550759
Short name T1016
Test name
Test status
Simulation time 169739157 ps
CPU time 2.93 seconds
Started Jul 31 07:16:49 PM PDT 24
Finished Jul 31 07:16:52 PM PDT 24
Peak memory 214528 kb
Host smart-31f164f4-e01e-484a-bb81-c48712a7f69e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562550759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.562550759
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3131636346
Short name T157
Test name
Test status
Simulation time 572442619 ps
CPU time 4.1 seconds
Started Jul 31 07:16:50 PM PDT 24
Finished Jul 31 07:16:54 PM PDT 24
Peak memory 214328 kb
Host smart-4773452f-934f-4eba-a91d-8ae317b0f513
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131636346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3131636346
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3665379827
Short name T1027
Test name
Test status
Simulation time 128137447 ps
CPU time 1.5 seconds
Started Jul 31 07:17:05 PM PDT 24
Finished Jul 31 07:17:07 PM PDT 24
Peak memory 214260 kb
Host smart-d22b2fdd-0d0f-40f4-8862-d3093be692e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665379827 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3665379827
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3904578320
Short name T1034
Test name
Test status
Simulation time 22141950 ps
CPU time 1.04 seconds
Started Jul 31 07:17:05 PM PDT 24
Finished Jul 31 07:17:07 PM PDT 24
Peak memory 206088 kb
Host smart-ed90e5e4-0331-4319-8fab-bc66f7dd52ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904578320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3904578320
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.897615898
Short name T1058
Test name
Test status
Simulation time 29868364 ps
CPU time 0.72 seconds
Started Jul 31 07:16:57 PM PDT 24
Finished Jul 31 07:16:58 PM PDT 24
Peak memory 205956 kb
Host smart-ef23ca00-aa54-471b-ad99-079378b84105
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897615898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.897615898
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3530772985
Short name T1070
Test name
Test status
Simulation time 112984319 ps
CPU time 2.28 seconds
Started Jul 31 07:17:04 PM PDT 24
Finished Jul 31 07:17:06 PM PDT 24
Peak memory 214512 kb
Host smart-68cfc935-b4bd-4e92-a6dc-f97506931cf1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530772985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3530772985
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1279667302
Short name T1051
Test name
Test status
Simulation time 161387042 ps
CPU time 1.84 seconds
Started Jul 31 07:16:55 PM PDT 24
Finished Jul 31 07:16:57 PM PDT 24
Peak memory 214776 kb
Host smart-3d22c058-c83a-454d-b9c1-5bd4f8249994
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279667302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.1279667302
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.732796943
Short name T1079
Test name
Test status
Simulation time 912375161 ps
CPU time 16.45 seconds
Started Jul 31 07:16:54 PM PDT 24
Finished Jul 31 07:17:10 PM PDT 24
Peak memory 214676 kb
Host smart-6f6e114a-0610-44c6-9b80-3722b3849b5e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732796943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.732796943
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2636275062
Short name T1087
Test name
Test status
Simulation time 135855621 ps
CPU time 1.82 seconds
Started Jul 31 07:16:57 PM PDT 24
Finished Jul 31 07:16:59 PM PDT 24
Peak memory 214388 kb
Host smart-fd4c7be5-1c50-47cb-ae9d-015cb9157be8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636275062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2636275062
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.4088078028
Short name T1090
Test name
Test status
Simulation time 206179555 ps
CPU time 2.47 seconds
Started Jul 31 07:17:18 PM PDT 24
Finished Jul 31 07:17:21 PM PDT 24
Peak memory 214500 kb
Host smart-de83293b-b34f-4f63-9b86-96110d43255a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088078028 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.4088078028
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.29304581
Short name T143
Test name
Test status
Simulation time 50637103 ps
CPU time 1.17 seconds
Started Jul 31 07:17:15 PM PDT 24
Finished Jul 31 07:17:16 PM PDT 24
Peak memory 206256 kb
Host smart-2b537bab-cf2a-4631-adcf-b3000d37ac2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29304581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.29304581
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.652161892
Short name T926
Test name
Test status
Simulation time 74006697 ps
CPU time 0.92 seconds
Started Jul 31 07:17:12 PM PDT 24
Finished Jul 31 07:17:13 PM PDT 24
Peak memory 205912 kb
Host smart-72067964-76dd-42e1-bad9-6b611cdb3552
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652161892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.652161892
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1046254172
Short name T1001
Test name
Test status
Simulation time 778667076 ps
CPU time 2.54 seconds
Started Jul 31 07:17:22 PM PDT 24
Finished Jul 31 07:17:25 PM PDT 24
Peak memory 206056 kb
Host smart-c4b487c9-cac5-46d6-897e-0daaad06b26c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046254172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1046254172
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2474707744
Short name T1039
Test name
Test status
Simulation time 870851456 ps
CPU time 2.88 seconds
Started Jul 31 07:17:06 PM PDT 24
Finished Jul 31 07:17:08 PM PDT 24
Peak memory 214660 kb
Host smart-6dcebd9d-8f14-44ac-a824-11b84bd0424d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474707744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2474707744
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2111845838
Short name T1023
Test name
Test status
Simulation time 251944282 ps
CPU time 5.1 seconds
Started Jul 31 07:17:04 PM PDT 24
Finished Jul 31 07:17:10 PM PDT 24
Peak memory 222696 kb
Host smart-5fdba64d-5813-4e13-9581-d2026a4cb976
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111845838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2111845838
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.291084513
Short name T1065
Test name
Test status
Simulation time 78950985 ps
CPU time 2.26 seconds
Started Jul 31 07:17:11 PM PDT 24
Finished Jul 31 07:17:14 PM PDT 24
Peak memory 214444 kb
Host smart-2fe18462-e0f3-4f44-aafc-e30a875362eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291084513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.291084513
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2267094294
Short name T159
Test name
Test status
Simulation time 243177952 ps
CPU time 5.07 seconds
Started Jul 31 07:17:11 PM PDT 24
Finished Jul 31 07:17:16 PM PDT 24
Peak memory 214364 kb
Host smart-995c3999-1cdc-402d-9643-a0167cfe7241
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267094294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2267094294
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1768054459
Short name T1040
Test name
Test status
Simulation time 124632539 ps
CPU time 1.23 seconds
Started Jul 31 07:17:19 PM PDT 24
Finished Jul 31 07:17:20 PM PDT 24
Peak memory 218184 kb
Host smart-ef6a674d-1356-437c-b59a-e92f65551d88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768054459 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1768054459
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2775856927
Short name T1022
Test name
Test status
Simulation time 16583126 ps
CPU time 1.21 seconds
Started Jul 31 07:17:19 PM PDT 24
Finished Jul 31 07:17:20 PM PDT 24
Peak memory 206192 kb
Host smart-bc47d7af-cc3a-4974-bbb9-8f62b5143903
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775856927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2775856927
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1059833549
Short name T1059
Test name
Test status
Simulation time 32566449 ps
CPU time 0.73 seconds
Started Jul 31 07:17:18 PM PDT 24
Finished Jul 31 07:17:19 PM PDT 24
Peak memory 205912 kb
Host smart-5cf55d5a-f25d-4e42-bbd7-7e80fdbdeeea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059833549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1059833549
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3034279635
Short name T1030
Test name
Test status
Simulation time 42222673 ps
CPU time 2.11 seconds
Started Jul 31 07:17:16 PM PDT 24
Finished Jul 31 07:17:18 PM PDT 24
Peak memory 206204 kb
Host smart-aca02f9b-f37a-4241-a8c8-1825963cdcda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034279635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3034279635
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2702736282
Short name T978
Test name
Test status
Simulation time 137383754 ps
CPU time 3.83 seconds
Started Jul 31 07:17:16 PM PDT 24
Finished Jul 31 07:17:20 PM PDT 24
Peak memory 219148 kb
Host smart-21bc6510-1ea7-41a2-af2e-8e7806485283
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702736282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2702736282
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1174518421
Short name T115
Test name
Test status
Simulation time 78188472 ps
CPU time 3.82 seconds
Started Jul 31 07:17:16 PM PDT 24
Finished Jul 31 07:17:19 PM PDT 24
Peak memory 214712 kb
Host smart-6babef04-177e-4f56-8138-7dfa17082f75
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174518421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1174518421
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1901439333
Short name T998
Test name
Test status
Simulation time 57842277 ps
CPU time 1.87 seconds
Started Jul 31 07:17:16 PM PDT 24
Finished Jul 31 07:17:18 PM PDT 24
Peak memory 215428 kb
Host smart-8f1d73a4-3616-457c-970c-2ec91b6ffe60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901439333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1901439333
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.186927207
Short name T928
Test name
Test status
Simulation time 124701852 ps
CPU time 1.49 seconds
Started Jul 31 07:17:17 PM PDT 24
Finished Jul 31 07:17:19 PM PDT 24
Peak memory 214480 kb
Host smart-d719a317-0e66-4926-b08a-edff7fd5143f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186927207 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.186927207
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.643450421
Short name T1036
Test name
Test status
Simulation time 22485495 ps
CPU time 1.03 seconds
Started Jul 31 07:17:18 PM PDT 24
Finished Jul 31 07:17:19 PM PDT 24
Peak memory 205960 kb
Host smart-cc5f35d4-56f1-416d-90dc-ca0195e234c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643450421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.643450421
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3344283887
Short name T930
Test name
Test status
Simulation time 14210065 ps
CPU time 0.75 seconds
Started Jul 31 07:17:29 PM PDT 24
Finished Jul 31 07:17:29 PM PDT 24
Peak memory 206008 kb
Host smart-51275bf7-cd61-4d54-bbfb-3e2b204bfda3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344283887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3344283887
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1091609824
Short name T140
Test name
Test status
Simulation time 290711677 ps
CPU time 2.15 seconds
Started Jul 31 07:17:17 PM PDT 24
Finished Jul 31 07:17:19 PM PDT 24
Peak memory 206144 kb
Host smart-2c23caf1-7e32-4aa4-920e-c70fe6332c39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091609824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1091609824
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1466882415
Short name T1004
Test name
Test status
Simulation time 533762751 ps
CPU time 2.64 seconds
Started Jul 31 07:17:17 PM PDT 24
Finished Jul 31 07:17:20 PM PDT 24
Peak memory 214552 kb
Host smart-1fd81062-8b23-4380-8d2a-409c44e57201
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466882415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1466882415
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3217929659
Short name T989
Test name
Test status
Simulation time 138414622 ps
CPU time 3.22 seconds
Started Jul 31 07:17:19 PM PDT 24
Finished Jul 31 07:17:22 PM PDT 24
Peak memory 217516 kb
Host smart-52a0c1c8-da01-4038-97c5-b830473f11a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217929659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3217929659
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.597754485
Short name T950
Test name
Test status
Simulation time 282534925 ps
CPU time 1.31 seconds
Started Jul 31 07:17:23 PM PDT 24
Finished Jul 31 07:17:24 PM PDT 24
Peak memory 214356 kb
Host smart-489029a6-8d76-4312-85a4-e9fe2783af29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597754485 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.597754485
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3881239120
Short name T961
Test name
Test status
Simulation time 22817472 ps
CPU time 1.05 seconds
Started Jul 31 07:17:17 PM PDT 24
Finished Jul 31 07:17:18 PM PDT 24
Peak memory 206116 kb
Host smart-c3d94110-e840-4578-b3e8-bc37c8f2dc1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881239120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3881239120
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.94353736
Short name T1029
Test name
Test status
Simulation time 27461280 ps
CPU time 0.76 seconds
Started Jul 31 07:17:18 PM PDT 24
Finished Jul 31 07:17:19 PM PDT 24
Peak memory 205924 kb
Host smart-abbc8757-b10d-4237-9c3e-9ba4fab20f1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94353736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.94353736
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.4131260469
Short name T984
Test name
Test status
Simulation time 152110298 ps
CPU time 2.41 seconds
Started Jul 31 07:17:15 PM PDT 24
Finished Jul 31 07:17:18 PM PDT 24
Peak memory 206180 kb
Host smart-f6246205-dbd5-4404-a258-2b1e1d13113d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131260469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.4131260469
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.921786213
Short name T973
Test name
Test status
Simulation time 403717850 ps
CPU time 3.61 seconds
Started Jul 31 07:17:18 PM PDT 24
Finished Jul 31 07:17:22 PM PDT 24
Peak memory 214664 kb
Host smart-c1d5478c-36fc-4d86-921c-299768b44a6d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921786213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.921786213
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3260697503
Short name T117
Test name
Test status
Simulation time 321639754 ps
CPU time 8.89 seconds
Started Jul 31 07:17:21 PM PDT 24
Finished Jul 31 07:17:30 PM PDT 24
Peak memory 214712 kb
Host smart-335fa749-3e10-40ca-b24c-f07d14ae9f2c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260697503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3260697503
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2030821157
Short name T1056
Test name
Test status
Simulation time 121167577 ps
CPU time 3.04 seconds
Started Jul 31 07:17:16 PM PDT 24
Finished Jul 31 07:17:20 PM PDT 24
Peak memory 214276 kb
Host smart-f5ec4199-82f0-467a-8df5-cfdfd7f0e6bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030821157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2030821157
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2561761262
Short name T173
Test name
Test status
Simulation time 105604169 ps
CPU time 5.28 seconds
Started Jul 31 07:17:17 PM PDT 24
Finished Jul 31 07:17:22 PM PDT 24
Peak memory 214328 kb
Host smart-6b4ae17a-6d0a-4808-8946-dab886b4b715
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561761262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2561761262
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1520610177
Short name T951
Test name
Test status
Simulation time 83245129 ps
CPU time 1.09 seconds
Started Jul 31 07:17:18 PM PDT 24
Finished Jul 31 07:17:19 PM PDT 24
Peak memory 205996 kb
Host smart-9aad8e39-12cb-4b60-8f1e-c61980bb5f97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520610177 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1520610177
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3806878374
Short name T1062
Test name
Test status
Simulation time 109279127 ps
CPU time 1.28 seconds
Started Jul 31 07:17:17 PM PDT 24
Finished Jul 31 07:17:18 PM PDT 24
Peak memory 206144 kb
Host smart-3ee5ab9a-04bf-484b-8ea3-49e3fd75f0cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806878374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3806878374
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3514540271
Short name T1050
Test name
Test status
Simulation time 18258088 ps
CPU time 0.71 seconds
Started Jul 31 07:17:18 PM PDT 24
Finished Jul 31 07:17:18 PM PDT 24
Peak memory 205836 kb
Host smart-af5ee321-88af-4699-93c2-937f790101cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514540271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3514540271
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.662552178
Short name T1012
Test name
Test status
Simulation time 115127978 ps
CPU time 2.13 seconds
Started Jul 31 07:17:16 PM PDT 24
Finished Jul 31 07:17:18 PM PDT 24
Peak memory 206236 kb
Host smart-18806f4a-70d2-44bb-aecf-c97c0b9344ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662552178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.662552178
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.15544309
Short name T953
Test name
Test status
Simulation time 71778962 ps
CPU time 2.29 seconds
Started Jul 31 07:17:18 PM PDT 24
Finished Jul 31 07:17:21 PM PDT 24
Peak memory 214676 kb
Host smart-7dbfdff3-43b3-4940-9f25-a8bd49e23b23
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15544309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow
_reg_errors.15544309
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.635185091
Short name T118
Test name
Test status
Simulation time 609993508 ps
CPU time 15.68 seconds
Started Jul 31 07:17:16 PM PDT 24
Finished Jul 31 07:17:32 PM PDT 24
Peak memory 214676 kb
Host smart-41be7144-b3ed-4b1c-b4ef-00ec1001a72d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635185091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_shadow_reg_errors_with_csr_rw.635185091
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1894645179
Short name T1008
Test name
Test status
Simulation time 45109173 ps
CPU time 3.15 seconds
Started Jul 31 07:17:17 PM PDT 24
Finished Jul 31 07:17:20 PM PDT 24
Peak memory 216880 kb
Host smart-dd8311b3-5840-4178-a39c-78fdca491d1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894645179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1894645179
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3374704686
Short name T172
Test name
Test status
Simulation time 426419504 ps
CPU time 3.41 seconds
Started Jul 31 07:17:17 PM PDT 24
Finished Jul 31 07:17:21 PM PDT 24
Peak memory 214444 kb
Host smart-a01c8eb7-4727-4a10-b473-402fa32c4ec0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374704686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.3374704686
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.916192999
Short name T1044
Test name
Test status
Simulation time 114581380 ps
CPU time 1.17 seconds
Started Jul 31 07:17:18 PM PDT 24
Finished Jul 31 07:17:19 PM PDT 24
Peak memory 214496 kb
Host smart-4dcddca5-388e-4ee4-a91f-dbcdfdfe58e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916192999 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.916192999
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1704353739
Short name T1073
Test name
Test status
Simulation time 93708416 ps
CPU time 1.07 seconds
Started Jul 31 07:17:17 PM PDT 24
Finished Jul 31 07:17:18 PM PDT 24
Peak memory 206160 kb
Host smart-26d40508-85dd-47c5-a89c-a10b2be80f6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704353739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1704353739
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.131185015
Short name T963
Test name
Test status
Simulation time 11818704 ps
CPU time 0.82 seconds
Started Jul 31 07:17:17 PM PDT 24
Finished Jul 31 07:17:18 PM PDT 24
Peak memory 205876 kb
Host smart-c7376db0-8e38-457e-a64a-b1f5312ea93f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131185015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.131185015
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3471370793
Short name T1081
Test name
Test status
Simulation time 415828451 ps
CPU time 3.64 seconds
Started Jul 31 07:17:18 PM PDT 24
Finished Jul 31 07:17:22 PM PDT 24
Peak memory 206140 kb
Host smart-b05e3f4f-e2b7-49a3-ab1d-74f159fc77a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471370793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3471370793
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1057564581
Short name T1011
Test name
Test status
Simulation time 117539759 ps
CPU time 1.87 seconds
Started Jul 31 07:17:18 PM PDT 24
Finished Jul 31 07:17:20 PM PDT 24
Peak memory 214636 kb
Host smart-dd86d71b-56a4-4b54-9d30-0bafde77a2bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057564581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1057564581
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.76568790
Short name T1028
Test name
Test status
Simulation time 151267019 ps
CPU time 4.6 seconds
Started Jul 31 07:17:17 PM PDT 24
Finished Jul 31 07:17:22 PM PDT 24
Peak memory 214612 kb
Host smart-2d3dbbee-40a3-40c1-a912-0681f2f0d743
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76568790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.k
eymgr_shadow_reg_errors_with_csr_rw.76568790
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3292443515
Short name T1017
Test name
Test status
Simulation time 249940741 ps
CPU time 2.59 seconds
Started Jul 31 07:17:18 PM PDT 24
Finished Jul 31 07:17:21 PM PDT 24
Peak memory 214348 kb
Host smart-d80a49a0-6373-4d6e-82d9-58d0b05d0892
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292443515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3292443515
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.666721661
Short name T161
Test name
Test status
Simulation time 3238916119 ps
CPU time 10.8 seconds
Started Jul 31 07:17:19 PM PDT 24
Finished Jul 31 07:17:29 PM PDT 24
Peak memory 214312 kb
Host smart-dba49413-359e-4d80-b4c6-63b2ea1ddbed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666721661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err
.666721661
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2918545286
Short name T979
Test name
Test status
Simulation time 33509214 ps
CPU time 1.35 seconds
Started Jul 31 07:17:18 PM PDT 24
Finished Jul 31 07:17:19 PM PDT 24
Peak memory 214368 kb
Host smart-8106f903-4a44-4315-8f9d-6d20b23fc7ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918545286 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2918545286
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3010421286
Short name T999
Test name
Test status
Simulation time 16915964 ps
CPU time 1.15 seconds
Started Jul 31 07:17:19 PM PDT 24
Finished Jul 31 07:17:20 PM PDT 24
Peak memory 206172 kb
Host smart-a3f1e6c0-6553-4610-a01d-a0af45cafe8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010421286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3010421286
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2295918400
Short name T947
Test name
Test status
Simulation time 10947858 ps
CPU time 0.71 seconds
Started Jul 31 07:17:18 PM PDT 24
Finished Jul 31 07:17:19 PM PDT 24
Peak memory 205896 kb
Host smart-8df750f1-9365-4d99-a4cf-a7edf2fda5c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295918400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2295918400
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2484461576
Short name T939
Test name
Test status
Simulation time 51621357 ps
CPU time 2.17 seconds
Started Jul 31 07:17:16 PM PDT 24
Finished Jul 31 07:17:18 PM PDT 24
Peak memory 206148 kb
Host smart-108d03c1-e98a-4581-889c-7892dbc71ad8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484461576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2484461576
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.267963337
Short name T113
Test name
Test status
Simulation time 154960445 ps
CPU time 4.92 seconds
Started Jul 31 07:17:17 PM PDT 24
Finished Jul 31 07:17:22 PM PDT 24
Peak memory 214624 kb
Host smart-64f66d3c-9d52-4bc0-80b8-fd3103cb97ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267963337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.267963337
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.192650721
Short name T1000
Test name
Test status
Simulation time 163685250 ps
CPU time 7.09 seconds
Started Jul 31 07:17:22 PM PDT 24
Finished Jul 31 07:17:29 PM PDT 24
Peak memory 220804 kb
Host smart-34d357c0-6cd1-4142-9639-62e656c99de3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192650721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.192650721
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3794190827
Short name T1002
Test name
Test status
Simulation time 33205200 ps
CPU time 2.3 seconds
Started Jul 31 07:17:18 PM PDT 24
Finished Jul 31 07:17:20 PM PDT 24
Peak memory 214436 kb
Host smart-28c34a57-82be-4b42-b3f5-d8634117ae32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794190827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3794190827
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2477040558
Short name T1026
Test name
Test status
Simulation time 69438473 ps
CPU time 1.53 seconds
Started Jul 31 07:17:24 PM PDT 24
Finished Jul 31 07:17:26 PM PDT 24
Peak memory 214456 kb
Host smart-a183e76c-c6bc-48ea-8fb9-f58c2af73604
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477040558 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2477040558
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3457159028
Short name T1075
Test name
Test status
Simulation time 14318942 ps
CPU time 1.07 seconds
Started Jul 31 07:17:23 PM PDT 24
Finished Jul 31 07:17:24 PM PDT 24
Peak memory 206068 kb
Host smart-e833ad9c-1468-4b7b-92ce-9ca14b9d6048
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457159028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3457159028
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2252205329
Short name T932
Test name
Test status
Simulation time 26700707 ps
CPU time 0.8 seconds
Started Jul 31 07:17:29 PM PDT 24
Finished Jul 31 07:17:30 PM PDT 24
Peak memory 205956 kb
Host smart-dee15cb2-2015-41d2-ab7b-4b9f4d6f4265
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252205329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2252205329
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.4087581295
Short name T1060
Test name
Test status
Simulation time 54242011 ps
CPU time 2.23 seconds
Started Jul 31 07:17:29 PM PDT 24
Finished Jul 31 07:17:31 PM PDT 24
Peak memory 206068 kb
Host smart-f27e2d1a-28cc-46cf-a004-865202c34ccd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087581295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.4087581295
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.753762005
Short name T1046
Test name
Test status
Simulation time 328767092 ps
CPU time 3.35 seconds
Started Jul 31 07:17:18 PM PDT 24
Finished Jul 31 07:17:21 PM PDT 24
Peak memory 214584 kb
Host smart-eb730379-7f95-4ac0-8af8-35797a480246
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753762005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.753762005
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2806151706
Short name T1015
Test name
Test status
Simulation time 503285609 ps
CPU time 6.81 seconds
Started Jul 31 07:17:17 PM PDT 24
Finished Jul 31 07:17:24 PM PDT 24
Peak memory 214636 kb
Host smart-5454cf8d-ed51-4c66-8a82-7ff3b037f665
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806151706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2806151706
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.563099943
Short name T942
Test name
Test status
Simulation time 43632079 ps
CPU time 1.51 seconds
Started Jul 31 07:17:24 PM PDT 24
Finished Jul 31 07:17:26 PM PDT 24
Peak memory 216464 kb
Host smart-45e78021-a2e8-41f1-b2b3-8f5d1e3f6050
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563099943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.563099943
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2781549242
Short name T171
Test name
Test status
Simulation time 255630931 ps
CPU time 8.43 seconds
Started Jul 31 07:17:24 PM PDT 24
Finished Jul 31 07:17:33 PM PDT 24
Peak memory 214276 kb
Host smart-728b58a6-2a80-444a-aef0-6f8592a15ebe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781549242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2781549242
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.52138648
Short name T1024
Test name
Test status
Simulation time 56711992 ps
CPU time 2.25 seconds
Started Jul 31 07:17:24 PM PDT 24
Finished Jul 31 07:17:26 PM PDT 24
Peak memory 214300 kb
Host smart-49d9f095-73c7-4a45-aa7d-351a460a4c02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52138648 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.52138648
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3744204117
Short name T1053
Test name
Test status
Simulation time 40643275 ps
CPU time 1.05 seconds
Started Jul 31 07:17:25 PM PDT 24
Finished Jul 31 07:17:26 PM PDT 24
Peak memory 206084 kb
Host smart-039ce496-1d0e-4203-b66f-68843d1d37e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744204117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3744204117
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1159986522
Short name T1025
Test name
Test status
Simulation time 39942120 ps
CPU time 0.82 seconds
Started Jul 31 07:17:24 PM PDT 24
Finished Jul 31 07:17:25 PM PDT 24
Peak memory 205964 kb
Host smart-d9a17985-b38b-4696-8c84-bb3cfe169110
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159986522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1159986522
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1230111493
Short name T144
Test name
Test status
Simulation time 141318564 ps
CPU time 2.68 seconds
Started Jul 31 07:17:23 PM PDT 24
Finished Jul 31 07:17:26 PM PDT 24
Peak memory 206152 kb
Host smart-0f0b2e96-f5af-4985-9fef-9d79b80f65a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230111493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1230111493
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2649485426
Short name T933
Test name
Test status
Simulation time 124069851 ps
CPU time 2.16 seconds
Started Jul 31 07:17:26 PM PDT 24
Finished Jul 31 07:17:29 PM PDT 24
Peak memory 214588 kb
Host smart-be06632b-b6aa-4fe9-99c6-edd62e8544fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649485426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2649485426
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2294425870
Short name T993
Test name
Test status
Simulation time 92687751 ps
CPU time 4.81 seconds
Started Jul 31 07:17:25 PM PDT 24
Finished Jul 31 07:17:30 PM PDT 24
Peak memory 214676 kb
Host smart-52f11be9-06b8-4513-bcd6-67225f245dfe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294425870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2294425870
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3967854425
Short name T1013
Test name
Test status
Simulation time 92961645 ps
CPU time 2.71 seconds
Started Jul 31 07:17:29 PM PDT 24
Finished Jul 31 07:17:31 PM PDT 24
Peak memory 214532 kb
Host smart-d914829e-7012-4efb-abfb-6ec6a9cc1122
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967854425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3967854425
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1803414821
Short name T1066
Test name
Test status
Simulation time 492651604 ps
CPU time 7.19 seconds
Started Jul 31 07:16:51 PM PDT 24
Finished Jul 31 07:16:58 PM PDT 24
Peak memory 206236 kb
Host smart-d8a8dc12-45ab-4808-8cc1-81dd313c5335
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803414821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
803414821
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2401323477
Short name T955
Test name
Test status
Simulation time 5058628400 ps
CPU time 16.35 seconds
Started Jul 31 07:16:49 PM PDT 24
Finished Jul 31 07:17:06 PM PDT 24
Peak memory 206152 kb
Host smart-5ec8b1d9-b113-42a4-8f54-0c7cdcf1ea25
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401323477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
401323477
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3570049744
Short name T935
Test name
Test status
Simulation time 31339296 ps
CPU time 0.9 seconds
Started Jul 31 07:16:50 PM PDT 24
Finished Jul 31 07:16:51 PM PDT 24
Peak memory 206036 kb
Host smart-617cb303-603a-4f7f-9510-4b94c18c8707
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570049744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
570049744
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3279891473
Short name T941
Test name
Test status
Simulation time 23822740 ps
CPU time 1.4 seconds
Started Jul 31 07:16:45 PM PDT 24
Finished Jul 31 07:16:46 PM PDT 24
Peak memory 206216 kb
Host smart-9660532f-9e76-4a15-acc2-a3bc3718df70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279891473 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3279891473
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3820383949
Short name T1078
Test name
Test status
Simulation time 45987576 ps
CPU time 1.42 seconds
Started Jul 31 07:16:45 PM PDT 24
Finished Jul 31 07:16:47 PM PDT 24
Peak memory 206196 kb
Host smart-599ca14c-6384-4264-b807-eca9e067942c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820383949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3820383949
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.997451937
Short name T1048
Test name
Test status
Simulation time 17430451 ps
CPU time 0.79 seconds
Started Jul 31 07:16:45 PM PDT 24
Finished Jul 31 07:16:46 PM PDT 24
Peak memory 205964 kb
Host smart-984e6cd0-eb49-4c5a-b239-270f1e08729f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997451937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.997451937
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3467618518
Short name T980
Test name
Test status
Simulation time 219950313 ps
CPU time 2.25 seconds
Started Jul 31 07:16:44 PM PDT 24
Finished Jul 31 07:16:47 PM PDT 24
Peak memory 206216 kb
Host smart-acfb49d9-fb87-421f-98d0-e8550e25b31f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467618518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3467618518
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.903190568
Short name T960
Test name
Test status
Simulation time 162234640 ps
CPU time 5.03 seconds
Started Jul 31 07:16:50 PM PDT 24
Finished Jul 31 07:16:55 PM PDT 24
Peak memory 214680 kb
Host smart-8ee4f032-b63f-417a-9a10-fd3e36abc2c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903190568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.903190568
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3727074004
Short name T1010
Test name
Test status
Simulation time 953270171 ps
CPU time 12.57 seconds
Started Jul 31 07:16:49 PM PDT 24
Finished Jul 31 07:17:02 PM PDT 24
Peak memory 220872 kb
Host smart-5b31f2f0-f235-4bf2-8fec-10a32761f2f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727074004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3727074004
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1758889658
Short name T1063
Test name
Test status
Simulation time 54065098 ps
CPU time 1.84 seconds
Started Jul 31 07:16:52 PM PDT 24
Finished Jul 31 07:16:54 PM PDT 24
Peak memory 214388 kb
Host smart-13a0981a-c758-4177-ab2d-3bd4381c4d05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758889658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1758889658
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.4092109641
Short name T1054
Test name
Test status
Simulation time 144397687 ps
CPU time 5.4 seconds
Started Jul 31 07:16:50 PM PDT 24
Finished Jul 31 07:16:55 PM PDT 24
Peak memory 214424 kb
Host smart-2d9a70da-966d-4bf1-ac6e-aec19aab76be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092109641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.4092109641
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3905127308
Short name T1020
Test name
Test status
Simulation time 106851363 ps
CPU time 0.73 seconds
Started Jul 31 07:17:25 PM PDT 24
Finished Jul 31 07:17:26 PM PDT 24
Peak memory 205872 kb
Host smart-2e0223e4-97c1-4647-bfda-5521c8867efe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905127308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3905127308
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3609574782
Short name T990
Test name
Test status
Simulation time 41895053 ps
CPU time 0.8 seconds
Started Jul 31 07:17:23 PM PDT 24
Finished Jul 31 07:17:24 PM PDT 24
Peak memory 205884 kb
Host smart-1d6cc10c-43fa-4c07-aadd-6d9a684cc3d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609574782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3609574782
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2904218135
Short name T988
Test name
Test status
Simulation time 11539692 ps
CPU time 0.78 seconds
Started Jul 31 07:17:25 PM PDT 24
Finished Jul 31 07:17:25 PM PDT 24
Peak memory 205868 kb
Host smart-4c3e6c86-2784-46d4-b0af-9fa165252d5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904218135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2904218135
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3976187788
Short name T975
Test name
Test status
Simulation time 15788479 ps
CPU time 0.82 seconds
Started Jul 31 07:17:24 PM PDT 24
Finished Jul 31 07:17:25 PM PDT 24
Peak memory 206040 kb
Host smart-d13ccb97-c0a4-44db-9c4c-833bd132fc06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976187788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3976187788
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3875347176
Short name T927
Test name
Test status
Simulation time 12654588 ps
CPU time 0.81 seconds
Started Jul 31 07:17:23 PM PDT 24
Finished Jul 31 07:17:24 PM PDT 24
Peak memory 205820 kb
Host smart-c48fcbf0-0501-4ed2-b26c-3be7253f78a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875347176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3875347176
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.161034288
Short name T1064
Test name
Test status
Simulation time 11205679 ps
CPU time 0.84 seconds
Started Jul 31 07:17:29 PM PDT 24
Finished Jul 31 07:17:30 PM PDT 24
Peak memory 205956 kb
Host smart-324e90d0-435d-4ca4-8931-0b8877f6fd29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161034288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.161034288
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3686761777
Short name T967
Test name
Test status
Simulation time 8377762 ps
CPU time 0.7 seconds
Started Jul 31 07:17:27 PM PDT 24
Finished Jul 31 07:17:28 PM PDT 24
Peak memory 205864 kb
Host smart-f964329b-61b2-4d16-ae24-b84771ef4749
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686761777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3686761777
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.53554329
Short name T1088
Test name
Test status
Simulation time 10243995 ps
CPU time 0.83 seconds
Started Jul 31 07:17:26 PM PDT 24
Finished Jul 31 07:17:27 PM PDT 24
Peak memory 205912 kb
Host smart-1c6a25a5-5d09-44fc-b0b3-b1bf43c22c49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53554329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.53554329
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2826374224
Short name T987
Test name
Test status
Simulation time 15462170 ps
CPU time 0.77 seconds
Started Jul 31 07:17:26 PM PDT 24
Finished Jul 31 07:17:27 PM PDT 24
Peak memory 205784 kb
Host smart-d69d6570-e37f-461e-aca2-bab242fc181c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826374224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2826374224
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3058954218
Short name T1068
Test name
Test status
Simulation time 24294742 ps
CPU time 0.75 seconds
Started Jul 31 07:17:27 PM PDT 24
Finished Jul 31 07:17:28 PM PDT 24
Peak memory 205788 kb
Host smart-52868f88-37b9-497d-8576-6ca78efb6f49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058954218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3058954218
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2401433960
Short name T1042
Test name
Test status
Simulation time 326877370 ps
CPU time 8.77 seconds
Started Jul 31 07:16:47 PM PDT 24
Finished Jul 31 07:16:56 PM PDT 24
Peak memory 206108 kb
Host smart-3c2bd2e6-b7ec-4314-85a0-1ba8e453e48a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401433960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
401433960
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.987748716
Short name T949
Test name
Test status
Simulation time 2667928079 ps
CPU time 16.95 seconds
Started Jul 31 07:16:49 PM PDT 24
Finished Jul 31 07:17:06 PM PDT 24
Peak memory 206328 kb
Host smart-0af3f771-4f20-491c-88a5-a50170cfe9c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987748716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.987748716
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1580207232
Short name T945
Test name
Test status
Simulation time 55033138 ps
CPU time 1.04 seconds
Started Jul 31 07:16:47 PM PDT 24
Finished Jul 31 07:16:48 PM PDT 24
Peak memory 205980 kb
Host smart-507e4c6b-5866-490f-b6e7-ef38e1bb2918
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580207232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
580207232
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2665771682
Short name T994
Test name
Test status
Simulation time 38859103 ps
CPU time 1.16 seconds
Started Jul 31 07:16:49 PM PDT 24
Finished Jul 31 07:16:50 PM PDT 24
Peak memory 206236 kb
Host smart-a7721915-cd97-4b46-a21f-eba12902f099
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665771682 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2665771682
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3176021818
Short name T1049
Test name
Test status
Simulation time 14952586 ps
CPU time 1 seconds
Started Jul 31 07:16:50 PM PDT 24
Finished Jul 31 07:16:51 PM PDT 24
Peak memory 205972 kb
Host smart-ed5b0eaf-a3de-4e0f-8c68-8252ba71c04f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176021818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3176021818
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2678986864
Short name T1061
Test name
Test status
Simulation time 34840015 ps
CPU time 0.81 seconds
Started Jul 31 07:16:49 PM PDT 24
Finished Jul 31 07:16:50 PM PDT 24
Peak memory 205752 kb
Host smart-5b0e4fc1-0d37-43fe-bd5e-347c45a3de9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678986864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2678986864
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.532715985
Short name T1021
Test name
Test status
Simulation time 21381738 ps
CPU time 1.36 seconds
Started Jul 31 07:16:50 PM PDT 24
Finished Jul 31 07:16:51 PM PDT 24
Peak memory 206156 kb
Host smart-d6eca644-ee23-4283-aca7-3b2984f53ab3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532715985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.532715985
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.253715223
Short name T968
Test name
Test status
Simulation time 511335770 ps
CPU time 2.82 seconds
Started Jul 31 07:16:50 PM PDT 24
Finished Jul 31 07:16:53 PM PDT 24
Peak memory 214784 kb
Host smart-cc5c4198-a95b-4d33-9495-f8b2ff88516c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253715223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.253715223
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1037145652
Short name T1033
Test name
Test status
Simulation time 220439899 ps
CPU time 9.66 seconds
Started Jul 31 07:16:44 PM PDT 24
Finished Jul 31 07:16:54 PM PDT 24
Peak memory 214676 kb
Host smart-d6039f04-2935-4485-8dc3-db43bdc803b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037145652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1037145652
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.4134147738
Short name T921
Test name
Test status
Simulation time 85150902 ps
CPU time 2.48 seconds
Started Jul 31 07:16:50 PM PDT 24
Finished Jul 31 07:16:53 PM PDT 24
Peak memory 214512 kb
Host smart-e96daefc-04e2-4679-8239-da03b9d81b2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134147738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.4134147738
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1624794248
Short name T167
Test name
Test status
Simulation time 148905439 ps
CPU time 5.66 seconds
Started Jul 31 07:16:45 PM PDT 24
Finished Jul 31 07:16:51 PM PDT 24
Peak memory 214236 kb
Host smart-aab89773-9e02-4de8-aae3-e299c457be9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624794248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1624794248
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3284804665
Short name T977
Test name
Test status
Simulation time 21046030 ps
CPU time 0.72 seconds
Started Jul 31 07:17:22 PM PDT 24
Finished Jul 31 07:17:23 PM PDT 24
Peak memory 205916 kb
Host smart-5a49f30c-5464-41cf-993d-409f5c2efb70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284804665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3284804665
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1175431490
Short name T959
Test name
Test status
Simulation time 45280510 ps
CPU time 0.84 seconds
Started Jul 31 07:17:24 PM PDT 24
Finished Jul 31 07:17:25 PM PDT 24
Peak memory 205876 kb
Host smart-16541aad-b704-4183-b4e5-5146075d1631
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175431490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1175431490
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.898887324
Short name T1082
Test name
Test status
Simulation time 27328154 ps
CPU time 0.78 seconds
Started Jul 31 07:17:25 PM PDT 24
Finished Jul 31 07:17:25 PM PDT 24
Peak memory 205960 kb
Host smart-5c90b880-35e2-4ce6-9d37-2db27c7b3775
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898887324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.898887324
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3220178336
Short name T1083
Test name
Test status
Simulation time 10485384 ps
CPU time 0.88 seconds
Started Jul 31 07:17:26 PM PDT 24
Finished Jul 31 07:17:27 PM PDT 24
Peak memory 205876 kb
Host smart-a425de85-277a-4d36-9c41-469bc5b22de5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220178336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3220178336
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2372921039
Short name T954
Test name
Test status
Simulation time 45633311 ps
CPU time 0.85 seconds
Started Jul 31 07:17:29 PM PDT 24
Finished Jul 31 07:17:30 PM PDT 24
Peak memory 205956 kb
Host smart-7ba0ee8d-f8dd-4837-a36e-ce29b9c6b664
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372921039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2372921039
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1978874367
Short name T946
Test name
Test status
Simulation time 18377591 ps
CPU time 0.79 seconds
Started Jul 31 07:17:29 PM PDT 24
Finished Jul 31 07:17:30 PM PDT 24
Peak memory 205956 kb
Host smart-47aac341-e030-4ddd-aa82-90a5500299ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978874367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1978874367
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3760779845
Short name T1038
Test name
Test status
Simulation time 26649612 ps
CPU time 0.76 seconds
Started Jul 31 07:17:27 PM PDT 24
Finished Jul 31 07:17:28 PM PDT 24
Peak memory 205904 kb
Host smart-a82af782-c34a-4db4-b8e6-89d62da7fe92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760779845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3760779845
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3732857050
Short name T1014
Test name
Test status
Simulation time 6749102 ps
CPU time 0.79 seconds
Started Jul 31 07:17:27 PM PDT 24
Finished Jul 31 07:17:28 PM PDT 24
Peak memory 205876 kb
Host smart-e3d526ab-7efb-42cb-8733-c4a086c3d822
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732857050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3732857050
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3996079352
Short name T985
Test name
Test status
Simulation time 21258802 ps
CPU time 0.83 seconds
Started Jul 31 07:17:26 PM PDT 24
Finished Jul 31 07:17:26 PM PDT 24
Peak memory 205948 kb
Host smart-f11ccace-af03-4db9-be55-1000a6eb8d44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996079352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3996079352
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2815838307
Short name T929
Test name
Test status
Simulation time 53001482 ps
CPU time 0.72 seconds
Started Jul 31 07:17:26 PM PDT 24
Finished Jul 31 07:17:27 PM PDT 24
Peak memory 205860 kb
Host smart-3585791f-2961-44dd-b6b4-984f29d232db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815838307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2815838307
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3006173910
Short name T145
Test name
Test status
Simulation time 2541573679 ps
CPU time 8.57 seconds
Started Jul 31 07:16:52 PM PDT 24
Finished Jul 31 07:17:00 PM PDT 24
Peak memory 206052 kb
Host smart-6e1758f8-5d54-4307-aa98-549b10743130
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006173910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
006173910
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3859951811
Short name T940
Test name
Test status
Simulation time 254938942 ps
CPU time 7.35 seconds
Started Jul 31 07:16:53 PM PDT 24
Finished Jul 31 07:17:00 PM PDT 24
Peak memory 206100 kb
Host smart-a685a450-77ea-4d7c-883b-c75bbbbe775c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859951811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
859951811
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2595456233
Short name T995
Test name
Test status
Simulation time 118332052 ps
CPU time 1.18 seconds
Started Jul 31 07:16:48 PM PDT 24
Finished Jul 31 07:16:49 PM PDT 24
Peak memory 206164 kb
Host smart-4e34b857-0067-4fca-89a2-c85f0030aed6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595456233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
595456233
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3350825345
Short name T1047
Test name
Test status
Simulation time 98744356 ps
CPU time 1.55 seconds
Started Jul 31 07:16:53 PM PDT 24
Finished Jul 31 07:16:55 PM PDT 24
Peak memory 214176 kb
Host smart-eee30393-5595-4d29-a094-caaeb30db0e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350825345 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3350825345
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3562275155
Short name T934
Test name
Test status
Simulation time 16238773 ps
CPU time 1.28 seconds
Started Jul 31 07:16:53 PM PDT 24
Finished Jul 31 07:16:54 PM PDT 24
Peak memory 206108 kb
Host smart-91de913b-5bcd-46dd-adf2-28cd413371ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562275155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3562275155
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.4029352737
Short name T971
Test name
Test status
Simulation time 12884362 ps
CPU time 0.82 seconds
Started Jul 31 07:16:48 PM PDT 24
Finished Jul 31 07:16:49 PM PDT 24
Peak memory 205852 kb
Host smart-285d815a-b4ba-4408-ba73-3c7e9361c685
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029352737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.4029352737
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1687547730
Short name T1035
Test name
Test status
Simulation time 51347727 ps
CPU time 2.06 seconds
Started Jul 31 07:16:53 PM PDT 24
Finished Jul 31 07:16:55 PM PDT 24
Peak memory 205720 kb
Host smart-af25f8e7-1f4a-4d41-bb40-8d8f36a91376
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687547730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1687547730
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.4074065790
Short name T969
Test name
Test status
Simulation time 69174047 ps
CPU time 2.34 seconds
Started Jul 31 07:16:51 PM PDT 24
Finished Jul 31 07:16:53 PM PDT 24
Peak memory 214632 kb
Host smart-2fd9cbab-3a9e-44fe-a89c-42155e60ddf2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074065790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.4074065790
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.747062337
Short name T112
Test name
Test status
Simulation time 405140643 ps
CPU time 7.64 seconds
Started Jul 31 07:16:48 PM PDT 24
Finished Jul 31 07:16:56 PM PDT 24
Peak memory 220492 kb
Host smart-149a08e1-3792-42c9-bbda-1dc86267e102
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747062337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.747062337
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2163061160
Short name T1041
Test name
Test status
Simulation time 124349960 ps
CPU time 2.25 seconds
Started Jul 31 07:16:57 PM PDT 24
Finished Jul 31 07:16:59 PM PDT 24
Peak memory 216968 kb
Host smart-f4fb613f-3b06-4d2e-976b-c81f87ceb238
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163061160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2163061160
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2161576409
Short name T164
Test name
Test status
Simulation time 151889889 ps
CPU time 6.57 seconds
Started Jul 31 07:16:52 PM PDT 24
Finished Jul 31 07:16:59 PM PDT 24
Peak memory 214364 kb
Host smart-b8b14502-ac3c-4600-b9cd-6e50d28cd9ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161576409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2161576409
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2655236667
Short name T1005
Test name
Test status
Simulation time 37410261 ps
CPU time 0.7 seconds
Started Jul 31 07:17:24 PM PDT 24
Finished Jul 31 07:17:25 PM PDT 24
Peak memory 205888 kb
Host smart-b85cae8c-eb95-4b53-87ce-ad15007761e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655236667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2655236667
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3814249901
Short name T1009
Test name
Test status
Simulation time 31111367 ps
CPU time 0.82 seconds
Started Jul 31 07:17:25 PM PDT 24
Finished Jul 31 07:17:26 PM PDT 24
Peak memory 205944 kb
Host smart-6149d5f9-1d4e-4c71-a24e-d5654de40328
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814249901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3814249901
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.4264508357
Short name T948
Test name
Test status
Simulation time 17275081 ps
CPU time 0.8 seconds
Started Jul 31 07:17:27 PM PDT 24
Finished Jul 31 07:17:28 PM PDT 24
Peak memory 205904 kb
Host smart-0f0ab99c-2501-4a0b-8d19-dc92b04b3bd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264508357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.4264508357
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3942036589
Short name T925
Test name
Test status
Simulation time 37977262 ps
CPU time 0.79 seconds
Started Jul 31 07:17:32 PM PDT 24
Finished Jul 31 07:17:33 PM PDT 24
Peak memory 205868 kb
Host smart-630b1430-e577-459e-9879-a0b5963bb9da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942036589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3942036589
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1875730674
Short name T1032
Test name
Test status
Simulation time 10629142 ps
CPU time 0.73 seconds
Started Jul 31 07:17:33 PM PDT 24
Finished Jul 31 07:17:34 PM PDT 24
Peak memory 205868 kb
Host smart-74449797-6c96-4de2-b24b-e69741c8c596
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875730674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1875730674
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.952324731
Short name T1074
Test name
Test status
Simulation time 30285058 ps
CPU time 0.76 seconds
Started Jul 31 07:17:34 PM PDT 24
Finished Jul 31 07:17:35 PM PDT 24
Peak memory 205956 kb
Host smart-f66adce8-aa79-4409-b426-222f80a53a1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952324731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.952324731
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3310830516
Short name T981
Test name
Test status
Simulation time 10567022 ps
CPU time 0.82 seconds
Started Jul 31 07:17:32 PM PDT 24
Finished Jul 31 07:17:33 PM PDT 24
Peak memory 205948 kb
Host smart-1ae40927-7a30-4955-9551-9df3fb64646b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310830516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3310830516
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.4164260053
Short name T1067
Test name
Test status
Simulation time 34622408 ps
CPU time 0.76 seconds
Started Jul 31 07:17:34 PM PDT 24
Finished Jul 31 07:17:35 PM PDT 24
Peak memory 205956 kb
Host smart-591bb83c-98d3-4660-bd36-b39a3b5f75d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164260053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.4164260053
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1294746952
Short name T1089
Test name
Test status
Simulation time 11672591 ps
CPU time 0.88 seconds
Started Jul 31 07:17:33 PM PDT 24
Finished Jul 31 07:17:34 PM PDT 24
Peak memory 205860 kb
Host smart-dce82675-b819-4bf7-ae97-11f110699d97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294746952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1294746952
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.275328873
Short name T943
Test name
Test status
Simulation time 103761686 ps
CPU time 0.71 seconds
Started Jul 31 07:17:34 PM PDT 24
Finished Jul 31 07:17:34 PM PDT 24
Peak memory 205900 kb
Host smart-ae795d38-28fa-4e47-aaf3-dc42f16b65bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275328873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.275328873
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2553646088
Short name T962
Test name
Test status
Simulation time 26923889 ps
CPU time 1.74 seconds
Started Jul 31 07:16:54 PM PDT 24
Finished Jul 31 07:16:56 PM PDT 24
Peak memory 214476 kb
Host smart-0fb16892-055e-4124-ab9f-16e8beed1af1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553646088 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2553646088
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.527736229
Short name T142
Test name
Test status
Simulation time 38240813 ps
CPU time 1.17 seconds
Started Jul 31 07:16:53 PM PDT 24
Finished Jul 31 07:16:55 PM PDT 24
Peak memory 206184 kb
Host smart-48ec0157-14df-45ff-b3f8-50dc14192ca4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527736229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.527736229
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3506609337
Short name T931
Test name
Test status
Simulation time 39852696 ps
CPU time 0.83 seconds
Started Jul 31 07:16:55 PM PDT 24
Finished Jul 31 07:16:56 PM PDT 24
Peak memory 205884 kb
Host smart-add81fb5-7f5d-4246-8587-e198ef688113
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506609337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3506609337
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1655509728
Short name T1045
Test name
Test status
Simulation time 85483311 ps
CPU time 3.42 seconds
Started Jul 31 07:16:55 PM PDT 24
Finished Jul 31 07:16:59 PM PDT 24
Peak memory 206096 kb
Host smart-c83c3bd8-b644-42a7-83ae-3c4b2f0e421d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655509728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.1655509728
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2487978400
Short name T982
Test name
Test status
Simulation time 58255998 ps
CPU time 2.36 seconds
Started Jul 31 07:16:56 PM PDT 24
Finished Jul 31 07:16:59 PM PDT 24
Peak memory 214664 kb
Host smart-8a62b065-a247-454b-a31e-87840f543158
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487978400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2487978400
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2729195728
Short name T952
Test name
Test status
Simulation time 959713810 ps
CPU time 7.67 seconds
Started Jul 31 07:16:53 PM PDT 24
Finished Jul 31 07:17:01 PM PDT 24
Peak memory 214688 kb
Host smart-3d1f7609-9962-4049-95f0-19c38d189aab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729195728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2729195728
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1903733625
Short name T1086
Test name
Test status
Simulation time 232432222 ps
CPU time 2.49 seconds
Started Jul 31 07:16:54 PM PDT 24
Finished Jul 31 07:16:56 PM PDT 24
Peak memory 216544 kb
Host smart-f96bb3a1-5721-40ef-a8aa-f91be91eddb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903733625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1903733625
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3278841875
Short name T1084
Test name
Test status
Simulation time 111046492 ps
CPU time 1.63 seconds
Started Jul 31 07:16:51 PM PDT 24
Finished Jul 31 07:16:52 PM PDT 24
Peak memory 214372 kb
Host smart-80c4df7d-d0b6-4942-8ef9-9d522afb9d6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278841875 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3278841875
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.109692559
Short name T1018
Test name
Test status
Simulation time 44043502 ps
CPU time 1.16 seconds
Started Jul 31 07:16:50 PM PDT 24
Finished Jul 31 07:16:52 PM PDT 24
Peak memory 206040 kb
Host smart-ca1ec32d-7e17-4cb0-a87c-7ee5c8cf43b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109692559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.109692559
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2723970696
Short name T1080
Test name
Test status
Simulation time 10594123 ps
CPU time 0.79 seconds
Started Jul 31 07:16:55 PM PDT 24
Finished Jul 31 07:16:56 PM PDT 24
Peak memory 205944 kb
Host smart-c2a398b8-1c24-4871-bd96-033f4d7f64ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723970696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2723970696
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1348077634
Short name T964
Test name
Test status
Simulation time 706823859 ps
CPU time 3.38 seconds
Started Jul 31 07:16:54 PM PDT 24
Finished Jul 31 07:16:57 PM PDT 24
Peak memory 206216 kb
Host smart-c47ab700-ee73-4a23-b517-d35330905eaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348077634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1348077634
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3701786248
Short name T1076
Test name
Test status
Simulation time 214179397 ps
CPU time 5.62 seconds
Started Jul 31 07:16:54 PM PDT 24
Finished Jul 31 07:17:00 PM PDT 24
Peak memory 214864 kb
Host smart-268f4f66-dd32-4c20-bf11-35ec810bfbb6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701786248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3701786248
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3559215345
Short name T1019
Test name
Test status
Simulation time 195637618 ps
CPU time 5.36 seconds
Started Jul 31 07:16:56 PM PDT 24
Finished Jul 31 07:17:01 PM PDT 24
Peak memory 214752 kb
Host smart-0eb50ca1-9cbc-4525-88f4-c79994a72900
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559215345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3559215345
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.4020193003
Short name T1069
Test name
Test status
Simulation time 444350770 ps
CPU time 2.82 seconds
Started Jul 31 07:16:55 PM PDT 24
Finished Jul 31 07:16:58 PM PDT 24
Peak memory 214548 kb
Host smart-0fb4b7ab-d345-48a1-aa4e-c7f5d98ea0ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020193003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.4020193003
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.77933548
Short name T162
Test name
Test status
Simulation time 101265864 ps
CPU time 2.6 seconds
Started Jul 31 07:16:55 PM PDT 24
Finished Jul 31 07:16:58 PM PDT 24
Peak memory 214300 kb
Host smart-82926ce1-61af-4f3e-aaed-6b4af4a0735d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77933548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.77933548
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3524206191
Short name T938
Test name
Test status
Simulation time 19274434 ps
CPU time 1.2 seconds
Started Jul 31 07:16:50 PM PDT 24
Finished Jul 31 07:16:51 PM PDT 24
Peak memory 206240 kb
Host smart-f7160545-1ffd-44f8-bd14-c4f7fd2079f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524206191 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3524206191
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2455096028
Short name T141
Test name
Test status
Simulation time 13615062 ps
CPU time 1.21 seconds
Started Jul 31 07:16:43 PM PDT 24
Finished Jul 31 07:16:45 PM PDT 24
Peak memory 206240 kb
Host smart-9704c50d-6694-4c82-8aa5-bff3ca6f38de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455096028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2455096028
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2455813723
Short name T986
Test name
Test status
Simulation time 15653702 ps
CPU time 0.73 seconds
Started Jul 31 07:16:54 PM PDT 24
Finished Jul 31 07:16:55 PM PDT 24
Peak memory 205884 kb
Host smart-676e2a30-376c-420f-b544-09def3084e88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455813723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2455813723
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2596908147
Short name T1003
Test name
Test status
Simulation time 90987973 ps
CPU time 2.45 seconds
Started Jul 31 07:16:50 PM PDT 24
Finished Jul 31 07:16:52 PM PDT 24
Peak memory 206228 kb
Host smart-18d2e707-2409-4c8d-ae94-ee046c66d996
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596908147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2596908147
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1171986120
Short name T966
Test name
Test status
Simulation time 138053172 ps
CPU time 1.61 seconds
Started Jul 31 07:16:54 PM PDT 24
Finished Jul 31 07:16:56 PM PDT 24
Peak memory 214628 kb
Host smart-a461b375-e28a-4804-8c18-f2b88c8792d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171986120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1171986120
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.901125092
Short name T116
Test name
Test status
Simulation time 1472424843 ps
CPU time 9.96 seconds
Started Jul 31 07:16:56 PM PDT 24
Finished Jul 31 07:17:06 PM PDT 24
Peak memory 214728 kb
Host smart-d59f1377-50b1-4f41-848d-a0887a3213eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901125092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.901125092
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3342449983
Short name T992
Test name
Test status
Simulation time 296633175 ps
CPU time 3.67 seconds
Started Jul 31 07:16:51 PM PDT 24
Finished Jul 31 07:16:55 PM PDT 24
Peak memory 214352 kb
Host smart-f8f079e0-b014-4d5b-ab56-070a20a773ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342449983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3342449983
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1465759114
Short name T174
Test name
Test status
Simulation time 400570443 ps
CPU time 3.52 seconds
Started Jul 31 07:16:54 PM PDT 24
Finished Jul 31 07:16:57 PM PDT 24
Peak memory 214212 kb
Host smart-e534b785-fb1e-4ca3-b415-0709a661c41e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465759114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1465759114
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3751332499
Short name T1037
Test name
Test status
Simulation time 193884387 ps
CPU time 2.32 seconds
Started Jul 31 07:16:52 PM PDT 24
Finished Jul 31 07:16:54 PM PDT 24
Peak memory 214424 kb
Host smart-4a2a19b3-a37c-4f44-920a-bb5ea5fb759b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751332499 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3751332499
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1546128720
Short name T937
Test name
Test status
Simulation time 63376074 ps
CPU time 1.08 seconds
Started Jul 31 07:16:54 PM PDT 24
Finished Jul 31 07:16:55 PM PDT 24
Peak memory 206168 kb
Host smart-1e562c9f-fde0-4299-be43-90345d62ec18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546128720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1546128720
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1248983236
Short name T922
Test name
Test status
Simulation time 87952536 ps
CPU time 0.75 seconds
Started Jul 31 07:16:55 PM PDT 24
Finished Jul 31 07:16:56 PM PDT 24
Peak memory 205972 kb
Host smart-f060d24f-c416-4b7d-b0b5-920cf0d9f159
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248983236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1248983236
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.368578065
Short name T1072
Test name
Test status
Simulation time 130031610 ps
CPU time 2.05 seconds
Started Jul 31 07:16:52 PM PDT 24
Finished Jul 31 07:16:54 PM PDT 24
Peak memory 206168 kb
Host smart-e77c52a1-6e26-418e-b53d-8b58f3e302c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368578065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.368578065
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1279853355
Short name T944
Test name
Test status
Simulation time 207588422 ps
CPU time 2.93 seconds
Started Jul 31 07:16:49 PM PDT 24
Finished Jul 31 07:16:52 PM PDT 24
Peak memory 214676 kb
Host smart-2e906454-5f5a-4ee5-8327-c65635999c63
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279853355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1279853355
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3444330250
Short name T965
Test name
Test status
Simulation time 204008120 ps
CPU time 7.45 seconds
Started Jul 31 07:16:50 PM PDT 24
Finished Jul 31 07:16:58 PM PDT 24
Peak memory 214612 kb
Host smart-b726f9e5-3873-4c1a-b632-203e0e64a77c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444330250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3444330250
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1448761678
Short name T923
Test name
Test status
Simulation time 130685546 ps
CPU time 4.55 seconds
Started Jul 31 07:16:53 PM PDT 24
Finished Jul 31 07:16:58 PM PDT 24
Peak memory 214364 kb
Host smart-3bf7028b-60ae-43ac-9ccc-56060c9210fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448761678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1448761678
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.654411399
Short name T1052
Test name
Test status
Simulation time 50114910 ps
CPU time 1.32 seconds
Started Jul 31 07:16:55 PM PDT 24
Finished Jul 31 07:16:56 PM PDT 24
Peak memory 206332 kb
Host smart-96ac6eda-fa5d-4144-93a0-31d34ba10683
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654411399 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.654411399
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1878503949
Short name T983
Test name
Test status
Simulation time 44828953 ps
CPU time 1.07 seconds
Started Jul 31 07:16:55 PM PDT 24
Finished Jul 31 07:16:56 PM PDT 24
Peak memory 206364 kb
Host smart-ad1fcd08-24eb-46f2-9628-825f8aa5b446
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878503949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1878503949
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2275783953
Short name T972
Test name
Test status
Simulation time 10862356 ps
CPU time 0.83 seconds
Started Jul 31 07:16:52 PM PDT 24
Finished Jul 31 07:16:53 PM PDT 24
Peak memory 205880 kb
Host smart-755b3140-b6ee-45f8-90bd-7df9e43e63ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275783953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2275783953
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2241857644
Short name T1057
Test name
Test status
Simulation time 20418883 ps
CPU time 1.24 seconds
Started Jul 31 07:16:51 PM PDT 24
Finished Jul 31 07:16:53 PM PDT 24
Peak memory 206164 kb
Host smart-7b82cda8-5e8e-4a62-bf20-8570aa0aab4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241857644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.2241857644
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2630425850
Short name T970
Test name
Test status
Simulation time 82362567 ps
CPU time 1.76 seconds
Started Jul 31 07:16:52 PM PDT 24
Finished Jul 31 07:16:54 PM PDT 24
Peak memory 214456 kb
Host smart-05136da8-ffa1-4809-9ff8-cb7009931161
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630425850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2630425850
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.4290293851
Short name T974
Test name
Test status
Simulation time 125527566 ps
CPU time 4.73 seconds
Started Jul 31 07:16:55 PM PDT 24
Finished Jul 31 07:17:00 PM PDT 24
Peak memory 214440 kb
Host smart-e9d9897f-96aa-4121-8376-d53d6f204f0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290293851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.4290293851
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2471162059
Short name T480
Test name
Test status
Simulation time 12335933 ps
CPU time 0.87 seconds
Started Jul 31 05:36:09 PM PDT 24
Finished Jul 31 05:36:10 PM PDT 24
Peak memory 205940 kb
Host smart-6db4317c-8e9b-49c3-9aff-b1e92aa1a6ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471162059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2471162059
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3905251822
Short name T132
Test name
Test status
Simulation time 105145005 ps
CPU time 3.39 seconds
Started Jul 31 05:36:09 PM PDT 24
Finished Jul 31 05:36:12 PM PDT 24
Peak memory 214292 kb
Host smart-982c8510-3401-4bb6-aa22-3d5444189e72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3905251822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3905251822
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3541998970
Short name T101
Test name
Test status
Simulation time 113874835 ps
CPU time 4.61 seconds
Started Jul 31 05:36:10 PM PDT 24
Finished Jul 31 05:36:15 PM PDT 24
Peak memory 214324 kb
Host smart-82891abb-5393-415e-975c-468e6bbdfb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541998970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3541998970
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.678857801
Short name T86
Test name
Test status
Simulation time 615682460 ps
CPU time 4.18 seconds
Started Jul 31 05:36:11 PM PDT 24
Finished Jul 31 05:36:15 PM PDT 24
Peak memory 214376 kb
Host smart-7a0ee17c-07ad-4835-816d-3681e8b3d726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678857801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.678857801
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1172986335
Short name T65
Test name
Test status
Simulation time 154040835 ps
CPU time 3.17 seconds
Started Jul 31 05:36:09 PM PDT 24
Finished Jul 31 05:36:12 PM PDT 24
Peak memory 209196 kb
Host smart-dc43eb35-1543-4eb1-9e0d-b8b0f43552f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172986335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1172986335
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.503580579
Short name T198
Test name
Test status
Simulation time 72964962 ps
CPU time 2.94 seconds
Started Jul 31 05:36:08 PM PDT 24
Finished Jul 31 05:36:11 PM PDT 24
Peak memory 214324 kb
Host smart-f2f42c26-763c-418c-bca9-f60c825253d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503580579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.503580579
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2006820466
Short name T653
Test name
Test status
Simulation time 249201037 ps
CPU time 2.83 seconds
Started Jul 31 05:36:08 PM PDT 24
Finished Jul 31 05:36:11 PM PDT 24
Peak memory 207944 kb
Host smart-d2ba544f-2925-49ed-9df8-2606dabc9a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006820466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2006820466
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.2628228162
Short name T732
Test name
Test status
Simulation time 423076986 ps
CPU time 2.21 seconds
Started Jul 31 05:36:09 PM PDT 24
Finished Jul 31 05:36:11 PM PDT 24
Peak memory 208880 kb
Host smart-994e3262-e0f0-4e90-ba44-c03c5107b67f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628228162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2628228162
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2867502194
Short name T893
Test name
Test status
Simulation time 951911174 ps
CPU time 12.8 seconds
Started Jul 31 05:36:11 PM PDT 24
Finished Jul 31 05:36:24 PM PDT 24
Peak memory 207948 kb
Host smart-1cb5eafc-e1dd-4668-a342-09cd1bcc3656
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867502194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2867502194
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3783338416
Short name T703
Test name
Test status
Simulation time 4038900975 ps
CPU time 25.99 seconds
Started Jul 31 05:36:10 PM PDT 24
Finished Jul 31 05:36:36 PM PDT 24
Peak memory 209004 kb
Host smart-2c0e4cb0-bdce-4c4f-9153-7f52923150e2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783338416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3783338416
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.3681124395
Short name T405
Test name
Test status
Simulation time 1074080703 ps
CPU time 4.09 seconds
Started Jul 31 05:36:09 PM PDT 24
Finished Jul 31 05:36:13 PM PDT 24
Peak memory 214308 kb
Host smart-ce8ffb91-e6c9-4c21-b692-105218796cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681124395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3681124395
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.888701780
Short name T491
Test name
Test status
Simulation time 414009826 ps
CPU time 6.77 seconds
Started Jul 31 05:36:09 PM PDT 24
Finished Jul 31 05:36:16 PM PDT 24
Peak memory 206756 kb
Host smart-5f85762c-b10c-4404-8592-acbbefd26a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888701780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.888701780
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.2349874145
Short name T258
Test name
Test status
Simulation time 193132400 ps
CPU time 14.38 seconds
Started Jul 31 05:36:12 PM PDT 24
Finished Jul 31 05:36:26 PM PDT 24
Peak memory 221532 kb
Host smart-0bd5d082-9082-48c0-aa19-cc6d10234ef5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349874145 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.2349874145
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.4183623721
Short name T506
Test name
Test status
Simulation time 174392271 ps
CPU time 4.09 seconds
Started Jul 31 05:36:07 PM PDT 24
Finished Jul 31 05:36:11 PM PDT 24
Peak memory 207224 kb
Host smart-b9fb9119-0226-4851-a9a4-ccb3908fbebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183623721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.4183623721
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.958284751
Short name T892
Test name
Test status
Simulation time 138141935 ps
CPU time 2.97 seconds
Started Jul 31 05:36:09 PM PDT 24
Finished Jul 31 05:36:12 PM PDT 24
Peak memory 210360 kb
Host smart-1e3ca661-fb65-4d8f-a56c-b654f44f811c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958284751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.958284751
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1975614269
Short name T575
Test name
Test status
Simulation time 10954002 ps
CPU time 0.75 seconds
Started Jul 31 05:36:18 PM PDT 24
Finished Jul 31 05:36:18 PM PDT 24
Peak memory 205944 kb
Host smart-fadb3294-69a1-454e-9a99-ccc89cf9ef6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975614269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1975614269
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3300160032
Short name T782
Test name
Test status
Simulation time 313752077 ps
CPU time 3.02 seconds
Started Jul 31 05:36:08 PM PDT 24
Finished Jul 31 05:36:11 PM PDT 24
Peak memory 214252 kb
Host smart-35ef3f3f-ee67-4def-aafe-1c6430caed12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300160032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3300160032
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3211646308
Short name T209
Test name
Test status
Simulation time 296616145 ps
CPU time 3.17 seconds
Started Jul 31 05:36:10 PM PDT 24
Finished Jul 31 05:36:13 PM PDT 24
Peak memory 215492 kb
Host smart-e7d77239-4b37-40bf-9cb1-fef768faef07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211646308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3211646308
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.684954510
Short name T686
Test name
Test status
Simulation time 87363007 ps
CPU time 3.82 seconds
Started Jul 31 05:36:09 PM PDT 24
Finished Jul 31 05:36:13 PM PDT 24
Peak memory 208824 kb
Host smart-c3793176-3c4f-4fe0-91f3-0b717fb030ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684954510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.684954510
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.900248624
Short name T368
Test name
Test status
Simulation time 55899996 ps
CPU time 2.34 seconds
Started Jul 31 05:36:09 PM PDT 24
Finished Jul 31 05:36:11 PM PDT 24
Peak memory 206972 kb
Host smart-e6a87abc-7afc-474b-ab52-4d287546c560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900248624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.900248624
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.864419702
Short name T623
Test name
Test status
Simulation time 855022431 ps
CPU time 2.99 seconds
Started Jul 31 05:36:09 PM PDT 24
Finished Jul 31 05:36:12 PM PDT 24
Peak memory 206816 kb
Host smart-17e0f7bc-fea9-4a03-859b-a4fdcdf1d22a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864419702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.864419702
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1766913886
Short name T680
Test name
Test status
Simulation time 379504025 ps
CPU time 7.39 seconds
Started Jul 31 05:36:11 PM PDT 24
Finished Jul 31 05:36:18 PM PDT 24
Peak memory 208448 kb
Host smart-3808ddce-a054-4987-8c2a-580cad1655cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766913886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1766913886
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2984241853
Short name T387
Test name
Test status
Simulation time 98855200 ps
CPU time 3.45 seconds
Started Jul 31 05:36:08 PM PDT 24
Finished Jul 31 05:36:12 PM PDT 24
Peak memory 208756 kb
Host smart-4968dd26-bd1a-4cae-8a67-2d64071c742e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984241853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2984241853
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.819023209
Short name T609
Test name
Test status
Simulation time 75738504 ps
CPU time 2.93 seconds
Started Jul 31 05:36:10 PM PDT 24
Finished Jul 31 05:36:13 PM PDT 24
Peak memory 218132 kb
Host smart-c896b6ce-5f94-4020-ae55-3fd92a63c947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819023209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.819023209
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.605283828
Short name T203
Test name
Test status
Simulation time 4747291209 ps
CPU time 25.37 seconds
Started Jul 31 05:36:08 PM PDT 24
Finished Jul 31 05:36:33 PM PDT 24
Peak memory 208808 kb
Host smart-faa94ed3-dac6-4f03-ad87-45dcf1a55199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605283828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.605283828
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.396704175
Short name T283
Test name
Test status
Simulation time 223209017 ps
CPU time 6.37 seconds
Started Jul 31 05:36:16 PM PDT 24
Finished Jul 31 05:36:23 PM PDT 24
Peak memory 215684 kb
Host smart-9d215681-a8a2-4cac-9a4c-cc46fc6c0bd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396704175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.396704175
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.3526312036
Short name T584
Test name
Test status
Simulation time 484523616 ps
CPU time 8.08 seconds
Started Jul 31 05:36:16 PM PDT 24
Finished Jul 31 05:36:24 PM PDT 24
Peak memory 222536 kb
Host smart-7d21e582-a958-488c-b86d-b3699abf8926
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526312036 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.3526312036
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2287622913
Short name T621
Test name
Test status
Simulation time 95446653 ps
CPU time 4.62 seconds
Started Jul 31 05:36:10 PM PDT 24
Finished Jul 31 05:36:15 PM PDT 24
Peak memory 207580 kb
Host smart-140c0704-7f9f-4465-804d-52f68e6511db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287622913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2287622913
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2068063006
Short name T789
Test name
Test status
Simulation time 87295197 ps
CPU time 2.12 seconds
Started Jul 31 05:36:07 PM PDT 24
Finished Jul 31 05:36:09 PM PDT 24
Peak memory 210760 kb
Host smart-46c4d817-4f3a-40b6-afe7-356d69fc3ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068063006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2068063006
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3354454191
Short name T805
Test name
Test status
Simulation time 16948872 ps
CPU time 0.76 seconds
Started Jul 31 05:36:51 PM PDT 24
Finished Jul 31 05:36:52 PM PDT 24
Peak memory 205980 kb
Host smart-36f72ade-baa5-4eb4-a9df-721de92f5a8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354454191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3354454191
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3881776797
Short name T423
Test name
Test status
Simulation time 1327438763 ps
CPU time 71.41 seconds
Started Jul 31 05:36:51 PM PDT 24
Finished Jul 31 05:38:03 PM PDT 24
Peak memory 214384 kb
Host smart-49f86717-5e05-4b08-a991-191cdbf02b99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3881776797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3881776797
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1392812317
Short name T26
Test name
Test status
Simulation time 151498134 ps
CPU time 3.88 seconds
Started Jul 31 05:36:57 PM PDT 24
Finished Jul 31 05:37:01 PM PDT 24
Peak memory 208896 kb
Host smart-eb3ae6d3-edf7-4c4f-b77a-c64020b521db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392812317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1392812317
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.605564549
Short name T197
Test name
Test status
Simulation time 219289778 ps
CPU time 1.91 seconds
Started Jul 31 05:36:53 PM PDT 24
Finished Jul 31 05:36:55 PM PDT 24
Peak memory 208176 kb
Host smart-9e6571d9-8c8e-477b-82ff-ebdf0bfeeb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605564549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.605564549
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2179726471
Short name T91
Test name
Test status
Simulation time 8608642558 ps
CPU time 66.92 seconds
Started Jul 31 05:36:51 PM PDT 24
Finished Jul 31 05:37:58 PM PDT 24
Peak memory 214348 kb
Host smart-093c32b6-8a7c-49f9-af2e-7b135d4e1b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179726471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2179726471
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3411051352
Short name T711
Test name
Test status
Simulation time 98793616 ps
CPU time 2.58 seconds
Started Jul 31 05:36:52 PM PDT 24
Finished Jul 31 05:36:54 PM PDT 24
Peak memory 219952 kb
Host smart-bc5c2569-e7c4-4012-b7e1-5a0967c892db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411051352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3411051352
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3365290615
Short name T604
Test name
Test status
Simulation time 51574620 ps
CPU time 2.37 seconds
Started Jul 31 05:36:56 PM PDT 24
Finished Jul 31 05:36:58 PM PDT 24
Peak memory 209612 kb
Host smart-57474f1b-bbe2-4342-a3db-7982ef5d9e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365290615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3365290615
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.489323304
Short name T590
Test name
Test status
Simulation time 905518428 ps
CPU time 5.29 seconds
Started Jul 31 05:36:50 PM PDT 24
Finished Jul 31 05:36:56 PM PDT 24
Peak memory 209688 kb
Host smart-67cc7a21-9ed2-4c08-9193-d8099adb4b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489323304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.489323304
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.728683548
Short name T724
Test name
Test status
Simulation time 209002893 ps
CPU time 3.16 seconds
Started Jul 31 05:36:49 PM PDT 24
Finished Jul 31 05:36:52 PM PDT 24
Peak memory 208588 kb
Host smart-b0c2dd96-9736-4629-adab-8f219cccbd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728683548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.728683548
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.510124049
Short name T556
Test name
Test status
Simulation time 306514396 ps
CPU time 3.05 seconds
Started Jul 31 05:36:47 PM PDT 24
Finished Jul 31 05:36:50 PM PDT 24
Peak memory 208844 kb
Host smart-a1b6e58b-3066-457f-bc1b-5d8042d755d1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510124049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.510124049
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1710139532
Short name T542
Test name
Test status
Simulation time 1055541949 ps
CPU time 14.41 seconds
Started Jul 31 05:36:48 PM PDT 24
Finished Jul 31 05:37:03 PM PDT 24
Peak memory 208992 kb
Host smart-ee0a94b2-4326-4d76-ae07-fc898067d8bf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710139532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1710139532
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.1578912710
Short name T503
Test name
Test status
Simulation time 72277479 ps
CPU time 3.38 seconds
Started Jul 31 05:36:50 PM PDT 24
Finished Jul 31 05:36:54 PM PDT 24
Peak memory 208900 kb
Host smart-818a7cf6-ebfa-4bea-8763-ac1962383b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578912710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1578912710
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.932818947
Short name T692
Test name
Test status
Simulation time 425455269 ps
CPU time 7.9 seconds
Started Jul 31 05:36:47 PM PDT 24
Finished Jul 31 05:36:55 PM PDT 24
Peak memory 208172 kb
Host smart-dea03450-38f0-4c63-920c-0b501031b768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932818947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.932818947
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3350852775
Short name T845
Test name
Test status
Simulation time 286333445 ps
CPU time 13.1 seconds
Started Jul 31 05:36:52 PM PDT 24
Finished Jul 31 05:37:06 PM PDT 24
Peak memory 219600 kb
Host smart-1638098c-086b-4bf0-8839-6769dd8fc6e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350852775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3350852775
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1277469902
Short name T185
Test name
Test status
Simulation time 29777180 ps
CPU time 0.81 seconds
Started Jul 31 05:36:57 PM PDT 24
Finished Jul 31 05:36:58 PM PDT 24
Peak memory 205948 kb
Host smart-ef390bf5-fcc0-455c-97c3-9355064fb9f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277469902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1277469902
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.4097876616
Short name T314
Test name
Test status
Simulation time 156182636 ps
CPU time 3.44 seconds
Started Jul 31 05:36:50 PM PDT 24
Finished Jul 31 05:36:54 PM PDT 24
Peak memory 215256 kb
Host smart-3c2c651f-8f28-4e47-af70-5cc0dc5aa16a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4097876616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.4097876616
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.651720621
Short name T40
Test name
Test status
Simulation time 327482121 ps
CPU time 4.89 seconds
Started Jul 31 05:36:56 PM PDT 24
Finished Jul 31 05:37:01 PM PDT 24
Peak memory 209380 kb
Host smart-46ce5793-8049-47cd-8c48-c4060e51c896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651720621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.651720621
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3930183865
Short name T75
Test name
Test status
Simulation time 772410933 ps
CPU time 4.18 seconds
Started Jul 31 05:36:52 PM PDT 24
Finished Jul 31 05:36:56 PM PDT 24
Peak memory 214324 kb
Host smart-cb6ae7fb-af43-4c18-9df6-00b32202ddfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930183865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3930183865
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1741174458
Short name T310
Test name
Test status
Simulation time 376574799 ps
CPU time 5.76 seconds
Started Jul 31 05:36:53 PM PDT 24
Finished Jul 31 05:36:58 PM PDT 24
Peak memory 214272 kb
Host smart-f80f174e-7044-4f1e-93cf-b5e35d72de57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741174458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1741174458
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1663185665
Short name T613
Test name
Test status
Simulation time 135506253 ps
CPU time 5.47 seconds
Started Jul 31 05:36:57 PM PDT 24
Finished Jul 31 05:37:03 PM PDT 24
Peak memory 214292 kb
Host smart-8dec218e-0c63-43ee-8172-30364e0fe538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663185665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1663185665
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.536054116
Short name T811
Test name
Test status
Simulation time 983029545 ps
CPU time 7.27 seconds
Started Jul 31 05:36:51 PM PDT 24
Finished Jul 31 05:36:59 PM PDT 24
Peak memory 208696 kb
Host smart-61ae5671-f142-4be0-99a8-17ac3e0cefc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536054116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.536054116
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.639200222
Short name T483
Test name
Test status
Simulation time 198034242 ps
CPU time 6.71 seconds
Started Jul 31 05:36:54 PM PDT 24
Finished Jul 31 05:37:01 PM PDT 24
Peak memory 207940 kb
Host smart-9829c879-be61-4c01-9585-8581512cbcb1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639200222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.639200222
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1809844819
Short name T598
Test name
Test status
Simulation time 363970923 ps
CPU time 3.86 seconds
Started Jul 31 05:36:56 PM PDT 24
Finished Jul 31 05:37:00 PM PDT 24
Peak memory 208844 kb
Host smart-0fb76928-b988-415f-b05d-f1f2194a2552
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809844819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1809844819
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3755132306
Short name T375
Test name
Test status
Simulation time 73219242 ps
CPU time 3.16 seconds
Started Jul 31 05:36:58 PM PDT 24
Finished Jul 31 05:37:01 PM PDT 24
Peak memory 209084 kb
Host smart-5032f0d9-5011-4286-87e5-541ea2c0f699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755132306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3755132306
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3213431206
Short name T630
Test name
Test status
Simulation time 146992203 ps
CPU time 2.5 seconds
Started Jul 31 05:36:52 PM PDT 24
Finished Jul 31 05:36:54 PM PDT 24
Peak memory 206680 kb
Host smart-d2ae70e2-6614-48e2-9298-844016186246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213431206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3213431206
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.4175848333
Short name T17
Test name
Test status
Simulation time 283884661 ps
CPU time 3.81 seconds
Started Jul 31 05:36:53 PM PDT 24
Finished Jul 31 05:36:57 PM PDT 24
Peak memory 208240 kb
Host smart-1b482440-c001-4180-9368-10f3b62fcecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175848333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.4175848333
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.443631291
Short name T633
Test name
Test status
Simulation time 368688032 ps
CPU time 2.75 seconds
Started Jul 31 05:36:57 PM PDT 24
Finished Jul 31 05:37:00 PM PDT 24
Peak memory 210344 kb
Host smart-7d9eb812-43a6-4839-a7a2-7855a22b4752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443631291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.443631291
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1586877931
Short name T701
Test name
Test status
Simulation time 40263003 ps
CPU time 0.72 seconds
Started Jul 31 05:36:56 PM PDT 24
Finished Jul 31 05:36:56 PM PDT 24
Peak memory 205964 kb
Host smart-1f3f155b-4c8f-409a-8a72-14e9d122a636
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586877931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1586877931
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3979950733
Short name T688
Test name
Test status
Simulation time 139308250 ps
CPU time 2.92 seconds
Started Jul 31 05:36:57 PM PDT 24
Finished Jul 31 05:37:00 PM PDT 24
Peak memory 209228 kb
Host smart-761478f0-7274-4c31-be22-2b57d55962ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979950733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3979950733
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2313971779
Short name T605
Test name
Test status
Simulation time 51658105 ps
CPU time 3.16 seconds
Started Jul 31 05:36:57 PM PDT 24
Finished Jul 31 05:37:01 PM PDT 24
Peak memory 208680 kb
Host smart-186c888b-10bb-4679-abd7-35b01cb98a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313971779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2313971779
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1448415209
Short name T303
Test name
Test status
Simulation time 42905239 ps
CPU time 2.17 seconds
Started Jul 31 05:36:56 PM PDT 24
Finished Jul 31 05:36:59 PM PDT 24
Peak memory 218856 kb
Host smart-61313cde-22f1-40a0-99a4-94f20f06b913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448415209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1448415209
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.838843176
Short name T509
Test name
Test status
Simulation time 195626185 ps
CPU time 3.56 seconds
Started Jul 31 05:37:03 PM PDT 24
Finished Jul 31 05:37:07 PM PDT 24
Peak memory 222440 kb
Host smart-2cc6c4c7-bf84-41b1-b301-f5526ce13642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838843176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.838843176
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.228600177
Short name T373
Test name
Test status
Simulation time 491099399 ps
CPU time 7.17 seconds
Started Jul 31 05:36:55 PM PDT 24
Finished Jul 31 05:37:02 PM PDT 24
Peak memory 210504 kb
Host smart-451f01ec-a2b8-4ca1-b794-9cb5c6c93924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228600177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.228600177
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.997559660
Short name T713
Test name
Test status
Simulation time 3768634993 ps
CPU time 71.24 seconds
Started Jul 31 05:36:59 PM PDT 24
Finished Jul 31 05:38:10 PM PDT 24
Peak memory 208648 kb
Host smart-fda24a20-cf61-42d5-b040-bb80ee22c9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997559660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.997559660
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2315848314
Short name T587
Test name
Test status
Simulation time 357965912 ps
CPU time 6.77 seconds
Started Jul 31 05:36:59 PM PDT 24
Finished Jul 31 05:37:05 PM PDT 24
Peak memory 207968 kb
Host smart-e78ed3aa-6005-4faf-a1dc-916c50d5b212
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315848314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2315848314
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.242239375
Short name T526
Test name
Test status
Simulation time 21376001 ps
CPU time 1.85 seconds
Started Jul 31 05:36:57 PM PDT 24
Finished Jul 31 05:36:59 PM PDT 24
Peak memory 207048 kb
Host smart-9035fc10-46f1-4cb2-960e-2000a57383cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242239375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.242239375
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.427054294
Short name T607
Test name
Test status
Simulation time 333616462 ps
CPU time 4.19 seconds
Started Jul 31 05:36:58 PM PDT 24
Finished Jul 31 05:37:03 PM PDT 24
Peak memory 208892 kb
Host smart-6e558f4e-4d9a-4cc7-bdd4-59cfc63ae070
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427054294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.427054294
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2926415214
Short name T204
Test name
Test status
Simulation time 359004465 ps
CPU time 7.87 seconds
Started Jul 31 05:36:57 PM PDT 24
Finished Jul 31 05:37:05 PM PDT 24
Peak memory 209880 kb
Host smart-63964047-6a97-467a-b711-91c74bbc567f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926415214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2926415214
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1689233570
Short name T638
Test name
Test status
Simulation time 82769940 ps
CPU time 3.11 seconds
Started Jul 31 05:36:58 PM PDT 24
Finished Jul 31 05:37:01 PM PDT 24
Peak memory 207924 kb
Host smart-870bbd05-3c14-4d76-84f3-a21d96e8c6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689233570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1689233570
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3852036266
Short name T576
Test name
Test status
Simulation time 80345224 ps
CPU time 4.07 seconds
Started Jul 31 05:36:59 PM PDT 24
Finished Jul 31 05:37:03 PM PDT 24
Peak memory 209828 kb
Host smart-293dd64e-6693-4155-8acb-76c67190db14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852036266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3852036266
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2957405920
Short name T187
Test name
Test status
Simulation time 139622511 ps
CPU time 2.17 seconds
Started Jul 31 05:37:03 PM PDT 24
Finished Jul 31 05:37:05 PM PDT 24
Peak memory 209936 kb
Host smart-e38dbb0b-d201-482c-a6ba-16663971f512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957405920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2957405920
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1374525376
Short name T917
Test name
Test status
Simulation time 48906501 ps
CPU time 1.51 seconds
Started Jul 31 05:37:04 PM PDT 24
Finished Jul 31 05:37:06 PM PDT 24
Peak memory 214532 kb
Host smart-171891d1-bf81-4c5f-bfdf-ac60eeb8b64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374525376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1374525376
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3170207815
Short name T63
Test name
Test status
Simulation time 108496010 ps
CPU time 4.01 seconds
Started Jul 31 05:36:58 PM PDT 24
Finished Jul 31 05:37:02 PM PDT 24
Peak memory 218248 kb
Host smart-ca4efe73-cac0-4875-95ab-21c951c05aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170207815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3170207815
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2269876769
Short name T385
Test name
Test status
Simulation time 162867175 ps
CPU time 3.1 seconds
Started Jul 31 05:37:05 PM PDT 24
Finished Jul 31 05:37:08 PM PDT 24
Peak memory 209736 kb
Host smart-c9e92adb-32fd-4c36-8a5f-66cf0a89f5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269876769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2269876769
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2019272305
Short name T679
Test name
Test status
Simulation time 207305486 ps
CPU time 2.88 seconds
Started Jul 31 05:37:04 PM PDT 24
Finished Jul 31 05:37:07 PM PDT 24
Peak memory 208968 kb
Host smart-12c05e99-7fa2-4002-8ad3-7a1250e00396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019272305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2019272305
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.4172164955
Short name T673
Test name
Test status
Simulation time 1402994430 ps
CPU time 9.29 seconds
Started Jul 31 05:37:03 PM PDT 24
Finished Jul 31 05:37:12 PM PDT 24
Peak memory 214288 kb
Host smart-6272cf5f-843d-4ade-ae8c-f6ced6e52726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172164955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.4172164955
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1287777375
Short name T910
Test name
Test status
Simulation time 18574968 ps
CPU time 1.63 seconds
Started Jul 31 05:36:56 PM PDT 24
Finished Jul 31 05:36:58 PM PDT 24
Peak memory 206700 kb
Host smart-f3a147d9-27c4-458a-8832-dd03ac0f9940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287777375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1287777375
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3706225998
Short name T762
Test name
Test status
Simulation time 29268128 ps
CPU time 2.27 seconds
Started Jul 31 05:37:01 PM PDT 24
Finished Jul 31 05:37:03 PM PDT 24
Peak memory 206964 kb
Host smart-0c498f1e-6ca6-4dfa-9852-30806d9d0e3e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706225998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3706225998
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3367938444
Short name T912
Test name
Test status
Simulation time 60698578 ps
CPU time 3.03 seconds
Started Jul 31 05:37:04 PM PDT 24
Finished Jul 31 05:37:07 PM PDT 24
Peak memory 207000 kb
Host smart-f7f718de-4b41-42b9-9d20-43633fd7c7a2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367938444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3367938444
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3394689633
Short name T755
Test name
Test status
Simulation time 49352606 ps
CPU time 2.53 seconds
Started Jul 31 05:36:58 PM PDT 24
Finished Jul 31 05:37:01 PM PDT 24
Peak memory 206928 kb
Host smart-6ecda394-750d-40c4-805f-4106f41638a5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394689633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3394689633
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2078396796
Short name T666
Test name
Test status
Simulation time 337705880 ps
CPU time 2.4 seconds
Started Jul 31 05:37:04 PM PDT 24
Finished Jul 31 05:37:07 PM PDT 24
Peak memory 208272 kb
Host smart-8264b34c-9c3d-4523-b737-ab38ef00b474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078396796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2078396796
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2793776940
Short name T567
Test name
Test status
Simulation time 235559890 ps
CPU time 2.58 seconds
Started Jul 31 05:36:58 PM PDT 24
Finished Jul 31 05:37:01 PM PDT 24
Peak memory 206700 kb
Host smart-a95d80f2-4b4f-424d-a502-1956c8f919df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793776940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2793776940
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3751432357
Short name T564
Test name
Test status
Simulation time 357490459 ps
CPU time 15.92 seconds
Started Jul 31 05:37:02 PM PDT 24
Finished Jul 31 05:37:18 PM PDT 24
Peak memory 216588 kb
Host smart-ce1af82b-ca32-425c-973c-d438e7a3df99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751432357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3751432357
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.732660784
Short name T129
Test name
Test status
Simulation time 209944739 ps
CPU time 3.34 seconds
Started Jul 31 05:37:03 PM PDT 24
Finished Jul 31 05:37:06 PM PDT 24
Peak memory 214316 kb
Host smart-2191956c-1eb8-44bd-b4a4-bc64b232acd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732660784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.732660784
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.915438924
Short name T452
Test name
Test status
Simulation time 21508425 ps
CPU time 1.08 seconds
Started Jul 31 05:37:04 PM PDT 24
Finished Jul 31 05:37:06 PM PDT 24
Peak memory 206100 kb
Host smart-2cd69de4-ec33-4de3-b97e-afd190484bcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915438924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.915438924
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3987982907
Short name T365
Test name
Test status
Simulation time 109649205 ps
CPU time 3.89 seconds
Started Jul 31 05:37:02 PM PDT 24
Finished Jul 31 05:37:06 PM PDT 24
Peak memory 215328 kb
Host smart-7c59a9df-3395-4b28-809b-422b34acdc30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3987982907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3987982907
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3241926598
Short name T33
Test name
Test status
Simulation time 24606040 ps
CPU time 1.42 seconds
Started Jul 31 05:37:01 PM PDT 24
Finished Jul 31 05:37:02 PM PDT 24
Peak memory 214256 kb
Host smart-0ac10e76-6860-4029-9c0a-8283bb47ac7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241926598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3241926598
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1335698431
Short name T884
Test name
Test status
Simulation time 341921926 ps
CPU time 7.33 seconds
Started Jul 31 05:37:05 PM PDT 24
Finished Jul 31 05:37:12 PM PDT 24
Peak memory 207284 kb
Host smart-67a68de7-cc3e-47e8-a3f5-86b7dc7bb4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335698431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1335698431
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.174294336
Short name T245
Test name
Test status
Simulation time 216942192 ps
CPU time 3.04 seconds
Started Jul 31 05:37:04 PM PDT 24
Finished Jul 31 05:37:07 PM PDT 24
Peak memory 214316 kb
Host smart-e1d8ec6c-1cb4-47e5-ab11-cd8fdc73ef8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174294336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.174294336
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3406843502
Short name T90
Test name
Test status
Simulation time 41525865 ps
CPU time 2.2 seconds
Started Jul 31 05:37:03 PM PDT 24
Finished Jul 31 05:37:06 PM PDT 24
Peak memory 222180 kb
Host smart-72a81a98-4a9e-4e61-88b7-ac765a90682c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406843502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3406843502
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2635940104
Short name T222
Test name
Test status
Simulation time 175394751 ps
CPU time 3.1 seconds
Started Jul 31 05:37:04 PM PDT 24
Finished Jul 31 05:37:08 PM PDT 24
Peak memory 214328 kb
Host smart-b01e41eb-bc5e-49b7-9864-4c7ce0cc4c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635940104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2635940104
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.4129726655
Short name T286
Test name
Test status
Simulation time 2529613803 ps
CPU time 9.73 seconds
Started Jul 31 05:37:02 PM PDT 24
Finished Jul 31 05:37:11 PM PDT 24
Peak memory 207444 kb
Host smart-de3a6190-58c6-4f8e-ba9a-930906b90977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129726655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.4129726655
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3174331519
Short name T259
Test name
Test status
Simulation time 517096810 ps
CPU time 4.7 seconds
Started Jul 31 05:37:04 PM PDT 24
Finished Jul 31 05:37:09 PM PDT 24
Peak memory 208464 kb
Host smart-fbb9311f-db93-4f61-a1dc-ee5c5fc34b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174331519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3174331519
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1259536952
Short name T608
Test name
Test status
Simulation time 21743746 ps
CPU time 1.83 seconds
Started Jul 31 05:37:02 PM PDT 24
Finished Jul 31 05:37:04 PM PDT 24
Peak memory 206932 kb
Host smart-516cc194-4c56-4b68-8b85-b4c4240be2cf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259536952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1259536952
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.245953924
Short name T677
Test name
Test status
Simulation time 21678577 ps
CPU time 1.86 seconds
Started Jul 31 05:37:03 PM PDT 24
Finished Jul 31 05:37:05 PM PDT 24
Peak memory 207004 kb
Host smart-6ea97178-86b4-4c87-b014-5ddc8d252932
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245953924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.245953924
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.444007519
Short name T470
Test name
Test status
Simulation time 463508402 ps
CPU time 5.53 seconds
Started Jul 31 05:37:06 PM PDT 24
Finished Jul 31 05:37:11 PM PDT 24
Peak memory 208176 kb
Host smart-d80060d4-f7da-41b4-967b-df7f2ea613de
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444007519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.444007519
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2658525705
Short name T538
Test name
Test status
Simulation time 227508911 ps
CPU time 3.08 seconds
Started Jul 31 05:37:03 PM PDT 24
Finished Jul 31 05:37:06 PM PDT 24
Peak memory 209540 kb
Host smart-826ced52-9620-46ab-8a4c-7247ac885d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658525705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2658525705
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1884584326
Short name T448
Test name
Test status
Simulation time 35760416 ps
CPU time 1.69 seconds
Started Jul 31 05:37:02 PM PDT 24
Finished Jul 31 05:37:03 PM PDT 24
Peak memory 207152 kb
Host smart-e1f33df7-7fc2-4299-8299-34cd4ed1dddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884584326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1884584326
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.3289124627
Short name T866
Test name
Test status
Simulation time 823590833 ps
CPU time 5.38 seconds
Started Jul 31 05:37:02 PM PDT 24
Finished Jul 31 05:37:08 PM PDT 24
Peak memory 208456 kb
Host smart-13bda024-657c-4ae6-a42b-0f389d86835f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289124627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3289124627
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.588429204
Short name T593
Test name
Test status
Simulation time 174695067 ps
CPU time 5.81 seconds
Started Jul 31 05:37:02 PM PDT 24
Finished Jul 31 05:37:08 PM PDT 24
Peak memory 207980 kb
Host smart-7643c55e-dcc3-4a9e-9ca2-368ced326d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588429204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.588429204
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3444426964
Short name T476
Test name
Test status
Simulation time 30802230 ps
CPU time 1.66 seconds
Started Jul 31 05:37:03 PM PDT 24
Finished Jul 31 05:37:05 PM PDT 24
Peak memory 210028 kb
Host smart-1e6d6907-13df-4b78-afa9-4495b26df7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444426964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3444426964
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3987210955
Short name T675
Test name
Test status
Simulation time 62915802 ps
CPU time 0.73 seconds
Started Jul 31 05:37:07 PM PDT 24
Finished Jul 31 05:37:08 PM PDT 24
Peak memory 205952 kb
Host smart-9f131164-1629-43c1-893a-57a741e9786c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987210955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3987210955
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.758548311
Short name T138
Test name
Test status
Simulation time 378542764 ps
CPU time 5.89 seconds
Started Jul 31 05:37:11 PM PDT 24
Finished Jul 31 05:37:17 PM PDT 24
Peak memory 214644 kb
Host smart-0af4894d-44bd-47bb-9ee6-94bcad164602
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=758548311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.758548311
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2489908326
Short name T817
Test name
Test status
Simulation time 861831742 ps
CPU time 2.61 seconds
Started Jul 31 05:37:11 PM PDT 24
Finished Jul 31 05:37:13 PM PDT 24
Peak memory 216672 kb
Host smart-de27b17f-c322-41f6-a5a3-76507cab4fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489908326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2489908326
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2173782163
Short name T441
Test name
Test status
Simulation time 2097370437 ps
CPU time 10.56 seconds
Started Jul 31 05:37:10 PM PDT 24
Finished Jul 31 05:37:21 PM PDT 24
Peak memory 208600 kb
Host smart-5c7445d4-ef52-4d6d-95cc-eef518dec592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173782163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2173782163
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2699738523
Short name T24
Test name
Test status
Simulation time 3148598861 ps
CPU time 34.71 seconds
Started Jul 31 05:37:07 PM PDT 24
Finished Jul 31 05:37:42 PM PDT 24
Peak memory 214312 kb
Host smart-d46ffd31-a7d9-4865-829f-5bb4690d0cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699738523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2699738523
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3341760105
Short name T251
Test name
Test status
Simulation time 75787849 ps
CPU time 3.51 seconds
Started Jul 31 05:37:09 PM PDT 24
Finished Jul 31 05:37:13 PM PDT 24
Peak memory 219728 kb
Host smart-fa16d295-8c40-4420-96b0-637edcecb828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341760105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3341760105
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3294914029
Short name T744
Test name
Test status
Simulation time 124524604 ps
CPU time 5.1 seconds
Started Jul 31 05:37:09 PM PDT 24
Finished Jul 31 05:37:14 PM PDT 24
Peak memory 214320 kb
Host smart-debcb259-8ea5-486c-858a-0bdd385a82bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294914029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3294914029
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2425543556
Short name T463
Test name
Test status
Simulation time 123749366 ps
CPU time 2.44 seconds
Started Jul 31 05:37:06 PM PDT 24
Finished Jul 31 05:37:08 PM PDT 24
Peak memory 207384 kb
Host smart-612470b3-50bf-4aaa-848f-2e6f5d09c799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425543556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2425543556
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2096778329
Short name T505
Test name
Test status
Simulation time 5234901799 ps
CPU time 46.39 seconds
Started Jul 31 05:37:03 PM PDT 24
Finished Jul 31 05:37:49 PM PDT 24
Peak memory 208456 kb
Host smart-253897b3-81ec-4c50-9887-8d77db230eee
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096778329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2096778329
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.258856784
Short name T440
Test name
Test status
Simulation time 488044811 ps
CPU time 4.4 seconds
Started Jul 31 05:37:04 PM PDT 24
Finished Jul 31 05:37:09 PM PDT 24
Peak memory 206980 kb
Host smart-45fccdd8-2fcf-45f8-a2af-0ca64a1c555a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258856784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.258856784
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.4170087485
Short name T644
Test name
Test status
Simulation time 238051897 ps
CPU time 3.26 seconds
Started Jul 31 05:37:02 PM PDT 24
Finished Jul 31 05:37:05 PM PDT 24
Peak memory 206956 kb
Host smart-fceb426f-bb51-4e0b-82c4-ce1cdc4a8e53
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170087485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.4170087485
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3580173525
Short name T362
Test name
Test status
Simulation time 166864844 ps
CPU time 1.76 seconds
Started Jul 31 05:37:08 PM PDT 24
Finished Jul 31 05:37:10 PM PDT 24
Peak memory 209908 kb
Host smart-a9a07903-6eba-4cc3-9751-56c526f3cc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580173525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3580173525
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2673817285
Short name T599
Test name
Test status
Simulation time 20949113 ps
CPU time 1.72 seconds
Started Jul 31 05:37:04 PM PDT 24
Finished Jul 31 05:37:06 PM PDT 24
Peak memory 206120 kb
Host smart-a73aa183-823b-4201-9ffe-8f58c9a72173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673817285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2673817285
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.2125120294
Short name T839
Test name
Test status
Simulation time 996436711 ps
CPU time 12.56 seconds
Started Jul 31 05:37:08 PM PDT 24
Finished Jul 31 05:37:21 PM PDT 24
Peak memory 222508 kb
Host smart-1712ed62-53ef-414c-9536-c30801e2ead2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125120294 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.2125120294
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1235982040
Short name T709
Test name
Test status
Simulation time 63379577 ps
CPU time 2.58 seconds
Started Jul 31 05:37:12 PM PDT 24
Finished Jul 31 05:37:15 PM PDT 24
Peak memory 207924 kb
Host smart-7d505045-5637-463f-8427-3384b234c5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235982040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1235982040
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1831427156
Short name T786
Test name
Test status
Simulation time 31541111 ps
CPU time 1.48 seconds
Started Jul 31 05:37:08 PM PDT 24
Finished Jul 31 05:37:10 PM PDT 24
Peak memory 209892 kb
Host smart-4bfd473a-f0c5-474e-bc21-dd3a37003a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831427156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1831427156
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3261981963
Short name T778
Test name
Test status
Simulation time 24011219 ps
CPU time 1 seconds
Started Jul 31 05:37:14 PM PDT 24
Finished Jul 31 05:37:15 PM PDT 24
Peak memory 206196 kb
Host smart-49f7f1b9-bd12-4f03-8c42-ceb8f9212cc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261981963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3261981963
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.2840285741
Short name T20
Test name
Test status
Simulation time 51421911 ps
CPU time 2.21 seconds
Started Jul 31 05:37:14 PM PDT 24
Finished Jul 31 05:37:17 PM PDT 24
Peak memory 221132 kb
Host smart-f9355953-b994-484a-ac04-a16ed7fe7055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840285741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.2840285741
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2081590340
Short name T336
Test name
Test status
Simulation time 100199999 ps
CPU time 1.94 seconds
Started Jul 31 05:37:09 PM PDT 24
Finished Jul 31 05:37:11 PM PDT 24
Peak memory 218228 kb
Host smart-422bd953-a218-46a1-bff2-eaf4cb333c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081590340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2081590340
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3498802079
Short name T823
Test name
Test status
Simulation time 15003839111 ps
CPU time 49.33 seconds
Started Jul 31 05:37:20 PM PDT 24
Finished Jul 31 05:38:09 PM PDT 24
Peak memory 214352 kb
Host smart-ae548ded-8c38-4572-98af-0d0253ab81ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498802079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3498802079
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3719696786
Short name T722
Test name
Test status
Simulation time 318596345 ps
CPU time 4.43 seconds
Started Jul 31 05:37:16 PM PDT 24
Finished Jul 31 05:37:21 PM PDT 24
Peak memory 221676 kb
Host smart-6c046114-894d-4142-a389-1ead7cff58b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719696786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3719696786
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.354301460
Short name T6
Test name
Test status
Simulation time 117914728 ps
CPU time 3.17 seconds
Started Jul 31 05:37:15 PM PDT 24
Finished Jul 31 05:37:18 PM PDT 24
Peak memory 214656 kb
Host smart-25fd45b1-602f-4725-b15f-c59dfe0fc4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354301460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.354301460
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3297299461
Short name T696
Test name
Test status
Simulation time 994282705 ps
CPU time 7.46 seconds
Started Jul 31 05:37:10 PM PDT 24
Finished Jul 31 05:37:17 PM PDT 24
Peak memory 215396 kb
Host smart-e81a2914-8b84-4a5d-a2ff-828187c30298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297299461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3297299461
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1269395875
Short name T757
Test name
Test status
Simulation time 106320820 ps
CPU time 2.34 seconds
Started Jul 31 05:37:09 PM PDT 24
Finished Jul 31 05:37:11 PM PDT 24
Peak memory 206900 kb
Host smart-7d489d01-19eb-48e2-97ce-ed0d08d5c0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269395875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1269395875
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3036067741
Short name T645
Test name
Test status
Simulation time 1605817700 ps
CPU time 54.73 seconds
Started Jul 31 05:37:07 PM PDT 24
Finished Jul 31 05:38:02 PM PDT 24
Peak memory 208348 kb
Host smart-8d3ae16f-2bd9-4722-a671-6c234337f63b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036067741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3036067741
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.4157687562
Short name T740
Test name
Test status
Simulation time 2326329997 ps
CPU time 6.53 seconds
Started Jul 31 05:37:08 PM PDT 24
Finished Jul 31 05:37:14 PM PDT 24
Peak memory 208080 kb
Host smart-b4d71587-e589-40aa-98a2-1a9bb15848db
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157687562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.4157687562
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1413312562
Short name T549
Test name
Test status
Simulation time 222906000 ps
CPU time 3.48 seconds
Started Jul 31 05:37:08 PM PDT 24
Finished Jul 31 05:37:12 PM PDT 24
Peak memory 208552 kb
Host smart-9b0515df-fec5-4ec7-bb0b-0bcb8944b366
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413312562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1413312562
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3691412956
Short name T697
Test name
Test status
Simulation time 38428543 ps
CPU time 2.18 seconds
Started Jul 31 05:37:11 PM PDT 24
Finished Jul 31 05:37:13 PM PDT 24
Peak memory 207356 kb
Host smart-27de007e-2ec3-46b4-bed6-406adceba9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691412956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3691412956
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.1723316822
Short name T530
Test name
Test status
Simulation time 1235516544 ps
CPU time 16.4 seconds
Started Jul 31 05:37:16 PM PDT 24
Finished Jul 31 05:37:32 PM PDT 24
Peak memory 219548 kb
Host smart-248d9de4-14db-4802-85aa-27162a0b432a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723316822 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.1723316822
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2743261772
Short name T363
Test name
Test status
Simulation time 562087460 ps
CPU time 6.32 seconds
Started Jul 31 05:37:17 PM PDT 24
Finished Jul 31 05:37:23 PM PDT 24
Peak memory 214280 kb
Host smart-5e22c118-e066-4be3-b9cf-9989be667c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743261772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2743261772
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3805863861
Short name T62
Test name
Test status
Simulation time 1586197349 ps
CPU time 9.23 seconds
Started Jul 31 05:37:17 PM PDT 24
Finished Jul 31 05:37:26 PM PDT 24
Peak memory 210836 kb
Host smart-d1356527-e253-41d3-a605-328df7c217ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805863861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3805863861
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1825076951
Short name T435
Test name
Test status
Simulation time 15913688 ps
CPU time 0.81 seconds
Started Jul 31 05:37:16 PM PDT 24
Finished Jul 31 05:37:17 PM PDT 24
Peak memory 205968 kb
Host smart-0b5ae998-dc3e-49f0-9214-3a371da5caa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825076951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1825076951
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1021890109
Short name T73
Test name
Test status
Simulation time 30515002 ps
CPU time 1.57 seconds
Started Jul 31 05:37:17 PM PDT 24
Finished Jul 31 05:37:19 PM PDT 24
Peak memory 207136 kb
Host smart-f162490e-7752-4744-ac1d-d2c26873a13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021890109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1021890109
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1680920820
Short name T381
Test name
Test status
Simulation time 82369253 ps
CPU time 2.34 seconds
Started Jul 31 05:37:20 PM PDT 24
Finished Jul 31 05:37:22 PM PDT 24
Peak memory 214328 kb
Host smart-19e8b567-77af-45fd-ad54-e978715ed84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680920820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1680920820
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.304847102
Short name T302
Test name
Test status
Simulation time 1131305123 ps
CPU time 4.9 seconds
Started Jul 31 05:37:15 PM PDT 24
Finished Jul 31 05:37:20 PM PDT 24
Peak memory 222420 kb
Host smart-e930468f-4f68-4b15-8285-c2724a3518fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304847102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.304847102
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.731994273
Short name T768
Test name
Test status
Simulation time 176365327 ps
CPU time 2.72 seconds
Started Jul 31 05:37:19 PM PDT 24
Finished Jul 31 05:37:22 PM PDT 24
Peak memory 209604 kb
Host smart-2a46f6da-f70f-44b5-b099-cb4d011e1182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731994273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.731994273
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3041357950
Short name T647
Test name
Test status
Simulation time 377282628 ps
CPU time 4.25 seconds
Started Jul 31 05:37:16 PM PDT 24
Finished Jul 31 05:37:21 PM PDT 24
Peak memory 214320 kb
Host smart-98bb3099-665d-4593-a487-b0c43d3afe57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041357950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3041357950
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.5274992
Short name T481
Test name
Test status
Simulation time 174521346 ps
CPU time 2.75 seconds
Started Jul 31 05:37:13 PM PDT 24
Finished Jul 31 05:37:16 PM PDT 24
Peak memory 207252 kb
Host smart-2e1376c1-13aa-4779-8e7a-e5d7138ca603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5274992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.5274992
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3836873723
Short name T442
Test name
Test status
Simulation time 397767069 ps
CPU time 3.2 seconds
Started Jul 31 05:37:14 PM PDT 24
Finished Jul 31 05:37:17 PM PDT 24
Peak memory 206816 kb
Host smart-d78de0ea-460d-46d3-aa7f-d0ccfd448981
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836873723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3836873723
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1471763200
Short name T899
Test name
Test status
Simulation time 275849539 ps
CPU time 2.67 seconds
Started Jul 31 05:37:16 PM PDT 24
Finished Jul 31 05:37:19 PM PDT 24
Peak memory 206948 kb
Host smart-2c66c39f-e434-4097-a710-7267fb35dd46
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471763200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1471763200
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2748177653
Short name T668
Test name
Test status
Simulation time 320412392 ps
CPU time 2.77 seconds
Started Jul 31 05:37:13 PM PDT 24
Finished Jul 31 05:37:16 PM PDT 24
Peak memory 206804 kb
Host smart-c5bffa7d-62f1-46e6-9ca8-bf48e6377c17
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748177653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2748177653
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3355587289
Short name T309
Test name
Test status
Simulation time 54788755 ps
CPU time 2.68 seconds
Started Jul 31 05:37:16 PM PDT 24
Finished Jul 31 05:37:19 PM PDT 24
Peak memory 220284 kb
Host smart-3028e6c0-a4cc-4e79-8dd7-a8b0bdd29a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355587289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3355587289
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1701345450
Short name T855
Test name
Test status
Simulation time 499480240 ps
CPU time 4.93 seconds
Started Jul 31 05:37:15 PM PDT 24
Finished Jul 31 05:37:20 PM PDT 24
Peak memory 206800 kb
Host smart-1254ffdd-9474-492a-9a95-7688bb5ed8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701345450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1701345450
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1387363853
Short name T228
Test name
Test status
Simulation time 4824869185 ps
CPU time 28.28 seconds
Started Jul 31 05:37:15 PM PDT 24
Finished Jul 31 05:37:43 PM PDT 24
Peak memory 217008 kb
Host smart-4e7accb0-3ba9-49b1-a245-6c1cee6c9d7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387363853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1387363853
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.2544077908
Short name T758
Test name
Test status
Simulation time 666237452 ps
CPU time 10.47 seconds
Started Jul 31 05:37:15 PM PDT 24
Finished Jul 31 05:37:25 PM PDT 24
Peak memory 222476 kb
Host smart-9da7e126-e0d3-4dfa-bc80-471370b88a17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544077908 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.2544077908
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2454402024
Short name T294
Test name
Test status
Simulation time 213600377 ps
CPU time 4.39 seconds
Started Jul 31 05:37:16 PM PDT 24
Finished Jul 31 05:37:20 PM PDT 24
Peak memory 214272 kb
Host smart-4ab035dc-799d-4fe3-9dab-9f53201215cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454402024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2454402024
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.924057589
Short name T570
Test name
Test status
Simulation time 346372275 ps
CPU time 3.37 seconds
Started Jul 31 05:37:17 PM PDT 24
Finished Jul 31 05:37:20 PM PDT 24
Peak memory 210500 kb
Host smart-609eb326-4697-4e4c-b887-58865f7a8cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924057589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.924057589
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1178901262
Short name T499
Test name
Test status
Simulation time 33368591 ps
CPU time 0.71 seconds
Started Jul 31 05:37:26 PM PDT 24
Finished Jul 31 05:37:27 PM PDT 24
Peak memory 205956 kb
Host smart-d112debe-e592-45c3-af8d-a6c17c0279fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178901262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1178901262
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1800030573
Short name T479
Test name
Test status
Simulation time 79442347 ps
CPU time 1.99 seconds
Started Jul 31 05:37:20 PM PDT 24
Finished Jul 31 05:37:22 PM PDT 24
Peak memory 216220 kb
Host smart-d06103c6-d96b-4808-b978-879d5e80dc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800030573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1800030573
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2765860593
Short name T783
Test name
Test status
Simulation time 197140501 ps
CPU time 2.53 seconds
Started Jul 31 05:37:21 PM PDT 24
Finished Jul 31 05:37:23 PM PDT 24
Peak memory 207236 kb
Host smart-21198dd0-4610-490b-9dc2-26e683d42358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765860593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2765860593
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.590193942
Short name T706
Test name
Test status
Simulation time 278807834 ps
CPU time 3.77 seconds
Started Jul 31 05:37:20 PM PDT 24
Finished Jul 31 05:37:24 PM PDT 24
Peak memory 214344 kb
Host smart-3f846a88-72f8-4455-ade5-efd987cf0638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590193942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.590193942
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.423046307
Short name T67
Test name
Test status
Simulation time 31698904 ps
CPU time 2.63 seconds
Started Jul 31 05:37:20 PM PDT 24
Finished Jul 31 05:37:23 PM PDT 24
Peak memory 220488 kb
Host smart-b89d7b48-7e87-46da-bc75-1662835cde24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423046307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.423046307
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3477971605
Short name T344
Test name
Test status
Simulation time 357490789 ps
CPU time 7.92 seconds
Started Jul 31 05:37:22 PM PDT 24
Finished Jul 31 05:37:30 PM PDT 24
Peak memory 207004 kb
Host smart-bbb240ac-9c8e-426d-ab58-cdb2062c3ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477971605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3477971605
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2034326213
Short name T458
Test name
Test status
Simulation time 525279009 ps
CPU time 14.84 seconds
Started Jul 31 05:37:20 PM PDT 24
Finished Jul 31 05:37:35 PM PDT 24
Peak memory 208292 kb
Host smart-66d52cdc-1f1b-442a-99e9-2e518fefb47f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034326213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2034326213
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3518369378
Short name T661
Test name
Test status
Simulation time 228052735 ps
CPU time 6.16 seconds
Started Jul 31 05:37:20 PM PDT 24
Finished Jul 31 05:37:26 PM PDT 24
Peak memory 208016 kb
Host smart-a3f250d9-aa3f-46b1-9ba6-f349145a7e3b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518369378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3518369378
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1562489348
Short name T850
Test name
Test status
Simulation time 451210864 ps
CPU time 6.6 seconds
Started Jul 31 05:37:22 PM PDT 24
Finished Jul 31 05:37:29 PM PDT 24
Peak memory 207976 kb
Host smart-ef587159-86e1-49d8-ad01-2d528435a6f4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562489348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1562489348
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3920346263
Short name T407
Test name
Test status
Simulation time 179052586 ps
CPU time 2.52 seconds
Started Jul 31 05:37:20 PM PDT 24
Finished Jul 31 05:37:23 PM PDT 24
Peak memory 208104 kb
Host smart-9e0fdf9e-2a8a-4f85-a501-23551bfc9b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920346263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3920346263
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.48771793
Short name T770
Test name
Test status
Simulation time 40461867 ps
CPU time 1.68 seconds
Started Jul 31 05:37:21 PM PDT 24
Finished Jul 31 05:37:23 PM PDT 24
Peak memory 206852 kb
Host smart-9c1a1643-7313-4d59-b602-cb22d5def17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48771793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.48771793
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2249749925
Short name T905
Test name
Test status
Simulation time 73236217 ps
CPU time 4.12 seconds
Started Jul 31 05:37:26 PM PDT 24
Finished Jul 31 05:37:30 PM PDT 24
Peak memory 222104 kb
Host smart-79dd42c1-440c-4680-977d-b5682ca95ef3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249749925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2249749925
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.3363624941
Short name T180
Test name
Test status
Simulation time 974960128 ps
CPU time 18.7 seconds
Started Jul 31 05:37:26 PM PDT 24
Finished Jul 31 05:37:45 PM PDT 24
Peak memory 221224 kb
Host smart-51d7cb86-1d38-49f7-b331-78e34dc74a30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363624941 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.3363624941
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1834824477
Short name T298
Test name
Test status
Simulation time 368641527 ps
CPU time 7.49 seconds
Started Jul 31 05:37:19 PM PDT 24
Finished Jul 31 05:37:27 PM PDT 24
Peak memory 219716 kb
Host smart-a7877b39-59fa-4536-bc16-cad95966e78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834824477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1834824477
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.32033574
Short name T918
Test name
Test status
Simulation time 161515122 ps
CPU time 1.94 seconds
Started Jul 31 05:37:20 PM PDT 24
Finished Jul 31 05:37:22 PM PDT 24
Peak memory 210008 kb
Host smart-7fa48966-f571-4072-9202-53a01b51fea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32033574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.32033574
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2333570019
Short name T832
Test name
Test status
Simulation time 12461728 ps
CPU time 0.88 seconds
Started Jul 31 05:37:26 PM PDT 24
Finished Jul 31 05:37:27 PM PDT 24
Peak memory 205944 kb
Host smart-5d8d15a4-28ed-443c-8147-9eebdb6c8a65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333570019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2333570019
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3503673690
Short name T908
Test name
Test status
Simulation time 134772616 ps
CPU time 7.15 seconds
Started Jul 31 05:37:24 PM PDT 24
Finished Jul 31 05:37:32 PM PDT 24
Peak memory 214840 kb
Host smart-c2783d72-078d-487f-b6ec-ed23e9d509ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3503673690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3503673690
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3211364244
Short name T521
Test name
Test status
Simulation time 142653076 ps
CPU time 3.3 seconds
Started Jul 31 05:37:24 PM PDT 24
Finished Jul 31 05:37:28 PM PDT 24
Peak memory 210184 kb
Host smart-9092f56a-f076-4f91-b3da-1a7d5f11435c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211364244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3211364244
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2921390166
Short name T292
Test name
Test status
Simulation time 115782093 ps
CPU time 2.67 seconds
Started Jul 31 05:37:26 PM PDT 24
Finished Jul 31 05:37:28 PM PDT 24
Peak memory 209944 kb
Host smart-86d6a343-b690-4241-bfb1-baa4ea0f02e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921390166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2921390166
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3678472461
Short name T94
Test name
Test status
Simulation time 575406253 ps
CPU time 15.43 seconds
Started Jul 31 05:37:25 PM PDT 24
Finished Jul 31 05:37:41 PM PDT 24
Peak memory 218488 kb
Host smart-f5418095-f823-46f6-bdda-251acb64af49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678472461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3678472461
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.667831535
Short name T356
Test name
Test status
Simulation time 210646420 ps
CPU time 5.14 seconds
Started Jul 31 05:37:24 PM PDT 24
Finished Jul 31 05:37:29 PM PDT 24
Peak memory 222428 kb
Host smart-dd99c396-8da8-4590-a283-f6673594065d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667831535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.667831535
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.3722178890
Short name T799
Test name
Test status
Simulation time 456366303 ps
CPU time 4.55 seconds
Started Jul 31 05:37:24 PM PDT 24
Finished Jul 31 05:37:28 PM PDT 24
Peak memory 214356 kb
Host smart-5e36cb7b-cd53-4ad3-917c-bebedce5ddaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722178890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3722178890
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2325245301
Short name T725
Test name
Test status
Simulation time 107100323 ps
CPU time 2.48 seconds
Started Jul 31 05:37:26 PM PDT 24
Finished Jul 31 05:37:28 PM PDT 24
Peak memory 209692 kb
Host smart-7aa3634e-22e5-4ec3-9e36-86b13a4a098f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325245301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2325245301
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3514959656
Short name T317
Test name
Test status
Simulation time 211483353 ps
CPU time 3.71 seconds
Started Jul 31 05:37:26 PM PDT 24
Finished Jul 31 05:37:30 PM PDT 24
Peak memory 208676 kb
Host smart-ddf6873b-16e1-4c4f-be60-8d89f32697d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514959656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3514959656
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.584721353
Short name T676
Test name
Test status
Simulation time 446011723 ps
CPU time 4.45 seconds
Started Jul 31 05:37:26 PM PDT 24
Finished Jul 31 05:37:31 PM PDT 24
Peak memory 208888 kb
Host smart-bb1716a1-cbd0-49d8-be71-881ae8659f9c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584721353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.584721353
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3431964639
Short name T415
Test name
Test status
Simulation time 5439035289 ps
CPU time 22.43 seconds
Started Jul 31 05:37:24 PM PDT 24
Finished Jul 31 05:37:47 PM PDT 24
Peak memory 208804 kb
Host smart-71701b55-8daa-4b4d-b93b-1c4d6cf6bebe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431964639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3431964639
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2939189827
Short name T756
Test name
Test status
Simulation time 45227056 ps
CPU time 1.94 seconds
Started Jul 31 05:37:27 PM PDT 24
Finished Jul 31 05:37:29 PM PDT 24
Peak memory 206852 kb
Host smart-a38a93fe-cfbd-42d1-9e31-afbcbe26b89d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939189827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2939189827
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.214034364
Short name T902
Test name
Test status
Simulation time 1043899006 ps
CPU time 18.77 seconds
Started Jul 31 05:37:25 PM PDT 24
Finished Jul 31 05:37:44 PM PDT 24
Peak memory 214352 kb
Host smart-fa4cdb71-7b58-4667-bf6c-04a5903d3528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214034364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.214034364
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.560218723
Short name T196
Test name
Test status
Simulation time 22635250 ps
CPU time 1.83 seconds
Started Jul 31 05:37:24 PM PDT 24
Finished Jul 31 05:37:26 PM PDT 24
Peak memory 206964 kb
Host smart-ae0c94de-f5e7-43e9-9e1a-2bb45e530f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560218723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.560218723
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3598201964
Short name T694
Test name
Test status
Simulation time 190339921 ps
CPU time 6.94 seconds
Started Jul 31 05:37:26 PM PDT 24
Finished Jul 31 05:37:33 PM PDT 24
Peak memory 221008 kb
Host smart-f5bf1bc7-392d-4410-a1d5-1293afdf1670
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598201964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3598201964
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3818819565
Short name T554
Test name
Test status
Simulation time 436724002 ps
CPU time 4.89 seconds
Started Jul 31 05:37:27 PM PDT 24
Finished Jul 31 05:37:32 PM PDT 24
Peak memory 208912 kb
Host smart-a1bf4308-a83f-487a-b210-040133747489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818819565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3818819565
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.606849538
Short name T681
Test name
Test status
Simulation time 105492611 ps
CPU time 3.3 seconds
Started Jul 31 05:37:25 PM PDT 24
Finished Jul 31 05:37:29 PM PDT 24
Peak memory 209844 kb
Host smart-97bfc366-b12e-40d1-a038-b06dcbc814b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606849538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.606849538
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.4198169928
Short name T501
Test name
Test status
Simulation time 15521314 ps
CPU time 0.93 seconds
Started Jul 31 05:36:15 PM PDT 24
Finished Jul 31 05:36:16 PM PDT 24
Peak memory 206128 kb
Host smart-cb5b49d7-8de4-452f-8cb3-73a24339f75f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198169928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.4198169928
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.14059671
Short name T223
Test name
Test status
Simulation time 4609810431 ps
CPU time 12.37 seconds
Started Jul 31 05:36:16 PM PDT 24
Finished Jul 31 05:36:29 PM PDT 24
Peak memory 209564 kb
Host smart-2915d514-9b28-41c8-8044-f1ce867a6fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14059671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.14059671
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2295947037
Short name T230
Test name
Test status
Simulation time 103171407 ps
CPU time 2.73 seconds
Started Jul 31 05:36:16 PM PDT 24
Finished Jul 31 05:36:19 PM PDT 24
Peak memory 218572 kb
Host smart-047aaccc-7baa-4311-8dc0-f1a688031b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295947037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2295947037
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.385833611
Short name T578
Test name
Test status
Simulation time 509000794 ps
CPU time 8.93 seconds
Started Jul 31 05:36:16 PM PDT 24
Finished Jul 31 05:36:25 PM PDT 24
Peak memory 222472 kb
Host smart-b163c0da-da83-42af-8b8e-8923cf9999ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385833611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.385833611
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.587189946
Short name T911
Test name
Test status
Simulation time 245830947 ps
CPU time 4.05 seconds
Started Jul 31 05:36:15 PM PDT 24
Finished Jul 31 05:36:19 PM PDT 24
Peak memory 208564 kb
Host smart-7ef5dcd7-d40d-4bab-9f5a-ed1d57fce4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587189946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.587189946
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1868910988
Short name T857
Test name
Test status
Simulation time 341249499 ps
CPU time 3.33 seconds
Started Jul 31 05:36:14 PM PDT 24
Finished Jul 31 05:36:17 PM PDT 24
Peak memory 208940 kb
Host smart-68c36ba4-e920-451d-9809-ff680852ef8b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868910988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1868910988
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1054148839
Short name T275
Test name
Test status
Simulation time 37355363 ps
CPU time 2.35 seconds
Started Jul 31 05:36:14 PM PDT 24
Finished Jul 31 05:36:17 PM PDT 24
Peak memory 208340 kb
Host smart-70b5ca5c-e79e-4800-9e12-f1c4abb029b7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054148839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1054148839
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3849668417
Short name T510
Test name
Test status
Simulation time 389964432 ps
CPU time 6.01 seconds
Started Jul 31 05:36:14 PM PDT 24
Finished Jul 31 05:36:20 PM PDT 24
Peak memory 207900 kb
Host smart-92cf090b-dad3-4346-b93e-f5b0f2d87114
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849668417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3849668417
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3874147650
Short name T335
Test name
Test status
Simulation time 116259622 ps
CPU time 2.35 seconds
Started Jul 31 05:36:15 PM PDT 24
Finished Jul 31 05:36:18 PM PDT 24
Peak memory 214332 kb
Host smart-447bce7b-724b-4d5b-8302-c7b709e84cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874147650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3874147650
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.235507271
Short name T735
Test name
Test status
Simulation time 754363636 ps
CPU time 12.06 seconds
Started Jul 31 05:36:15 PM PDT 24
Finished Jul 31 05:36:27 PM PDT 24
Peak memory 207908 kb
Host smart-a0e09e4c-c95c-43cc-acd3-6daa0275f9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235507271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.235507271
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1765942285
Short name T903
Test name
Test status
Simulation time 98310956 ps
CPU time 4.58 seconds
Started Jul 31 05:36:14 PM PDT 24
Finished Jul 31 05:36:19 PM PDT 24
Peak memory 214308 kb
Host smart-aa7c2d5e-b3c3-4755-a545-880115d1bb51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765942285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1765942285
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2416438356
Short name T322
Test name
Test status
Simulation time 63789738 ps
CPU time 3.29 seconds
Started Jul 31 05:36:15 PM PDT 24
Finished Jul 31 05:36:18 PM PDT 24
Peak memory 207452 kb
Host smart-6b251505-ba56-4fb7-b773-5cc070a5bc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416438356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2416438356
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.943718966
Short name T399
Test name
Test status
Simulation time 405000342 ps
CPU time 2.31 seconds
Started Jul 31 05:36:14 PM PDT 24
Finished Jul 31 05:36:16 PM PDT 24
Peak memory 210316 kb
Host smart-d632e07a-3857-48a9-aec2-7c8d8d11bba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943718966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.943718966
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3578324360
Short name T822
Test name
Test status
Simulation time 31553600 ps
CPU time 0.72 seconds
Started Jul 31 05:37:31 PM PDT 24
Finished Jul 31 05:37:32 PM PDT 24
Peak memory 205892 kb
Host smart-3a07ef92-e00e-4312-b1b4-474328f90cd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578324360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3578324360
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2612343498
Short name T522
Test name
Test status
Simulation time 142372371 ps
CPU time 3.28 seconds
Started Jul 31 05:37:30 PM PDT 24
Finished Jul 31 05:37:33 PM PDT 24
Peak memory 214404 kb
Host smart-f09c1d2e-f5a7-41ef-bd13-6b812957448f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2612343498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2612343498
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3817394995
Short name T29
Test name
Test status
Simulation time 670154592 ps
CPU time 3.3 seconds
Started Jul 31 05:37:31 PM PDT 24
Finished Jul 31 05:37:35 PM PDT 24
Peak memory 222672 kb
Host smart-d04f4004-8b65-4bad-9af9-b29db10e6571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817394995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3817394995
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2889839025
Short name T66
Test name
Test status
Simulation time 289134915 ps
CPU time 3.32 seconds
Started Jul 31 05:37:36 PM PDT 24
Finished Jul 31 05:37:39 PM PDT 24
Peak memory 210064 kb
Host smart-7ea005dc-d228-4bfd-a23c-250a6e2fcc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889839025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2889839025
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3959685362
Short name T779
Test name
Test status
Simulation time 294759909 ps
CPU time 3.71 seconds
Started Jul 31 05:37:29 PM PDT 24
Finished Jul 31 05:37:32 PM PDT 24
Peak memory 222432 kb
Host smart-99d22139-d8b5-4e20-baea-4e89ba317f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959685362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3959685362
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.140427789
Short name T887
Test name
Test status
Simulation time 694875158 ps
CPU time 4.93 seconds
Started Jul 31 05:37:32 PM PDT 24
Finished Jul 31 05:37:37 PM PDT 24
Peak memory 218340 kb
Host smart-36abc7ad-b75e-4af1-8e17-2f55a217478a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140427789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.140427789
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2421399692
Short name T473
Test name
Test status
Simulation time 220928538 ps
CPU time 5.68 seconds
Started Jul 31 05:37:27 PM PDT 24
Finished Jul 31 05:37:33 PM PDT 24
Peak memory 208304 kb
Host smart-60d69f31-c7c4-4856-9a49-fd198cd82bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421399692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2421399692
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3337630853
Short name T736
Test name
Test status
Simulation time 433134819 ps
CPU time 5.47 seconds
Started Jul 31 05:37:33 PM PDT 24
Finished Jul 31 05:37:38 PM PDT 24
Peak memory 207104 kb
Host smart-b8d07c00-b8de-4b57-b92c-6c8ba878fd44
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337630853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3337630853
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3651809672
Short name T14
Test name
Test status
Simulation time 115923915 ps
CPU time 3.1 seconds
Started Jul 31 05:37:24 PM PDT 24
Finished Jul 31 05:37:27 PM PDT 24
Peak memory 206896 kb
Host smart-2eba5529-cb67-4ad6-b40d-bc4fab809ad1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651809672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3651809672
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.23437052
Short name T388
Test name
Test status
Simulation time 42172501 ps
CPU time 2.36 seconds
Started Jul 31 05:37:33 PM PDT 24
Finished Jul 31 05:37:35 PM PDT 24
Peak memory 206984 kb
Host smart-90d0f690-4e4c-4524-b6c5-33980755051a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23437052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.23437052
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.4102186452
Short name T877
Test name
Test status
Simulation time 80444788 ps
CPU time 2.43 seconds
Started Jul 31 05:37:30 PM PDT 24
Finished Jul 31 05:37:33 PM PDT 24
Peak memory 207252 kb
Host smart-42c4cfce-ec01-49ed-aa64-d7a4f78b8cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102186452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.4102186452
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1491649375
Short name T548
Test name
Test status
Simulation time 295616531 ps
CPU time 2.37 seconds
Started Jul 31 05:37:26 PM PDT 24
Finished Jul 31 05:37:29 PM PDT 24
Peak memory 206856 kb
Host smart-61b7eec3-244c-4139-9b81-081e4aa2428e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491649375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1491649375
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1525061763
Short name T2
Test name
Test status
Simulation time 156034802 ps
CPU time 5.41 seconds
Started Jul 31 05:37:31 PM PDT 24
Finished Jul 31 05:37:36 PM PDT 24
Peak memory 214304 kb
Host smart-c6549496-73b2-4c5d-850e-3e73e87a41b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525061763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1525061763
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.506801980
Short name T515
Test name
Test status
Simulation time 214051488 ps
CPU time 2.32 seconds
Started Jul 31 05:37:35 PM PDT 24
Finished Jul 31 05:37:37 PM PDT 24
Peak memory 209704 kb
Host smart-a99e6a16-6076-4252-93da-94b07f2b325a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506801980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.506801980
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1944856223
Short name T830
Test name
Test status
Simulation time 9743579 ps
CPU time 0.72 seconds
Started Jul 31 05:37:32 PM PDT 24
Finished Jul 31 05:37:33 PM PDT 24
Peak memory 205892 kb
Host smart-6ba09526-ca72-4e91-b1f5-f7da7abc7e20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944856223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1944856223
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2164133992
Short name T137
Test name
Test status
Simulation time 33806877 ps
CPU time 2.45 seconds
Started Jul 31 05:37:31 PM PDT 24
Finished Jul 31 05:37:34 PM PDT 24
Peak memory 214680 kb
Host smart-f80d99c4-5ab3-4668-bc34-7185f470e21c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2164133992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2164133992
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2498837872
Short name T18
Test name
Test status
Simulation time 88490001 ps
CPU time 1.7 seconds
Started Jul 31 05:37:31 PM PDT 24
Finished Jul 31 05:37:33 PM PDT 24
Peak memory 222304 kb
Host smart-c0abf7fe-aad3-4115-a6f9-3cb544f20a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498837872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2498837872
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.4215025479
Short name T49
Test name
Test status
Simulation time 55213835 ps
CPU time 2.01 seconds
Started Jul 31 05:37:33 PM PDT 24
Finished Jul 31 05:37:35 PM PDT 24
Peak memory 209140 kb
Host smart-848bc124-6e0d-4418-a56d-57969a1a60bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215025479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.4215025479
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1189859250
Short name T361
Test name
Test status
Simulation time 137085761 ps
CPU time 6.01 seconds
Started Jul 31 05:37:34 PM PDT 24
Finished Jul 31 05:37:40 PM PDT 24
Peak memory 221364 kb
Host smart-535b52df-a369-4484-a0f4-edc8687bb080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189859250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1189859250
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3343202135
Short name T380
Test name
Test status
Simulation time 52106469 ps
CPU time 2.48 seconds
Started Jul 31 05:37:33 PM PDT 24
Finished Jul 31 05:37:35 PM PDT 24
Peak memory 214224 kb
Host smart-2aef960c-ab93-48d1-bf3b-6eef889347d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343202135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3343202135
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2673603438
Short name T772
Test name
Test status
Simulation time 171517540 ps
CPU time 3.42 seconds
Started Jul 31 05:37:35 PM PDT 24
Finished Jul 31 05:37:39 PM PDT 24
Peak memory 214420 kb
Host smart-3cd6e5e1-7553-4daa-95be-bc43e3630627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673603438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2673603438
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2192404117
Short name T498
Test name
Test status
Simulation time 319516657 ps
CPU time 4.42 seconds
Started Jul 31 05:37:31 PM PDT 24
Finished Jul 31 05:37:36 PM PDT 24
Peak memory 214304 kb
Host smart-70fd207e-6c22-46dd-9de0-d200b2288ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192404117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2192404117
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3237580197
Short name T472
Test name
Test status
Simulation time 2367166656 ps
CPU time 44.52 seconds
Started Jul 31 05:37:32 PM PDT 24
Finished Jul 31 05:38:16 PM PDT 24
Peak memory 208608 kb
Host smart-335f5114-43f4-4149-8690-d022e33fb4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237580197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3237580197
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2675031947
Short name T320
Test name
Test status
Simulation time 278292418 ps
CPU time 3.46 seconds
Started Jul 31 05:37:31 PM PDT 24
Finished Jul 31 05:37:35 PM PDT 24
Peak memory 207000 kb
Host smart-e574a881-cf7b-4925-aaae-1bab75bd1607
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675031947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2675031947
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2645836090
Short name T533
Test name
Test status
Simulation time 191558815 ps
CPU time 2.53 seconds
Started Jul 31 05:37:36 PM PDT 24
Finished Jul 31 05:37:39 PM PDT 24
Peak memory 206100 kb
Host smart-83440baa-3761-4c91-9e2f-96ef48489bbd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645836090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2645836090
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2961962973
Short name T634
Test name
Test status
Simulation time 33694283 ps
CPU time 2.43 seconds
Started Jul 31 05:37:28 PM PDT 24
Finished Jul 31 05:37:31 PM PDT 24
Peak memory 206944 kb
Host smart-1f5dccef-ecef-493c-8992-76fd44892f3a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961962973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2961962973
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2860657570
Short name T248
Test name
Test status
Simulation time 532941730 ps
CPU time 3.52 seconds
Started Jul 31 05:37:32 PM PDT 24
Finished Jul 31 05:37:36 PM PDT 24
Peak memory 214348 kb
Host smart-b4435528-ed30-492e-9991-afac27c3daa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860657570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2860657570
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.2632051397
Short name T765
Test name
Test status
Simulation time 664525517 ps
CPU time 4.26 seconds
Started Jul 31 05:37:31 PM PDT 24
Finished Jul 31 05:37:36 PM PDT 24
Peak memory 208632 kb
Host smart-2a01264f-4f4f-4fe6-9f32-399bb595997d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632051397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2632051397
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.574283431
Short name T178
Test name
Test status
Simulation time 1289809313 ps
CPU time 25.45 seconds
Started Jul 31 05:37:32 PM PDT 24
Finished Jul 31 05:37:57 PM PDT 24
Peak memory 222464 kb
Host smart-fc773a6a-859a-4b6b-bfac-4cc9a301c59c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574283431 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.574283431
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1114814972
Short name T577
Test name
Test status
Simulation time 202165152 ps
CPU time 6.55 seconds
Started Jul 31 05:37:33 PM PDT 24
Finished Jul 31 05:37:39 PM PDT 24
Peak memory 209220 kb
Host smart-73d14445-2196-4ec5-b028-a1abe0fb487c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114814972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1114814972
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.146406141
Short name T133
Test name
Test status
Simulation time 697847273 ps
CPU time 2.64 seconds
Started Jul 31 05:37:32 PM PDT 24
Finished Jul 31 05:37:35 PM PDT 24
Peak memory 210040 kb
Host smart-fe44a27c-d704-4347-a766-76f9753ddbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146406141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.146406141
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.174681432
Short name T876
Test name
Test status
Simulation time 15055850 ps
CPU time 0.73 seconds
Started Jul 31 05:37:38 PM PDT 24
Finished Jul 31 05:37:39 PM PDT 24
Peak memory 205976 kb
Host smart-ae97963e-49da-4bfc-af42-9d0779d14ae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174681432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.174681432
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.98672640
Short name T432
Test name
Test status
Simulation time 273262113 ps
CPU time 1.36 seconds
Started Jul 31 05:37:44 PM PDT 24
Finished Jul 31 05:37:45 PM PDT 24
Peak memory 206704 kb
Host smart-a9524ca5-db6c-4af3-8e7f-907bf76ad9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98672640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.98672640
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3266955228
Short name T658
Test name
Test status
Simulation time 120788308 ps
CPU time 2.72 seconds
Started Jul 31 05:37:35 PM PDT 24
Finished Jul 31 05:37:38 PM PDT 24
Peak memory 214284 kb
Host smart-d7980441-5911-4166-9b65-adfb0d5ba15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266955228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3266955228
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.321764132
Short name T477
Test name
Test status
Simulation time 228785473 ps
CPU time 2.06 seconds
Started Jul 31 05:37:36 PM PDT 24
Finished Jul 31 05:37:38 PM PDT 24
Peak memory 207760 kb
Host smart-46f244eb-b54e-425a-a178-c5ce281dbb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321764132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.321764132
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3032879419
Short name T528
Test name
Test status
Simulation time 229280502 ps
CPU time 7.4 seconds
Started Jul 31 05:37:34 PM PDT 24
Finished Jul 31 05:37:42 PM PDT 24
Peak memory 218312 kb
Host smart-0d62628f-7fc9-4497-beb8-cb663b7b7fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032879419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3032879419
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.279398162
Short name T257
Test name
Test status
Simulation time 107358362 ps
CPU time 4.5 seconds
Started Jul 31 05:37:36 PM PDT 24
Finished Jul 31 05:37:41 PM PDT 24
Peak memory 206928 kb
Host smart-91198078-4394-4d54-8eb4-3463c9e63916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279398162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.279398162
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1619250427
Short name T206
Test name
Test status
Simulation time 64035349 ps
CPU time 3.29 seconds
Started Jul 31 05:37:37 PM PDT 24
Finished Jul 31 05:37:40 PM PDT 24
Peak memory 206992 kb
Host smart-e81450c6-8793-4f27-80b6-bf395b03e4fa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619250427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1619250427
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.650321874
Short name T728
Test name
Test status
Simulation time 82589727 ps
CPU time 2.92 seconds
Started Jul 31 05:37:37 PM PDT 24
Finished Jul 31 05:37:40 PM PDT 24
Peak memory 207236 kb
Host smart-14e94082-2b99-4064-a39e-ee78c4842a6b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650321874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.650321874
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.4092890598
Short name T913
Test name
Test status
Simulation time 60624077 ps
CPU time 2.85 seconds
Started Jul 31 05:37:37 PM PDT 24
Finished Jul 31 05:37:40 PM PDT 24
Peak memory 206900 kb
Host smart-217a89b8-7a03-4327-940c-ceca5dba2d4d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092890598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.4092890598
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.4047629584
Short name T753
Test name
Test status
Simulation time 183322210 ps
CPU time 3.23 seconds
Started Jul 31 05:37:44 PM PDT 24
Finished Jul 31 05:37:48 PM PDT 24
Peak memory 209208 kb
Host smart-38f79c00-efa0-4a29-84cf-1841d882dcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047629584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.4047629584
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1408636345
Short name T428
Test name
Test status
Simulation time 145832440 ps
CPU time 4.29 seconds
Started Jul 31 05:37:37 PM PDT 24
Finished Jul 31 05:37:42 PM PDT 24
Peak memory 208496 kb
Host smart-f737f6ac-8e7f-469b-8536-2aa3ac3fa534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408636345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1408636345
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3693750413
Short name T614
Test name
Test status
Simulation time 1775383344 ps
CPU time 13.17 seconds
Started Jul 31 05:37:44 PM PDT 24
Finished Jul 31 05:37:57 PM PDT 24
Peak memory 214956 kb
Host smart-9bcf8f6c-8182-49ee-a270-447e1104b873
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693750413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3693750413
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.1644108557
Short name T181
Test name
Test status
Simulation time 519504285 ps
CPU time 17.37 seconds
Started Jul 31 05:37:45 PM PDT 24
Finished Jul 31 05:38:02 PM PDT 24
Peak memory 222572 kb
Host smart-48c8a275-b39a-4532-8abd-94ffd5b70141
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644108557 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.1644108557
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1663550798
Short name T707
Test name
Test status
Simulation time 394397498 ps
CPU time 2.83 seconds
Started Jul 31 05:37:44 PM PDT 24
Finished Jul 31 05:37:47 PM PDT 24
Peak memory 209848 kb
Host smart-b1d41b73-ef56-45d3-84be-13774b28d68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663550798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1663550798
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1676497294
Short name T401
Test name
Test status
Simulation time 112258528 ps
CPU time 2.4 seconds
Started Jul 31 05:37:41 PM PDT 24
Finished Jul 31 05:37:44 PM PDT 24
Peak memory 210176 kb
Host smart-92128c16-ee3e-4889-aedd-db24411a3811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676497294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1676497294
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3956780624
Short name T82
Test name
Test status
Simulation time 21107704 ps
CPU time 0.84 seconds
Started Jul 31 05:37:40 PM PDT 24
Finished Jul 31 05:37:41 PM PDT 24
Peak memory 205964 kb
Host smart-23c9e690-258d-476b-ab77-47ddc9bcf216
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956780624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3956780624
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.319267263
Short name T424
Test name
Test status
Simulation time 1155999659 ps
CPU time 15.55 seconds
Started Jul 31 05:37:35 PM PDT 24
Finished Jul 31 05:37:51 PM PDT 24
Peak memory 214336 kb
Host smart-080048c4-da5c-4f1d-bce2-221db1920015
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=319267263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.319267263
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.574775113
Short name T419
Test name
Test status
Simulation time 910036665 ps
CPU time 3.66 seconds
Started Jul 31 05:37:44 PM PDT 24
Finished Jul 31 05:37:48 PM PDT 24
Peak memory 218352 kb
Host smart-853939b4-6c7b-4772-92fc-15defa3f9256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574775113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.574775113
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.317059252
Short name T804
Test name
Test status
Simulation time 8402297170 ps
CPU time 53.19 seconds
Started Jul 31 05:37:35 PM PDT 24
Finished Jul 31 05:38:28 PM PDT 24
Peak memory 214320 kb
Host smart-85e4bbc7-4e2d-4bd0-975f-29ab8fc3be95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317059252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.317059252
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.376535911
Short name T888
Test name
Test status
Simulation time 155624867 ps
CPU time 4.1 seconds
Started Jul 31 05:37:36 PM PDT 24
Finished Jul 31 05:37:40 PM PDT 24
Peak memory 209848 kb
Host smart-c802e0ad-c767-4cb8-a261-17622e14874c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376535911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.376535911
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.675732408
Short name T126
Test name
Test status
Simulation time 3309026940 ps
CPU time 12.96 seconds
Started Jul 31 05:37:37 PM PDT 24
Finished Jul 31 05:37:50 PM PDT 24
Peak memory 208032 kb
Host smart-c299f6e1-50d3-438d-b18d-276f72a9dd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675732408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.675732408
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2354994731
Short name T507
Test name
Test status
Simulation time 297354261 ps
CPU time 6.71 seconds
Started Jul 31 05:37:45 PM PDT 24
Finished Jul 31 05:37:52 PM PDT 24
Peak memory 208392 kb
Host smart-005f8e9f-65b3-4f77-9851-9d5cad80006d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354994731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2354994731
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1924042389
Short name T534
Test name
Test status
Simulation time 530833411 ps
CPU time 7.74 seconds
Started Jul 31 05:37:44 PM PDT 24
Finished Jul 31 05:37:52 PM PDT 24
Peak memory 207116 kb
Host smart-fea104b3-0291-4bbc-920e-ec90c801c653
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924042389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1924042389
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2118578453
Short name T631
Test name
Test status
Simulation time 388640844 ps
CPU time 3.27 seconds
Started Jul 31 05:37:36 PM PDT 24
Finished Jul 31 05:37:39 PM PDT 24
Peak memory 208356 kb
Host smart-545d7fc5-a6df-4b59-b38c-3062c6a0e13c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118578453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2118578453
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3490787358
Short name T500
Test name
Test status
Simulation time 36228248 ps
CPU time 2.36 seconds
Started Jul 31 05:37:44 PM PDT 24
Finished Jul 31 05:37:46 PM PDT 24
Peak memory 208636 kb
Host smart-4c7aeec5-84de-4754-9cf7-e6ad4215afbb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490787358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3490787358
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.3464852615
Short name T625
Test name
Test status
Simulation time 33378048 ps
CPU time 2.26 seconds
Started Jul 31 05:37:44 PM PDT 24
Finished Jul 31 05:37:46 PM PDT 24
Peak memory 207852 kb
Host smart-10dc8b19-1db2-4333-9070-fe2f93768c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464852615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3464852615
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1833267109
Short name T684
Test name
Test status
Simulation time 185336292 ps
CPU time 5.5 seconds
Started Jul 31 05:37:36 PM PDT 24
Finished Jul 31 05:37:42 PM PDT 24
Peak memory 206708 kb
Host smart-fddf4046-cd90-4343-9c4a-97d74e844669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833267109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1833267109
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1179195558
Short name T376
Test name
Test status
Simulation time 252541077 ps
CPU time 2.76 seconds
Started Jul 31 05:37:35 PM PDT 24
Finished Jul 31 05:37:38 PM PDT 24
Peak memory 208160 kb
Host smart-6ac521b4-8fbd-4351-9f5f-f718ab47b5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179195558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1179195558
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.6587598
Short name T175
Test name
Test status
Simulation time 1094367173 ps
CPU time 2.97 seconds
Started Jul 31 05:37:39 PM PDT 24
Finished Jul 31 05:37:42 PM PDT 24
Peak memory 209536 kb
Host smart-2679d254-f97f-4b4d-b00b-3b4f0e8c45b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6587598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.6587598
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2558916163
Short name T497
Test name
Test status
Simulation time 131035620 ps
CPU time 0.83 seconds
Started Jul 31 05:37:41 PM PDT 24
Finished Jul 31 05:37:42 PM PDT 24
Peak memory 205940 kb
Host smart-e739a61b-b8f6-4c97-bdbf-a2018499a3d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558916163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2558916163
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1692263638
Short name T420
Test name
Test status
Simulation time 379840396 ps
CPU time 5.92 seconds
Started Jul 31 05:37:40 PM PDT 24
Finished Jul 31 05:37:46 PM PDT 24
Peak memory 214296 kb
Host smart-ea64ae1b-0bd9-41c5-be82-7ac3ad0179e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1692263638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1692263638
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.4048510832
Short name T41
Test name
Test status
Simulation time 242316112 ps
CPU time 6.39 seconds
Started Jul 31 05:37:43 PM PDT 24
Finished Jul 31 05:37:50 PM PDT 24
Peak memory 209228 kb
Host smart-efdd2969-ba77-49bc-a379-48fbbe91a078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048510832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.4048510832
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2726202541
Short name T745
Test name
Test status
Simulation time 308685247 ps
CPU time 4.4 seconds
Started Jul 31 05:37:43 PM PDT 24
Finished Jul 31 05:37:47 PM PDT 24
Peak memory 214288 kb
Host smart-eb82f583-2b20-402d-b3e7-e1245032dd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726202541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2726202541
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.71584060
Short name T243
Test name
Test status
Simulation time 403767477 ps
CPU time 5.13 seconds
Started Jul 31 05:37:45 PM PDT 24
Finished Jul 31 05:37:50 PM PDT 24
Peak memory 220372 kb
Host smart-f85e60df-18c8-4f24-b4b6-eb8ef422615d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71584060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.71584060
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.277490182
Short name T45
Test name
Test status
Simulation time 441123432 ps
CPU time 3.18 seconds
Started Jul 31 05:37:41 PM PDT 24
Finished Jul 31 05:37:45 PM PDT 24
Peak memory 209512 kb
Host smart-e6a4b9f5-cc34-4886-9916-b443614b1d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277490182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.277490182
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.3149692540
Short name T828
Test name
Test status
Simulation time 71712291 ps
CPU time 3.73 seconds
Started Jul 31 05:37:40 PM PDT 24
Finished Jul 31 05:37:44 PM PDT 24
Peak memory 209320 kb
Host smart-4f14ba17-426e-4b67-bb04-b9884fc169c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149692540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3149692540
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.68782938
Short name T682
Test name
Test status
Simulation time 127849909 ps
CPU time 4.31 seconds
Started Jul 31 05:37:46 PM PDT 24
Finished Jul 31 05:37:51 PM PDT 24
Peak memory 208524 kb
Host smart-ef8bfa0a-5548-4715-8bfb-9db6254ce370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68782938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.68782938
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3406286780
Short name T563
Test name
Test status
Simulation time 290411001 ps
CPU time 3.88 seconds
Started Jul 31 05:37:42 PM PDT 24
Finished Jul 31 05:37:46 PM PDT 24
Peak memory 206960 kb
Host smart-5e9020d9-d66b-4bd8-bf41-3a8343d44758
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406286780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3406286780
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1906758578
Short name T749
Test name
Test status
Simulation time 1582155934 ps
CPU time 38.37 seconds
Started Jul 31 05:37:41 PM PDT 24
Finished Jul 31 05:38:20 PM PDT 24
Peak memory 209124 kb
Host smart-0ba5f6a6-53c8-495e-9ea1-935f553a3249
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906758578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1906758578
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1124318619
Short name T727
Test name
Test status
Simulation time 315580222 ps
CPU time 3.28 seconds
Started Jul 31 05:37:45 PM PDT 24
Finished Jul 31 05:37:48 PM PDT 24
Peak memory 208752 kb
Host smart-4576b90d-334d-4d3c-a599-cbb8d710b59e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124318619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1124318619
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3679648443
Short name T603
Test name
Test status
Simulation time 789588986 ps
CPU time 8.09 seconds
Started Jul 31 05:37:44 PM PDT 24
Finished Jul 31 05:37:52 PM PDT 24
Peak memory 208568 kb
Host smart-178ea532-a002-4c3a-8e4d-85ff2b640c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679648443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3679648443
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3492365124
Short name T414
Test name
Test status
Simulation time 2575148178 ps
CPU time 9.98 seconds
Started Jul 31 05:37:40 PM PDT 24
Finished Jul 31 05:37:50 PM PDT 24
Peak memory 208384 kb
Host smart-345e6c71-ae79-4e15-afd6-c36760daa5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492365124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3492365124
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3212870880
Short name T583
Test name
Test status
Simulation time 28993781733 ps
CPU time 466.9 seconds
Started Jul 31 05:37:45 PM PDT 24
Finished Jul 31 05:45:32 PM PDT 24
Peak memory 230096 kb
Host smart-974e77ee-b42e-4421-95f8-05e8f8558bca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212870880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3212870880
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.2898833523
Short name T120
Test name
Test status
Simulation time 324105462 ps
CPU time 10.43 seconds
Started Jul 31 05:37:43 PM PDT 24
Finished Jul 31 05:37:53 PM PDT 24
Peak memory 219060 kb
Host smart-4af24a69-a6ba-4ad4-8229-aa036f42dc76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898833523 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.2898833523
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3667797431
Short name T487
Test name
Test status
Simulation time 242689769 ps
CPU time 2.53 seconds
Started Jul 31 05:37:40 PM PDT 24
Finished Jul 31 05:37:43 PM PDT 24
Peak memory 207596 kb
Host smart-9f217e58-afa0-4bac-b6a5-f77c9dc6ad9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667797431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3667797431
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3266801431
Short name T155
Test name
Test status
Simulation time 70172846 ps
CPU time 2.61 seconds
Started Jul 31 05:37:40 PM PDT 24
Finished Jul 31 05:37:43 PM PDT 24
Peak memory 210540 kb
Host smart-e0d15a4c-0899-4928-ad60-92036d6bbe49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266801431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3266801431
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2114998125
Short name T919
Test name
Test status
Simulation time 9769748 ps
CPU time 0.9 seconds
Started Jul 31 05:37:56 PM PDT 24
Finished Jul 31 05:37:57 PM PDT 24
Peak memory 205888 kb
Host smart-f6e58571-1b5f-4845-a8f5-2fbce2174b2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114998125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2114998125
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.785976402
Short name T426
Test name
Test status
Simulation time 171340777 ps
CPU time 3.31 seconds
Started Jul 31 05:37:41 PM PDT 24
Finished Jul 31 05:37:44 PM PDT 24
Peak memory 214312 kb
Host smart-213d7ab1-c529-4f3d-9f2a-90b27134be96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=785976402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.785976402
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2335405797
Short name T691
Test name
Test status
Simulation time 191585282 ps
CPU time 2.62 seconds
Started Jul 31 05:37:40 PM PDT 24
Finished Jul 31 05:37:43 PM PDT 24
Peak memory 214276 kb
Host smart-1753dc8e-7115-4a97-9a9f-492ab509f812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335405797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2335405797
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.165107227
Short name T715
Test name
Test status
Simulation time 96476629 ps
CPU time 4.78 seconds
Started Jul 31 05:37:44 PM PDT 24
Finished Jul 31 05:37:49 PM PDT 24
Peak memory 214372 kb
Host smart-734d2395-f25c-4887-a341-dd80967df3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165107227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.165107227
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2949955151
Short name T38
Test name
Test status
Simulation time 328431513 ps
CPU time 2.12 seconds
Started Jul 31 05:37:43 PM PDT 24
Finished Jul 31 05:37:45 PM PDT 24
Peak memory 214280 kb
Host smart-5c4f3694-d647-429c-9c85-1a7576323bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949955151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2949955151
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1740351516
Short name T60
Test name
Test status
Simulation time 47679204 ps
CPU time 2.87 seconds
Started Jul 31 05:37:44 PM PDT 24
Finished Jul 31 05:37:47 PM PDT 24
Peak memory 216040 kb
Host smart-42366d04-5dce-418d-89b8-12014c9d9070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740351516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1740351516
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3811047158
Short name T654
Test name
Test status
Simulation time 450392298 ps
CPU time 5.39 seconds
Started Jul 31 05:37:43 PM PDT 24
Finished Jul 31 05:37:48 PM PDT 24
Peak memory 210552 kb
Host smart-f6a96a9e-9c06-43ef-a845-a0f8b6050f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811047158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3811047158
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2898862248
Short name T710
Test name
Test status
Simulation time 539951514 ps
CPU time 8.06 seconds
Started Jul 31 05:37:46 PM PDT 24
Finished Jul 31 05:37:54 PM PDT 24
Peak memory 206884 kb
Host smart-a719cf8d-b262-4126-a11c-1a97703c5f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898862248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2898862248
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.4277929091
Short name T235
Test name
Test status
Simulation time 177823296 ps
CPU time 3.08 seconds
Started Jul 31 05:37:46 PM PDT 24
Finished Jul 31 05:37:49 PM PDT 24
Peak memory 206956 kb
Host smart-5b9e7ee8-4144-4209-a655-deed974a4d79
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277929091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.4277929091
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2199045483
Short name T652
Test name
Test status
Simulation time 184673170 ps
CPU time 7.15 seconds
Started Jul 31 05:37:40 PM PDT 24
Finished Jul 31 05:37:48 PM PDT 24
Peak memory 207972 kb
Host smart-90c0a8b9-1bc3-4b10-9d4b-95b0193963f3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199045483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2199045483
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.4253907394
Short name T520
Test name
Test status
Simulation time 31621971 ps
CPU time 2.3 seconds
Started Jul 31 05:37:42 PM PDT 24
Finished Jul 31 05:37:45 PM PDT 24
Peak memory 207028 kb
Host smart-09d42125-10c8-47c1-b2b6-181e8cb1392c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253907394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.4253907394
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.491967868
Short name T806
Test name
Test status
Simulation time 99969713 ps
CPU time 2.27 seconds
Started Jul 31 05:37:51 PM PDT 24
Finished Jul 31 05:37:54 PM PDT 24
Peak memory 210040 kb
Host smart-899e40fb-f156-4799-b573-19c9c57d1640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491967868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.491967868
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1273151269
Short name T557
Test name
Test status
Simulation time 9801113144 ps
CPU time 28.6 seconds
Started Jul 31 05:37:44 PM PDT 24
Finished Jul 31 05:38:13 PM PDT 24
Peak memory 208324 kb
Host smart-bf819df9-357e-42da-9692-ef5ae3922e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273151269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1273151269
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.4002288547
Short name T299
Test name
Test status
Simulation time 556739153 ps
CPU time 12.69 seconds
Started Jul 31 05:37:51 PM PDT 24
Finished Jul 31 05:38:03 PM PDT 24
Peak memory 217024 kb
Host smart-c1e8cbab-fa6e-4c20-9977-38c9eed4d2e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002288547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.4002288547
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2556845293
Short name T125
Test name
Test status
Simulation time 221207066 ps
CPU time 13.77 seconds
Started Jul 31 05:37:53 PM PDT 24
Finished Jul 31 05:38:07 PM PDT 24
Peak memory 222520 kb
Host smart-62327cb5-c2ed-4a38-b715-cfb23a1f7b79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556845293 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2556845293
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2770458836
Short name T199
Test name
Test status
Simulation time 112278354 ps
CPU time 4.2 seconds
Started Jul 31 05:37:38 PM PDT 24
Finished Jul 31 05:37:42 PM PDT 24
Peak memory 210176 kb
Host smart-3cbc0afd-5c02-4509-ac5d-e10fb59d7a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770458836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2770458836
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.4030992459
Short name T761
Test name
Test status
Simulation time 77972687 ps
CPU time 3.18 seconds
Started Jul 31 05:37:53 PM PDT 24
Finished Jul 31 05:37:56 PM PDT 24
Peak memory 209912 kb
Host smart-39d84475-acd3-48a7-ba96-665f1f93aa0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030992459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.4030992459
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.284857662
Short name T636
Test name
Test status
Simulation time 7658650 ps
CPU time 0.69 seconds
Started Jul 31 05:37:53 PM PDT 24
Finished Jul 31 05:37:53 PM PDT 24
Peak memory 205972 kb
Host smart-b76b1bc0-705d-480e-b698-ff13a2f12e0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284857662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.284857662
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2505528630
Short name T372
Test name
Test status
Simulation time 38569339 ps
CPU time 3.31 seconds
Started Jul 31 05:37:52 PM PDT 24
Finished Jul 31 05:37:56 PM PDT 24
Peak memory 215560 kb
Host smart-9527f85a-16c8-4697-a891-18a3a727ab97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2505528630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2505528630
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2604784542
Short name T875
Test name
Test status
Simulation time 235028595 ps
CPU time 1.66 seconds
Started Jul 31 05:37:53 PM PDT 24
Finished Jul 31 05:37:55 PM PDT 24
Peak memory 216472 kb
Host smart-c5848f0b-22f8-4063-a4f3-c75fc6052a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604784542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2604784542
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.261240143
Short name T622
Test name
Test status
Simulation time 99071412 ps
CPU time 2.93 seconds
Started Jul 31 05:37:51 PM PDT 24
Finished Jul 31 05:37:54 PM PDT 24
Peak memory 207548 kb
Host smart-f1881b3d-36e1-42e6-9bff-1c2fc7c9d470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261240143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.261240143
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.4096877273
Short name T846
Test name
Test status
Simulation time 114093707 ps
CPU time 3.78 seconds
Started Jul 31 05:37:50 PM PDT 24
Finished Jul 31 05:37:54 PM PDT 24
Peak memory 214396 kb
Host smart-20256856-af2f-4137-ab21-35972185ca77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096877273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.4096877273
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1424061727
Short name T330
Test name
Test status
Simulation time 129412793 ps
CPU time 2.18 seconds
Started Jul 31 05:37:53 PM PDT 24
Finished Jul 31 05:37:55 PM PDT 24
Peak memory 220532 kb
Host smart-b04e7743-eb8f-484e-816c-4475b9778276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424061727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1424061727
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.4272536156
Short name T233
Test name
Test status
Simulation time 79758328 ps
CPU time 4.65 seconds
Started Jul 31 05:37:56 PM PDT 24
Finished Jul 31 05:38:01 PM PDT 24
Peak memory 219220 kb
Host smart-8e33cf2e-9f15-41f6-af76-868a25882de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272536156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.4272536156
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.675557838
Short name T906
Test name
Test status
Simulation time 148970387 ps
CPU time 4.82 seconds
Started Jul 31 05:37:52 PM PDT 24
Finished Jul 31 05:37:57 PM PDT 24
Peak memory 207512 kb
Host smart-e8efa8d3-7f84-40ed-b196-2cdbc92f31f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675557838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.675557838
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3366925661
Short name T867
Test name
Test status
Simulation time 3356799193 ps
CPU time 18.55 seconds
Started Jul 31 05:37:54 PM PDT 24
Finished Jul 31 05:38:12 PM PDT 24
Peak memory 208156 kb
Host smart-6db75abe-b745-4c4f-8ed3-a2077b933734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366925661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3366925661
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3161654791
Short name T719
Test name
Test status
Simulation time 64423616 ps
CPU time 2.99 seconds
Started Jul 31 05:37:53 PM PDT 24
Finished Jul 31 05:37:56 PM PDT 24
Peak memory 208748 kb
Host smart-beefe9d0-566f-4267-9f77-0e310623bbe7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161654791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3161654791
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.4036467465
Short name T640
Test name
Test status
Simulation time 62463042 ps
CPU time 2.35 seconds
Started Jul 31 05:37:52 PM PDT 24
Finished Jul 31 05:37:55 PM PDT 24
Peak memory 206908 kb
Host smart-2c13005b-bf19-451b-9536-23b166b3c490
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036467465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.4036467465
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2652116728
Short name T907
Test name
Test status
Simulation time 175585260 ps
CPU time 5.37 seconds
Started Jul 31 05:37:53 PM PDT 24
Finished Jul 31 05:37:59 PM PDT 24
Peak memory 208632 kb
Host smart-44713a46-1698-4a44-9497-d7110cb73169
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652116728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2652116728
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1065247364
Short name T572
Test name
Test status
Simulation time 1428245602 ps
CPU time 6.76 seconds
Started Jul 31 05:37:53 PM PDT 24
Finished Jul 31 05:37:59 PM PDT 24
Peak memory 218432 kb
Host smart-3bd2ad41-f927-43eb-9b9b-1b94adc35342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065247364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1065247364
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3177257380
Short name T546
Test name
Test status
Simulation time 60757101 ps
CPU time 2.82 seconds
Started Jul 31 05:37:57 PM PDT 24
Finished Jul 31 05:38:00 PM PDT 24
Peak memory 207112 kb
Host smart-6eacc88b-7a31-4ba6-884f-314111d08427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177257380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3177257380
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.367325024
Short name T519
Test name
Test status
Simulation time 319731838 ps
CPU time 13.27 seconds
Started Jul 31 05:37:53 PM PDT 24
Finished Jul 31 05:38:06 PM PDT 24
Peak memory 219776 kb
Host smart-0835eb82-e4b4-47b6-9c28-5b99e5a2efb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367325024 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.367325024
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2956000440
Short name T427
Test name
Test status
Simulation time 335397043 ps
CPU time 4.66 seconds
Started Jul 31 05:37:51 PM PDT 24
Finished Jul 31 05:37:56 PM PDT 24
Peak memory 214300 kb
Host smart-d7d5eedf-5f37-4926-8e2b-9bcd1c732665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956000440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2956000440
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1602157227
Short name T562
Test name
Test status
Simulation time 119694087 ps
CPU time 2.02 seconds
Started Jul 31 05:37:53 PM PDT 24
Finished Jul 31 05:37:55 PM PDT 24
Peak memory 210596 kb
Host smart-da7561d5-a953-4205-8e3c-ffc56da2b0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602157227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1602157227
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.1954368179
Short name T444
Test name
Test status
Simulation time 17864811 ps
CPU time 0.81 seconds
Started Jul 31 05:37:54 PM PDT 24
Finished Jul 31 05:37:55 PM PDT 24
Peak memory 205972 kb
Host smart-bcb42f10-49fb-420b-b55a-6c2315eb9e6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954368179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1954368179
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1953674523
Short name T305
Test name
Test status
Simulation time 7050351773 ps
CPU time 94.9 seconds
Started Jul 31 05:37:52 PM PDT 24
Finished Jul 31 05:39:27 PM PDT 24
Peak memory 217724 kb
Host smart-dd210e23-032c-41d0-ba83-48901a481e82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1953674523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1953674523
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1725427191
Short name T909
Test name
Test status
Simulation time 432303341 ps
CPU time 11.54 seconds
Started Jul 31 05:37:54 PM PDT 24
Finished Jul 31 05:38:06 PM PDT 24
Peak memory 218232 kb
Host smart-c0ea0c2f-eb2c-47f2-8708-df4b9ce55abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725427191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1725427191
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3507171690
Short name T80
Test name
Test status
Simulation time 3174217746 ps
CPU time 11.82 seconds
Started Jul 31 05:37:55 PM PDT 24
Finished Jul 31 05:38:07 PM PDT 24
Peak memory 218344 kb
Host smart-75eed481-a6d3-44a9-ab05-aa9c2a4e7efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507171690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3507171690
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2097855900
Short name T97
Test name
Test status
Simulation time 180315778 ps
CPU time 5.72 seconds
Started Jul 31 05:37:55 PM PDT 24
Finished Jul 31 05:38:01 PM PDT 24
Peak memory 222412 kb
Host smart-62e691b4-24e9-4cff-a26a-b0540fe06d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097855900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2097855900
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1913943722
Short name T304
Test name
Test status
Simulation time 142422196 ps
CPU time 2.04 seconds
Started Jul 31 05:37:59 PM PDT 24
Finished Jul 31 05:38:01 PM PDT 24
Peak memory 214252 kb
Host smart-696cf0a4-77e4-4e94-b2f9-68ce7a94474e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913943722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1913943722
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1742646010
Short name T449
Test name
Test status
Simulation time 142626837 ps
CPU time 2.77 seconds
Started Jul 31 05:37:53 PM PDT 24
Finished Jul 31 05:37:56 PM PDT 24
Peak memory 216652 kb
Host smart-45426d80-2bd1-4b16-a250-f2687c7f0409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742646010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1742646010
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1135064562
Short name T316
Test name
Test status
Simulation time 154721109 ps
CPU time 6.21 seconds
Started Jul 31 05:37:57 PM PDT 24
Finished Jul 31 05:38:03 PM PDT 24
Peak memory 214220 kb
Host smart-71497beb-fa6a-47d9-8cae-131383dbe311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135064562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1135064562
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2977325087
Short name T731
Test name
Test status
Simulation time 37655035 ps
CPU time 2.51 seconds
Started Jul 31 05:37:50 PM PDT 24
Finished Jul 31 05:37:53 PM PDT 24
Peak memory 206944 kb
Host smart-70cf4025-9b55-4ff8-8b94-62ea3a9b4d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977325087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2977325087
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3323300051
Short name T504
Test name
Test status
Simulation time 120578184 ps
CPU time 3.03 seconds
Started Jul 31 05:37:53 PM PDT 24
Finished Jul 31 05:37:56 PM PDT 24
Peak memory 207104 kb
Host smart-2ef17596-898d-4cad-b591-5f36e4c534b8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323300051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3323300051
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.782324251
Short name T338
Test name
Test status
Simulation time 277751472 ps
CPU time 3.76 seconds
Started Jul 31 05:37:52 PM PDT 24
Finished Jul 31 05:37:56 PM PDT 24
Peak memory 208664 kb
Host smart-78bf44f6-21ee-41c0-ae37-307cb0d76535
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782324251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.782324251
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1016197526
Short name T738
Test name
Test status
Simulation time 98388355 ps
CPU time 2.11 seconds
Started Jul 31 05:37:52 PM PDT 24
Finished Jul 31 05:37:54 PM PDT 24
Peak memory 208760 kb
Host smart-cb299928-ca14-455a-87a8-a9d4f52d97d2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016197526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1016197526
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3387255392
Short name T537
Test name
Test status
Simulation time 272012893 ps
CPU time 2.06 seconds
Started Jul 31 05:37:54 PM PDT 24
Finished Jul 31 05:37:56 PM PDT 24
Peak memory 215872 kb
Host smart-30bf99c7-ec54-4325-b219-fd12b82c79e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387255392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3387255392
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.171326220
Short name T433
Test name
Test status
Simulation time 314463406 ps
CPU time 2.3 seconds
Started Jul 31 05:37:50 PM PDT 24
Finished Jul 31 05:37:53 PM PDT 24
Peak memory 206904 kb
Host smart-8544228a-a7bd-409d-8887-99d07475ccc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171326220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.171326220
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3642512005
Short name T693
Test name
Test status
Simulation time 338057028 ps
CPU time 4.43 seconds
Started Jul 31 05:37:56 PM PDT 24
Finished Jul 31 05:38:01 PM PDT 24
Peak memory 208156 kb
Host smart-3a3ce138-189a-4c3e-bf63-a6aaccfc00b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642512005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3642512005
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.888082406
Short name T192
Test name
Test status
Simulation time 534255483 ps
CPU time 6.75 seconds
Started Jul 31 05:37:53 PM PDT 24
Finished Jul 31 05:38:00 PM PDT 24
Peak memory 210292 kb
Host smart-4ec23939-78d5-4604-86d1-ad6af20c7c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888082406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.888082406
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1057687137
Short name T820
Test name
Test status
Simulation time 8584907 ps
CPU time 0.83 seconds
Started Jul 31 05:37:59 PM PDT 24
Finished Jul 31 05:38:00 PM PDT 24
Peak memory 205932 kb
Host smart-6db80506-1e0f-4850-8ed8-bfd6c6c91191
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057687137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1057687137
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1192865027
Short name T417
Test name
Test status
Simulation time 437894106 ps
CPU time 12.73 seconds
Started Jul 31 05:37:55 PM PDT 24
Finished Jul 31 05:38:07 PM PDT 24
Peak memory 215372 kb
Host smart-24bee0a9-99c4-4969-bbfc-bf324e730578
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1192865027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1192865027
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1609632500
Short name T787
Test name
Test status
Simulation time 490941160 ps
CPU time 4.07 seconds
Started Jul 31 05:37:55 PM PDT 24
Finished Jul 31 05:37:59 PM PDT 24
Peak memory 218072 kb
Host smart-afe9753d-be72-4d5f-abfb-5c6ad1a662ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609632500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1609632500
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.717887486
Short name T321
Test name
Test status
Simulation time 832697511 ps
CPU time 8.2 seconds
Started Jul 31 05:37:55 PM PDT 24
Finished Jul 31 05:38:03 PM PDT 24
Peak memory 206936 kb
Host smart-bdcc51c9-087d-494d-a9d8-83ea1bf4ecac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717887486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.717887486
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1611584287
Short name T689
Test name
Test status
Simulation time 109520531 ps
CPU time 4.63 seconds
Started Jul 31 05:37:56 PM PDT 24
Finished Jul 31 05:38:01 PM PDT 24
Peak memory 222020 kb
Host smart-3346cb7f-fda0-4ee5-a234-cb7dc8b6fa5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611584287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1611584287
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1254920428
Short name T360
Test name
Test status
Simulation time 158091342 ps
CPU time 1.98 seconds
Started Jul 31 05:37:58 PM PDT 24
Finished Jul 31 05:38:00 PM PDT 24
Peak memory 214300 kb
Host smart-68042932-c409-4822-86f0-ab52656532b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254920428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1254920428
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1407049754
Short name T553
Test name
Test status
Simulation time 534214262 ps
CPU time 6.13 seconds
Started Jul 31 05:37:55 PM PDT 24
Finished Jul 31 05:38:01 PM PDT 24
Peak memory 210292 kb
Host smart-26054742-fe5e-4fe1-baee-3588cd9f8194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407049754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1407049754
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1903144116
Short name T750
Test name
Test status
Simulation time 474801445 ps
CPU time 5.74 seconds
Started Jul 31 05:37:55 PM PDT 24
Finished Jul 31 05:38:01 PM PDT 24
Peak memory 209212 kb
Host smart-7c2ca7b8-7f0d-4392-8741-a8a7f9049d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903144116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1903144116
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.442084511
Short name T838
Test name
Test status
Simulation time 137296797 ps
CPU time 2.93 seconds
Started Jul 31 05:37:55 PM PDT 24
Finished Jul 31 05:37:58 PM PDT 24
Peak memory 206112 kb
Host smart-897c87cf-d429-4548-be4a-c91c70ab1237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442084511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.442084511
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2620709226
Short name T637
Test name
Test status
Simulation time 572525529 ps
CPU time 6.34 seconds
Started Jul 31 05:37:53 PM PDT 24
Finished Jul 31 05:37:59 PM PDT 24
Peak memory 208704 kb
Host smart-20b59a7b-1f94-4b2f-9afe-4637a52953b3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620709226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2620709226
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3291226056
Short name T626
Test name
Test status
Simulation time 126167515 ps
CPU time 2.59 seconds
Started Jul 31 05:37:56 PM PDT 24
Finished Jul 31 05:37:59 PM PDT 24
Peak memory 208652 kb
Host smart-042484bd-dd2f-4d35-90fe-2830c89df40b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291226056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3291226056
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1206898001
Short name T678
Test name
Test status
Simulation time 89186023 ps
CPU time 2.57 seconds
Started Jul 31 05:37:55 PM PDT 24
Finished Jul 31 05:37:58 PM PDT 24
Peak memory 208912 kb
Host smart-71ac859f-eaf0-41fe-b85a-ac445805aa5a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206898001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1206898001
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1592459929
Short name T201
Test name
Test status
Simulation time 787106830 ps
CPU time 5.84 seconds
Started Jul 31 05:38:00 PM PDT 24
Finished Jul 31 05:38:06 PM PDT 24
Peak memory 209152 kb
Host smart-9acee567-97ba-4fb8-b92c-e703e583d53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592459929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1592459929
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1963564600
Short name T430
Test name
Test status
Simulation time 530326411 ps
CPU time 13.65 seconds
Started Jul 31 05:37:54 PM PDT 24
Finished Jul 31 05:38:08 PM PDT 24
Peak memory 208108 kb
Host smart-aa3f2d2b-a135-4fe2-a8b0-a8bba2aa1bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963564600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1963564600
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3622663270
Short name T48
Test name
Test status
Simulation time 613338249 ps
CPU time 12.59 seconds
Started Jul 31 05:38:02 PM PDT 24
Finished Jul 31 05:38:15 PM PDT 24
Peak memory 214420 kb
Host smart-dfa5a5b0-146a-4f47-b073-167e228df359
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622663270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3622663270
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.1922258258
Short name T916
Test name
Test status
Simulation time 186176453 ps
CPU time 9.42 seconds
Started Jul 31 05:37:59 PM PDT 24
Finished Jul 31 05:38:09 PM PDT 24
Peak memory 222496 kb
Host smart-fa6563fd-4b70-44ff-9dfd-afe27f9fa2ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922258258 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.1922258258
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1909628676
Short name T200
Test name
Test status
Simulation time 411321970 ps
CPU time 6.17 seconds
Started Jul 31 05:37:58 PM PDT 24
Finished Jul 31 05:38:04 PM PDT 24
Peak memory 207572 kb
Host smart-93d42f48-9803-4ede-ac16-3f561c35a8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909628676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1909628676
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.908137989
Short name T402
Test name
Test status
Simulation time 90103217 ps
CPU time 3.46 seconds
Started Jul 31 05:38:03 PM PDT 24
Finished Jul 31 05:38:07 PM PDT 24
Peak memory 210224 kb
Host smart-26b3bcad-6c31-4304-b9e5-f98e926431aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908137989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.908137989
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.422579438
Short name T843
Test name
Test status
Simulation time 49739225 ps
CPU time 0.86 seconds
Started Jul 31 05:37:58 PM PDT 24
Finished Jul 31 05:37:59 PM PDT 24
Peak memory 205956 kb
Host smart-f4fce5d1-9785-4e4e-9805-a6b918ca8472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422579438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.422579438
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.4213284348
Short name T268
Test name
Test status
Simulation time 443722639 ps
CPU time 23.91 seconds
Started Jul 31 05:37:58 PM PDT 24
Finished Jul 31 05:38:22 PM PDT 24
Peak memory 215924 kb
Host smart-efd41bd3-47eb-4456-87e5-e297cf867fd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4213284348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.4213284348
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.488451157
Short name T219
Test name
Test status
Simulation time 227225403 ps
CPU time 3.3 seconds
Started Jul 31 05:37:59 PM PDT 24
Finished Jul 31 05:38:02 PM PDT 24
Peak memory 214548 kb
Host smart-8de4634b-f601-432e-b322-1c9c7bf31d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488451157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.488451157
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.414098269
Short name T348
Test name
Test status
Simulation time 369454085 ps
CPU time 4.1 seconds
Started Jul 31 05:37:58 PM PDT 24
Finished Jul 31 05:38:02 PM PDT 24
Peak memory 210232 kb
Host smart-7c29b95a-e4ce-459e-8e89-8a6cdf35da4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414098269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.414098269
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.1061383719
Short name T89
Test name
Test status
Simulation time 828419844 ps
CPU time 6.25 seconds
Started Jul 31 05:37:59 PM PDT 24
Finished Jul 31 05:38:05 PM PDT 24
Peak memory 221980 kb
Host smart-1b71fc8d-fcc1-4b03-bd87-56e3b2b749e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061383719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.1061383719
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3158471745
Short name T790
Test name
Test status
Simulation time 175444896 ps
CPU time 3 seconds
Started Jul 31 05:38:00 PM PDT 24
Finished Jul 31 05:38:03 PM PDT 24
Peak memory 214336 kb
Host smart-ea6b2a15-0ad6-4360-a611-127d934a6ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158471745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3158471745
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.4196677226
Short name T512
Test name
Test status
Simulation time 620127414 ps
CPU time 7.75 seconds
Started Jul 31 05:38:00 PM PDT 24
Finished Jul 31 05:38:08 PM PDT 24
Peak memory 208644 kb
Host smart-fc85020a-ea0f-4513-835d-4816b009e606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196677226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.4196677226
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2165332437
Short name T781
Test name
Test status
Simulation time 122280495 ps
CPU time 2.07 seconds
Started Jul 31 05:38:00 PM PDT 24
Finished Jul 31 05:38:02 PM PDT 24
Peak memory 208744 kb
Host smart-1117483b-87dc-435b-bde9-fae1fe9c91ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165332437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2165332437
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1856397526
Short name T550
Test name
Test status
Simulation time 181929311 ps
CPU time 2.62 seconds
Started Jul 31 05:38:01 PM PDT 24
Finished Jul 31 05:38:04 PM PDT 24
Peak memory 208476 kb
Host smart-8c541ae0-f5e8-42f7-bd64-eff0d0205946
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856397526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1856397526
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.223517385
Short name T270
Test name
Test status
Simulation time 190636390 ps
CPU time 2.78 seconds
Started Jul 31 05:38:01 PM PDT 24
Finished Jul 31 05:38:04 PM PDT 24
Peak memory 208320 kb
Host smart-a9667508-fe3c-440e-9924-c96b637cd820
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223517385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.223517385
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.2090052234
Short name T131
Test name
Test status
Simulation time 25718854 ps
CPU time 2.06 seconds
Started Jul 31 05:38:01 PM PDT 24
Finished Jul 31 05:38:04 PM PDT 24
Peak memory 208260 kb
Host smart-839eb724-c940-4bdc-9040-bd11163dc405
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090052234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2090052234
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1673842065
Short name T366
Test name
Test status
Simulation time 100644762 ps
CPU time 3.06 seconds
Started Jul 31 05:37:59 PM PDT 24
Finished Jul 31 05:38:03 PM PDT 24
Peak memory 209660 kb
Host smart-3eb66706-f172-432d-b9b9-0c0580606d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673842065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1673842065
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2538904441
Short name T485
Test name
Test status
Simulation time 79284711 ps
CPU time 1.66 seconds
Started Jul 31 05:38:04 PM PDT 24
Finished Jul 31 05:38:05 PM PDT 24
Peak memory 206920 kb
Host smart-883bc1e0-9e93-4539-8e92-d042c49bd1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538904441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2538904441
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2934487469
Short name T568
Test name
Test status
Simulation time 787539813 ps
CPU time 9.2 seconds
Started Jul 31 05:37:59 PM PDT 24
Finished Jul 31 05:38:08 PM PDT 24
Peak memory 215216 kb
Host smart-068cbaf7-8920-4e85-a15f-0e6244a80509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934487469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2934487469
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.2829486977
Short name T176
Test name
Test status
Simulation time 1063731768 ps
CPU time 11.66 seconds
Started Jul 31 05:37:59 PM PDT 24
Finished Jul 31 05:38:11 PM PDT 24
Peak memory 222472 kb
Host smart-a91a4f15-5021-4f1a-9fa0-aabff77a4a7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829486977 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.2829486977
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1366663817
Short name T748
Test name
Test status
Simulation time 75298336 ps
CPU time 3.67 seconds
Started Jul 31 05:38:01 PM PDT 24
Finished Jul 31 05:38:05 PM PDT 24
Peak memory 214308 kb
Host smart-a9c26586-db14-4ede-b025-08cc058cf6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366663817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1366663817
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.518269845
Short name T194
Test name
Test status
Simulation time 322636484 ps
CPU time 2.75 seconds
Started Jul 31 05:37:59 PM PDT 24
Finished Jul 31 05:38:02 PM PDT 24
Peak memory 209956 kb
Host smart-ae1f48a3-6955-4138-939d-9b12a45a41e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518269845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.518269845
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.3958368980
Short name T486
Test name
Test status
Simulation time 14948319 ps
CPU time 0.75 seconds
Started Jul 31 05:36:20 PM PDT 24
Finished Jul 31 05:36:21 PM PDT 24
Peak memory 205944 kb
Host smart-c2288198-7e1c-4a74-a31a-135c60edef9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958368980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3958368980
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2810483428
Short name T315
Test name
Test status
Simulation time 35885909 ps
CPU time 2.87 seconds
Started Jul 31 05:36:18 PM PDT 24
Finished Jul 31 05:36:21 PM PDT 24
Peak memory 214408 kb
Host smart-aa9a4ff8-efb7-43b9-ad3c-246b4929b9cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2810483428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2810483428
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2923789322
Short name T261
Test name
Test status
Simulation time 211571519 ps
CPU time 2.73 seconds
Started Jul 31 05:36:19 PM PDT 24
Finished Jul 31 05:36:22 PM PDT 24
Peak memory 218452 kb
Host smart-670f9536-155a-448a-9d74-26b91d692944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923789322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2923789322
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2442602936
Short name T331
Test name
Test status
Simulation time 85539256 ps
CPU time 2.03 seconds
Started Jul 31 05:36:18 PM PDT 24
Finished Jul 31 05:36:20 PM PDT 24
Peak memory 214232 kb
Host smart-be08be23-58b3-4c90-aeeb-b0d6d3ad8190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442602936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2442602936
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3347926520
Short name T785
Test name
Test status
Simulation time 127300918 ps
CPU time 5.55 seconds
Started Jul 31 05:36:22 PM PDT 24
Finished Jul 31 05:36:28 PM PDT 24
Peak memory 222392 kb
Host smart-f3eba0a3-e506-4c2e-adde-3716d3b47f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347926520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3347926520
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.203874598
Short name T221
Test name
Test status
Simulation time 251435002 ps
CPU time 3.1 seconds
Started Jul 31 05:36:20 PM PDT 24
Finished Jul 31 05:36:23 PM PDT 24
Peak memory 219168 kb
Host smart-f6bb6202-3000-413e-ab91-b768f2cd2468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203874598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.203874598
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.781720544
Short name T591
Test name
Test status
Simulation time 1105219458 ps
CPU time 7.88 seconds
Started Jul 31 05:36:25 PM PDT 24
Finished Jul 31 05:36:33 PM PDT 24
Peak memory 207988 kb
Host smart-02f2c011-43fc-47f9-aa60-c323fa742eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781720544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.781720544
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.932483915
Short name T107
Test name
Test status
Simulation time 235707813 ps
CPU time 5.95 seconds
Started Jul 31 05:36:20 PM PDT 24
Finished Jul 31 05:36:27 PM PDT 24
Peak memory 229360 kb
Host smart-1a03c6da-de88-492c-915b-b7ece17bbdae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932483915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.932483915
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.2836713582
Short name T535
Test name
Test status
Simulation time 152775238 ps
CPU time 2.3 seconds
Started Jul 31 05:36:14 PM PDT 24
Finished Jul 31 05:36:16 PM PDT 24
Peak memory 206884 kb
Host smart-4f04206f-1a26-48d3-b786-7bd3e2d24e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836713582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.2836713582
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.440116477
Short name T436
Test name
Test status
Simulation time 53433142 ps
CPU time 2.49 seconds
Started Jul 31 05:36:18 PM PDT 24
Finished Jul 31 05:36:21 PM PDT 24
Peak memory 207992 kb
Host smart-70a7ca40-7130-41aa-9c83-65333b05e4de
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440116477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.440116477
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1717319477
Short name T529
Test name
Test status
Simulation time 41238098 ps
CPU time 1.87 seconds
Started Jul 31 05:36:16 PM PDT 24
Finished Jul 31 05:36:18 PM PDT 24
Peak memory 206964 kb
Host smart-1bb16ea3-b6e6-4121-9043-664298503147
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717319477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1717319477
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1796426634
Short name T914
Test name
Test status
Simulation time 54149420 ps
CPU time 2.79 seconds
Started Jul 31 05:36:15 PM PDT 24
Finished Jul 31 05:36:18 PM PDT 24
Peak memory 208700 kb
Host smart-11878f4e-ac3e-4fa8-90fd-55798131fa64
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796426634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1796426634
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.4137167073
Short name T517
Test name
Test status
Simulation time 135906223 ps
CPU time 2.02 seconds
Started Jul 31 05:36:21 PM PDT 24
Finished Jul 31 05:36:23 PM PDT 24
Peak memory 208276 kb
Host smart-83413375-ceed-4849-b8b9-cd83e3aa24a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137167073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.4137167073
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2933934223
Short name T619
Test name
Test status
Simulation time 118516078 ps
CPU time 2.5 seconds
Started Jul 31 05:36:18 PM PDT 24
Finished Jul 31 05:36:20 PM PDT 24
Peak memory 206824 kb
Host smart-c5ea4c1b-c410-40b0-8742-1275f34f9e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933934223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2933934223
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1212130863
Short name T224
Test name
Test status
Simulation time 244939248 ps
CPU time 12.7 seconds
Started Jul 31 05:36:19 PM PDT 24
Finished Jul 31 05:36:31 PM PDT 24
Peak memory 215940 kb
Host smart-8b5d42e1-ac6d-48be-a0d4-3ccb3a547391
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212130863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1212130863
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.3335280142
Short name T183
Test name
Test status
Simulation time 213194650 ps
CPU time 5.95 seconds
Started Jul 31 05:36:19 PM PDT 24
Finished Jul 31 05:36:25 PM PDT 24
Peak memory 222424 kb
Host smart-b8ae0943-0891-414f-88ba-a19a989c9a42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335280142 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.3335280142
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2539181509
Short name T493
Test name
Test status
Simulation time 400938048 ps
CPU time 6.68 seconds
Started Jul 31 05:36:20 PM PDT 24
Finished Jul 31 05:36:27 PM PDT 24
Peak memory 209076 kb
Host smart-816d1285-4535-4ed8-831c-95967f7100ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539181509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2539181509
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1719484954
Short name T880
Test name
Test status
Simulation time 76285319 ps
CPU time 2.78 seconds
Started Jul 31 05:36:19 PM PDT 24
Finished Jul 31 05:36:22 PM PDT 24
Peak memory 210064 kb
Host smart-4771837d-b06f-4596-8837-b6f1ed3ff574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719484954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1719484954
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2624684938
Short name T450
Test name
Test status
Simulation time 20564856 ps
CPU time 0.74 seconds
Started Jul 31 05:38:05 PM PDT 24
Finished Jul 31 05:38:06 PM PDT 24
Peak memory 205964 kb
Host smart-8a8d5a1d-541c-4ebd-8410-b5d2f9972bf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624684938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2624684938
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.3308696420
Short name T271
Test name
Test status
Simulation time 358767845 ps
CPU time 4.21 seconds
Started Jul 31 05:38:01 PM PDT 24
Finished Jul 31 05:38:06 PM PDT 24
Peak memory 214976 kb
Host smart-02792a05-c55e-4fcf-9409-2632ee11f1c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3308696420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3308696420
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2540994863
Short name T848
Test name
Test status
Simulation time 65498373 ps
CPU time 1.88 seconds
Started Jul 31 05:38:03 PM PDT 24
Finished Jul 31 05:38:05 PM PDT 24
Peak memory 219132 kb
Host smart-72c18af7-f04f-4222-8b6c-20a46b0be8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540994863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2540994863
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.660212599
Short name T326
Test name
Test status
Simulation time 84944318 ps
CPU time 3.22 seconds
Started Jul 31 05:38:02 PM PDT 24
Finished Jul 31 05:38:06 PM PDT 24
Peak memory 214300 kb
Host smart-f96491ac-f171-4ac7-a4dc-664b207930c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660212599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.660212599
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1550977237
Short name T246
Test name
Test status
Simulation time 24901421 ps
CPU time 2.12 seconds
Started Jul 31 05:38:03 PM PDT 24
Finished Jul 31 05:38:05 PM PDT 24
Peak memory 214320 kb
Host smart-e0b1079e-2366-4050-ba2f-7c23aaec4a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550977237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1550977237
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3087381713
Short name T632
Test name
Test status
Simulation time 66975306 ps
CPU time 2.26 seconds
Started Jul 31 05:38:02 PM PDT 24
Finished Jul 31 05:38:05 PM PDT 24
Peak memory 214972 kb
Host smart-9ab46d11-2831-40bc-9b36-48bf4bd9b833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087381713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3087381713
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2673047052
Short name T58
Test name
Test status
Simulation time 88993841 ps
CPU time 2.61 seconds
Started Jul 31 05:38:07 PM PDT 24
Finished Jul 31 05:38:10 PM PDT 24
Peak memory 216696 kb
Host smart-07f60bef-206d-41c3-a6ed-a67acdf9b5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673047052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2673047052
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1522107858
Short name T810
Test name
Test status
Simulation time 86405749 ps
CPU time 4.24 seconds
Started Jul 31 05:37:57 PM PDT 24
Finished Jul 31 05:38:01 PM PDT 24
Peak memory 214300 kb
Host smart-1308cb3e-28b3-41e0-aebb-43805e27556a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522107858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1522107858
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2934619522
Short name T311
Test name
Test status
Simulation time 79495183 ps
CPU time 2.99 seconds
Started Jul 31 05:38:04 PM PDT 24
Finished Jul 31 05:38:07 PM PDT 24
Peak memory 207912 kb
Host smart-55c5b476-dd97-4d4e-b74d-7a4f5e9ae5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934619522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2934619522
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3672647613
Short name T809
Test name
Test status
Simulation time 525923954 ps
CPU time 6.77 seconds
Started Jul 31 05:37:58 PM PDT 24
Finished Jul 31 05:38:05 PM PDT 24
Peak memory 208204 kb
Host smart-00136999-9682-41e6-a7fc-6f7cec0cb990
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672647613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3672647613
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1617411503
Short name T207
Test name
Test status
Simulation time 2173212096 ps
CPU time 9.3 seconds
Started Jul 31 05:38:00 PM PDT 24
Finished Jul 31 05:38:10 PM PDT 24
Peak memory 208380 kb
Host smart-71bc3dd4-4710-4cc4-9025-44f6ebf664b7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617411503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1617411503
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1027696324
Short name T313
Test name
Test status
Simulation time 40508778 ps
CPU time 2.68 seconds
Started Jul 31 05:38:02 PM PDT 24
Finished Jul 31 05:38:05 PM PDT 24
Peak memory 208676 kb
Host smart-e84c8544-5aef-4063-af16-8ad4298e821e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027696324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1027696324
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3595635230
Short name T879
Test name
Test status
Simulation time 173537110 ps
CPU time 2.07 seconds
Started Jul 31 05:38:05 PM PDT 24
Finished Jul 31 05:38:07 PM PDT 24
Peak memory 206976 kb
Host smart-b278d68e-33a8-458c-af8a-301acfcd19ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595635230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3595635230
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.811288852
Short name T889
Test name
Test status
Simulation time 79331381 ps
CPU time 2.16 seconds
Started Jul 31 05:38:02 PM PDT 24
Finished Jul 31 05:38:05 PM PDT 24
Peak memory 206740 kb
Host smart-58272a1d-18be-4d3b-b273-81aa0717f9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811288852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.811288852
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.993660739
Short name T307
Test name
Test status
Simulation time 1466858771 ps
CPU time 30.01 seconds
Started Jul 31 05:38:06 PM PDT 24
Finished Jul 31 05:38:36 PM PDT 24
Peak memory 222520 kb
Host smart-95373f37-08e0-43c9-ba62-97f4f97f03a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993660739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.993660739
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1344498120
Short name T332
Test name
Test status
Simulation time 362903456 ps
CPU time 4.09 seconds
Started Jul 31 05:38:03 PM PDT 24
Finished Jul 31 05:38:08 PM PDT 24
Peak memory 210136 kb
Host smart-7b7d677a-e0d6-4625-be6c-702f49202421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344498120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1344498120
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1361278044
Short name T791
Test name
Test status
Simulation time 414632141 ps
CPU time 2.78 seconds
Started Jul 31 05:38:05 PM PDT 24
Finished Jul 31 05:38:08 PM PDT 24
Peak memory 210392 kb
Host smart-43dc0fcf-007b-4de4-80d7-0254d77265bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361278044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1361278044
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3612408675
Short name T496
Test name
Test status
Simulation time 44777606 ps
CPU time 0.79 seconds
Started Jul 31 05:38:10 PM PDT 24
Finished Jul 31 05:38:11 PM PDT 24
Peak memory 205960 kb
Host smart-35e26eeb-03a6-4411-9a3a-0264c3d40c0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612408675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3612408675
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.608519437
Short name T136
Test name
Test status
Simulation time 184834425 ps
CPU time 7.38 seconds
Started Jul 31 05:38:05 PM PDT 24
Finished Jul 31 05:38:13 PM PDT 24
Peak memory 214648 kb
Host smart-59f63d46-059f-4c9d-ad53-c464978d88a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=608519437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.608519437
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2377281971
Short name T27
Test name
Test status
Simulation time 184166444 ps
CPU time 7.13 seconds
Started Jul 31 05:38:11 PM PDT 24
Finished Jul 31 05:38:18 PM PDT 24
Peak memory 214532 kb
Host smart-95dc658b-da83-4cf8-8b26-41f1aa59896b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377281971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2377281971
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3428555261
Short name T443
Test name
Test status
Simulation time 21287230 ps
CPU time 1.75 seconds
Started Jul 31 05:38:05 PM PDT 24
Finished Jul 31 05:38:07 PM PDT 24
Peak memory 207416 kb
Host smart-5d350465-a99f-4f03-8a44-3bd2b62a11d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428555261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3428555261
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2605879263
Short name T95
Test name
Test status
Simulation time 145208901 ps
CPU time 5.42 seconds
Started Jul 31 05:38:12 PM PDT 24
Finished Jul 31 05:38:17 PM PDT 24
Peak memory 221424 kb
Host smart-4667a108-0c5d-4c4e-a4ac-cfdbe0d4a18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605879263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2605879263
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1151303265
Short name T290
Test name
Test status
Simulation time 917036974 ps
CPU time 4.05 seconds
Started Jul 31 05:38:10 PM PDT 24
Finished Jul 31 05:38:14 PM PDT 24
Peak memory 214356 kb
Host smart-7f1780c9-69ec-402a-ba90-51359fb891a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151303265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1151303265
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2560570647
Short name T561
Test name
Test status
Simulation time 96237910 ps
CPU time 1.46 seconds
Started Jul 31 05:38:05 PM PDT 24
Finished Jul 31 05:38:06 PM PDT 24
Peak memory 207032 kb
Host smart-7c1066bc-103e-450c-9043-2da73d3ab7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560570647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2560570647
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3249131222
Short name T685
Test name
Test status
Simulation time 124629811 ps
CPU time 4.71 seconds
Started Jul 31 05:38:06 PM PDT 24
Finished Jul 31 05:38:11 PM PDT 24
Peak memory 209472 kb
Host smart-b84b051d-e5c5-446b-bee7-dceca4c54fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249131222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3249131222
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.615428101
Short name T585
Test name
Test status
Simulation time 78899964 ps
CPU time 3 seconds
Started Jul 31 05:38:05 PM PDT 24
Finished Jul 31 05:38:09 PM PDT 24
Peak memory 207136 kb
Host smart-fda59d0b-6cd0-4a18-8f8e-9d4e103e8975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615428101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.615428101
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.4093353798
Short name T274
Test name
Test status
Simulation time 122874318 ps
CPU time 2.37 seconds
Started Jul 31 05:38:02 PM PDT 24
Finished Jul 31 05:38:05 PM PDT 24
Peak memory 207484 kb
Host smart-d9c85487-6d12-4dce-8b0d-725c99dc2e50
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093353798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.4093353798
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3250632140
Short name T612
Test name
Test status
Simulation time 303682634 ps
CPU time 3.48 seconds
Started Jul 31 05:38:05 PM PDT 24
Finished Jul 31 05:38:09 PM PDT 24
Peak memory 206972 kb
Host smart-f7315624-bfb0-4e2a-87b7-5d20b5bfe4d1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250632140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3250632140
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1111037955
Short name T489
Test name
Test status
Simulation time 99710076 ps
CPU time 3.06 seconds
Started Jul 31 05:38:04 PM PDT 24
Finished Jul 31 05:38:07 PM PDT 24
Peak memory 206976 kb
Host smart-ee110e24-a443-445a-9c3b-dac7b113f564
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111037955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1111037955
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1119774091
Short name T853
Test name
Test status
Simulation time 1014279564 ps
CPU time 6.8 seconds
Started Jul 31 05:38:09 PM PDT 24
Finished Jul 31 05:38:16 PM PDT 24
Peak memory 209040 kb
Host smart-bd5e73d8-dd84-4abb-b5f8-3b7a0528c31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119774091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1119774091
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3225712854
Short name T582
Test name
Test status
Simulation time 66260673 ps
CPU time 2.72 seconds
Started Jul 31 05:38:07 PM PDT 24
Finished Jul 31 05:38:10 PM PDT 24
Peak memory 208372 kb
Host smart-edceb78e-64f5-4d10-a497-14ec623754df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225712854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3225712854
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.2210219836
Short name T723
Test name
Test status
Simulation time 87436691 ps
CPU time 6.43 seconds
Started Jul 31 05:38:11 PM PDT 24
Finished Jul 31 05:38:18 PM PDT 24
Peak memory 220080 kb
Host smart-c4f885c9-068b-4fe1-9ab5-2aa419f4bc21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210219836 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.2210219836
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.3424588097
Short name T312
Test name
Test status
Simulation time 117624614 ps
CPU time 5.29 seconds
Started Jul 31 05:38:04 PM PDT 24
Finished Jul 31 05:38:10 PM PDT 24
Peak memory 208632 kb
Host smart-ed00bcf3-8e04-4dab-b0e8-6d27e2ac932c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424588097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3424588097
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3094697280
Short name T39
Test name
Test status
Simulation time 135637985 ps
CPU time 3.14 seconds
Started Jul 31 05:38:13 PM PDT 24
Finished Jul 31 05:38:16 PM PDT 24
Peak memory 210672 kb
Host smart-30e0cac4-845c-4c7e-8432-287aee515381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094697280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3094697280
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2342408142
Short name T580
Test name
Test status
Simulation time 12331886 ps
CPU time 0.82 seconds
Started Jul 31 05:38:17 PM PDT 24
Finished Jul 31 05:38:18 PM PDT 24
Peak memory 205948 kb
Host smart-12a5827b-515b-4173-b9cb-dbd9a9bfe6a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342408142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2342408142
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3046605056
Short name T269
Test name
Test status
Simulation time 246582689 ps
CPU time 5.22 seconds
Started Jul 31 05:38:08 PM PDT 24
Finished Jul 31 05:38:13 PM PDT 24
Peak memory 215064 kb
Host smart-8bdbef60-d50f-4308-b841-032fd37bb55e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3046605056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3046605056
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.337753044
Short name T30
Test name
Test status
Simulation time 71734985 ps
CPU time 2.88 seconds
Started Jul 31 05:38:10 PM PDT 24
Finished Jul 31 05:38:13 PM PDT 24
Peak memory 217652 kb
Host smart-c598c75f-707d-412a-b19f-e8ffe6917d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337753044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.337753044
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2387185053
Short name T77
Test name
Test status
Simulation time 90939072 ps
CPU time 1.84 seconds
Started Jul 31 05:38:10 PM PDT 24
Finished Jul 31 05:38:11 PM PDT 24
Peak memory 218424 kb
Host smart-8acc50a5-5bb4-4516-92c6-922216fbbf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387185053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2387185053
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.2603103704
Short name T23
Test name
Test status
Simulation time 191898809 ps
CPU time 6.21 seconds
Started Jul 31 05:38:11 PM PDT 24
Finished Jul 31 05:38:17 PM PDT 24
Peak memory 214288 kb
Host smart-3fbb3260-7599-47e3-89a2-335bd314f3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603103704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2603103704
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2647970765
Short name T358
Test name
Test status
Simulation time 107037501 ps
CPU time 4.03 seconds
Started Jul 31 05:38:11 PM PDT 24
Finished Jul 31 05:38:16 PM PDT 24
Peak memory 214228 kb
Host smart-019d6b3a-76e5-4b20-a611-f4241a5d57bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647970765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2647970765
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1021300508
Short name T451
Test name
Test status
Simulation time 147709400 ps
CPU time 3 seconds
Started Jul 31 05:38:09 PM PDT 24
Finished Jul 31 05:38:13 PM PDT 24
Peak memory 219844 kb
Host smart-db4d5916-b83d-46e5-a797-03f74f41a208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021300508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1021300508
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3653328349
Short name T393
Test name
Test status
Simulation time 105420873 ps
CPU time 4.56 seconds
Started Jul 31 05:38:09 PM PDT 24
Finished Jul 31 05:38:14 PM PDT 24
Peak memory 207496 kb
Host smart-e28000c7-8b85-449c-8faa-56e9b0212899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653328349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3653328349
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1632374117
Short name T439
Test name
Test status
Simulation time 181430771 ps
CPU time 5.26 seconds
Started Jul 31 05:38:16 PM PDT 24
Finished Jul 31 05:38:21 PM PDT 24
Peak memory 207864 kb
Host smart-252ca9af-e9a9-4b74-bf5a-6d0194806bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632374117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1632374117
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3641504899
Short name T191
Test name
Test status
Simulation time 103694466 ps
CPU time 3.83 seconds
Started Jul 31 05:38:12 PM PDT 24
Finished Jul 31 05:38:16 PM PDT 24
Peak memory 207000 kb
Host smart-6bf77bf1-3fad-4021-9fa8-28c6832691b8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641504899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3641504899
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.266705691
Short name T189
Test name
Test status
Simulation time 76711510 ps
CPU time 3.69 seconds
Started Jul 31 05:38:12 PM PDT 24
Finished Jul 31 05:38:16 PM PDT 24
Peak memory 208716 kb
Host smart-d4b7f6b0-4daf-421c-90c3-fff21c46b79e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266705691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.266705691
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2697533116
Short name T511
Test name
Test status
Simulation time 170917253 ps
CPU time 2.74 seconds
Started Jul 31 05:38:10 PM PDT 24
Finished Jul 31 05:38:13 PM PDT 24
Peak memory 207480 kb
Host smart-720f24ed-07dd-4a0d-944b-9d9c54a3bd22
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697533116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2697533116
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2900952063
Short name T408
Test name
Test status
Simulation time 282804634 ps
CPU time 2.49 seconds
Started Jul 31 05:38:08 PM PDT 24
Finished Jul 31 05:38:11 PM PDT 24
Peak memory 215904 kb
Host smart-5f3b5ebe-ecb4-46c6-98f5-f25c743336bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900952063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2900952063
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.91320618
Short name T816
Test name
Test status
Simulation time 133947959 ps
CPU time 2.89 seconds
Started Jul 31 05:38:09 PM PDT 24
Finished Jul 31 05:38:12 PM PDT 24
Peak memory 208168 kb
Host smart-b3e75a5b-902f-4f10-8dc5-6734397da84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91320618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.91320618
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2996106765
Short name T860
Test name
Test status
Simulation time 5350159626 ps
CPU time 31.96 seconds
Started Jul 31 05:38:10 PM PDT 24
Finished Jul 31 05:38:42 PM PDT 24
Peak memory 220120 kb
Host smart-6ede0635-b3f0-4828-bc4f-524c6911175f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996106765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2996106765
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.352391568
Short name T342
Test name
Test status
Simulation time 947761375 ps
CPU time 7.45 seconds
Started Jul 31 05:38:12 PM PDT 24
Finished Jul 31 05:38:19 PM PDT 24
Peak memory 210240 kb
Host smart-d59eda80-234a-4988-ae5a-fba732eb4a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352391568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.352391568
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2389341368
Short name T195
Test name
Test status
Simulation time 94282353 ps
CPU time 2.32 seconds
Started Jul 31 05:38:10 PM PDT 24
Finished Jul 31 05:38:12 PM PDT 24
Peak memory 210208 kb
Host smart-d7e208f4-3be8-4d20-aa1f-c51af7b033f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389341368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2389341368
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1071849416
Short name T127
Test name
Test status
Simulation time 13236957 ps
CPU time 0.88 seconds
Started Jul 31 05:38:14 PM PDT 24
Finished Jul 31 05:38:15 PM PDT 24
Peak memory 205912 kb
Host smart-99508591-adf4-4d71-a7a8-97786d566c03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071849416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1071849416
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3453501508
Short name T34
Test name
Test status
Simulation time 220118148 ps
CPU time 4.59 seconds
Started Jul 31 05:38:17 PM PDT 24
Finished Jul 31 05:38:22 PM PDT 24
Peak memory 221836 kb
Host smart-64be235a-e00d-490d-b941-60a91af7886c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453501508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3453501508
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1926466365
Short name T460
Test name
Test status
Simulation time 74645270 ps
CPU time 3.28 seconds
Started Jul 31 05:38:15 PM PDT 24
Finished Jul 31 05:38:18 PM PDT 24
Peak memory 207924 kb
Host smart-5999b4b6-deb3-41ac-9345-98adc0122be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926466365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1926466365
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.722947052
Short name T99
Test name
Test status
Simulation time 907013094 ps
CPU time 5.81 seconds
Started Jul 31 05:38:17 PM PDT 24
Finished Jul 31 05:38:23 PM PDT 24
Peak memory 222400 kb
Host smart-05e7080b-9399-4e30-ad8d-82e848ea43df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722947052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.722947052
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.777253800
Short name T328
Test name
Test status
Simulation time 88911282 ps
CPU time 4.48 seconds
Started Jul 31 05:38:16 PM PDT 24
Finished Jul 31 05:38:21 PM PDT 24
Peak memory 220872 kb
Host smart-f48998de-1c78-49d2-a1bf-a780db5995d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777253800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.777253800
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2873131470
Short name T808
Test name
Test status
Simulation time 1093153559 ps
CPU time 7.31 seconds
Started Jul 31 05:38:16 PM PDT 24
Finished Jul 31 05:38:24 PM PDT 24
Peak memory 220208 kb
Host smart-2046532a-2126-471b-9272-b71a400de863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873131470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2873131470
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1191063843
Short name T610
Test name
Test status
Simulation time 164540186 ps
CPU time 3.36 seconds
Started Jul 31 05:38:18 PM PDT 24
Finished Jul 31 05:38:21 PM PDT 24
Peak memory 218304 kb
Host smart-4bbf400a-aeea-4153-9653-a30384023ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191063843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1191063843
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.74908498
Short name T618
Test name
Test status
Simulation time 76493674 ps
CPU time 2.92 seconds
Started Jul 31 05:38:16 PM PDT 24
Finished Jul 31 05:38:19 PM PDT 24
Peak memory 206752 kb
Host smart-b4d43e4b-5bb5-4e83-8bf1-b3f9d8107b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74908498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.74908498
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.4132307737
Short name T488
Test name
Test status
Simulation time 293070191 ps
CPU time 3.17 seconds
Started Jul 31 05:38:14 PM PDT 24
Finished Jul 31 05:38:17 PM PDT 24
Peak memory 206948 kb
Host smart-8e8f7e50-4395-42fe-aadc-504e5c54cf49
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132307737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.4132307737
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2952048825
Short name T333
Test name
Test status
Simulation time 1629683654 ps
CPU time 40.11 seconds
Started Jul 31 05:38:19 PM PDT 24
Finished Jul 31 05:38:59 PM PDT 24
Peak memory 209040 kb
Host smart-070fde67-d5e6-4f11-af76-37dba04de388
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952048825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2952048825
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3508104224
Short name T410
Test name
Test status
Simulation time 1837610376 ps
CPU time 31.46 seconds
Started Jul 31 05:38:16 PM PDT 24
Finished Jul 31 05:38:47 PM PDT 24
Peak memory 208240 kb
Host smart-62344082-2db1-4cbc-9111-1f33982c2478
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508104224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3508104224
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1968371011
Short name T413
Test name
Test status
Simulation time 55567757 ps
CPU time 2.5 seconds
Started Jul 31 05:38:20 PM PDT 24
Finished Jul 31 05:38:22 PM PDT 24
Peak memory 207188 kb
Host smart-63f88436-5e38-408b-8a45-b969d6d9446e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968371011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1968371011
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3975876761
Short name T543
Test name
Test status
Simulation time 924968020 ps
CPU time 4.44 seconds
Started Jul 31 05:38:15 PM PDT 24
Finished Jul 31 05:38:20 PM PDT 24
Peak memory 208884 kb
Host smart-243879f6-89b1-4dc6-9fc3-af8367c9494e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975876761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3975876761
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.760670413
Short name T47
Test name
Test status
Simulation time 3137414858 ps
CPU time 35.09 seconds
Started Jul 31 05:38:15 PM PDT 24
Finished Jul 31 05:38:50 PM PDT 24
Peak memory 216728 kb
Host smart-30c79c56-6ab5-42c5-a1ab-6979de6516b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760670413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.760670413
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1071762701
Short name T343
Test name
Test status
Simulation time 723538422 ps
CPU time 30.4 seconds
Started Jul 31 05:38:18 PM PDT 24
Finished Jul 31 05:38:49 PM PDT 24
Peak memory 221580 kb
Host smart-4fdaee21-2736-461a-8265-72e9ea08210c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071762701 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1071762701
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3824454551
Short name T260
Test name
Test status
Simulation time 3016959124 ps
CPU time 5.71 seconds
Started Jul 31 05:38:15 PM PDT 24
Finished Jul 31 05:38:21 PM PDT 24
Peak memory 207960 kb
Host smart-512fe4d4-7104-4475-830c-9e94a2614794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824454551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3824454551
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3329285399
Short name T122
Test name
Test status
Simulation time 696762034 ps
CPU time 2.48 seconds
Started Jul 31 05:38:17 PM PDT 24
Finished Jul 31 05:38:19 PM PDT 24
Peak memory 210180 kb
Host smart-4e2cb174-71fb-4a18-9226-3e8ce6c1e259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329285399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3329285399
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.675534557
Short name T434
Test name
Test status
Simulation time 13989817 ps
CPU time 0.83 seconds
Started Jul 31 05:38:21 PM PDT 24
Finished Jul 31 05:38:22 PM PDT 24
Peak memory 205924 kb
Host smart-7c7742da-dc87-450b-a062-365e694d628c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675534557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.675534557
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3604190927
Short name T273
Test name
Test status
Simulation time 167711745 ps
CPU time 5.54 seconds
Started Jul 31 05:38:19 PM PDT 24
Finished Jul 31 05:38:25 PM PDT 24
Peak memory 215384 kb
Host smart-d4c8b401-d615-4729-82d2-e24cfa527e43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3604190927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3604190927
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2522154918
Short name T71
Test name
Test status
Simulation time 1326797280 ps
CPU time 2.74 seconds
Started Jul 31 05:38:17 PM PDT 24
Finished Jul 31 05:38:20 PM PDT 24
Peak memory 222596 kb
Host smart-a0f9922f-7211-4ef3-86bc-cdac5512ae3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522154918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2522154918
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1576047172
Short name T56
Test name
Test status
Simulation time 74654876 ps
CPU time 1.71 seconds
Started Jul 31 05:38:15 PM PDT 24
Finished Jul 31 05:38:17 PM PDT 24
Peak memory 207612 kb
Host smart-2502b6db-baab-4f71-bb09-0a1020d0e422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576047172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1576047172
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3773447031
Short name T98
Test name
Test status
Simulation time 872091703 ps
CPU time 20.9 seconds
Started Jul 31 05:38:19 PM PDT 24
Finished Jul 31 05:38:41 PM PDT 24
Peak memory 214340 kb
Host smart-33c9c3c3-baea-4156-bccf-7e6eb326b676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773447031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3773447031
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2495340425
Short name T890
Test name
Test status
Simulation time 92467392 ps
CPU time 2.57 seconds
Started Jul 31 05:38:15 PM PDT 24
Finished Jul 31 05:38:18 PM PDT 24
Peak memory 220736 kb
Host smart-b37bd323-cffd-48e3-ab51-d63722c1fa1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495340425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2495340425
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2964054995
Short name T852
Test name
Test status
Simulation time 419259744 ps
CPU time 2.95 seconds
Started Jul 31 05:38:17 PM PDT 24
Finished Jul 31 05:38:20 PM PDT 24
Peak memory 219932 kb
Host smart-344edb5f-8d31-485b-a0f7-6e5f94abe0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964054995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2964054995
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.3785169754
Short name T737
Test name
Test status
Simulation time 4912943441 ps
CPU time 24.88 seconds
Started Jul 31 05:38:14 PM PDT 24
Finished Jul 31 05:38:39 PM PDT 24
Peak memory 214364 kb
Host smart-270abd2a-c4f9-4c1b-9e06-e82ac62f1939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785169754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3785169754
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.1867546330
Short name T743
Test name
Test status
Simulation time 190860079 ps
CPU time 2.84 seconds
Started Jul 31 05:38:16 PM PDT 24
Finished Jul 31 05:38:19 PM PDT 24
Peak memory 206892 kb
Host smart-fdadb595-e747-4191-8947-474bc074eede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867546330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.1867546330
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1812930395
Short name T555
Test name
Test status
Simulation time 3907094661 ps
CPU time 5.75 seconds
Started Jul 31 05:38:18 PM PDT 24
Finished Jul 31 05:38:24 PM PDT 24
Peak memory 207908 kb
Host smart-30bee990-9105-426c-b958-aebcc6ca887f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812930395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1812930395
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3439283527
Short name T282
Test name
Test status
Simulation time 163249276 ps
CPU time 2.47 seconds
Started Jul 31 05:38:18 PM PDT 24
Finished Jul 31 05:38:20 PM PDT 24
Peak memory 207000 kb
Host smart-fe5362ae-029a-4de9-a440-665ec5d19303
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439283527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3439283527
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2043213089
Short name T662
Test name
Test status
Simulation time 48531566 ps
CPU time 2.7 seconds
Started Jul 31 05:38:18 PM PDT 24
Finished Jul 31 05:38:21 PM PDT 24
Peak memory 207028 kb
Host smart-ee541b71-59aa-4f8f-aa8b-5e06c884c6ae
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043213089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2043213089
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.2132100708
Short name T854
Test name
Test status
Simulation time 326753051 ps
CPU time 2.68 seconds
Started Jul 31 05:38:15 PM PDT 24
Finished Jul 31 05:38:18 PM PDT 24
Peak memory 207224 kb
Host smart-f581ff2a-aaa9-43af-9fac-16e7e436000c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132100708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2132100708
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.3810827450
Short name T579
Test name
Test status
Simulation time 475227205 ps
CPU time 3.06 seconds
Started Jul 31 05:38:14 PM PDT 24
Finished Jul 31 05:38:17 PM PDT 24
Peak memory 208296 kb
Host smart-a59c6d46-a493-4469-a80b-6790f8e29194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810827450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3810827450
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.330969381
Short name T669
Test name
Test status
Simulation time 155483300 ps
CPU time 4.63 seconds
Started Jul 31 05:38:21 PM PDT 24
Finished Jul 31 05:38:26 PM PDT 24
Peak memory 210404 kb
Host smart-c1740ed5-11b7-4499-837e-9f7a0cb93836
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330969381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.330969381
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.4017809250
Short name T374
Test name
Test status
Simulation time 215064240 ps
CPU time 6.19 seconds
Started Jul 31 05:38:17 PM PDT 24
Finished Jul 31 05:38:24 PM PDT 24
Peak memory 218464 kb
Host smart-9471fbe5-a7db-449f-81ee-797c250c0a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017809250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.4017809250
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1603155542
Short name T447
Test name
Test status
Simulation time 103058432 ps
CPU time 3.51 seconds
Started Jul 31 05:38:22 PM PDT 24
Finished Jul 31 05:38:25 PM PDT 24
Peak memory 210352 kb
Host smart-2766fa5d-608e-46bc-8a7f-650f0a0a50e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603155542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1603155542
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1272491614
Short name T539
Test name
Test status
Simulation time 31625350 ps
CPU time 0.83 seconds
Started Jul 31 05:38:23 PM PDT 24
Finished Jul 31 05:38:24 PM PDT 24
Peak memory 205920 kb
Host smart-23e7cbee-15aa-4130-8217-19d2343cae99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272491614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1272491614
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3101870598
Short name T421
Test name
Test status
Simulation time 651753127 ps
CPU time 9.32 seconds
Started Jul 31 05:38:22 PM PDT 24
Finished Jul 31 05:38:31 PM PDT 24
Peak memory 216032 kb
Host smart-e3edf7be-2109-4051-bc6d-3f6162a0e7e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3101870598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3101870598
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.2355225434
Short name T552
Test name
Test status
Simulation time 81805373 ps
CPU time 2.02 seconds
Started Jul 31 05:38:20 PM PDT 24
Finished Jul 31 05:38:22 PM PDT 24
Peak memory 206088 kb
Host smart-8da7ec3c-126e-4869-88d9-cf88c74482dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355225434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2355225434
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.978715893
Short name T79
Test name
Test status
Simulation time 355394763 ps
CPU time 3.47 seconds
Started Jul 31 05:38:21 PM PDT 24
Finished Jul 31 05:38:24 PM PDT 24
Peak memory 209844 kb
Host smart-e43b8cee-7be2-4302-b630-837bc58e8b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978715893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.978715893
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.2194547967
Short name T102
Test name
Test status
Simulation time 3691906184 ps
CPU time 10.91 seconds
Started Jul 31 05:38:21 PM PDT 24
Finished Jul 31 05:38:32 PM PDT 24
Peak memory 214356 kb
Host smart-a88649f3-3092-40bf-b287-b1d846d1b535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194547967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.2194547967
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2675237919
Short name T815
Test name
Test status
Simulation time 1095702020 ps
CPU time 3.38 seconds
Started Jul 31 05:38:22 PM PDT 24
Finished Jul 31 05:38:26 PM PDT 24
Peak memory 214256 kb
Host smart-14d4eeef-028e-49f5-aede-5cbf5aa283b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675237919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2675237919
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_random.2189122900
Short name T596
Test name
Test status
Simulation time 620558457 ps
CPU time 6.81 seconds
Started Jul 31 05:38:23 PM PDT 24
Finished Jul 31 05:38:30 PM PDT 24
Peak memory 214312 kb
Host smart-2ae4691b-ac3c-40c2-93ca-7b6e82ad72e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189122900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2189122900
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2878494409
Short name T83
Test name
Test status
Simulation time 830919226 ps
CPU time 31.49 seconds
Started Jul 31 05:38:20 PM PDT 24
Finished Jul 31 05:38:51 PM PDT 24
Peak memory 206948 kb
Host smart-0f210f39-e40e-4ed4-9385-6904380a2956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878494409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2878494409
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.736716469
Short name T886
Test name
Test status
Simulation time 463368804 ps
CPU time 2.99 seconds
Started Jul 31 05:38:21 PM PDT 24
Finished Jul 31 05:38:24 PM PDT 24
Peak memory 208920 kb
Host smart-33634217-27a6-47ba-933d-7d148e81a6cb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736716469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.736716469
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2162407042
Short name T651
Test name
Test status
Simulation time 104865898 ps
CPU time 2.92 seconds
Started Jul 31 05:38:22 PM PDT 24
Finished Jul 31 05:38:25 PM PDT 24
Peak memory 206992 kb
Host smart-332e143c-efec-49d3-a703-9bff7ccc6c6b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162407042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2162407042
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.4179194782
Short name T340
Test name
Test status
Simulation time 86321671 ps
CPU time 3.2 seconds
Started Jul 31 05:38:22 PM PDT 24
Finished Jul 31 05:38:25 PM PDT 24
Peak memory 208392 kb
Host smart-91b44f01-c323-457a-a353-fae0caebd21b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179194782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.4179194782
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3911692851
Short name T729
Test name
Test status
Simulation time 114236169 ps
CPU time 1.85 seconds
Started Jul 31 05:38:23 PM PDT 24
Finished Jul 31 05:38:25 PM PDT 24
Peak memory 207432 kb
Host smart-1cb21799-e118-4f0d-833c-aeab45505e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911692851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3911692851
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1009257201
Short name T492
Test name
Test status
Simulation time 519988026 ps
CPU time 3.04 seconds
Started Jul 31 05:38:21 PM PDT 24
Finished Jul 31 05:38:24 PM PDT 24
Peak memory 206984 kb
Host smart-c3aae850-6ddc-4dc4-8f06-a9eea1a8d069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009257201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1009257201
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3833448244
Short name T898
Test name
Test status
Simulation time 5928376287 ps
CPU time 122.88 seconds
Started Jul 31 05:38:23 PM PDT 24
Finished Jul 31 05:40:26 PM PDT 24
Peak memory 216208 kb
Host smart-e156f273-d514-4c04-af8d-2f81a47fdca3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833448244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3833448244
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.421156210
Short name T655
Test name
Test status
Simulation time 119111950 ps
CPU time 5.19 seconds
Started Jul 31 05:38:20 PM PDT 24
Finished Jul 31 05:38:26 PM PDT 24
Peak memory 218480 kb
Host smart-de9bccc4-f410-4215-b5bc-d8ccc9ee6a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421156210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.421156210
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2505583999
Short name T540
Test name
Test status
Simulation time 123716802 ps
CPU time 3.1 seconds
Started Jul 31 05:38:20 PM PDT 24
Finished Jul 31 05:38:23 PM PDT 24
Peak memory 210624 kb
Host smart-48a04bbd-890e-4bdc-b364-9b5595f81cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505583999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2505583999
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.802838190
Short name T536
Test name
Test status
Simulation time 14151996 ps
CPU time 0.72 seconds
Started Jul 31 05:38:26 PM PDT 24
Finished Jul 31 05:38:26 PM PDT 24
Peak memory 205964 kb
Host smart-13cef587-78d4-4bbf-a451-ce50f01b42c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802838190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.802838190
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3665179866
Short name T280
Test name
Test status
Simulation time 158325391 ps
CPU time 3.77 seconds
Started Jul 31 05:38:20 PM PDT 24
Finished Jul 31 05:38:23 PM PDT 24
Peak memory 214384 kb
Host smart-5fb619c4-a396-4aeb-9078-cdc7469839d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3665179866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3665179866
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.3815733197
Short name T28
Test name
Test status
Simulation time 551377528 ps
CPU time 3.35 seconds
Started Jul 31 05:38:19 PM PDT 24
Finished Jul 31 05:38:23 PM PDT 24
Peak memory 209740 kb
Host smart-10675777-20c1-4c3e-ad33-bf416aa323a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815733197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3815733197
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3065004577
Short name T870
Test name
Test status
Simulation time 75701477 ps
CPU time 2.31 seconds
Started Jul 31 05:38:21 PM PDT 24
Finished Jul 31 05:38:24 PM PDT 24
Peak memory 207416 kb
Host smart-71d50133-1cab-48a1-b29a-f010e4d4807a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065004577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3065004577
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2550054013
Short name T885
Test name
Test status
Simulation time 28958832 ps
CPU time 2.3 seconds
Started Jul 31 05:38:23 PM PDT 24
Finished Jul 31 05:38:25 PM PDT 24
Peak memory 214252 kb
Host smart-62442698-d4ab-48e7-84e1-f726f4957a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550054013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2550054013
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2064424020
Short name T812
Test name
Test status
Simulation time 54021645 ps
CPU time 2.08 seconds
Started Jul 31 05:38:20 PM PDT 24
Finished Jul 31 05:38:23 PM PDT 24
Peak memory 214232 kb
Host smart-3455eb93-26ca-4b2e-990e-1d01ea5912b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064424020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2064424020
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_random.1927771659
Short name T276
Test name
Test status
Simulation time 80905237 ps
CPU time 3.98 seconds
Started Jul 31 05:38:22 PM PDT 24
Finished Jul 31 05:38:26 PM PDT 24
Peak memory 218492 kb
Host smart-7e83897c-883e-4ab2-ba44-608aad723a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927771659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1927771659
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3171206174
Short name T456
Test name
Test status
Simulation time 85309060 ps
CPU time 2.43 seconds
Started Jul 31 05:38:20 PM PDT 24
Finished Jul 31 05:38:23 PM PDT 24
Peak memory 206756 kb
Host smart-9edcdb55-a399-4dab-a91e-f8e8a625f1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171206174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3171206174
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1562432434
Short name T369
Test name
Test status
Simulation time 955507338 ps
CPU time 6.97 seconds
Started Jul 31 05:38:20 PM PDT 24
Finished Jul 31 05:38:27 PM PDT 24
Peak memory 208272 kb
Host smart-9122c5db-280a-486b-b89f-d3651f7ed08b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562432434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1562432434
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.963048607
Short name T85
Test name
Test status
Simulation time 88784390 ps
CPU time 2.27 seconds
Started Jul 31 05:38:21 PM PDT 24
Finished Jul 31 05:38:24 PM PDT 24
Peak memory 206832 kb
Host smart-697eb28b-1431-4d11-b3e6-09d65c35edc9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963048607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.963048607
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.803162303
Short name T663
Test name
Test status
Simulation time 27637806 ps
CPU time 1.99 seconds
Started Jul 31 05:38:29 PM PDT 24
Finished Jul 31 05:38:31 PM PDT 24
Peak memory 207796 kb
Host smart-729fbee3-6932-481c-8bd9-7d7a4e920531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803162303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.803162303
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1510563260
Short name T409
Test name
Test status
Simulation time 579102403 ps
CPU time 3.98 seconds
Started Jul 31 05:38:22 PM PDT 24
Finished Jul 31 05:38:26 PM PDT 24
Peak memory 208804 kb
Host smart-41cf5d2f-ddf6-4726-9ee1-a16072c4120d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510563260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1510563260
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2760964435
Short name T193
Test name
Test status
Simulation time 2683099120 ps
CPU time 25.27 seconds
Started Jul 31 05:38:25 PM PDT 24
Finished Jul 31 05:38:50 PM PDT 24
Peak memory 216892 kb
Host smart-e1fa89b6-026b-4d4b-acbf-11db58412493
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760964435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2760964435
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1196374885
Short name T238
Test name
Test status
Simulation time 3820763659 ps
CPU time 51.36 seconds
Started Jul 31 05:38:21 PM PDT 24
Finished Jul 31 05:39:12 PM PDT 24
Peak memory 222552 kb
Host smart-7ca2d583-36b2-4767-b074-b855f904ffc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196374885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1196374885
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.778019550
Short name T702
Test name
Test status
Simulation time 8845767 ps
CPU time 0.8 seconds
Started Jul 31 05:38:26 PM PDT 24
Finished Jul 31 05:38:27 PM PDT 24
Peak memory 205924 kb
Host smart-0e018d31-67b5-4ec9-a390-0370bb0a6ed5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778019550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.778019550
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1976498947
Short name T897
Test name
Test status
Simulation time 147424514 ps
CPU time 3.35 seconds
Started Jul 31 05:38:25 PM PDT 24
Finished Jul 31 05:38:28 PM PDT 24
Peak memory 222568 kb
Host smart-a12f9d0a-1313-478b-84b2-940fc6cf79a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1976498947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1976498947
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.76251361
Short name T864
Test name
Test status
Simulation time 190700745 ps
CPU time 2.73 seconds
Started Jul 31 05:38:28 PM PDT 24
Finished Jul 31 05:38:31 PM PDT 24
Peak memory 207440 kb
Host smart-3eb20f5e-f7b0-4703-9206-d1bf11d35819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76251361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.76251361
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.4170643858
Short name T780
Test name
Test status
Simulation time 125949109 ps
CPU time 3.29 seconds
Started Jul 31 05:38:26 PM PDT 24
Finished Jul 31 05:38:30 PM PDT 24
Peak memory 214328 kb
Host smart-efbfe137-5398-499a-8c78-fa5fb5615f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170643858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.4170643858
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2285966989
Short name T265
Test name
Test status
Simulation time 270683993 ps
CPU time 1.83 seconds
Started Jul 31 05:38:29 PM PDT 24
Finished Jul 31 05:38:31 PM PDT 24
Peak memory 214320 kb
Host smart-0670cb56-f7e0-40a7-9fe6-236e0038204f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285966989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2285966989
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.4110429227
Short name T210
Test name
Test status
Simulation time 46385509 ps
CPU time 3.13 seconds
Started Jul 31 05:38:28 PM PDT 24
Finished Jul 31 05:38:31 PM PDT 24
Peak memory 214280 kb
Host smart-401af681-f958-455a-aca8-bb06add51357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110429227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.4110429227
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2017330983
Short name T837
Test name
Test status
Simulation time 377109058 ps
CPU time 5.01 seconds
Started Jul 31 05:38:27 PM PDT 24
Finished Jul 31 05:38:32 PM PDT 24
Peak memory 214360 kb
Host smart-8463739a-07dd-43c9-bd7a-a500816375f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017330983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2017330983
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2050215612
Short name T478
Test name
Test status
Simulation time 187290318 ps
CPU time 5.3 seconds
Started Jul 31 05:38:34 PM PDT 24
Finished Jul 31 05:38:40 PM PDT 24
Peak memory 208000 kb
Host smart-a37821eb-2f4e-4e4a-9aca-fe2eca7b4dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050215612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2050215612
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1790997913
Short name T831
Test name
Test status
Simulation time 108125326 ps
CPU time 4.88 seconds
Started Jul 31 05:38:28 PM PDT 24
Finished Jul 31 05:38:33 PM PDT 24
Peak memory 208696 kb
Host smart-48ec0c4b-9072-46df-8985-592a66646648
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790997913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1790997913
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.28056517
Short name T466
Test name
Test status
Simulation time 1890441428 ps
CPU time 14.3 seconds
Started Jul 31 05:38:36 PM PDT 24
Finished Jul 31 05:38:50 PM PDT 24
Peak memory 209064 kb
Host smart-85b74c90-ac6c-4e9f-9b15-72beb87125cc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28056517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.28056517
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.1366765277
Short name T872
Test name
Test status
Simulation time 330542129 ps
CPU time 3.33 seconds
Started Jul 31 05:38:27 PM PDT 24
Finished Jul 31 05:38:30 PM PDT 24
Peak memory 208848 kb
Host smart-97ed5745-8128-4dea-abfe-5708e4469432
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366765277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1366765277
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2786468993
Short name T659
Test name
Test status
Simulation time 605191108 ps
CPU time 4.17 seconds
Started Jul 31 05:38:36 PM PDT 24
Finished Jul 31 05:38:40 PM PDT 24
Peak memory 208908 kb
Host smart-076d237f-8443-4c2b-ad2e-7ad51ce7c124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786468993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2786468993
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2232231512
Short name T900
Test name
Test status
Simulation time 185975963 ps
CPU time 2.63 seconds
Started Jul 31 05:38:28 PM PDT 24
Finished Jul 31 05:38:31 PM PDT 24
Peak memory 206676 kb
Host smart-8e732247-5740-4ba0-a398-d574e365b57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232231512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2232231512
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.1036856769
Short name T819
Test name
Test status
Simulation time 484042601 ps
CPU time 7.31 seconds
Started Jul 31 05:38:29 PM PDT 24
Finished Jul 31 05:38:36 PM PDT 24
Peak memory 215100 kb
Host smart-4bc014ff-cf8f-45eb-a688-4253a9ca2d80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036856769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.1036856769
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2504751869
Short name T771
Test name
Test status
Simulation time 244316607 ps
CPU time 4.14 seconds
Started Jul 31 05:38:25 PM PDT 24
Finished Jul 31 05:38:30 PM PDT 24
Peak memory 214308 kb
Host smart-cc0f4cd1-8383-4e5d-9a04-3734c70e08b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504751869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2504751869
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1312178784
Short name T687
Test name
Test status
Simulation time 177722744 ps
CPU time 2.67 seconds
Started Jul 31 05:38:30 PM PDT 24
Finished Jul 31 05:38:32 PM PDT 24
Peak memory 209892 kb
Host smart-7a19cd52-a0d1-4377-8be3-8e0dc8483929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312178784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1312178784
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2653206215
Short name T105
Test name
Test status
Simulation time 64710444 ps
CPU time 0.82 seconds
Started Jul 31 05:38:31 PM PDT 24
Finished Jul 31 05:38:32 PM PDT 24
Peak memory 206092 kb
Host smart-71883c90-6748-437c-a90e-eaedade576a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653206215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2653206215
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.1915493191
Short name T403
Test name
Test status
Simulation time 58350097 ps
CPU time 4.2 seconds
Started Jul 31 05:38:31 PM PDT 24
Finished Jul 31 05:38:35 PM PDT 24
Peak memory 214320 kb
Host smart-46c3be11-7e0d-4444-8504-65fdb5d23606
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1915493191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1915493191
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.385377035
Short name T541
Test name
Test status
Simulation time 391178768 ps
CPU time 3 seconds
Started Jul 31 05:38:32 PM PDT 24
Finished Jul 31 05:38:35 PM PDT 24
Peak memory 209460 kb
Host smart-5c7b3e51-25f3-49d2-ab48-c0564441f199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385377035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.385377035
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.4286206975
Short name T337
Test name
Test status
Simulation time 106528360 ps
CPU time 4.88 seconds
Started Jul 31 05:38:31 PM PDT 24
Finished Jul 31 05:38:36 PM PDT 24
Peak memory 210484 kb
Host smart-2ece14b7-5632-4f7f-9a4b-6449887bd5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286206975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.4286206975
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3684093626
Short name T92
Test name
Test status
Simulation time 82986635 ps
CPU time 3.72 seconds
Started Jul 31 05:38:34 PM PDT 24
Finished Jul 31 05:38:38 PM PDT 24
Peak memory 222448 kb
Host smart-5274ed68-b045-4813-b22d-3d7cc1d7f49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684093626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3684093626
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3977674412
Short name T208
Test name
Test status
Simulation time 86910753 ps
CPU time 2.83 seconds
Started Jul 31 05:38:33 PM PDT 24
Finished Jul 31 05:38:36 PM PDT 24
Peak memory 206160 kb
Host smart-b0687c2e-a1c1-496d-a554-7b2cfc4a7c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977674412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3977674412
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_random.2370664439
Short name T250
Test name
Test status
Simulation time 151085692 ps
CPU time 3.77 seconds
Started Jul 31 05:38:33 PM PDT 24
Finished Jul 31 05:38:36 PM PDT 24
Peak memory 214404 kb
Host smart-f1155f34-8893-4758-9b15-99fc56e54846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370664439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2370664439
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2776873289
Short name T795
Test name
Test status
Simulation time 299274581 ps
CPU time 4.39 seconds
Started Jul 31 05:38:28 PM PDT 24
Finished Jul 31 05:38:32 PM PDT 24
Peak memory 208420 kb
Host smart-f44481f9-3a84-4775-94ba-9cd726b98282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776873289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2776873289
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.96090377
Short name T462
Test name
Test status
Simulation time 175054867 ps
CPU time 5.5 seconds
Started Jul 31 05:38:27 PM PDT 24
Finished Jul 31 05:38:32 PM PDT 24
Peak memory 207932 kb
Host smart-185fd2c1-7124-4f83-af3a-82f4d6aba92c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96090377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.96090377
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1522055910
Short name T788
Test name
Test status
Simulation time 138956595 ps
CPU time 2.84 seconds
Started Jul 31 05:38:36 PM PDT 24
Finished Jul 31 05:38:39 PM PDT 24
Peak memory 208676 kb
Host smart-0efc2128-ae66-45bb-ab24-d4b2fd4d681e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522055910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1522055910
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3349052894
Short name T716
Test name
Test status
Simulation time 178197532 ps
CPU time 4.11 seconds
Started Jul 31 05:38:36 PM PDT 24
Finished Jul 31 05:38:40 PM PDT 24
Peak memory 207004 kb
Host smart-a8d34709-cefb-4d96-9047-f7906ba91f81
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349052894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3349052894
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.14867019
Short name T202
Test name
Test status
Simulation time 44435488 ps
CPU time 2.02 seconds
Started Jul 31 05:38:32 PM PDT 24
Finished Jul 31 05:38:34 PM PDT 24
Peak memory 215360 kb
Host smart-5e80f623-b665-4ff8-b66a-a024dc2c93ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14867019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.14867019
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.279874831
Short name T851
Test name
Test status
Simulation time 2667077741 ps
CPU time 34.1 seconds
Started Jul 31 05:38:27 PM PDT 24
Finished Jul 31 05:39:01 PM PDT 24
Peak memory 208412 kb
Host smart-cde64fbb-e504-4794-b100-c0ead3255d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279874831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.279874831
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.1002279032
Short name T78
Test name
Test status
Simulation time 2664141360 ps
CPU time 34.02 seconds
Started Jul 31 05:38:33 PM PDT 24
Finished Jul 31 05:39:07 PM PDT 24
Peak memory 216484 kb
Host smart-ad82090b-51f0-496a-8b49-306ab27a6d86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002279032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1002279032
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.261456915
Short name T465
Test name
Test status
Simulation time 451435139 ps
CPU time 5.19 seconds
Started Jul 31 05:38:32 PM PDT 24
Finished Jul 31 05:38:37 PM PDT 24
Peak memory 214332 kb
Host smart-47c1af99-12c5-4e3c-b209-a92977a029a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261456915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.261456915
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.278190037
Short name T64
Test name
Test status
Simulation time 2373170455 ps
CPU time 20.64 seconds
Started Jul 31 05:38:34 PM PDT 24
Finished Jul 31 05:38:55 PM PDT 24
Peak memory 210348 kb
Host smart-74ab404f-cbd7-4070-b97d-22b1739ffb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278190037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.278190037
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3840595934
Short name T891
Test name
Test status
Simulation time 25843368 ps
CPU time 0.8 seconds
Started Jul 31 05:38:40 PM PDT 24
Finished Jul 31 05:38:41 PM PDT 24
Peak memory 205904 kb
Host smart-7816a0f1-9e10-4396-8d15-ff8e5c38e6bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840595934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3840595934
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3027974773
Short name T915
Test name
Test status
Simulation time 1090356945 ps
CPU time 8.65 seconds
Started Jul 31 05:38:39 PM PDT 24
Finished Jul 31 05:38:48 PM PDT 24
Peak memory 214232 kb
Host smart-2b18143a-220c-4078-ba21-00f19df10740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027974773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3027974773
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1769250918
Short name T484
Test name
Test status
Simulation time 110579046 ps
CPU time 2.78 seconds
Started Jul 31 05:38:35 PM PDT 24
Finished Jul 31 05:38:38 PM PDT 24
Peak memory 208096 kb
Host smart-adaaf87f-aac0-42ea-b022-f8b53fc6bd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769250918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1769250918
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2736025459
Short name T104
Test name
Test status
Simulation time 4088908778 ps
CPU time 12.92 seconds
Started Jul 31 05:38:36 PM PDT 24
Finished Jul 31 05:38:49 PM PDT 24
Peak memory 214348 kb
Host smart-031039b9-9bc1-4254-a0b3-78be41d7f436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736025459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2736025459
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.1224701210
Short name T835
Test name
Test status
Simulation time 60292512 ps
CPU time 2.53 seconds
Started Jul 31 05:38:35 PM PDT 24
Finished Jul 31 05:38:37 PM PDT 24
Peak memory 209844 kb
Host smart-44eeb19b-b0c0-4583-9c2f-af2ac63a8206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224701210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1224701210
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.997325769
Short name T469
Test name
Test status
Simulation time 231169381 ps
CPU time 3.75 seconds
Started Jul 31 05:38:34 PM PDT 24
Finished Jul 31 05:38:37 PM PDT 24
Peak memory 208180 kb
Host smart-33b284fb-6b49-4b53-88a1-65101cbc1b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997325769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.997325769
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3038040945
Short name T597
Test name
Test status
Simulation time 464772140 ps
CPU time 2.76 seconds
Started Jul 31 05:38:33 PM PDT 24
Finished Jul 31 05:38:36 PM PDT 24
Peak memory 206868 kb
Host smart-bdd24ff5-03c9-47b1-ae41-7c8c8d0f3165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038040945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3038040945
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1804405248
Short name T670
Test name
Test status
Simulation time 515818370 ps
CPU time 3.27 seconds
Started Jul 31 05:38:34 PM PDT 24
Finished Jul 31 05:38:37 PM PDT 24
Peak memory 206884 kb
Host smart-22f46d1a-ea24-4124-a767-688175ed1629
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804405248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1804405248
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2214741234
Short name T834
Test name
Test status
Simulation time 1506103187 ps
CPU time 38.38 seconds
Started Jul 31 05:38:35 PM PDT 24
Finished Jul 31 05:39:13 PM PDT 24
Peak memory 208020 kb
Host smart-b2977d93-25f1-4d1b-baf9-b5b5bfa60952
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214741234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2214741234
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.168776500
Short name T827
Test name
Test status
Simulation time 559670711 ps
CPU time 18.38 seconds
Started Jul 31 05:38:32 PM PDT 24
Finished Jul 31 05:38:51 PM PDT 24
Peak memory 208584 kb
Host smart-fd677497-18d1-42d1-8a0a-ba4644fd89a2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168776500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.168776500
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2562153430
Short name T767
Test name
Test status
Simulation time 122754782 ps
CPU time 4.39 seconds
Started Jul 31 05:38:36 PM PDT 24
Finished Jul 31 05:38:40 PM PDT 24
Peak memory 209876 kb
Host smart-f7e9732c-e477-4e77-98cd-41dd23209c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562153430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2562153430
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.929128922
Short name T453
Test name
Test status
Simulation time 182879381 ps
CPU time 2.3 seconds
Started Jul 31 05:38:32 PM PDT 24
Finished Jul 31 05:38:35 PM PDT 24
Peak memory 206844 kb
Host smart-0e246dff-df0d-4c27-bd35-fc6a305c6792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929128922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.929128922
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.1941059362
Short name T3
Test name
Test status
Simulation time 598582696 ps
CPU time 5.08 seconds
Started Jul 31 05:38:37 PM PDT 24
Finished Jul 31 05:38:42 PM PDT 24
Peak memory 208684 kb
Host smart-41aaaf2c-1763-4ac9-be1d-ccda710a8669
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941059362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1941059362
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3753515103
Short name T646
Test name
Test status
Simulation time 110536073 ps
CPU time 4.11 seconds
Started Jul 31 05:38:36 PM PDT 24
Finished Jul 31 05:38:40 PM PDT 24
Peak memory 218132 kb
Host smart-5e55f740-101c-4058-9265-9de9095cf150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753515103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3753515103
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2087967797
Short name T665
Test name
Test status
Simulation time 1246512292 ps
CPU time 23.84 seconds
Started Jul 31 05:38:35 PM PDT 24
Finished Jul 31 05:38:59 PM PDT 24
Peak memory 210940 kb
Host smart-4311af58-d8f1-4f34-881f-740d0d0d2548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087967797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2087967797
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1621736931
Short name T490
Test name
Test status
Simulation time 38441160 ps
CPU time 0.86 seconds
Started Jul 31 05:36:27 PM PDT 24
Finished Jul 31 05:36:28 PM PDT 24
Peak memory 205940 kb
Host smart-45e92cbb-766e-4c36-b140-a3feb85f6e01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621736931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1621736931
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.199142422
Short name T422
Test name
Test status
Simulation time 92780367 ps
CPU time 5.1 seconds
Started Jul 31 05:36:19 PM PDT 24
Finished Jul 31 05:36:25 PM PDT 24
Peak memory 215180 kb
Host smart-d98ef15b-b402-4abd-930a-c01fb566c5b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=199142422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.199142422
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.857412404
Short name T467
Test name
Test status
Simulation time 57465465 ps
CPU time 2.2 seconds
Started Jul 31 05:36:20 PM PDT 24
Finished Jul 31 05:36:22 PM PDT 24
Peak memory 209880 kb
Host smart-c36aaad7-558c-4d3b-a91e-33365e61453c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857412404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.857412404
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3317898304
Short name T752
Test name
Test status
Simulation time 49560991 ps
CPU time 2.05 seconds
Started Jul 31 05:36:18 PM PDT 24
Finished Jul 31 05:36:20 PM PDT 24
Peak memory 214312 kb
Host smart-dcd9987d-795c-446a-9972-6080e2976724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317898304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3317898304
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3241823090
Short name T667
Test name
Test status
Simulation time 64492268 ps
CPU time 2.63 seconds
Started Jul 31 05:36:18 PM PDT 24
Finished Jul 31 05:36:20 PM PDT 24
Peak memory 214268 kb
Host smart-15f5d0ce-50fe-44e2-9bc6-b4c9079b4af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241823090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3241823090
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.29805941
Short name T803
Test name
Test status
Simulation time 265985839 ps
CPU time 3.36 seconds
Started Jul 31 05:36:23 PM PDT 24
Finished Jul 31 05:36:27 PM PDT 24
Peak memory 209532 kb
Host smart-b4dbe810-a679-44b8-899b-ca3292dd728c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29805941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.29805941
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.550259775
Short name T642
Test name
Test status
Simulation time 2909995215 ps
CPU time 7.34 seconds
Started Jul 31 05:36:22 PM PDT 24
Finished Jul 31 05:36:29 PM PDT 24
Peak memory 208324 kb
Host smart-f2485064-4a54-4a54-96c6-e604f9d10e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550259775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.550259775
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3149284897
Short name T44
Test name
Test status
Simulation time 347887252 ps
CPU time 6.64 seconds
Started Jul 31 05:36:24 PM PDT 24
Finished Jul 31 05:36:31 PM PDT 24
Peak memory 238244 kb
Host smart-35dd7a44-316b-42ce-a385-a1d473a53823
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149284897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3149284897
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.333783652
Short name T648
Test name
Test status
Simulation time 42656195 ps
CPU time 2.92 seconds
Started Jul 31 05:36:22 PM PDT 24
Finished Jul 31 05:36:25 PM PDT 24
Peak memory 209012 kb
Host smart-e62d073e-543a-4e0f-8560-4b3e5bda8c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333783652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.333783652
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3412418677
Short name T377
Test name
Test status
Simulation time 30158520 ps
CPU time 2.12 seconds
Started Jul 31 05:36:21 PM PDT 24
Finished Jul 31 05:36:23 PM PDT 24
Peak memory 206996 kb
Host smart-62c0777b-4493-4f10-bcdd-fe75b89ae81e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412418677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3412418677
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.422593768
Short name T863
Test name
Test status
Simulation time 40281871 ps
CPU time 2.89 seconds
Started Jul 31 05:36:20 PM PDT 24
Finished Jul 31 05:36:23 PM PDT 24
Peak memory 209104 kb
Host smart-7911b2a2-45ee-4080-849f-3d0d701f2db6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422593768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.422593768
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2787869695
Short name T807
Test name
Test status
Simulation time 51139288 ps
CPU time 2.83 seconds
Started Jul 31 05:36:23 PM PDT 24
Finished Jul 31 05:36:26 PM PDT 24
Peak memory 207024 kb
Host smart-b32a679e-e631-48da-91df-a417d933cff6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787869695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2787869695
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1202488870
Short name T793
Test name
Test status
Simulation time 664069052 ps
CPU time 4.14 seconds
Started Jul 31 05:36:21 PM PDT 24
Finished Jul 31 05:36:25 PM PDT 24
Peak memory 214324 kb
Host smart-9d7e355d-b698-48d6-9130-e2d7355ad4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202488870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1202488870
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3781286881
Short name T560
Test name
Test status
Simulation time 64498872 ps
CPU time 2.14 seconds
Started Jul 31 05:36:20 PM PDT 24
Finished Jul 31 05:36:22 PM PDT 24
Peak memory 206856 kb
Host smart-8659d38a-7c3b-495c-9352-b46bb8421545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781286881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3781286881
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.484894942
Short name T232
Test name
Test status
Simulation time 1730733671 ps
CPU time 46.27 seconds
Started Jul 31 05:36:28 PM PDT 24
Finished Jul 31 05:37:14 PM PDT 24
Peak memory 220680 kb
Host smart-c51a3e88-ecc6-4297-ab0d-c169e0f62a81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484894942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.484894942
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.4132467638
Short name T392
Test name
Test status
Simulation time 784481471 ps
CPU time 20.2 seconds
Started Jul 31 05:36:23 PM PDT 24
Finished Jul 31 05:36:44 PM PDT 24
Peak memory 222500 kb
Host smart-80e69a41-86da-41dc-8df1-3ac456eb315a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132467638 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.4132467638
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1137050614
Short name T664
Test name
Test status
Simulation time 89132383 ps
CPU time 3.82 seconds
Started Jul 31 05:36:21 PM PDT 24
Finished Jul 31 05:36:25 PM PDT 24
Peak memory 209996 kb
Host smart-4b2f326c-0761-4d29-910f-18ff83a7e22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137050614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1137050614
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3058055156
Short name T705
Test name
Test status
Simulation time 29157374 ps
CPU time 1.68 seconds
Started Jul 31 05:36:31 PM PDT 24
Finished Jul 31 05:36:33 PM PDT 24
Peak memory 209824 kb
Host smart-d1396a7d-07fc-45b4-b923-aec94033edf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058055156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3058055156
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2331344251
Short name T606
Test name
Test status
Simulation time 29411841 ps
CPU time 0.83 seconds
Started Jul 31 05:38:38 PM PDT 24
Finished Jul 31 05:38:38 PM PDT 24
Peak memory 205952 kb
Host smart-f07e058e-daf1-459d-b2fe-169d8ea4bb8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331344251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2331344251
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.4169104662
Short name T894
Test name
Test status
Simulation time 75005350 ps
CPU time 3.55 seconds
Started Jul 31 05:38:37 PM PDT 24
Finished Jul 31 05:38:41 PM PDT 24
Peak memory 214208 kb
Host smart-36bc15dc-b2b0-4cf3-be0e-f9b182a8545c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169104662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.4169104662
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.232251378
Short name T733
Test name
Test status
Simulation time 2636424316 ps
CPU time 31.65 seconds
Started Jul 31 05:38:38 PM PDT 24
Finished Jul 31 05:39:09 PM PDT 24
Peak memory 219728 kb
Host smart-797d7e13-86b3-416f-9786-a9fe3bd391e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232251378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.232251378
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.393826731
Short name T639
Test name
Test status
Simulation time 28732734 ps
CPU time 1.71 seconds
Started Jul 31 05:38:38 PM PDT 24
Finished Jul 31 05:38:40 PM PDT 24
Peak memory 214372 kb
Host smart-bf14e6b5-6011-4bc8-9a99-904943d54fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393826731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.393826731
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2254610495
Short name T592
Test name
Test status
Simulation time 37184829 ps
CPU time 2.93 seconds
Started Jul 31 05:38:39 PM PDT 24
Finished Jul 31 05:38:42 PM PDT 24
Peak memory 220176 kb
Host smart-576badf3-5818-4868-8ce7-a6a4853924e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254610495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2254610495
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1832010201
Short name T773
Test name
Test status
Simulation time 1999902136 ps
CPU time 3.56 seconds
Started Jul 31 05:38:37 PM PDT 24
Finished Jul 31 05:38:41 PM PDT 24
Peak memory 215708 kb
Host smart-aa059c88-8205-490d-a50e-c2725d88413e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832010201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1832010201
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.3285395647
Short name T842
Test name
Test status
Simulation time 2566233734 ps
CPU time 41.35 seconds
Started Jul 31 05:38:37 PM PDT 24
Finished Jul 31 05:39:19 PM PDT 24
Peak memory 209668 kb
Host smart-dc3e9542-9b36-4ffb-b194-534c71621d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285395647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3285395647
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2989997725
Short name T797
Test name
Test status
Simulation time 1645462847 ps
CPU time 11.41 seconds
Started Jul 31 05:38:36 PM PDT 24
Finished Jul 31 05:38:47 PM PDT 24
Peak memory 208080 kb
Host smart-f07a84f5-f391-479d-8b51-8bb96dc60c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989997725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2989997725
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2311620065
Short name T416
Test name
Test status
Simulation time 82271121 ps
CPU time 1.96 seconds
Started Jul 31 05:38:37 PM PDT 24
Finished Jul 31 05:38:39 PM PDT 24
Peak memory 207368 kb
Host smart-e6f3b22c-a0f0-4411-bbcf-0b725f4cc8fc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311620065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2311620065
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.1867949130
Short name T324
Test name
Test status
Simulation time 55989356 ps
CPU time 2.55 seconds
Started Jul 31 05:38:37 PM PDT 24
Finished Jul 31 05:38:40 PM PDT 24
Peak memory 206896 kb
Host smart-059b1b08-5c89-414e-9e6f-afc911d50199
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867949130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1867949130
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.4043318810
Short name T253
Test name
Test status
Simulation time 222706733 ps
CPU time 5.39 seconds
Started Jul 31 05:38:39 PM PDT 24
Finished Jul 31 05:38:44 PM PDT 24
Peak memory 207944 kb
Host smart-2b27d8d6-61ba-4a48-af78-389b4211cda1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043318810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.4043318810
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.555864863
Short name T841
Test name
Test status
Simulation time 45967823 ps
CPU time 2.49 seconds
Started Jul 31 05:38:35 PM PDT 24
Finished Jul 31 05:38:38 PM PDT 24
Peak memory 215576 kb
Host smart-a20d4316-20b3-4523-a470-d3b47a86578d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555864863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.555864863
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1296727165
Short name T547
Test name
Test status
Simulation time 2974733059 ps
CPU time 25.58 seconds
Started Jul 31 05:38:37 PM PDT 24
Finished Jul 31 05:39:02 PM PDT 24
Peak memory 208836 kb
Host smart-2d9cce32-5017-4f47-8ee8-f3c43f0f245e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296727165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1296727165
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.468962922
Short name T355
Test name
Test status
Simulation time 1320475133 ps
CPU time 19.03 seconds
Started Jul 31 05:38:38 PM PDT 24
Finished Jul 31 05:38:57 PM PDT 24
Peak memory 215524 kb
Host smart-60d0b785-40fa-4a2f-83ef-59a7da18ad76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468962922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.468962922
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.632633419
Short name T836
Test name
Test status
Simulation time 23577421413 ps
CPU time 47.94 seconds
Started Jul 31 05:38:38 PM PDT 24
Finished Jul 31 05:39:26 PM PDT 24
Peak memory 209588 kb
Host smart-95a78077-4404-4408-b797-fc1a1e0f9abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632633419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.632633419
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.644357960
Short name T37
Test name
Test status
Simulation time 716275751 ps
CPU time 1.86 seconds
Started Jul 31 05:38:38 PM PDT 24
Finished Jul 31 05:38:40 PM PDT 24
Peak memory 209760 kb
Host smart-888f517b-f4dd-4a12-833b-9a70560ea104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644357960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.644357960
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.223789767
Short name T878
Test name
Test status
Simulation time 20213038 ps
CPU time 1.04 seconds
Started Jul 31 05:38:42 PM PDT 24
Finished Jul 31 05:38:43 PM PDT 24
Peak memory 206204 kb
Host smart-d9b991e9-13e2-450c-a12e-f6ca0f7a81be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223789767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.223789767
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.535548825
Short name T874
Test name
Test status
Simulation time 7251611666 ps
CPU time 78.91 seconds
Started Jul 31 05:38:40 PM PDT 24
Finished Jul 31 05:39:59 PM PDT 24
Peak memory 215848 kb
Host smart-b06ad633-dfb4-4acc-a546-528f73560e26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=535548825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.535548825
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.3946321444
Short name T31
Test name
Test status
Simulation time 117995087 ps
CPU time 3.41 seconds
Started Jul 31 05:38:40 PM PDT 24
Finished Jul 31 05:38:43 PM PDT 24
Peak memory 209940 kb
Host smart-b31d6458-6718-481d-900b-4fbbe6d51381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946321444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3946321444
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1624861418
Short name T775
Test name
Test status
Simulation time 204030822 ps
CPU time 2.31 seconds
Started Jul 31 05:38:36 PM PDT 24
Finished Jul 31 05:38:39 PM PDT 24
Peak memory 210072 kb
Host smart-435637b1-4564-4464-9aae-fe95ba297729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624861418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1624861418
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3673003504
Short name T267
Test name
Test status
Simulation time 113369327 ps
CPU time 2.22 seconds
Started Jul 31 05:38:45 PM PDT 24
Finished Jul 31 05:38:47 PM PDT 24
Peak memory 222568 kb
Host smart-1c155891-19e0-484e-8158-ac904c916e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673003504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3673003504
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2893101373
Short name T734
Test name
Test status
Simulation time 327398132 ps
CPU time 3.24 seconds
Started Jul 31 05:38:43 PM PDT 24
Finished Jul 31 05:38:47 PM PDT 24
Peak memory 222448 kb
Host smart-6633f107-1f4f-4c2b-bc69-af8e7ae926a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893101373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2893101373
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.4020031322
Short name T502
Test name
Test status
Simulation time 32509914 ps
CPU time 2.33 seconds
Started Jul 31 05:38:40 PM PDT 24
Finished Jul 31 05:38:43 PM PDT 24
Peak memory 214304 kb
Host smart-d34a5223-1de9-49d5-b948-80ea4c5ad3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020031322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.4020031322
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1864053852
Short name T704
Test name
Test status
Simulation time 45627475 ps
CPU time 3.06 seconds
Started Jul 31 05:38:40 PM PDT 24
Finished Jul 31 05:38:44 PM PDT 24
Peak memory 207552 kb
Host smart-a325c72d-ab61-4ee6-b6b1-a42701a5c5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864053852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1864053852
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1307058368
Short name T241
Test name
Test status
Simulation time 320711208 ps
CPU time 3.96 seconds
Started Jul 31 05:38:41 PM PDT 24
Finished Jul 31 05:38:45 PM PDT 24
Peak memory 207932 kb
Host smart-42fd4321-0612-47c2-ac5e-4e6dc1dbf34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307058368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1307058368
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.26357210
Short name T617
Test name
Test status
Simulation time 82847904 ps
CPU time 2.41 seconds
Started Jul 31 05:38:35 PM PDT 24
Finished Jul 31 05:38:38 PM PDT 24
Peak memory 207000 kb
Host smart-06a8e1e5-a2c5-4fe4-901e-c7084835dcca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26357210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.26357210
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.2114793580
Short name T656
Test name
Test status
Simulation time 440133968 ps
CPU time 3.84 seconds
Started Jul 31 05:38:40 PM PDT 24
Finished Jul 31 05:38:43 PM PDT 24
Peak memory 206852 kb
Host smart-86ce4719-bc71-430b-8322-770453c280cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114793580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2114793580
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.679950612
Short name T700
Test name
Test status
Simulation time 110886261 ps
CPU time 3.76 seconds
Started Jul 31 05:38:41 PM PDT 24
Finished Jul 31 05:38:45 PM PDT 24
Peak memory 207008 kb
Host smart-090d98cb-dcd8-4f92-9194-a5bd2f14b570
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679950612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.679950612
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1541909458
Short name T237
Test name
Test status
Simulation time 77981629 ps
CPU time 2.3 seconds
Started Jul 31 05:38:44 PM PDT 24
Finished Jul 31 05:38:47 PM PDT 24
Peak memory 207384 kb
Host smart-3aca3daa-9ca5-406b-8244-ac7a04becabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541909458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1541909458
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1497415985
Short name T527
Test name
Test status
Simulation time 83921001 ps
CPU time 3.33 seconds
Started Jul 31 05:38:40 PM PDT 24
Finished Jul 31 05:38:44 PM PDT 24
Peak memory 208456 kb
Host smart-69b5f0ac-1b3b-4732-a7f6-6f3fa353651a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497415985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1497415985
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3791698968
Short name T226
Test name
Test status
Simulation time 379138289 ps
CPU time 19.29 seconds
Started Jul 31 05:38:44 PM PDT 24
Finished Jul 31 05:39:03 PM PDT 24
Peak memory 215652 kb
Host smart-7f8eccdb-e981-4ffc-ab3a-ce1eae650c4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791698968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3791698968
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.3859965798
Short name T163
Test name
Test status
Simulation time 407460339 ps
CPU time 26.45 seconds
Started Jul 31 05:38:41 PM PDT 24
Finished Jul 31 05:39:08 PM PDT 24
Peak memory 223368 kb
Host smart-6892d53c-4663-425e-afb2-0085f563e105
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859965798 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.3859965798
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2252557185
Short name T759
Test name
Test status
Simulation time 1217703208 ps
CPU time 8.47 seconds
Started Jul 31 05:38:44 PM PDT 24
Finished Jul 31 05:38:53 PM PDT 24
Peak memory 218704 kb
Host smart-6ac4eb14-f1f3-4cf5-9748-03d862b7b55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252557185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2252557185
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2840968028
Short name T601
Test name
Test status
Simulation time 95282472 ps
CPU time 2.69 seconds
Started Jul 31 05:38:44 PM PDT 24
Finished Jul 31 05:38:47 PM PDT 24
Peak memory 210300 kb
Host smart-c3089b75-5b4b-4f71-8243-cfe181bf333b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840968028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2840968028
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1930415743
Short name T429
Test name
Test status
Simulation time 22449777 ps
CPU time 0.86 seconds
Started Jul 31 05:38:41 PM PDT 24
Finished Jul 31 05:38:42 PM PDT 24
Peak memory 205908 kb
Host smart-765ea5b9-1865-4ebd-b794-760de4bb7f74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930415743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1930415743
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.3846619989
Short name T11
Test name
Test status
Simulation time 50202846 ps
CPU time 3.26 seconds
Started Jul 31 05:38:43 PM PDT 24
Finished Jul 31 05:38:46 PM PDT 24
Peak memory 215512 kb
Host smart-67d7ae2f-04d6-4b46-a182-617ca55359d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3846619989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3846619989
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3600679247
Short name T214
Test name
Test status
Simulation time 143421758 ps
CPU time 3.3 seconds
Started Jul 31 05:38:45 PM PDT 24
Finished Jul 31 05:38:49 PM PDT 24
Peak memory 222708 kb
Host smart-ab653ac5-3070-4188-99fa-99c0b0bf8ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600679247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3600679247
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.390381340
Short name T437
Test name
Test status
Simulation time 97602392 ps
CPU time 2.43 seconds
Started Jul 31 05:38:42 PM PDT 24
Finished Jul 31 05:38:45 PM PDT 24
Peak memory 214280 kb
Host smart-e64f2582-0911-4c2f-9b99-dbd0a9ba2532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390381340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.390381340
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2143131316
Short name T384
Test name
Test status
Simulation time 51151742 ps
CPU time 2.3 seconds
Started Jul 31 05:38:46 PM PDT 24
Finished Jul 31 05:38:48 PM PDT 24
Peak memory 214332 kb
Host smart-f28e3c63-1167-4073-a658-86c9498161da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143131316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2143131316
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3556263980
Short name T266
Test name
Test status
Simulation time 116511029 ps
CPU time 4.13 seconds
Started Jul 31 05:38:41 PM PDT 24
Finished Jul 31 05:38:45 PM PDT 24
Peak memory 214316 kb
Host smart-f299b649-9554-418c-80bf-446a012433f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556263980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3556263980
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_random.2914672546
Short name T858
Test name
Test status
Simulation time 195028373 ps
CPU time 2.91 seconds
Started Jul 31 05:38:41 PM PDT 24
Finished Jul 31 05:38:44 PM PDT 24
Peak memory 209644 kb
Host smart-d4ca8dd5-46ad-418f-8f03-6da54321dc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914672546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2914672546
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1847858619
Short name T524
Test name
Test status
Simulation time 51662507 ps
CPU time 2.68 seconds
Started Jul 31 05:38:43 PM PDT 24
Finished Jul 31 05:38:46 PM PDT 24
Peak memory 208668 kb
Host smart-a8131f9c-a7f5-43df-ad20-e4d1169b2e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847858619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1847858619
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.1061908848
Short name T35
Test name
Test status
Simulation time 64959688 ps
CPU time 3.5 seconds
Started Jul 31 05:38:42 PM PDT 24
Finished Jul 31 05:38:46 PM PDT 24
Peak memory 208776 kb
Host smart-d322e9bc-0b9c-4009-8d19-7255b9f821c3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061908848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1061908848
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3190266018
Short name T883
Test name
Test status
Simulation time 71231749 ps
CPU time 3.41 seconds
Started Jul 31 05:38:44 PM PDT 24
Finished Jul 31 05:38:48 PM PDT 24
Peak memory 208312 kb
Host smart-00b76d10-b65b-49af-8e43-99bba6cb0302
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190266018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3190266018
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1231135375
Short name T471
Test name
Test status
Simulation time 20220932 ps
CPU time 1.74 seconds
Started Jul 31 05:38:43 PM PDT 24
Finished Jul 31 05:38:45 PM PDT 24
Peak memory 206912 kb
Host smart-4e0b8a28-0dcf-413a-aabc-1879e35f8d45
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231135375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1231135375
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.3720082295
Short name T559
Test name
Test status
Simulation time 132636615 ps
CPU time 4.17 seconds
Started Jul 31 05:38:44 PM PDT 24
Finished Jul 31 05:38:49 PM PDT 24
Peak memory 218116 kb
Host smart-f3dc1142-7aff-4199-87e6-198628d98e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720082295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3720082295
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.4029108813
Short name T641
Test name
Test status
Simulation time 126558449 ps
CPU time 2.25 seconds
Started Jul 31 05:38:46 PM PDT 24
Finished Jul 31 05:38:48 PM PDT 24
Peak memory 206100 kb
Host smart-480c1619-7b25-4ca1-afb8-c95d29cd1c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029108813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.4029108813
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.452639798
Short name T544
Test name
Test status
Simulation time 560157714 ps
CPU time 17.03 seconds
Started Jul 31 05:38:41 PM PDT 24
Finished Jul 31 05:38:59 PM PDT 24
Peak memory 216260 kb
Host smart-e2a2536f-d1ce-4ab9-966b-3915e43fade1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452639798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.452639798
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.1907663491
Short name T177
Test name
Test status
Simulation time 201639656 ps
CPU time 7.44 seconds
Started Jul 31 05:38:44 PM PDT 24
Finished Jul 31 05:38:51 PM PDT 24
Peak memory 221908 kb
Host smart-e6de7c4d-fe50-4800-be2b-cd0f56c5d31f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907663491 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.1907663491
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2406833715
Short name T285
Test name
Test status
Simulation time 34300674 ps
CPU time 2.45 seconds
Started Jul 31 05:38:45 PM PDT 24
Finished Jul 31 05:38:47 PM PDT 24
Peak memory 207536 kb
Host smart-7373e8cb-0f90-4a8a-8b78-b1cbeec1503c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406833715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2406833715
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1665186744
Short name T188
Test name
Test status
Simulation time 54871774 ps
CPU time 2.22 seconds
Started Jul 31 05:38:43 PM PDT 24
Finished Jul 31 05:38:45 PM PDT 24
Peak memory 210148 kb
Host smart-acd6c34b-615e-4ca8-be90-ee2b851487be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665186744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1665186744
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1028234027
Short name T624
Test name
Test status
Simulation time 46178760 ps
CPU time 0.8 seconds
Started Jul 31 05:38:49 PM PDT 24
Finished Jul 31 05:38:50 PM PDT 24
Peak memory 205944 kb
Host smart-52d468b9-1cf1-41d0-85d3-d1529418a490
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028234027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1028234027
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1443174455
Short name T130
Test name
Test status
Simulation time 69515168 ps
CPU time 4.86 seconds
Started Jul 31 05:38:43 PM PDT 24
Finished Jul 31 05:38:48 PM PDT 24
Peak memory 214844 kb
Host smart-5028c31e-b6d6-40d2-aa1d-de56d50b9d27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1443174455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1443174455
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3661699831
Short name T69
Test name
Test status
Simulation time 256669901 ps
CPU time 2.62 seconds
Started Jul 31 05:38:47 PM PDT 24
Finished Jul 31 05:38:50 PM PDT 24
Peak memory 217196 kb
Host smart-e952e707-ea12-4c69-b94d-d562f280d47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661699831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3661699831
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.866884162
Short name T262
Test name
Test status
Simulation time 103378362 ps
CPU time 2.92 seconds
Started Jul 31 05:38:45 PM PDT 24
Finished Jul 31 05:38:48 PM PDT 24
Peak memory 219892 kb
Host smart-689139c2-6694-4ac8-ad0f-249f67a3fc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866884162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.866884162
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3028810988
Short name T96
Test name
Test status
Simulation time 251949449 ps
CPU time 4.11 seconds
Started Jul 31 05:38:48 PM PDT 24
Finished Jul 31 05:38:52 PM PDT 24
Peak memory 222068 kb
Host smart-4c2b782e-0439-4068-8b04-f430b5ad235b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028810988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3028810988
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.4236705662
Short name T796
Test name
Test status
Simulation time 89242425 ps
CPU time 3.46 seconds
Started Jul 31 05:38:47 PM PDT 24
Finished Jul 31 05:38:50 PM PDT 24
Peak memory 222352 kb
Host smart-2e1e175c-2604-4be2-adb1-5e5579de05bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236705662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.4236705662
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3349989617
Short name T718
Test name
Test status
Simulation time 66139488 ps
CPU time 2.31 seconds
Started Jul 31 05:38:43 PM PDT 24
Finished Jul 31 05:38:45 PM PDT 24
Peak memory 206176 kb
Host smart-1c956342-7e8e-4551-a433-719c329f0909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349989617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3349989617
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1774771966
Short name T514
Test name
Test status
Simulation time 64240524 ps
CPU time 3.05 seconds
Started Jul 31 05:38:42 PM PDT 24
Finished Jul 31 05:38:45 PM PDT 24
Peak memory 214344 kb
Host smart-ae7b8b67-24f4-4960-ba8b-6ce0d17d732d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774771966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1774771966
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.553050614
Short name T643
Test name
Test status
Simulation time 96037262 ps
CPU time 2.23 seconds
Started Jul 31 05:38:42 PM PDT 24
Finished Jul 31 05:38:45 PM PDT 24
Peak memory 208560 kb
Host smart-b8c94f80-8065-48b3-a54a-17ab5ee53f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553050614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.553050614
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.426063323
Short name T895
Test name
Test status
Simulation time 369713413 ps
CPU time 3.27 seconds
Started Jul 31 05:39:07 PM PDT 24
Finished Jul 31 05:39:11 PM PDT 24
Peak memory 209040 kb
Host smart-70425606-1b8b-403c-9037-b8d6273b4824
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426063323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.426063323
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2580557475
Short name T532
Test name
Test status
Simulation time 677397527 ps
CPU time 2.17 seconds
Started Jul 31 05:38:45 PM PDT 24
Finished Jul 31 05:38:47 PM PDT 24
Peak memory 206940 kb
Host smart-ed2a3038-0518-4e91-9cb2-ce7d016bab9c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580557475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2580557475
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.3259927633
Short name T595
Test name
Test status
Simulation time 159797671 ps
CPU time 2.32 seconds
Started Jul 31 05:38:42 PM PDT 24
Finished Jul 31 05:38:44 PM PDT 24
Peak memory 206840 kb
Host smart-d80a4e5e-2d6f-4991-8952-d383a850a4ea
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259927633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3259927633
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3702870491
Short name T406
Test name
Test status
Simulation time 1437116817 ps
CPU time 39.32 seconds
Started Jul 31 05:38:51 PM PDT 24
Finished Jul 31 05:39:31 PM PDT 24
Peak memory 208444 kb
Host smart-8c5f6628-2b60-4abb-ad40-ff15d4b93f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702870491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3702870491
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.404821339
Short name T766
Test name
Test status
Simulation time 53357200 ps
CPU time 2.47 seconds
Started Jul 31 05:38:45 PM PDT 24
Finished Jul 31 05:38:48 PM PDT 24
Peak memory 208216 kb
Host smart-29f0f18b-62e3-4520-aa9f-2d0e0d6a37f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404821339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.404821339
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.291770801
Short name T325
Test name
Test status
Simulation time 372849185 ps
CPU time 5.04 seconds
Started Jul 31 05:38:50 PM PDT 24
Finished Jul 31 05:38:56 PM PDT 24
Peak memory 209708 kb
Host smart-b6175e3f-5332-40ec-8e74-83fe792f2a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291770801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.291770801
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3053407459
Short name T847
Test name
Test status
Simulation time 305040065 ps
CPU time 3.3 seconds
Started Jul 31 05:38:48 PM PDT 24
Finished Jul 31 05:38:52 PM PDT 24
Peak memory 210200 kb
Host smart-053da398-b42c-43fc-b7f4-5d26d4aab998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053407459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3053407459
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3858212479
Short name T581
Test name
Test status
Simulation time 16378235 ps
CPU time 0.94 seconds
Started Jul 31 05:38:48 PM PDT 24
Finished Jul 31 05:38:49 PM PDT 24
Peak memory 206168 kb
Host smart-06ffe3cd-d447-4cad-abb0-707c003136e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858212479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3858212479
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2093723079
Short name T297
Test name
Test status
Simulation time 255032921 ps
CPU time 13.4 seconds
Started Jul 31 05:38:48 PM PDT 24
Finished Jul 31 05:39:01 PM PDT 24
Peak memory 214884 kb
Host smart-b6129018-7da4-47cb-ba41-35fb10e9576a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2093723079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2093723079
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.1247667097
Short name T42
Test name
Test status
Simulation time 87794129 ps
CPU time 2.37 seconds
Started Jul 31 05:38:50 PM PDT 24
Finished Jul 31 05:38:52 PM PDT 24
Peak memory 209588 kb
Host smart-b61b7235-6b43-45df-9c28-49ec7470367a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247667097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1247667097
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1628452532
Short name T291
Test name
Test status
Simulation time 5080028375 ps
CPU time 14.47 seconds
Started Jul 31 05:38:49 PM PDT 24
Finished Jul 31 05:39:03 PM PDT 24
Peak memory 220716 kb
Host smart-10a655c7-78b6-4c52-8d4f-5897ca723726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628452532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1628452532
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1606250427
Short name T87
Test name
Test status
Simulation time 55214944 ps
CPU time 1.94 seconds
Started Jul 31 05:38:48 PM PDT 24
Finished Jul 31 05:38:50 PM PDT 24
Peak memory 214332 kb
Host smart-219b7889-8836-4985-85c1-3c6e4c138274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606250427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1606250427
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3585966111
Short name T383
Test name
Test status
Simulation time 46696762 ps
CPU time 3.08 seconds
Started Jul 31 05:38:48 PM PDT 24
Finished Jul 31 05:38:51 PM PDT 24
Peak memory 214240 kb
Host smart-a3b67099-2f3a-4ae4-9d1b-a5ca157a8f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585966111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3585966111
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3162605315
Short name T862
Test name
Test status
Simulation time 139141049 ps
CPU time 2.43 seconds
Started Jul 31 05:38:49 PM PDT 24
Finished Jul 31 05:38:52 PM PDT 24
Peak memory 222440 kb
Host smart-fd448b62-e76c-4f12-9991-59d619c9e9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162605315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3162605315
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.108648959
Short name T386
Test name
Test status
Simulation time 773560385 ps
CPU time 4.68 seconds
Started Jul 31 05:38:50 PM PDT 24
Finished Jul 31 05:38:54 PM PDT 24
Peak memory 214344 kb
Host smart-5335b1d8-ece5-44b4-be14-333966fdba0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108648959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.108648959
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1985894102
Short name T730
Test name
Test status
Simulation time 310093091 ps
CPU time 3.21 seconds
Started Jul 31 05:38:48 PM PDT 24
Finished Jul 31 05:38:51 PM PDT 24
Peak memory 206860 kb
Host smart-ff0b6b49-2541-45ae-8527-11a8bfa09a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985894102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1985894102
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3979252909
Short name T620
Test name
Test status
Simulation time 455555453 ps
CPU time 5.53 seconds
Started Jul 31 05:38:50 PM PDT 24
Finished Jul 31 05:38:56 PM PDT 24
Peak memory 208244 kb
Host smart-9c89c30d-27e4-45af-ad27-6b7555a34cd6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979252909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3979252909
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2061837075
Short name T829
Test name
Test status
Simulation time 271623991 ps
CPU time 3.25 seconds
Started Jul 31 05:38:48 PM PDT 24
Finished Jul 31 05:38:52 PM PDT 24
Peak memory 209048 kb
Host smart-97d183d7-40f2-4d7a-a907-f7808782dbcd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061837075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2061837075
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3254764804
Short name T859
Test name
Test status
Simulation time 33636443 ps
CPU time 2.36 seconds
Started Jul 31 05:38:50 PM PDT 24
Finished Jul 31 05:38:52 PM PDT 24
Peak memory 208744 kb
Host smart-fbeaa239-0e98-4235-a18f-95932ffcdbeb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254764804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3254764804
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.943356463
Short name T699
Test name
Test status
Simulation time 579726938 ps
CPU time 3.7 seconds
Started Jul 31 05:38:49 PM PDT 24
Finished Jul 31 05:38:52 PM PDT 24
Peak memory 218520 kb
Host smart-bbdc832c-aa3b-4781-850f-6a1fd0250288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943356463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.943356463
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2240457023
Short name T833
Test name
Test status
Simulation time 891812104 ps
CPU time 19.27 seconds
Started Jul 31 05:38:48 PM PDT 24
Finished Jul 31 05:39:07 PM PDT 24
Peak memory 208128 kb
Host smart-2883fbf6-da6c-4072-aac7-eaabed670ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240457023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2240457023
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.524347658
Short name T306
Test name
Test status
Simulation time 228749959 ps
CPU time 12.14 seconds
Started Jul 31 05:38:48 PM PDT 24
Finished Jul 31 05:39:01 PM PDT 24
Peak memory 215112 kb
Host smart-9f13d927-315a-4cbc-a64b-e7b74c3a19b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524347658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.524347658
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.38090838
Short name T179
Test name
Test status
Simulation time 1174792856 ps
CPU time 12.37 seconds
Started Jul 31 05:38:47 PM PDT 24
Finished Jul 31 05:39:00 PM PDT 24
Peak memory 222468 kb
Host smart-f3384b85-1099-4565-a694-0e515472cb5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38090838 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.38090838
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2528619143
Short name T525
Test name
Test status
Simulation time 1100347887 ps
CPU time 4.67 seconds
Started Jul 31 05:38:49 PM PDT 24
Finished Jul 31 05:38:54 PM PDT 24
Peak memory 207160 kb
Host smart-206931e2-88cd-4c5a-a7b9-772c9fb2c50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528619143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2528619143
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1893128471
Short name T754
Test name
Test status
Simulation time 637674552 ps
CPU time 3.6 seconds
Started Jul 31 05:38:47 PM PDT 24
Finished Jul 31 05:38:51 PM PDT 24
Peak memory 210428 kb
Host smart-f662550b-0edd-44b0-b3d9-9c2632753c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893128471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1893128471
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2137866662
Short name T871
Test name
Test status
Simulation time 16956373 ps
CPU time 0.76 seconds
Started Jul 31 05:38:54 PM PDT 24
Finished Jul 31 05:38:55 PM PDT 24
Peak memory 205928 kb
Host smart-be3d88bf-7633-4031-84e1-c1f1df18a224
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137866662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2137866662
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3077248267
Short name T353
Test name
Test status
Simulation time 82436617 ps
CPU time 4.02 seconds
Started Jul 31 05:38:54 PM PDT 24
Finished Jul 31 05:38:59 PM PDT 24
Peak memory 214372 kb
Host smart-1761376f-7ea5-4968-bed2-994af3e44629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077248267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3077248267
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.786518380
Short name T88
Test name
Test status
Simulation time 744742978 ps
CPU time 8.89 seconds
Started Jul 31 05:38:52 PM PDT 24
Finished Jul 31 05:39:01 PM PDT 24
Peak memory 214396 kb
Host smart-b6882461-81c5-40e3-8bb7-b9272bdba727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786518380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.786518380
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1270264451
Short name T359
Test name
Test status
Simulation time 174911499 ps
CPU time 6.71 seconds
Started Jul 31 05:38:51 PM PDT 24
Finished Jul 31 05:38:57 PM PDT 24
Peak memory 214248 kb
Host smart-d852b228-4028-4ee3-8a10-fa332970fcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270264451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1270264451
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_random.2038547334
Short name T821
Test name
Test status
Simulation time 991121544 ps
CPU time 6.42 seconds
Started Jul 31 05:38:52 PM PDT 24
Finished Jul 31 05:38:58 PM PDT 24
Peak memory 214228 kb
Host smart-0e658016-6336-4720-9988-85032b7217d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038547334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2038547334
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.4141601238
Short name T345
Test name
Test status
Simulation time 133371810 ps
CPU time 3.89 seconds
Started Jul 31 05:38:47 PM PDT 24
Finished Jul 31 05:38:51 PM PDT 24
Peak memory 208340 kb
Host smart-7c1535e3-9416-4116-9317-9dc4d5101420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141601238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.4141601238
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2737110129
Short name T516
Test name
Test status
Simulation time 66041623 ps
CPU time 3.41 seconds
Started Jul 31 05:38:54 PM PDT 24
Finished Jul 31 05:38:57 PM PDT 24
Peak memory 208604 kb
Host smart-5a932ef7-9acb-47b7-a7df-6935bc5bc638
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737110129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2737110129
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3808672596
Short name T518
Test name
Test status
Simulation time 149501370 ps
CPU time 3.62 seconds
Started Jul 31 05:38:52 PM PDT 24
Finished Jul 31 05:38:56 PM PDT 24
Peak memory 208972 kb
Host smart-3b8823b8-79d9-4e9f-84be-5841968c39d9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808672596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3808672596
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1634324000
Short name T882
Test name
Test status
Simulation time 594614773 ps
CPU time 4.56 seconds
Started Jul 31 05:38:54 PM PDT 24
Finished Jul 31 05:38:59 PM PDT 24
Peak memory 208796 kb
Host smart-c787f22c-8a86-49dc-a75f-07eeca5c0594
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634324000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1634324000
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.4261640661
Short name T672
Test name
Test status
Simulation time 512318849 ps
CPU time 3.08 seconds
Started Jul 31 05:38:55 PM PDT 24
Finished Jul 31 05:38:58 PM PDT 24
Peak memory 214284 kb
Host smart-b7a571e5-c245-4c76-810a-02e0273df863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261640661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.4261640661
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2842543062
Short name T695
Test name
Test status
Simulation time 62097775 ps
CPU time 2.23 seconds
Started Jul 31 05:38:51 PM PDT 24
Finished Jul 31 05:38:53 PM PDT 24
Peak memory 206876 kb
Host smart-7409a24c-0cb4-485d-975a-2daf16169321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842543062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2842543062
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3835061332
Short name T494
Test name
Test status
Simulation time 121304810 ps
CPU time 3.81 seconds
Started Jul 31 05:38:53 PM PDT 24
Finished Jul 31 05:38:56 PM PDT 24
Peak memory 209564 kb
Host smart-ee4a682c-6cde-46ee-9fcc-349d833b8eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835061332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3835061332
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3942788751
Short name T495
Test name
Test status
Simulation time 50427798 ps
CPU time 1.55 seconds
Started Jul 31 05:38:54 PM PDT 24
Finished Jul 31 05:38:56 PM PDT 24
Peak memory 209924 kb
Host smart-d26c73ee-cb29-4a1d-8c87-749c4718bcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942788751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3942788751
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1253132871
Short name T739
Test name
Test status
Simulation time 12686035 ps
CPU time 0.77 seconds
Started Jul 31 05:38:59 PM PDT 24
Finished Jul 31 05:39:00 PM PDT 24
Peak memory 205956 kb
Host smart-60416028-40d0-4cf8-aef5-55dab5ce56f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253132871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1253132871
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1312050052
Short name T236
Test name
Test status
Simulation time 1076719555 ps
CPU time 29.01 seconds
Started Jul 31 05:38:53 PM PDT 24
Finished Jul 31 05:39:22 PM PDT 24
Peak memory 214520 kb
Host smart-96ed61fd-5f4e-4a7d-8160-e6be35921f03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1312050052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1312050052
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3470883079
Short name T21
Test name
Test status
Simulation time 58816406 ps
CPU time 1.27 seconds
Started Jul 31 05:38:59 PM PDT 24
Finished Jul 31 05:39:00 PM PDT 24
Peak memory 214876 kb
Host smart-87934ad0-9135-4459-a48a-be046323761f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470883079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3470883079
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.418309982
Short name T390
Test name
Test status
Simulation time 174668449 ps
CPU time 4.09 seconds
Started Jul 31 05:38:56 PM PDT 24
Finished Jul 31 05:39:00 PM PDT 24
Peak memory 209708 kb
Host smart-53439663-2d41-4705-828b-f7f29ce9bb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418309982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.418309982
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2571382644
Short name T289
Test name
Test status
Simulation time 192250428 ps
CPU time 8.7 seconds
Started Jul 31 05:39:00 PM PDT 24
Finished Jul 31 05:39:09 PM PDT 24
Peak memory 222348 kb
Host smart-affd96e4-cfe9-4ecc-a288-6d13f3a934a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571382644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2571382644
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.1558848077
Short name T764
Test name
Test status
Simulation time 225110432 ps
CPU time 3.27 seconds
Started Jul 31 05:38:56 PM PDT 24
Finished Jul 31 05:38:59 PM PDT 24
Peak memory 222424 kb
Host smart-af65b865-4943-45f8-a68a-b03371980269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558848077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1558848077
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.3692313659
Short name T627
Test name
Test status
Simulation time 757216935 ps
CPU time 5.58 seconds
Started Jul 31 05:38:52 PM PDT 24
Finished Jul 31 05:38:58 PM PDT 24
Peak memory 208964 kb
Host smart-cd3ed6d1-ad0e-4296-af7d-555ac7af7dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692313659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3692313659
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3734308689
Short name T717
Test name
Test status
Simulation time 301464647 ps
CPU time 2.32 seconds
Started Jul 31 05:38:51 PM PDT 24
Finished Jul 31 05:38:53 PM PDT 24
Peak memory 208748 kb
Host smart-4c3f0445-1ca3-4f44-8b60-306436ebec35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734308689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3734308689
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1494411100
Short name T660
Test name
Test status
Simulation time 86674185 ps
CPU time 3.86 seconds
Started Jul 31 05:38:54 PM PDT 24
Finished Jul 31 05:38:58 PM PDT 24
Peak memory 208752 kb
Host smart-6ec2e3f8-5b02-4835-9c06-910a2f8847f3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494411100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1494411100
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1840029220
Short name T318
Test name
Test status
Simulation time 387478498 ps
CPU time 4.22 seconds
Started Jul 31 05:38:52 PM PDT 24
Finished Jul 31 05:38:57 PM PDT 24
Peak memory 207020 kb
Host smart-730a4528-3229-4bfc-ac5f-c3049af1a393
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840029220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1840029220
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2796677966
Short name T826
Test name
Test status
Simulation time 54095956 ps
CPU time 2.21 seconds
Started Jul 31 05:38:55 PM PDT 24
Finished Jul 31 05:38:57 PM PDT 24
Peak memory 206908 kb
Host smart-daf6ad26-1be1-43af-a2b9-39297ad040d8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796677966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2796677966
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.4241540573
Short name T920
Test name
Test status
Simulation time 65045021 ps
CPU time 2.61 seconds
Started Jul 31 05:38:58 PM PDT 24
Finished Jul 31 05:39:01 PM PDT 24
Peak memory 209824 kb
Host smart-81f43bb2-35a7-46e3-9bc2-6e0ee19daf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241540573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.4241540573
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.4132463455
Short name T411
Test name
Test status
Simulation time 448410985 ps
CPU time 4.48 seconds
Started Jul 31 05:38:51 PM PDT 24
Finished Jul 31 05:38:55 PM PDT 24
Peak memory 208408 kb
Host smart-5e5fd91a-1f10-4335-8f9c-844681273273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132463455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.4132463455
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2979521663
Short name T216
Test name
Test status
Simulation time 23457516631 ps
CPU time 137.48 seconds
Started Jul 31 05:38:57 PM PDT 24
Finished Jul 31 05:41:15 PM PDT 24
Peak memory 216836 kb
Host smart-92af5851-c78e-4d94-841e-2cdb9ce67d17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979521663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2979521663
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.3594920944
Short name T124
Test name
Test status
Simulation time 2380721171 ps
CPU time 14.3 seconds
Started Jul 31 05:38:58 PM PDT 24
Finished Jul 31 05:39:12 PM PDT 24
Peak memory 222612 kb
Host smart-03b7cd95-2d29-4ee5-9e60-dd56e2e5f893
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594920944 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.3594920944
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2059472517
Short name T378
Test name
Test status
Simulation time 48481366 ps
CPU time 3.16 seconds
Started Jul 31 05:38:51 PM PDT 24
Finished Jul 31 05:38:55 PM PDT 24
Peak memory 214336 kb
Host smart-b904d132-8b1d-421b-90eb-850f85ea5d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059472517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2059472517
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.395491824
Short name T698
Test name
Test status
Simulation time 46334316 ps
CPU time 0.81 seconds
Started Jul 31 05:38:58 PM PDT 24
Finished Jul 31 05:38:59 PM PDT 24
Peak memory 205988 kb
Host smart-64d145ad-e0cc-4e2a-9748-41419155cf4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395491824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.395491824
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1627413669
Short name T418
Test name
Test status
Simulation time 520678337 ps
CPU time 12.85 seconds
Started Jul 31 05:38:58 PM PDT 24
Finished Jul 31 05:39:11 PM PDT 24
Peak memory 214788 kb
Host smart-63d320d5-856f-4114-a6d5-6ce34a07fdb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1627413669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1627413669
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.497605389
Short name T714
Test name
Test status
Simulation time 132601530 ps
CPU time 2.51 seconds
Started Jul 31 05:38:58 PM PDT 24
Finished Jul 31 05:39:01 PM PDT 24
Peak memory 208248 kb
Host smart-248cdcd1-27ba-4ea8-ac64-f40bd29d13d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497605389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.497605389
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.3213840470
Short name T288
Test name
Test status
Simulation time 112253982 ps
CPU time 3.75 seconds
Started Jul 31 05:38:59 PM PDT 24
Finished Jul 31 05:39:02 PM PDT 24
Peak memory 222448 kb
Host smart-7f7e8085-6705-45d9-a6a2-9bf0d85266d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213840470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3213840470
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2343830760
Short name T461
Test name
Test status
Simulation time 78640646 ps
CPU time 2.73 seconds
Started Jul 31 05:38:59 PM PDT 24
Finished Jul 31 05:39:02 PM PDT 24
Peak memory 209072 kb
Host smart-7037eb19-130c-4707-a325-8c7bdb3984e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343830760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2343830760
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3717611023
Short name T774
Test name
Test status
Simulation time 216131380 ps
CPU time 4.86 seconds
Started Jul 31 05:38:57 PM PDT 24
Finished Jul 31 05:39:02 PM PDT 24
Peak memory 209316 kb
Host smart-73016a47-5531-4ee3-aefd-03203baccbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717611023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3717611023
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3840272700
Short name T352
Test name
Test status
Simulation time 54082968 ps
CPU time 3.08 seconds
Started Jul 31 05:39:02 PM PDT 24
Finished Jul 31 05:39:05 PM PDT 24
Peak memory 207072 kb
Host smart-6768e462-ba92-4871-80fb-0720f34b0449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840272700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3840272700
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2744871138
Short name T545
Test name
Test status
Simulation time 612820268 ps
CPU time 14.87 seconds
Started Jul 31 05:38:58 PM PDT 24
Finished Jul 31 05:39:13 PM PDT 24
Peak memory 208064 kb
Host smart-ff05e7cf-d7cc-451b-ab6c-55651e1b5b83
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744871138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2744871138
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.4151127965
Short name T849
Test name
Test status
Simulation time 4561091184 ps
CPU time 47.35 seconds
Started Jul 31 05:39:06 PM PDT 24
Finished Jul 31 05:39:54 PM PDT 24
Peak memory 208592 kb
Host smart-34e8f680-496b-451b-bcbf-447d93055db4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151127965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.4151127965
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.4105018407
Short name T464
Test name
Test status
Simulation time 129910256 ps
CPU time 2.48 seconds
Started Jul 31 05:38:56 PM PDT 24
Finished Jul 31 05:38:59 PM PDT 24
Peak memory 206756 kb
Host smart-0cd43d89-1b9c-4ac3-9f6e-2b519d61c7a8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105018407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.4105018407
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1790461540
Short name T769
Test name
Test status
Simulation time 96586221 ps
CPU time 1.39 seconds
Started Jul 31 05:38:59 PM PDT 24
Finished Jul 31 05:39:00 PM PDT 24
Peak memory 207472 kb
Host smart-b71721be-5e05-4263-b178-73b799bea97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790461540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1790461540
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1908567032
Short name T431
Test name
Test status
Simulation time 1260397264 ps
CPU time 21.14 seconds
Started Jul 31 05:38:59 PM PDT 24
Finished Jul 31 05:39:20 PM PDT 24
Peak memory 208480 kb
Host smart-9f1a1cbd-30b7-4f92-b550-e5fa8e80827c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908567032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1908567032
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.3009737546
Short name T746
Test name
Test status
Simulation time 869495951 ps
CPU time 8.44 seconds
Started Jul 31 05:39:07 PM PDT 24
Finished Jul 31 05:39:16 PM PDT 24
Peak memory 222480 kb
Host smart-fac37135-b5db-495b-bf3c-fc2dd2bc8c02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009737546 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.3009737546
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.1938596152
Short name T840
Test name
Test status
Simulation time 667550928 ps
CPU time 9.31 seconds
Started Jul 31 05:39:08 PM PDT 24
Finished Jul 31 05:39:17 PM PDT 24
Peak memory 214312 kb
Host smart-743228db-ced0-47a3-8297-26e76dac6eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938596152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1938596152
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2198477614
Short name T457
Test name
Test status
Simulation time 1096689602 ps
CPU time 3.46 seconds
Started Jul 31 05:38:56 PM PDT 24
Finished Jul 31 05:39:00 PM PDT 24
Peak memory 210628 kb
Host smart-778a6108-83e4-4756-a327-de617bfa2572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198477614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2198477614
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2639736653
Short name T896
Test name
Test status
Simulation time 86650704 ps
CPU time 0.77 seconds
Started Jul 31 05:39:05 PM PDT 24
Finished Jul 31 05:39:06 PM PDT 24
Peak memory 205900 kb
Host smart-62fce439-678b-4370-abad-39ca88bcd4fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639736653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2639736653
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3515847834
Short name T776
Test name
Test status
Simulation time 267864991 ps
CPU time 3.73 seconds
Started Jul 31 05:39:05 PM PDT 24
Finished Jul 31 05:39:08 PM PDT 24
Peak memory 214484 kb
Host smart-533778ee-1524-42ed-a8b1-ca7f371e49de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515847834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3515847834
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1147456502
Short name T350
Test name
Test status
Simulation time 189026095 ps
CPU time 2.93 seconds
Started Jul 31 05:39:03 PM PDT 24
Finished Jul 31 05:39:06 PM PDT 24
Peak memory 207400 kb
Host smart-6b4ce571-554a-48a7-b0b1-e5def0651214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147456502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1147456502
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1307606142
Short name T301
Test name
Test status
Simulation time 49448170 ps
CPU time 2.11 seconds
Started Jul 31 05:39:03 PM PDT 24
Finished Jul 31 05:39:06 PM PDT 24
Peak memory 214692 kb
Host smart-091a63f1-b9fa-45ee-80f3-8c023e5ebc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307606142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1307606142
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1848248971
Short name T53
Test name
Test status
Simulation time 95164481 ps
CPU time 2.85 seconds
Started Jul 31 05:39:03 PM PDT 24
Finished Jul 31 05:39:06 PM PDT 24
Peak memory 222564 kb
Host smart-db016507-8019-44ce-b530-422e097978fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848248971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1848248971
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3149712908
Short name T389
Test name
Test status
Simulation time 1079818609 ps
CPU time 6.36 seconds
Started Jul 31 05:39:05 PM PDT 24
Finished Jul 31 05:39:12 PM PDT 24
Peak memory 207588 kb
Host smart-0439f050-f42f-4f2f-8533-3eac5af7bb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149712908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3149712908
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.929898852
Short name T602
Test name
Test status
Simulation time 88156079 ps
CPU time 1.99 seconds
Started Jul 31 05:38:57 PM PDT 24
Finished Jul 31 05:38:59 PM PDT 24
Peak memory 208776 kb
Host smart-17be0fe3-fe45-47e4-9d20-31a215fa40f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929898852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.929898852
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1692996667
Short name T438
Test name
Test status
Simulation time 246453528 ps
CPU time 6.84 seconds
Started Jul 31 05:38:58 PM PDT 24
Finished Jul 31 05:39:05 PM PDT 24
Peak memory 208444 kb
Host smart-96415899-f72c-4379-9b9b-445690898e3d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692996667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1692996667
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.4049706108
Short name T865
Test name
Test status
Simulation time 2758116386 ps
CPU time 25.77 seconds
Started Jul 31 05:39:07 PM PDT 24
Finished Jul 31 05:39:33 PM PDT 24
Peak memory 208480 kb
Host smart-6ec6743d-30b3-4ffe-870b-de50200ce5ab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049706108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.4049706108
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.4067084429
Short name T777
Test name
Test status
Simulation time 1579306287 ps
CPU time 40.91 seconds
Started Jul 31 05:39:09 PM PDT 24
Finished Jul 31 05:39:50 PM PDT 24
Peak memory 208808 kb
Host smart-1cc33a24-5ad1-4997-91cd-e6965f438770
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067084429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.4067084429
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.2019799048
Short name T794
Test name
Test status
Simulation time 3454162754 ps
CPU time 37 seconds
Started Jul 31 05:39:07 PM PDT 24
Finished Jul 31 05:39:44 PM PDT 24
Peak memory 210420 kb
Host smart-7275df26-c460-411a-95fe-073eb477ac37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019799048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2019799048
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.1356762310
Short name T566
Test name
Test status
Simulation time 31428338 ps
CPU time 2.05 seconds
Started Jul 31 05:39:07 PM PDT 24
Finished Jul 31 05:39:09 PM PDT 24
Peak memory 207428 kb
Host smart-9fa019eb-4ade-4ece-ad54-0454a4425602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356762310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1356762310
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3876261836
Short name T881
Test name
Test status
Simulation time 275376882 ps
CPU time 17.29 seconds
Started Jul 31 05:39:04 PM PDT 24
Finished Jul 31 05:39:21 PM PDT 24
Peak memory 221192 kb
Host smart-2ea94aaa-6258-451a-8597-a44c9a424eb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876261836 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3876261836
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1350948472
Short name T346
Test name
Test status
Simulation time 818055198 ps
CPU time 6.87 seconds
Started Jul 31 05:39:06 PM PDT 24
Finished Jul 31 05:39:13 PM PDT 24
Peak memory 207820 kb
Host smart-2c119a8f-e764-43af-b029-3d8cc0ee9736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350948472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1350948472
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3284474805
Short name T398
Test name
Test status
Simulation time 97194399 ps
CPU time 2.91 seconds
Started Jul 31 05:39:04 PM PDT 24
Finished Jul 31 05:39:07 PM PDT 24
Peak memory 210248 kb
Host smart-f94bdfb1-0de2-4dfd-9cc7-8cae03648d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284474805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3284474805
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.926890733
Short name T81
Test name
Test status
Simulation time 19402268 ps
CPU time 0.89 seconds
Started Jul 31 05:39:02 PM PDT 24
Finished Jul 31 05:39:03 PM PDT 24
Peak memory 205936 kb
Host smart-1ec8f8ab-ed00-40e0-adef-4b4b7acd5f5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926890733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.926890733
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.487770392
Short name T4
Test name
Test status
Simulation time 331725725 ps
CPU time 3.18 seconds
Started Jul 31 05:39:08 PM PDT 24
Finished Jul 31 05:39:11 PM PDT 24
Peak memory 218592 kb
Host smart-545e57c8-532a-48e6-b8b2-26062a12fa89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487770392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.487770392
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3336321135
Short name T300
Test name
Test status
Simulation time 21594590 ps
CPU time 1.65 seconds
Started Jul 31 05:39:05 PM PDT 24
Finished Jul 31 05:39:07 PM PDT 24
Peak memory 206780 kb
Host smart-24760467-b735-4141-8995-02771ca0c98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336321135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3336321135
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.904829035
Short name T856
Test name
Test status
Simulation time 4851011260 ps
CPU time 39.59 seconds
Started Jul 31 05:39:05 PM PDT 24
Finished Jul 31 05:39:44 PM PDT 24
Peak memory 214384 kb
Host smart-39deba7e-45bf-4517-bb90-170b44bba1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904829035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.904829035
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.3643797154
Short name T247
Test name
Test status
Simulation time 682685307 ps
CPU time 3.28 seconds
Started Jul 31 05:39:04 PM PDT 24
Finished Jul 31 05:39:07 PM PDT 24
Peak memory 220676 kb
Host smart-8c352e47-5e03-4f34-ba94-4435bb776400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643797154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3643797154
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3255074883
Short name T57
Test name
Test status
Simulation time 124684235 ps
CPU time 2.92 seconds
Started Jul 31 05:39:03 PM PDT 24
Finished Jul 31 05:39:06 PM PDT 24
Peak memory 218936 kb
Host smart-26810753-1ab4-4688-a00b-8aa9ea2cbc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255074883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3255074883
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.617785173
Short name T508
Test name
Test status
Simulation time 736115206 ps
CPU time 8.66 seconds
Started Jul 31 05:39:05 PM PDT 24
Finished Jul 31 05:39:14 PM PDT 24
Peak memory 209064 kb
Host smart-aef7203d-c8a3-407d-9ba3-476253160355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617785173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.617785173
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2551806401
Short name T784
Test name
Test status
Simulation time 23635412 ps
CPU time 2.03 seconds
Started Jul 31 05:39:05 PM PDT 24
Finished Jul 31 05:39:07 PM PDT 24
Peak memory 208604 kb
Host smart-2261b12e-87c3-4faf-a96e-29f2db7cb1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551806401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2551806401
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2580234939
Short name T351
Test name
Test status
Simulation time 74478664 ps
CPU time 3.09 seconds
Started Jul 31 05:39:08 PM PDT 24
Finished Jul 31 05:39:11 PM PDT 24
Peak memory 207408 kb
Host smart-2b56bdce-5e36-48f6-88a0-58b6f99477c3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580234939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2580234939
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3815173862
Short name T445
Test name
Test status
Simulation time 1356124466 ps
CPU time 14.65 seconds
Started Jul 31 05:39:03 PM PDT 24
Finished Jul 31 05:39:17 PM PDT 24
Peak memory 208124 kb
Host smart-5f2b02f1-4792-40b9-aef4-ff0880d88d10
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815173862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3815173862
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.697331247
Short name T588
Test name
Test status
Simulation time 591783990 ps
CPU time 3.55 seconds
Started Jul 31 05:39:05 PM PDT 24
Finished Jul 31 05:39:09 PM PDT 24
Peak memory 206872 kb
Host smart-bec7dc29-f578-461f-994d-639e2b9a2822
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697331247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.697331247
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2782376918
Short name T551
Test name
Test status
Simulation time 169055832 ps
CPU time 3.82 seconds
Started Jul 31 05:39:04 PM PDT 24
Finished Jul 31 05:39:08 PM PDT 24
Peak memory 209012 kb
Host smart-4e5a2dac-b455-4886-8cf1-4f5e232dc70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782376918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2782376918
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2173426469
Short name T801
Test name
Test status
Simulation time 201255110 ps
CPU time 5.08 seconds
Started Jul 31 05:39:05 PM PDT 24
Finished Jul 31 05:39:10 PM PDT 24
Peak memory 208100 kb
Host smart-74e6e290-dcd7-4408-bcf8-c69f1d7de1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173426469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2173426469
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.4014595276
Short name T225
Test name
Test status
Simulation time 4603730408 ps
CPU time 45.28 seconds
Started Jul 31 05:39:02 PM PDT 24
Finished Jul 31 05:39:48 PM PDT 24
Peak memory 222468 kb
Host smart-7bbd0091-1c32-47a6-9c95-8fa8d742f413
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014595276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.4014595276
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.2965734422
Short name T394
Test name
Test status
Simulation time 1174499803 ps
CPU time 16.97 seconds
Started Jul 31 05:39:01 PM PDT 24
Finished Jul 31 05:39:19 PM PDT 24
Peak memory 222560 kb
Host smart-4214801a-ac09-4fa3-9580-5a308980736e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965734422 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.2965734422
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2201271375
Short name T573
Test name
Test status
Simulation time 164688594 ps
CPU time 6.96 seconds
Started Jul 31 05:39:06 PM PDT 24
Finished Jul 31 05:39:13 PM PDT 24
Peak memory 214336 kb
Host smart-4dd18e1a-6c2d-41fb-8a53-5b3089387c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201271375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2201271375
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1707410898
Short name T611
Test name
Test status
Simulation time 242398598 ps
CPU time 1.97 seconds
Started Jul 31 05:39:06 PM PDT 24
Finished Jul 31 05:39:09 PM PDT 24
Peak memory 209728 kb
Host smart-febd3d81-6c07-4b0a-bcd6-c86575bb85b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707410898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1707410898
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2009305764
Short name T13
Test name
Test status
Simulation time 10852068 ps
CPU time 0.86 seconds
Started Jul 31 05:36:31 PM PDT 24
Finished Jul 31 05:36:32 PM PDT 24
Peak memory 205980 kb
Host smart-69e4379d-5e1a-41e3-bed2-b06902e17610
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009305764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2009305764
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.224614283
Short name T190
Test name
Test status
Simulation time 4086079921 ps
CPU time 50.43 seconds
Started Jul 31 05:36:26 PM PDT 24
Finished Jul 31 05:37:16 PM PDT 24
Peak memory 215504 kb
Host smart-07ad12f1-6f94-47c6-81a5-abf4a8f436e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=224614283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.224614283
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2679258526
Short name T844
Test name
Test status
Simulation time 1426860730 ps
CPU time 34.76 seconds
Started Jul 31 05:36:23 PM PDT 24
Finished Jul 31 05:36:58 PM PDT 24
Peak memory 214312 kb
Host smart-0783bfc2-109f-4f22-8c7a-b8188a28cdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679258526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2679258526
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.4192087723
Short name T339
Test name
Test status
Simulation time 1016858684 ps
CPU time 10.54 seconds
Started Jul 31 05:36:24 PM PDT 24
Finished Jul 31 05:36:35 PM PDT 24
Peak memory 222028 kb
Host smart-b8f165d0-3356-41ff-880b-f08a5b0ae675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192087723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.4192087723
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3904793278
Short name T751
Test name
Test status
Simulation time 198680361 ps
CPU time 3.22 seconds
Started Jul 31 05:36:23 PM PDT 24
Finished Jul 31 05:36:26 PM PDT 24
Peak memory 214212 kb
Host smart-1369ec01-411b-4ca9-b795-7aaa42ebcee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904793278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3904793278
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.279678647
Short name T565
Test name
Test status
Simulation time 122277478 ps
CPU time 3.43 seconds
Started Jul 31 05:36:26 PM PDT 24
Finished Jul 31 05:36:30 PM PDT 24
Peak memory 209752 kb
Host smart-1f826b75-050c-4556-ba79-6ff8364da4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279678647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.279678647
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3514904519
Short name T558
Test name
Test status
Simulation time 143256560 ps
CPU time 5.61 seconds
Started Jul 31 05:36:24 PM PDT 24
Finished Jul 31 05:36:30 PM PDT 24
Peak memory 214308 kb
Host smart-894b644f-8f2c-49d1-8e5d-3eb9aa81e4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514904519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3514904519
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1293462770
Short name T600
Test name
Test status
Simulation time 266262859 ps
CPU time 6.86 seconds
Started Jul 31 05:36:25 PM PDT 24
Finished Jul 31 05:36:32 PM PDT 24
Peak memory 208984 kb
Host smart-e4b983a1-887c-4d76-b566-57faa0cf6da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293462770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1293462770
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3902936930
Short name T741
Test name
Test status
Simulation time 390071010 ps
CPU time 3.6 seconds
Started Jul 31 05:36:28 PM PDT 24
Finished Jul 31 05:36:32 PM PDT 24
Peak memory 208644 kb
Host smart-3009a597-41ac-4402-82c3-37729e5ba3de
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902936930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3902936930
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.4287989783
Short name T474
Test name
Test status
Simulation time 140197078 ps
CPU time 3.55 seconds
Started Jul 31 05:36:29 PM PDT 24
Finished Jul 31 05:36:33 PM PDT 24
Peak memory 208692 kb
Host smart-ce85fedd-b584-44e5-9681-e20526f91222
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287989783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.4287989783
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1392591579
Short name T574
Test name
Test status
Simulation time 394781717 ps
CPU time 7.53 seconds
Started Jul 31 05:36:28 PM PDT 24
Finished Jul 31 05:36:36 PM PDT 24
Peak memory 208088 kb
Host smart-0ba901a3-45b3-4cc0-9805-af2c90138659
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392591579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1392591579
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1203521548
Short name T824
Test name
Test status
Simulation time 573547335 ps
CPU time 3.21 seconds
Started Jul 31 05:36:30 PM PDT 24
Finished Jul 31 05:36:33 PM PDT 24
Peak memory 218252 kb
Host smart-ea10ad2b-85ca-4772-bd0b-32ac46799ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203521548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1203521548
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1224422188
Short name T615
Test name
Test status
Simulation time 403767331 ps
CPU time 3.14 seconds
Started Jul 31 05:36:24 PM PDT 24
Finished Jul 31 05:36:27 PM PDT 24
Peak memory 208608 kb
Host smart-6c713c60-47f3-42a5-8ca4-f643d32c684e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224422188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1224422188
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2042233955
Short name T742
Test name
Test status
Simulation time 1768470450 ps
CPU time 17.52 seconds
Started Jul 31 05:36:27 PM PDT 24
Finished Jul 31 05:36:45 PM PDT 24
Peak memory 208876 kb
Host smart-2fc37518-0163-4463-b64a-ee323e2edcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042233955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2042233955
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.343001329
Short name T134
Test name
Test status
Simulation time 469572349 ps
CPU time 3 seconds
Started Jul 31 05:36:22 PM PDT 24
Finished Jul 31 05:36:25 PM PDT 24
Peak memory 210496 kb
Host smart-ac649267-b907-4258-98a6-cf9bd4328f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343001329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.343001329
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3253666350
Short name T763
Test name
Test status
Simulation time 56301628 ps
CPU time 0.9 seconds
Started Jul 31 05:36:37 PM PDT 24
Finished Jul 31 05:36:38 PM PDT 24
Peak memory 206208 kb
Host smart-996eb0ce-5edc-42b7-b17b-ad013d5cb550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253666350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3253666350
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1842440984
Short name T628
Test name
Test status
Simulation time 516839122 ps
CPU time 7.07 seconds
Started Jul 31 05:36:29 PM PDT 24
Finished Jul 31 05:36:36 PM PDT 24
Peak memory 219772 kb
Host smart-6434c56d-6cce-4e4a-a6f6-da8146766eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842440984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1842440984
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1784610093
Short name T240
Test name
Test status
Simulation time 2144487645 ps
CPU time 75.09 seconds
Started Jul 31 05:36:31 PM PDT 24
Finished Jul 31 05:37:47 PM PDT 24
Peak memory 214284 kb
Host smart-782f20a7-9148-481c-bc6e-8a0f05836ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784610093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1784610093
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1513285293
Short name T868
Test name
Test status
Simulation time 83474548 ps
CPU time 3.4 seconds
Started Jul 31 05:36:35 PM PDT 24
Finished Jul 31 05:36:38 PM PDT 24
Peak memory 222504 kb
Host smart-bc294539-2055-4173-9afd-8f1c7b018833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513285293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1513285293
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3848564073
Short name T901
Test name
Test status
Simulation time 155591716 ps
CPU time 3.36 seconds
Started Jul 31 05:36:35 PM PDT 24
Finished Jul 31 05:36:38 PM PDT 24
Peak memory 214316 kb
Host smart-12cd1a16-abc2-4dfa-8305-8210f372a4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848564073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3848564073
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.685427468
Short name T800
Test name
Test status
Simulation time 266638495 ps
CPU time 4.5 seconds
Started Jul 31 05:36:31 PM PDT 24
Finished Jul 31 05:36:36 PM PDT 24
Peak memory 207628 kb
Host smart-f8d39a5f-ed39-4b68-8142-b9232b7e362c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685427468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.685427468
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.212648758
Short name T747
Test name
Test status
Simulation time 82572525 ps
CPU time 3.01 seconds
Started Jul 31 05:36:30 PM PDT 24
Finished Jul 31 05:36:33 PM PDT 24
Peak memory 206932 kb
Host smart-c9a1aefb-dda3-4213-9fbc-a8153c410f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212648758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.212648758
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1154730813
Short name T513
Test name
Test status
Simulation time 65149658 ps
CPU time 3.26 seconds
Started Jul 31 05:36:30 PM PDT 24
Finished Jul 31 05:36:34 PM PDT 24
Peak memory 208696 kb
Host smart-9dac3bc6-621c-4b51-a634-8ba3f515af6b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154730813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1154730813
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2261793904
Short name T319
Test name
Test status
Simulation time 1309845569 ps
CPU time 3.13 seconds
Started Jul 31 05:36:31 PM PDT 24
Finished Jul 31 05:36:34 PM PDT 24
Peak memory 206968 kb
Host smart-6bcb4022-04f4-4c3a-97bc-eb6d66d4eff7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261793904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2261793904
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3085780925
Short name T468
Test name
Test status
Simulation time 299572385 ps
CPU time 2.61 seconds
Started Jul 31 05:36:29 PM PDT 24
Finished Jul 31 05:36:32 PM PDT 24
Peak memory 206896 kb
Host smart-9407dc37-f966-4a1c-963c-e8246691c1f7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085780925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3085780925
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2151153881
Short name T293
Test name
Test status
Simulation time 267628455 ps
CPU time 3.69 seconds
Started Jul 31 05:36:36 PM PDT 24
Finished Jul 31 05:36:40 PM PDT 24
Peak memory 210288 kb
Host smart-3b5a1f78-e0db-4854-877f-4594575aabb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151153881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2151153881
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.825384190
Short name T454
Test name
Test status
Simulation time 191592005 ps
CPU time 4.37 seconds
Started Jul 31 05:36:31 PM PDT 24
Finished Jul 31 05:36:35 PM PDT 24
Peak memory 206812 kb
Host smart-a91cf3c2-e4fb-495c-95ad-39aa1860d75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825384190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.825384190
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.4032105680
Short name T760
Test name
Test status
Simulation time 568819306 ps
CPU time 21.96 seconds
Started Jul 31 05:36:36 PM PDT 24
Finished Jul 31 05:36:58 PM PDT 24
Peak memory 216192 kb
Host smart-985ec508-f137-4edc-be84-00ac9440e43b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032105680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.4032105680
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3176104450
Short name T721
Test name
Test status
Simulation time 193313827 ps
CPU time 3.57 seconds
Started Jul 31 05:36:31 PM PDT 24
Finished Jul 31 05:36:35 PM PDT 24
Peak memory 207656 kb
Host smart-141f9e2a-0a81-4663-b9e2-c0ef81abcb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176104450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3176104450
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.597710423
Short name T400
Test name
Test status
Simulation time 87970591 ps
CPU time 2.05 seconds
Started Jul 31 05:36:36 PM PDT 24
Finished Jul 31 05:36:38 PM PDT 24
Peak memory 210160 kb
Host smart-aef55df4-062c-4391-9f41-e57cba86ae32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597710423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.597710423
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.844137488
Short name T873
Test name
Test status
Simulation time 13964567 ps
CPU time 0.76 seconds
Started Jul 31 05:36:42 PM PDT 24
Finished Jul 31 05:36:43 PM PDT 24
Peak memory 205984 kb
Host smart-1612446d-2386-4bbc-a2f5-11f1e32cec7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844137488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.844137488
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2722086585
Short name T108
Test name
Test status
Simulation time 810710630 ps
CPU time 10.78 seconds
Started Jul 31 05:36:43 PM PDT 24
Finished Jul 31 05:36:54 PM PDT 24
Peak memory 214252 kb
Host smart-f1bc0df4-0dad-4924-bef1-436af2865eba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2722086585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2722086585
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.967770151
Short name T32
Test name
Test status
Simulation time 59781938 ps
CPU time 2.34 seconds
Started Jul 31 05:36:42 PM PDT 24
Finished Jul 31 05:36:45 PM PDT 24
Peak memory 220316 kb
Host smart-95e301fa-d235-46ba-930c-330ad4a435f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967770151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.967770151
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.531391367
Short name T523
Test name
Test status
Simulation time 102824980 ps
CPU time 2.85 seconds
Started Jul 31 05:36:41 PM PDT 24
Finished Jul 31 05:36:44 PM PDT 24
Peak memory 207936 kb
Host smart-19848641-337f-48a9-bdb7-5004e212c2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531391367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.531391367
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.763865593
Short name T103
Test name
Test status
Simulation time 83297879 ps
CPU time 3.99 seconds
Started Jul 31 05:36:42 PM PDT 24
Finished Jul 31 05:36:46 PM PDT 24
Peak memory 208936 kb
Host smart-bca559eb-e248-400d-8d38-03dba2e251fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763865593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.763865593
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3127106066
Short name T683
Test name
Test status
Simulation time 75515772 ps
CPU time 1.85 seconds
Started Jul 31 05:36:42 PM PDT 24
Finished Jul 31 05:36:44 PM PDT 24
Peak memory 219800 kb
Host smart-0d7eece6-a311-45d8-a75b-e6c84e4bdafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127106066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3127106066
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.808741419
Short name T455
Test name
Test status
Simulation time 57446066 ps
CPU time 2.19 seconds
Started Jul 31 05:36:49 PM PDT 24
Finished Jul 31 05:36:51 PM PDT 24
Peak memory 206724 kb
Host smart-4c5ddb55-6675-4150-9fae-bbb708a04cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808741419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.808741419
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.2482510949
Short name T347
Test name
Test status
Simulation time 2826828006 ps
CPU time 15.27 seconds
Started Jul 31 05:36:48 PM PDT 24
Finished Jul 31 05:37:03 PM PDT 24
Peak memory 214344 kb
Host smart-41849ed3-c65c-42ff-9476-ba908d230d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482510949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2482510949
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.527743045
Short name T459
Test name
Test status
Simulation time 612910474 ps
CPU time 18.29 seconds
Started Jul 31 05:36:37 PM PDT 24
Finished Jul 31 05:36:56 PM PDT 24
Peak memory 208056 kb
Host smart-8d3004c8-b6b2-4d0e-95f7-05d16fd08f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527743045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.527743045
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.4031573827
Short name T671
Test name
Test status
Simulation time 109329624 ps
CPU time 2.86 seconds
Started Jul 31 05:36:33 PM PDT 24
Finished Jul 31 05:36:36 PM PDT 24
Peak memory 209032 kb
Host smart-0423e4da-aef0-498a-83c5-bc88e4cbf757
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031573827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.4031573827
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3383030607
Short name T475
Test name
Test status
Simulation time 1217494114 ps
CPU time 13.18 seconds
Started Jul 31 05:36:36 PM PDT 24
Finished Jul 31 05:36:49 PM PDT 24
Peak memory 208288 kb
Host smart-906884ff-df08-40d2-af72-530a75fc25bf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383030607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3383030607
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3104448926
Short name T818
Test name
Test status
Simulation time 66946258 ps
CPU time 3.15 seconds
Started Jul 31 05:36:37 PM PDT 24
Finished Jul 31 05:36:41 PM PDT 24
Peak memory 208856 kb
Host smart-c872c77e-439e-4127-9122-2e0478313461
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104448926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3104448926
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1967029503
Short name T869
Test name
Test status
Simulation time 45650219 ps
CPU time 2.57 seconds
Started Jul 31 05:36:39 PM PDT 24
Finished Jul 31 05:36:42 PM PDT 24
Peak memory 209824 kb
Host smart-8ea15957-ade8-4f1e-85fd-6e19e4412b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967029503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1967029503
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3594060000
Short name T571
Test name
Test status
Simulation time 319089005 ps
CPU time 3.22 seconds
Started Jul 31 05:36:37 PM PDT 24
Finished Jul 31 05:36:41 PM PDT 24
Peak memory 208376 kb
Host smart-27f837a1-7111-4cae-b069-752246952ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594060000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3594060000
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2219783185
Short name T904
Test name
Test status
Simulation time 91339895 ps
CPU time 2.44 seconds
Started Jul 31 05:36:42 PM PDT 24
Finished Jul 31 05:36:45 PM PDT 24
Peak memory 208816 kb
Host smart-dceb2a5d-9110-49a1-9db5-ade64461a596
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219783185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2219783185
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.2873272592
Short name T182
Test name
Test status
Simulation time 277378958 ps
CPU time 10.63 seconds
Started Jul 31 05:36:42 PM PDT 24
Finished Jul 31 05:36:53 PM PDT 24
Peak memory 220960 kb
Host smart-fdf69529-47ca-4b0e-a6e2-cc0bb02c79ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873272592 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.2873272592
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2013322406
Short name T690
Test name
Test status
Simulation time 101676361 ps
CPU time 4.68 seconds
Started Jul 31 05:36:49 PM PDT 24
Finished Jul 31 05:36:54 PM PDT 24
Peak memory 208784 kb
Host smart-208e1b86-13e0-4de5-8d1b-b1a94120a345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013322406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2013322406
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.949374785
Short name T531
Test name
Test status
Simulation time 103125057 ps
CPU time 0.76 seconds
Started Jul 31 05:36:48 PM PDT 24
Finished Jul 31 05:36:49 PM PDT 24
Peak memory 205952 kb
Host smart-0d4ec097-b9d4-4f95-8954-e1563d09f46c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949374785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.949374785
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.390598854
Short name T218
Test name
Test status
Simulation time 67154392 ps
CPU time 3.88 seconds
Started Jul 31 05:36:41 PM PDT 24
Finished Jul 31 05:36:45 PM PDT 24
Peak memory 210052 kb
Host smart-581768cc-ed85-418a-bc8b-2e84dfca01e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390598854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.390598854
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2347957204
Short name T589
Test name
Test status
Simulation time 485527582 ps
CPU time 11.98 seconds
Started Jul 31 05:36:42 PM PDT 24
Finished Jul 31 05:36:54 PM PDT 24
Peak memory 218132 kb
Host smart-1f5f79c9-3a0f-4e30-a7c3-b2942057beee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347957204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2347957204
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1067772265
Short name T712
Test name
Test status
Simulation time 623434311 ps
CPU time 4.13 seconds
Started Jul 31 05:36:42 PM PDT 24
Finished Jul 31 05:36:47 PM PDT 24
Peak memory 214324 kb
Host smart-fed2e582-fcf0-46f9-a506-fe6c328e14f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067772265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1067772265
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2810410079
Short name T395
Test name
Test status
Simulation time 126418036 ps
CPU time 2.65 seconds
Started Jul 31 05:36:48 PM PDT 24
Finished Jul 31 05:36:52 PM PDT 24
Peak memory 214236 kb
Host smart-e6d0c395-17e6-4468-8a0c-bb07c4cafb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810410079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2810410079
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.363596784
Short name T674
Test name
Test status
Simulation time 197380129 ps
CPU time 2.38 seconds
Started Jul 31 05:36:48 PM PDT 24
Finished Jul 31 05:36:51 PM PDT 24
Peak memory 210212 kb
Host smart-0ed1a3e3-3d9e-479d-90e4-f8f874bae8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363596784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.363596784
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1219166967
Short name T255
Test name
Test status
Simulation time 66329489 ps
CPU time 3.77 seconds
Started Jul 31 05:36:41 PM PDT 24
Finished Jul 31 05:36:45 PM PDT 24
Peak memory 207424 kb
Host smart-f4da06f2-87b7-424f-af4b-be457f6e3b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219166967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1219166967
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1648300998
Short name T249
Test name
Test status
Simulation time 466732842 ps
CPU time 3.99 seconds
Started Jul 31 05:36:42 PM PDT 24
Finished Jul 31 05:36:46 PM PDT 24
Peak memory 208516 kb
Host smart-4b247ad5-14b2-46e3-8de7-c0af23f5d796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648300998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1648300998
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.810153049
Short name T825
Test name
Test status
Simulation time 76854266 ps
CPU time 2.83 seconds
Started Jul 31 05:36:41 PM PDT 24
Finished Jul 31 05:36:44 PM PDT 24
Peak memory 206948 kb
Host smart-9b746c99-fa56-4117-bc12-dceaa315cf0d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810153049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.810153049
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3366143860
Short name T323
Test name
Test status
Simulation time 822755007 ps
CPU time 22.31 seconds
Started Jul 31 05:36:43 PM PDT 24
Finished Jul 31 05:37:06 PM PDT 24
Peak memory 208236 kb
Host smart-6d3f0d92-8f47-4c8b-b142-ad09fe5cb9e5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366143860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3366143860
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2549556018
Short name T279
Test name
Test status
Simulation time 759904873 ps
CPU time 8.59 seconds
Started Jul 31 05:36:43 PM PDT 24
Finished Jul 31 05:36:52 PM PDT 24
Peak memory 208748 kb
Host smart-1acfce96-8a69-4be3-9166-122b06963369
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549556018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2549556018
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.3860705931
Short name T16
Test name
Test status
Simulation time 180526219 ps
CPU time 2.25 seconds
Started Jul 31 05:36:43 PM PDT 24
Finished Jul 31 05:36:45 PM PDT 24
Peak memory 206816 kb
Host smart-26dcaff0-573c-48c7-b726-a85995cd8f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860705931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3860705931
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.2823631132
Short name T586
Test name
Test status
Simulation time 38418624 ps
CPU time 1.61 seconds
Started Jul 31 05:36:42 PM PDT 24
Finished Jul 31 05:36:44 PM PDT 24
Peak memory 206704 kb
Host smart-9fe829a4-c335-47d0-ab2b-666f418365a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823631132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2823631132
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.430535879
Short name T813
Test name
Test status
Simulation time 788238578 ps
CPU time 12.39 seconds
Started Jul 31 05:36:46 PM PDT 24
Finished Jul 31 05:36:58 PM PDT 24
Peak memory 222540 kb
Host smart-e162c994-b11f-425b-ab36-cfdddc6bbc2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430535879 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.430535879
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.755336390
Short name T802
Test name
Test status
Simulation time 440017339 ps
CPU time 5.96 seconds
Started Jul 31 05:36:48 PM PDT 24
Finished Jul 31 05:36:54 PM PDT 24
Peak memory 208272 kb
Host smart-89d41c61-a52d-4460-b49a-5f520fb06f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755336390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.755336390
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.4068090439
Short name T135
Test name
Test status
Simulation time 88602282 ps
CPU time 1.56 seconds
Started Jul 31 05:36:46 PM PDT 24
Finished Jul 31 05:36:47 PM PDT 24
Peak memory 209528 kb
Host smart-3b1c3f0d-3faf-49c1-a0a3-dd1637aef5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068090439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.4068090439
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1870998113
Short name T814
Test name
Test status
Simulation time 194111341 ps
CPU time 0.85 seconds
Started Jul 31 05:36:49 PM PDT 24
Finished Jul 31 05:36:50 PM PDT 24
Peak memory 205940 kb
Host smart-99a50279-84cc-4228-aa4f-53ce3d0c80a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870998113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1870998113
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3937304006
Short name T128
Test name
Test status
Simulation time 35207430 ps
CPU time 2.45 seconds
Started Jul 31 05:36:45 PM PDT 24
Finished Jul 31 05:36:48 PM PDT 24
Peak memory 218492 kb
Host smart-1188df63-ee6f-4520-9bae-6cc0c11a7dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937304006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3937304006
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2541421343
Short name T263
Test name
Test status
Simulation time 157176921 ps
CPU time 4.41 seconds
Started Jul 31 05:36:47 PM PDT 24
Finished Jul 31 05:36:52 PM PDT 24
Peak memory 220528 kb
Host smart-d05aedb5-c122-41aa-9754-224e8a49ba61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541421343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2541421343
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.4199923532
Short name T186
Test name
Test status
Simulation time 61095436 ps
CPU time 2.77 seconds
Started Jul 31 05:36:49 PM PDT 24
Finished Jul 31 05:36:52 PM PDT 24
Peak memory 209384 kb
Host smart-221fef9f-7d9d-465b-9628-298e02b46aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199923532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.4199923532
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1080475070
Short name T861
Test name
Test status
Simulation time 191992748 ps
CPU time 4.88 seconds
Started Jul 31 05:36:48 PM PDT 24
Finished Jul 31 05:36:53 PM PDT 24
Peak memory 208908 kb
Host smart-fd743b22-dd27-44a5-b22e-a4913f5577c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080475070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1080475070
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1545924143
Short name T616
Test name
Test status
Simulation time 50563565 ps
CPU time 2.75 seconds
Started Jul 31 05:36:48 PM PDT 24
Finished Jul 31 05:36:52 PM PDT 24
Peak memory 208444 kb
Host smart-81489efa-0318-4a01-a9ef-234e026c6719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545924143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1545924143
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2283848730
Short name T629
Test name
Test status
Simulation time 47121548 ps
CPU time 2.72 seconds
Started Jul 31 05:36:47 PM PDT 24
Finished Jul 31 05:36:50 PM PDT 24
Peak memory 208412 kb
Host smart-c502cf1b-5e98-49e4-842e-bdfc5664e5f3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283848730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2283848730
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3116057684
Short name T594
Test name
Test status
Simulation time 224761708 ps
CPU time 3.13 seconds
Started Jul 31 05:36:47 PM PDT 24
Finished Jul 31 05:36:50 PM PDT 24
Peak memory 208696 kb
Host smart-4cdc0b27-ceb9-4984-8c73-8dd8ef71d0cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116057684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3116057684
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3312048840
Short name T635
Test name
Test status
Simulation time 56202402 ps
CPU time 2.32 seconds
Started Jul 31 05:36:46 PM PDT 24
Finished Jul 31 05:36:49 PM PDT 24
Peak memory 207204 kb
Host smart-ece7fb44-194c-4cf3-a878-99708a5cad12
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312048840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3312048840
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3455122511
Short name T482
Test name
Test status
Simulation time 344468694 ps
CPU time 2.43 seconds
Started Jul 31 05:36:46 PM PDT 24
Finished Jul 31 05:36:48 PM PDT 24
Peak memory 208520 kb
Host smart-852dfb7e-f798-4bac-b3d3-bb928c88e7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455122511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3455122511
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1467581155
Short name T708
Test name
Test status
Simulation time 104228150 ps
CPU time 3.05 seconds
Started Jul 31 05:36:46 PM PDT 24
Finished Jul 31 05:36:49 PM PDT 24
Peak memory 206684 kb
Host smart-a9f54dd7-060e-4ec4-84f3-dd75a6ba3d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467581155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1467581155
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1009544831
Short name T798
Test name
Test status
Simulation time 1751328935 ps
CPU time 36.05 seconds
Started Jul 31 05:36:45 PM PDT 24
Finished Jul 31 05:37:22 PM PDT 24
Peak memory 215632 kb
Host smart-694ef1de-74d0-489c-880c-22bbc3ea7768
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009544831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1009544831
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.1783705012
Short name T412
Test name
Test status
Simulation time 199704414 ps
CPU time 8.02 seconds
Started Jul 31 05:36:49 PM PDT 24
Finished Jul 31 05:36:57 PM PDT 24
Peak memory 219120 kb
Host smart-14f37b44-3f8b-42d7-95fb-c8c9a3e521a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783705012 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.1783705012
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.176080565
Short name T341
Test name
Test status
Simulation time 507740979 ps
CPU time 7.66 seconds
Started Jul 31 05:36:49 PM PDT 24
Finished Jul 31 05:36:57 PM PDT 24
Peak memory 214280 kb
Host smart-89c6c575-95f3-4be5-bc3f-9194b6156639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176080565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.176080565
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.659271715
Short name T397
Test name
Test status
Simulation time 114436801 ps
CPU time 2.29 seconds
Started Jul 31 05:36:47 PM PDT 24
Finished Jul 31 05:36:49 PM PDT 24
Peak memory 209744 kb
Host smart-02a9344a-addf-4884-97db-3d6b1d914a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659271715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.659271715
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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