Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
74.60	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	15	34	69.39

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	14	21	60.00	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	37	1			T5	2		T45	1		T46	2
auto[OpGenId]	15	1			T31	1		T60	1		T137	1
auto[OpGenSwOut]	18	1			T5	1		T46	1		T136	1
auto[OpGenHwOut]	15	1			T4	1		T5	1		T30	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1693	1			T44	3		T93	3		T4	2
auto[StInit]	87	1			T17	1		T4	2		T54	2
auto[StCreatorRootKey]	60	1			T52	1		T54	1		T45	1
auto[StOwnerIntKey]	45	1			T36	1		T146	1		T46	1
auto[StOwnerKey]	33	1			T16	1		T18	1		T6	1
auto[StDisabled]	446	1			T13	1		T44	9		T25	10
auto[StInvalid]	49	1			T1	1		T15	1		T37	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3409

1

T1

2

T2

1

T3

1

auto[1]

85

1

T4

1

T5

4

T30

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1684	1			T44	3		T93	3		T4	2
auto[StReset]	auto[1]	9	1			T30	1		T49	1		T139	1
auto[StInit]	auto[0]	51	1			T17	1		T4	1		T54	2
auto[StInit]	auto[1]	36	1			T4	1		T5	4		T45	1
auto[StCreatorRootKey]	auto[0]	42	1			T52	1		T54	1		T45	1
auto[StCreatorRootKey]	auto[1]	18	1			T31	1		T46	1		T204	1
auto[StOwnerIntKey]	auto[0]	34	1			T36	1		T146	1		T40	1
auto[StOwnerIntKey]	auto[1]	11	1			T46	1		T137	1		T57	1
auto[StOwnerKey]	auto[0]	28	1			T16	1		T18	1		T60	1
auto[StOwnerKey]	auto[1]	5	1			T6	1		T60	1		T176	1
auto[StDisabled]	auto[0]	440	1			T13	1		T44	9		T25	10
auto[StDisabled]	auto[1]	6	1			T46	2		T205	1		T206	1
auto[StInvalid]	auto[0]	49	1			T1	1		T15	1		T37	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	14	21	60.00	14

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId]]	0	1	1
[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[StOwnerKey]]	[auto[OpGenSwOut]]	0	1	1
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	6	1			T49	1		T50	1		T207	1
auto[StReset]	auto[OpGenSwOut]	2	1			T139	1		T145	1		-	-
auto[StReset]	auto[OpGenHwOut]	1	1			T30	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	15	1			T5	2		T45	1		T69	1
auto[StInit]	auto[OpGenId]	6	1			T208	1		T209	1		T143	1
auto[StInit]	auto[OpGenSwOut]	9	1			T5	1		T136	1		T210	1
auto[StInit]	auto[OpGenHwOut]	6	1			T4	1		T5	1		T211	1
auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T69	1		T212	1		T213	1
auto[StCreatorRootKey]	auto[OpGenId]	3	1			T31	1		T134	1		T21	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T204	1		T214	1		T63	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	5	1			T46	1		T69	1		T215	1
auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T57	1		T58	1		T216	1
auto[StOwnerIntKey]	auto[OpGenId]	3	1			T137	1		T189	1		T217	1
auto[StOwnerIntKey]	auto[OpGenSwOut]	2	1			T46	1		T218	1		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	2	1			T219	1		T220	1		-	-
auto[StOwnerKey]	auto[OpAdvance]	2	1			T221	1		T222	1		-	-
auto[StOwnerKey]	auto[OpGenId]	2	1			T60	1		T176	1		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	1	1			T6	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	3	1			T46	2		T223	1		-	-
auto[StDisabled]	auto[OpGenId]	1	1			T206	1		-	-		-	-
auto[StDisabled]	auto[OpGenSwOut]	2	1			T205	1		T224	1		-	-