Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	75	255	77.27

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	56	224	80.00	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4686

1

T1

4

T2

5

T3

6

auto[1]

520

1

T2

2

T44

3

T25

2

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4686

1

T1

4

T2

5

T3

6

auto[1]

520

1

T2

2

T44

3

T25

2

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4653

1

T1

4

T2

4

T3

6

auto[1]

553

1

T2

3

T12

3

T13

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4653

1

T1

4

T2

4

T3

6

auto[1]

553

1

T2

3

T12

3

T13

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	390	1			T1	1		T2	4		T25	6
auto[OpGenId]	1137	1			T1	1		T2	1		T3	3
auto[OpGenSwOut]	1113	1			T1	1		T3	1		T10	1
auto[OpGenHwOut]	2495	1			T1	1		T2	2		T3	1
auto[OpDisable]	71	1			T3	1		T11	1		T34	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	390	1			T1	1		T2	4		T25	6
auto[OpGenId]	1137	1			T1	1		T2	1		T3	3
auto[OpGenSwOut]	1113	1			T1	1		T3	1		T10	1
auto[OpGenHwOut]	2495	1			T1	1		T2	2		T3	1
auto[OpDisable]	71	1			T3	1		T11	1		T34	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4672

1

T1

4

T2

6

T3

6

auto[1]

534

1

T2

1

T11

1

T13

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4672

1

T1

4

T2

6

T3

6

auto[1]

534

1

T2

1

T11

1

T13

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4913

1

T1

4

T2

5

T3

6

auto[1]

293

1

T2

2

T133

5

T225

4

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1776	1			T1	2		T2	2		T3	2
auto[1]	711	1			T2	1		T3	2		T13	1
auto[2]	673	1			T3	1		T10	1		T12	1
auto[3]	668	1			T1	1		T2	2		T12	2
auto[4]	333	1			T44	1		T25	6		T93	2
auto[5]	330	1			T12	2		T13	1		T44	1
auto[6]	350	1			T3	1		T16	1		T35	1
auto[7]	365	1			T1	1		T2	2		T11	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1378	1			T1	1		T2	2		T3	1
clear_one[1]	711	1			T2	1		T3	2		T13	1
clear_one[2]	673	1			T3	1		T10	1		T12	1
clear_one[3]	668	1			T1	1		T2	2		T12	2
clear_none	1776	1			T1	2		T2	2		T3	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	935	1			T3	4		T15	1		T44	3
auto[StInit]	627	1			T1	1		T2	2		T10	1
auto[StCreatorRootKey]	557	1			T2	2		T10	1		T11	1
auto[StOwnerIntKey]	510	1			T12	1		T16	1		T35	1
auto[StOwnerKey]	472	1			T2	1		T12	1		T35	1
auto[StDisabled]	1862	1			T2	2		T3	2		T11	1
auto[StInvalid]	243	1			T1	3		T15	2		T37	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	935	1			T3	4		T15	1		T44	3
auto[StInit]	627	1			T1	1		T2	2		T10	1
auto[StCreatorRootKey]	557	1			T2	2		T10	1		T11	1
auto[StOwnerIntKey]	510	1			T12	1		T16	1		T35	1
auto[StOwnerKey]	472	1			T2	1		T12	1		T35	1
auto[StDisabled]	1862	1			T2	2		T3	2		T11	1
auto[StInvalid]	243	1			T1	3		T15	2		T37	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	56	224	80.00	56

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[2]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[2]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[3] - auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[3] - auto[4]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[3] - auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[3] - auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[5]]	[auto[StOwnerKey]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[6] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[6] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	2	1			T226	1		T227	1		-	-
auto[0]	auto[StReset]	auto[OpGenId]	151	1			T15	1		T25	1		T26	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	159	1			T3	1		T25	1		T93	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	225	1			T3	1		T44	2		T25	3
auto[0]	auto[StInit]	auto[OpAdvance]	35	1			T1	1		T25	2		T5	2
auto[0]	auto[StInit]	auto[OpGenId]	83	1			T25	1		T54	1		T45	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	93	1			T10	1		T44	2		T25	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	195	1			T2	1		T12	1		T13	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	25	1			T53	1		T60	1		T182	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	57	1			T25	1		T4	1		T121	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	39	1			T11	1		T25	1		T186	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	80	1			T12	1		T16	1		T201	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	17	1			T46	2		T228	2		T229	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	31	1			T25	1		T64	1		T4	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	30	1			T44	1		T27	1		T230	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	66	1			T35	1		T25	1		T200	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	13	1			T231	2		T226	1		T232	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	27	1			T25	1		T5	1		T60	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T53	1		T231	1		T70	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	39	1			T35	1		T201	1		T233	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	23	1			T25	1		T181	1		T227	1
auto[0]	auto[StDisabled]	auto[OpGenId]	63	1			T2	1		T4	1		T234	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	64	1			T93	2		T5	1		T235	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	158	1			T25	1		T76	1		T201	1
auto[0]	auto[StDisabled]	auto[OpDisable]	18	1			T34	1		T53	2		T236	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	12	1			T237	1		T238	1		T94	1
auto[0]	auto[StInvalid]	auto[OpGenId]	18	1			T37	1		T239	2		T240	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T81	1		T241	1		T242	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	28	1			T1	1		T15	1		T48	1
auto[1]	auto[StReset]	auto[OpGenId]	25	1			T3	1		T5	1		T243	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	21	1			T69	1		T57	1		T210	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	42	1			T44	1		T67	1		T244	1
auto[1]	auto[StInit]	auto[OpAdvance]	6	1			T227	2		T89	1		T83	1
auto[1]	auto[StInit]	auto[OpGenId]	8	1			T25	1		T245	1		T246	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	14	1			T57	1		T247	1		T248	4
auto[1]	auto[StInit]	auto[OpGenHwOut]	26	1			T5	1		T46	1		T59	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T4	1		T124	1		T249	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	17	1			T77	1		T54	1		T80	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	19	1			T25	1		T54	1		T45	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	37	1			T54	1		T202	1		T200	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T45	1		T250	1		T251	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	17	1			T60	1		T79	1		T252	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T25	1		T253	1		T254	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	42	1			T76	1		T54	1		T5	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T225	1		T255	1		T256	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	23	1			T187	1		T257	1		T258	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T25	1		T5	1		T194	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	35	1			T202	1		T259	1		T260	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	16	1			T2	1		T25	1		T4	1
auto[1]	auto[StDisabled]	auto[OpGenId]	52	1			T13	1		T44	1		T5	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	53	1			T25	2		T26	1		T54	2
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	156	1			T25	2		T76	1		T201	1
auto[1]	auto[StDisabled]	auto[OpDisable]	16	1			T3	1		T44	1		T25	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	5	1			T261	1		T94	1		T262	1
auto[1]	auto[StInvalid]	auto[OpGenId]	7	1			T47	1		T241	1		T263	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T261	1		T264	1		T265	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T239	1		T180	1		T183	1
auto[2]	auto[StReset]	auto[OpAdvance]	1	1			T266	1		-	-		-	-
auto[2]	auto[StReset]	auto[OpGenId]	21	1			T3	1		T4	1		T5	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	28	1			T25	1		T67	1		T88	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	40	1			T4	1		T235	1		T46	1
auto[2]	auto[StInit]	auto[OpAdvance]	3	1			T267	1		T213	1		T268	1
auto[2]	auto[StInit]	auto[OpGenId]	17	1			T231	3		T127	1		T24	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	6	1			T269	1		T126	1		T270	2
auto[2]	auto[StInit]	auto[OpGenHwOut]	15	1			T136	1		T271	1		T272	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T273	1		T274	1		T275	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T53	1		T126	1		T270	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T44	1		T276	1		T270	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	34	1			T10	1		T44	1		T25	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T219	1		-	-		-	-
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T25	1		T60	1		T277	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T25	1		T77	1		T278	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	35	1			T4	1		T202	1		T258	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T179	1		T279	1		T280	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	14	1			T45	1		T53	1		T205	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T69	1		T281	1		T282	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	38	1			T76	1		T196	1		T283	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	23	1			T5	1		T45	1		T69	1
auto[2]	auto[StDisabled]	auto[OpGenId]	66	1			T44	1		T25	6		T4	2
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	74	1			T44	2		T54	1		T55	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	155	1			T12	1		T35	3		T76	2
auto[2]	auto[StDisabled]	auto[OpDisable]	4	1			T284	1		T213	1		T285	1
auto[2]	auto[StInvalid]	auto[OpGenId]	8	1			T82	1		T239	1		T286	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T15	1		T37	1		T47	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	12	1			T37	1		T48	1		T287	1
auto[3]	auto[StReset]	auto[OpGenId]	12	1			T5	1		T287	1		T231	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	21	1			T235	1		T288	1		T276	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	37	1			T202	2		T200	1		T193	1
auto[3]	auto[StInit]	auto[OpAdvance]	2	1			T133	1		T138	1		-	-
auto[3]	auto[StInit]	auto[OpGenId]	8	1			T25	1		T99	1		T289	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	5	1			T58	1		T221	1		T290	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	19	1			T4	1		T200	1		T53	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T2	1		T25	1		T235	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T187	1		T31	1		T263	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T258	1		T254	1		T105	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	41	1			T76	1		T5	1		T230	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T25	1		T227	1		T291	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T5	1		T192	1		T292	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T54	1		T46	1		T60	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	41	1			T201	1		T68	1		T293	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T5	1		T294	1		T295	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	13	1			T276	1		T228	1		T296	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T25	2		T133	3		T60	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	34	1			T2	1		T12	1		T54	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	21	1			T235	1		T297	1		T46	1
auto[3]	auto[StDisabled]	auto[OpGenId]	51	1			T34	1		T44	1		T54	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	56	1			T27	1		T187	1		T45	2
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	157	1			T12	1		T35	1		T88	1
auto[3]	auto[StDisabled]	auto[OpDisable]	9	1			T60	1		T205	1		T298	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	5	1			T287	1		T299	2		T300	1
auto[3]	auto[StInvalid]	auto[OpGenId]	11	1			T241	1		T239	1		T286	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T1	1		T238	1		T56	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T238	1		T197	1		T242	1
auto[4]	auto[StReset]	auto[OpGenId]	10	1			T93	1		T48	1		T136	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	5	1			T47	1		T30	1		T301	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	18	1			T302	2		T257	1		T196	1
auto[4]	auto[StInit]	auto[OpAdvance]	1	1			T303	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenId]	2	1			T53	1		T304	1		-	-
auto[4]	auto[StInit]	auto[OpGenSwOut]	5	1			T88	1		T54	1		T305	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	11	1			T54	1		T202	1		T302	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T69	1		T33	1		T303	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T249	2		T176	1		T306	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T93	1		T67	1		T249	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	15	1			T25	1		T307	1		T308	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T235	1		T291	1		T309	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	3	1			T60	1		T221	1		T310	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T4	1		T205	1		T246	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T302	1		T49	1		T188	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T311	1		T213	1		T312	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	11	1			T295	1		T291	1		T273	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T25	1		T228	1		T273	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T45	1		T313	1		T314	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	11	1			T226	1		T247	1		T315	1
auto[4]	auto[StDisabled]	auto[OpGenId]	40	1			T25	3		T235	1		T244	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	21	1			T25	1		T316	1		T296	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	81	1			T44	1		T202	1		T233	1
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T317	1		T318	1		T188	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	2	1			T319	1		T320	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	2	1			T197	1		T321	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T48	1		T241	1		T183	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T37	1		T56	1		T322	1
auto[5]	auto[StReset]	auto[OpGenId]	4	1			T4	1		T53	1		T69	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	11	1			T48	1		T244	1		T323	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	26	1			T5	1		T202	1		T45	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T45	1		T324	1		-	-
auto[5]	auto[StInit]	auto[OpGenId]	2	1			T25	1		T325	1		-	-
auto[5]	auto[StInit]	auto[OpGenSwOut]	1	1			T326	1		-	-		-	-
auto[5]	auto[StInit]	auto[OpGenHwOut]	9	1			T327	1		T23	1		T85	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T328	1		T270	2		T329	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T13	1		T330	1		T51	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T18	1		T60	1		T331	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T193	1		T212	1		T332	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T56	1		T51	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T316	1		T333	1		T267	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T105	1		T109	1		T325	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T12	1		T44	1		T334	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	11	1			T335	1		T270	2		T263	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T93	1		T336	1		T337	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	26	1			T77	1		T293	1		T302	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	19	1			T88	1		T123	2		T328	1
auto[5]	auto[StDisabled]	auto[OpGenId]	20	1			T53	1		T105	1		T70	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	14	1			T25	1		T328	2		T338	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	84	1			T12	1		T4	1		T200	1
auto[5]	auto[StDisabled]	auto[OpDisable]	4	1			T213	1		T339	1		T340	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	1	1			T341	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	5	1			T81	1		T261	1		T299	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T287	1		T241	1		T322	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T47	1		T239	1		T240	1
auto[6]	auto[StReset]	auto[OpGenId]	10	1			T342	1		T343	1		T49	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	11	1			T37	1		T80	1		T19	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	18	1			T37	1		T197	1		T69	1
auto[6]	auto[StInit]	auto[OpAdvance]	4	1			T18	1		T80	1		T127	2
auto[6]	auto[StInit]	auto[OpGenId]	4	1			T342	1		T22	1		T205	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	10	1			T45	1		T344	1		T212	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	9	1			T328	1		T22	1		T291	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T324	1		T222	1		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T25	1		T45	1		T63	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T25	1		T26	1		T191	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	15	1			T35	1		T233	1		T260	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T225	1		T232	1		T345	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T225	2		T176	1		T275	2
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T16	1		T54	1		T346	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T347	1		T314	1		T332	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T243	1		T348	1		T345	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	12	1			T46	1		T349	1		T250	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T244	1		T225	1		T350	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	12	1			T307	1		T351	1		T308	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	12	1			T192	1		T124	1		T127	1
auto[6]	auto[StDisabled]	auto[OpGenId]	42	1			T3	1		T25	3		T4	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	37	1			T44	1		T25	2		T5	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	66	1			T4	1		T202	1		T302	1
auto[6]	auto[StDisabled]	auto[OpDisable]	7	1			T45	1		T352	1		T114	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	1	1			T353	1		-	-		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	4	1			T82	1		T354	1		T341	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T263	1		T355	1		T356	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T320	1		T357	1		T358	1
auto[7]	auto[StReset]	auto[OpGenId]	5	1			T69	1		T188	1		T359	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	11	1			T55	1		T46	1		T342	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	21	1			T25	2		T302	1		T196	1
auto[7]	auto[StInit]	auto[OpAdvance]	3	1			T2	1		T360	1		T361	1
auto[7]	auto[StInit]	auto[OpGenId]	8	1			T214	1		T140	1		T362	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	9	1			T53	1		T275	1		T251	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	12	1			T363	1		T205	1		T364	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T2	1		T328	1		T24	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T61	1		T365	1		T219	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T44	1		T24	1		T366	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T5	1		T302	1		T334	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T4	1		T249	1		T367	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T328	1		T49	1		T360	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T133	1		T243	1		T368	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T93	1		T5	1		T53	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T369	1		T370	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	4	1			T371	1		T289	1		T372	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T373	1		T188	1		T374	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T5	1		T269	1		T363	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	20	1			T45	1		T244	1		T80	1
auto[7]	auto[StDisabled]	auto[OpGenId]	25	1			T26	1		T4	1		T5	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	22	1			T25	1		T4	1		T5	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	89	1			T12	1		T44	1		T4	1
auto[7]	auto[StDisabled]	auto[OpDisable]	7	1			T11	1		T93	1		T67	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	6	1			T355	1		T375	1		T376	1
auto[7]	auto[StInvalid]	auto[OpGenId]	7	1			T1	1		T82	1		T287	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T376	1		T377	1		T353	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T356	1		T321	1		T378	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1378

1

T1

1

T2

2

T3

1

clear_one[1]

auto[0]

auto[0]

auto[0]

421

1

T3

2

T44

3

T25

6

clear_one[1]

auto[0]

auto[0]

auto[1]

124

1

T25

2

T201

1

T27

1

clear_one[1]

auto[0]

auto[1]

auto[0]

134

1

T2

1

T25

2

T76

2

clear_one[1]

auto[0]

auto[1]

auto[1]

32

1

T13

1

T5

2

T45

1

clear_one[2]

auto[0]

auto[0]

auto[0]

395

1

T3

1

T10

1

T12

1

clear_one[2]

auto[0]

auto[0]

auto[1]

119

1

T44

1

T25

2

T201

2

clear_one[2]

auto[1]

auto[0]

auto[0]

117

1

T44

1

T4

2

T5

1

clear_one[2]

auto[1]

auto[0]

auto[1]

42

1

T44

1

T77

1

T5

1

clear_one[3]

auto[0]

auto[0]

auto[0]

396

1

T1

1

T2

1

T34

1

clear_one[3]

auto[0]

auto[1]

auto[0]

120

1

T12

2

T35

1

T25

1

clear_one[3]

auto[1]

auto[0]

auto[0]

113

1

T44

1

T200

1

T203

1

clear_one[3]

auto[1]

auto[1]

auto[0]

39

1

T2

1

T88

1

T54

2

clear_none

auto[0]

auto[0]

auto[0]

1268

1

T1

2

T2

1

T3

2

clear_none

auto[0]

auto[0]

auto[1]

132

1

T11

1

T34

1

T201

3

clear_none

auto[0]

auto[1]

auto[0]

132

1

T12

1

T35

2

T76

1

clear_none

auto[0]

auto[1]

auto[1]

35

1

T44

1

T45

1

T269

1

clear_none

auto[1]

auto[0]

auto[0]

124

1

T25

1

T64

1

T4

1

clear_none

auto[1]

auto[0]

auto[1]

24

1

T25

1

T235

1

T234

1

clear_none

auto[1]

auto[1]

auto[0]

35

1

T344

1

T231

3

T349

1

clear_none

auto[1]

auto[1]

auto[1]

26

1

T2

1

T379

1

T380

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1276	1			T1	1		T2	1		T3	1
clear_all	auto[1]	102	1			T2	1		T225	2		T123	2
clear_one[1]	auto[0]	668	1			T2	1		T3	2		T13	1
clear_one[1]	auto[1]	43	1			T133	2		T225	2		T124	1
clear_one[2]	auto[0]	633	1			T3	1		T10	1		T12	1
clear_one[2]	auto[1]	40	1			T231	2		T328	2		T125	2
clear_one[3]	auto[0]	642	1			T1	1		T2	1		T12	2
clear_one[3]	auto[1]	26	1			T2	1		T133	2		T123	1
clear_none	auto[0]	1694	1			T1	2		T2	2		T3	2
clear_none	auto[1]	82	1			T133	1		T123	1		T231	6