Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10973

1

T1

3

T2

7

T3

19

auto[Attestation]

7794

1

T1

1

T2

12

T3

3

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2711	1			T1	1		T2	3		T3	3
auto[Aes]	3432	1			T1	3		T2	7		T3	4
auto[Kmac]	3291	1			T2	2		T3	3		T11	1
auto[Otbn]	3350	1			T2	3		T10	3		T11	5

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7626	1			T1	4		T2	8		T3	1
auto[OpGenId]	5983	1			T2	4		T3	12		T10	1
auto[OpGenSwOut]	6027	1			T1	3		T2	4		T3	5
auto[OpGenHwOut]	6757	1			T1	1		T2	11		T3	5
auto[OpDisable]	135	1			T3	1		T11	1		T34	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10527

1

T1

7

T2

9

T3

2

auto[OpDoneFail]

16001

1

T1

1

T2

18

T3

22

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6470	1			T1	1		T2	1		T3	18
auto[StInit]	3687	1			T1	1		T2	5		T3	2
auto[StCreatorRootKey]	3162	1			T1	2		T2	1		T10	3
auto[StOwnerIntKey]	2750	1			T1	4		T2	3		T10	2
auto[StOwnerKey]	2383	1			T2	3		T10	5		T12	2
auto[StDisabled]	8076	1			T2	14		T3	4		T11	1

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	333	1			T11	1		T44	1		T25	8
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	114	1			T44	3		T25	1		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	89	1			T44	3		T75	1		T93	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	60	1			T77	1		T4	2		T119	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	60	1			T10	1		T4	1		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	223	1			T2	1		T25	3		T27	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	336	1			T3	2		T15	1		T44	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	119	1			T11	1		T44	2		T93	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	76	1			T1	1		T11	1		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	76	1			T1	1		T16	2		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	69	1			T10	1		T44	1		T25	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	199	1			T2	2		T44	1		T25	7
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	320	1			T3	2		T44	1		T25	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	101	1			T44	1		T25	1		T93	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	99	1			T16	1		T44	1		T25	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	80	1			T118	1		T54	1		T78	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	54	1			T44	1		T4	1		T185	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	205	1			T34	1		T44	3		T25	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	363	1			T11	1		T15	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	78	1			T10	1		T34	1		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	88	1			T25	2		T77	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	63	1			T44	1		T25	1		T75	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	60	1			T44	1		T25	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	242	1			T13	1		T34	1		T44	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	104	1			T44	2		T4	4		T54	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	108	1			T3	1		T10	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	71	1			T25	1		T4	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	57	1			T1	1		T10	1		T25	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	60	1			T44	1		T25	1		T75	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	214	1			T13	1		T44	2		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	107	1			T44	1		T4	3		T37	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	110	1			T2	1		T10	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	74	1			T25	1		T26	1		T54	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	66	1			T64	1		T36	1		T5	5
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	57	1			T44	1		T25	2		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	225	1			T13	1		T44	3		T25	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	85	1			T44	2		T4	4		T37	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	102	1			T11	1		T17	1		T88	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	100	1			T44	1		T25	1		T55	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	62	1			T4	1		T121	1		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	66	1			T64	1		T4	1		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	228	1			T13	1		T44	3		T25	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	76	1			T44	1		T4	1		T54	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	88	1			T10	1		T44	1		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	85	1			T44	1		T25	2		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	73	1			T25	2		T27	1		T88	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	59	1			T13	1		T93	1		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	243	1			T44	2		T25	6		T5	4
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	285	1			T3	1		T15	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	79	1			T25	1		T26	1		T120	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	69	1			T64	1		T27	1		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	62	1			T121	2		T5	2		T68	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	41	1			T25	1		T27	1		T119	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	168	1			T13	1		T44	1		T25	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	467	1			T3	2		T15	1		T25	4
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	121	1			T25	2		T67	1		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	117	1			T54	2		T5	1		T200	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	100	1			T1	1		T2	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	76	1			T2	1		T10	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	304	1			T13	1		T44	3		T25	6
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	394	1			T3	1		T25	4		T67	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	120	1			T35	1		T25	1		T76	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	106	1			T35	1		T44	1		T76	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	95	1			T76	1		T93	1		T54	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	80	1			T35	1		T25	1		T76	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	268	1			T12	2		T13	1		T35	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	392	1			T11	2		T44	1		T25	4
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	120	1			T34	1		T44	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	95	1			T11	1		T44	1		T201	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	103	1			T77	1		T5	2		T202	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	80	1			T25	2		T201	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	283	1			T2	1		T44	2		T25	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	68	1			T44	1		T4	2		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	93	1			T2	1		T17	1		T119	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	78	1			T10	1		T13	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	54	1			T2	1		T121	1		T54	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	44	1			T26	1		T54	2		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	177	1			T3	1		T44	1		T25	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	65	1			T44	5		T4	1		T54	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	120	1			T2	1		T13	1		T119	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	92	1			T25	1		T186	2		T203	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	100	1			T25	1		T4	1		T121	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	78	1			T10	1		T44	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	278	1			T2	1		T25	2		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	61	1			T44	2		T4	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	106	1			T12	1		T34	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	103	1			T12	1		T13	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	88	1			T12	1		T35	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	82	1			T2	1		T12	1		T119	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	286	1			T2	1		T12	2		T13	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	66	1			T4	2		T54	2		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	134	1			T2	1		T11	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	95	1			T34	1		T44	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	87	1			T44	2		T201	1		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	67	1			T10	1		T25	1		T77	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	310	1			T2	1		T13	2		T25	5

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	195	1			T10	1		T44	3		T75	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	684	1			T2	1		T11	1		T44	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	202	1			T1	2		T10	1		T11	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	673	1			T2	2		T3	2		T11	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	219	1			T16	1		T44	2		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	640	1			T3	2		T34	1		T44	5
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	194	1			T44	2		T25	4		T75	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	700	1			T10	1		T11	1		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	178	1			T1	1		T10	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	436	1			T3	1		T10	1		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	182	1			T44	1		T25	3		T64	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	457	1			T2	1		T10	1		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	210	1			T44	1		T64	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	433	1			T11	1		T13	1		T44	5
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	206	1			T13	1		T44	1		T25	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	418	1			T10	1		T44	4		T25	7
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	162	1			T25	1		T64	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	542	1			T3	1		T13	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	276	1			T1	1		T2	2		T10	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	909	1			T3	2		T13	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	268	1			T35	2		T44	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	795	1			T3	1		T12	2		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	262	1			T11	1		T44	1		T25	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	811	1			T2	1		T11	2		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	164	1			T2	1		T10	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	350	1			T2	1		T3	1		T44	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	256	1			T10	1		T44	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	477	1			T2	2		T13	1		T44	5
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	262	1			T2	1		T12	3		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	464	1			T2	1		T12	3		T13	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	239	1			T10	1		T34	1		T44	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	520	1			T2	2		T11	1		T13	2