Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32646

1

T1

28

T2

32

T3

24

auto[1]

320

1

T2

4

T133

5

T225

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32657	1			T1	28		T2	33		T3	24
auto[134217728:268435455]	10	1			T123	1		T124	1		T98	1
auto[268435456:402653183]	7	1			T133	1		T231	1		T249	1
auto[402653184:536870911]	10	1			T123	2		T360	1		T415	1
auto[536870912:671088639]	11	1			T2	1		T123	1		T338	1
auto[671088640:805306367]	12	1			T328	1		T226	1		T127	1
auto[805306368:939524095]	7	1			T226	1		T249	1		T247	3
auto[939524096:1073741823]	10	1			T226	1		T127	1		T360	1
auto[1073741824:1207959551]	9	1			T124	2		T125	2		T416	1
auto[1207959552:1342177279]	3	1			T328	1		T226	1		T247	1
auto[1342177280:1476395007]	9	1			T225	1		T417	1		T418	1
auto[1476395008:1610612735]	17	1			T126	3		T127	1		T360	1
auto[1610612736:1744830463]	8	1			T127	2		T419	1		T399	1
auto[1744830464:1879048191]	9	1			T123	1		T231	1		T295	1
auto[1879048192:2013265919]	14	1			T123	1		T126	1		T127	1
auto[2013265920:2147483647]	5	1			T127	1		T227	1		T273	1
auto[2147483648:2281701375]	13	1			T133	1		T231	1		T125	1
auto[2281701376:2415919103]	7	1			T249	1		T338	1		T227	1
auto[2415919104:2550136831]	14	1			T2	1		T133	1		T226	1
auto[2550136832:2684354559]	9	1			T125	2		T227	1		T418	1
auto[2684354560:2818572287]	9	1			T270	1		T415	1		T337	1
auto[2818572288:2952790015]	7	1			T417	1		T337	1		T247	1
auto[2952790016:3087007743]	8	1			T328	1		T226	1		T127	1
auto[3087007744:3221225471]	9	1			T328	1		T249	2		T273	1
auto[3221225472:3355443199]	11	1			T133	1		T126	1		T127	2
auto[3355443200:3489660927]	13	1			T126	1		T249	1		T338	1
auto[3489660928:3623878655]	10	1			T2	1		T125	1		T127	1
auto[3623878656:3758096383]	17	1			T133	1		T231	1		T124	1
auto[3758096384:3892314111]	9	1			T226	1		T126	1		T227	1
auto[3892314112:4026531839]	15	1			T231	1		T226	1		T125	1
auto[4026531840:4160749567]	6	1			T360	1		T420	1		T418	1
auto[4160749568:4294967295]	11	1			T231	1		T417	1		T415	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32646	1			T1	28		T2	32		T3	24
auto[0:134217727]	auto[1]	11	1			T2	1		T126	1		T227	1
auto[134217728:268435455]	auto[1]	10	1			T123	1		T124	1		T98	1
auto[268435456:402653183]	auto[1]	7	1			T133	1		T231	1		T249	1
auto[402653184:536870911]	auto[1]	10	1			T123	2		T360	1		T415	1
auto[536870912:671088639]	auto[1]	11	1			T2	1		T123	1		T338	1
auto[671088640:805306367]	auto[1]	12	1			T328	1		T226	1		T127	1
auto[805306368:939524095]	auto[1]	7	1			T226	1		T249	1		T247	3
auto[939524096:1073741823]	auto[1]	10	1			T226	1		T127	1		T360	1
auto[1073741824:1207959551]	auto[1]	9	1			T124	2		T125	2		T416	1
auto[1207959552:1342177279]	auto[1]	3	1			T328	1		T226	1		T247	1
auto[1342177280:1476395007]	auto[1]	9	1			T225	1		T417	1		T418	1
auto[1476395008:1610612735]	auto[1]	17	1			T126	3		T127	1		T360	1
auto[1610612736:1744830463]	auto[1]	8	1			T127	2		T419	1		T399	1
auto[1744830464:1879048191]	auto[1]	9	1			T123	1		T231	1		T295	1
auto[1879048192:2013265919]	auto[1]	14	1			T123	1		T126	1		T127	1
auto[2013265920:2147483647]	auto[1]	5	1			T127	1		T227	1		T273	1
auto[2147483648:2281701375]	auto[1]	13	1			T133	1		T231	1		T125	1
auto[2281701376:2415919103]	auto[1]	7	1			T249	1		T338	1		T227	1
auto[2415919104:2550136831]	auto[1]	14	1			T2	1		T133	1		T226	1
auto[2550136832:2684354559]	auto[1]	9	1			T125	2		T227	1		T418	1
auto[2684354560:2818572287]	auto[1]	9	1			T270	1		T415	1		T337	1
auto[2818572288:2952790015]	auto[1]	7	1			T417	1		T337	1		T247	1
auto[2952790016:3087007743]	auto[1]	8	1			T328	1		T226	1		T127	1
auto[3087007744:3221225471]	auto[1]	9	1			T328	1		T249	2		T273	1
auto[3221225472:3355443199]	auto[1]	11	1			T133	1		T126	1		T127	2
auto[3355443200:3489660927]	auto[1]	13	1			T126	1		T249	1		T338	1
auto[3489660928:3623878655]	auto[1]	10	1			T2	1		T125	1		T127	1
auto[3623878656:3758096383]	auto[1]	17	1			T133	1		T231	1		T124	1
auto[3758096384:3892314111]	auto[1]	9	1			T226	1		T126	1		T227	1
auto[3892314112:4026531839]	auto[1]	15	1			T231	1		T226	1		T125	1
auto[4026531840:4160749567]	auto[1]	6	1			T360	1		T420	1		T418	1
auto[4160749568:4294967295]	auto[1]	11	1			T231	1		T417	1		T415	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1581

1

T1

5

T2

2

T3

3

auto[1]

1770

1

T1

1

T2

3

T3

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	117	1			T16	1		T27	1		T88	1
auto[134217728:268435455]	102	1			T3	1		T4	2		T54	1
auto[268435456:402653183]	120	1			T15	1		T25	1		T4	4
auto[402653184:536870911]	85	1			T26	1		T119	1		T37	1
auto[536870912:671088639]	103	1			T11	1		T25	1		T64	1
auto[671088640:805306367]	101	1			T3	1		T25	2		T77	1
auto[805306368:939524095]	98	1			T13	1		T34	1		T4	2
auto[939524096:1073741823]	102	1			T1	1		T2	1		T15	1
auto[1073741824:1207959551]	100	1			T67	1		T4	1		T37	1
auto[1207959552:1342177279]	93	1			T25	1		T64	1		T119	1
auto[1342177280:1476395007]	127	1			T1	1		T2	1		T15	1
auto[1476395008:1610612735]	96	1			T25	3		T26	1		T93	1
auto[1610612736:1744830463]	112	1			T10	1		T34	1		T25	2
auto[1744830464:1879048191]	118	1			T1	1		T15	1		T16	1
auto[1879048192:2013265919]	107	1			T2	1		T4	3		T28	1
auto[2013265920:2147483647]	117	1			T15	1		T34	1		T44	1
auto[2147483648:2281701375]	103	1			T2	1		T3	1		T25	1
auto[2281701376:2415919103]	85	1			T237	1		T269	2		T408	2
auto[2415919104:2550136831]	111	1			T2	1		T25	1		T93	1
auto[2550136832:2684354559]	106	1			T44	1		T77	1		T64	1
auto[2684354560:2818572287]	95	1			T25	2		T54	1		T5	1
auto[2818572288:2952790015]	99	1			T3	1		T10	1		T25	1
auto[2952790016:3087007743]	93	1			T1	1		T13	1		T25	1
auto[3087007744:3221225471]	113	1			T44	1		T67	1		T5	1
auto[3221225472:3355443199]	99	1			T13	1		T44	1		T64	1
auto[3355443200:3489660927]	98	1			T1	1		T25	1		T26	1
auto[3489660928:3623878655]	111	1			T13	1		T16	1		T44	1
auto[3623878656:3758096383]	106	1			T1	1		T13	1		T15	1
auto[3758096384:3892314111]	105	1			T44	1		T5	2		T45	1
auto[3892314112:4026531839]	103	1			T16	1		T25	1		T4	1
auto[4026531840:4160749567]	119	1			T10	1		T26	1		T5	1
auto[4160749568:4294967295]	107	1			T16	1		T25	1		T27	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	63	1			T16	1		T27	1		T88	1
auto[0:134217727]	auto[1]	54	1			T54	2		T82	1		T241	1
auto[134217728:268435455]	auto[0]	51	1			T3	1		T4	1		T54	1
auto[134217728:268435455]	auto[1]	51	1			T4	1		T55	1		T421	1
auto[268435456:402653183]	auto[0]	60	1			T15	1		T4	4		T48	1
auto[268435456:402653183]	auto[1]	60	1			T25	1		T5	1		T53	1
auto[402653184:536870911]	auto[0]	45	1			T37	1		T121	1		T54	1
auto[402653184:536870911]	auto[1]	40	1			T26	1		T119	1		T53	1
auto[536870912:671088639]	auto[0]	42	1			T11	1		T64	1		T54	3
auto[536870912:671088639]	auto[1]	61	1			T25	1		T5	1		T30	1
auto[671088640:805306367]	auto[0]	49	1			T27	1		T4	1		T37	1
auto[671088640:805306367]	auto[1]	52	1			T3	1		T25	2		T77	1
auto[805306368:939524095]	auto[0]	45	1			T34	1		T4	2		T45	1
auto[805306368:939524095]	auto[1]	53	1			T13	1		T5	1		T237	1
auto[939524096:1073741823]	auto[0]	47	1			T1	1		T26	1		T67	1
auto[939524096:1073741823]	auto[1]	55	1			T2	1		T15	1		T44	1
auto[1073741824:1207959551]	auto[0]	41	1			T67	1		T4	1		T45	2
auto[1073741824:1207959551]	auto[1]	59	1			T37	1		T55	1		T5	1
auto[1207959552:1342177279]	auto[0]	48	1			T25	1		T119	1		T54	1
auto[1207959552:1342177279]	auto[1]	45	1			T64	1		T78	1		T123	1
auto[1342177280:1476395007]	auto[0]	58	1			T1	1		T2	1		T25	1
auto[1342177280:1476395007]	auto[1]	69	1			T15	1		T25	2		T37	1
auto[1476395008:1610612735]	auto[0]	50	1			T25	1		T5	1		T45	2
auto[1476395008:1610612735]	auto[1]	46	1			T25	2		T26	1		T93	1
auto[1610612736:1744830463]	auto[0]	52	1			T25	1		T4	1		T37	1
auto[1610612736:1744830463]	auto[1]	60	1			T10	1		T34	1		T25	1
auto[1744830464:1879048191]	auto[0]	65	1			T15	1		T37	1		T5	3
auto[1744830464:1879048191]	auto[1]	53	1			T1	1		T16	1		T25	1
auto[1879048192:2013265919]	auto[0]	51	1			T4	2		T28	1		T5	1
auto[1879048192:2013265919]	auto[1]	56	1			T2	1		T4	1		T5	1
auto[2013265920:2147483647]	auto[0]	58	1			T15	1		T34	1		T25	1
auto[2013265920:2147483647]	auto[1]	59	1			T44	1		T25	1		T5	1
auto[2147483648:2281701375]	auto[0]	37	1			T2	1		T3	1		T4	1
auto[2147483648:2281701375]	auto[1]	66	1			T25	1		T77	1		T64	1
auto[2281701376:2415919103]	auto[0]	44	1			T269	1		T53	1		T46	1
auto[2281701376:2415919103]	auto[1]	41	1			T237	1		T269	1		T408	2
auto[2415919104:2550136831]	auto[0]	53	1			T88	1		T4	1		T28	1
auto[2415919104:2550136831]	auto[1]	58	1			T2	1		T25	1		T93	1
auto[2550136832:2684354559]	auto[0]	48	1			T45	1		T244	1		T53	1
auto[2550136832:2684354559]	auto[1]	58	1			T44	1		T77	1		T64	1
auto[2684354560:2818572287]	auto[0]	44	1			T25	2		T5	1		T408	1
auto[2684354560:2818572287]	auto[1]	51	1			T54	1		T68	1		T297	1
auto[2818572288:2952790015]	auto[0]	40	1			T3	1		T25	1		T4	2
auto[2818572288:2952790015]	auto[1]	59	1			T10	1		T346	1		T86	1
auto[2952790016:3087007743]	auto[0]	38	1			T1	1		T54	1		T5	1
auto[2952790016:3087007743]	auto[1]	55	1			T13	1		T25	1		T52	1
auto[3087007744:3221225471]	auto[0]	52	1			T44	1		T5	1		T47	1
auto[3087007744:3221225471]	auto[1]	61	1			T67	1		T81	1		T82	1
auto[3221225472:3355443199]	auto[0]	43	1			T44	1		T4	1		T37	1
auto[3221225472:3355443199]	auto[1]	56	1			T13	1		T64	1		T67	1
auto[3355443200:3489660927]	auto[0]	48	1			T1	1		T26	1		T67	1
auto[3355443200:3489660927]	auto[1]	50	1			T25	1		T27	1		T4	1
auto[3489660928:3623878655]	auto[0]	53	1			T44	1		T25	1		T54	1
auto[3489660928:3623878655]	auto[1]	58	1			T13	1		T16	1		T54	2
auto[3623878656:3758096383]	auto[0]	56	1			T1	1		T15	1		T44	1
auto[3623878656:3758096383]	auto[1]	50	1			T13	1		T4	1		T52	1
auto[3758096384:3892314111]	auto[0]	49	1			T5	2		T45	1		T234	1
auto[3758096384:3892314111]	auto[1]	56	1			T44	1		T316	1		T53	1
auto[3892314112:4026531839]	auto[0]	57	1			T4	1		T5	2		T45	1
auto[3892314112:4026531839]	auto[1]	46	1			T16	1		T25	1		T5	1
auto[4026531840:4160749567]	auto[0]	47	1			T45	1		T238	1		T257	1
auto[4026531840:4160749567]	auto[1]	72	1			T10	1		T26	1		T5	1
auto[4160749568:4294967295]	auto[0]	47	1			T4	1		T54	1		T5	3
auto[4160749568:4294967295]	auto[1]	60	1			T16	1		T25	1		T27	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1581

1

T1

6

T2

2

T3

3

auto[1]

1770

1

T2

3

T3

1

T10

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	88	1			T13	2		T4	1		T54	1
auto[134217728:268435455]	93	1			T15	1		T44	1		T4	1
auto[268435456:402653183]	115	1			T15	1		T4	3		T28	1
auto[402653184:536870911]	106	1			T3	1		T25	2		T64	1
auto[536870912:671088639]	88	1			T2	1		T25	1		T77	1
auto[671088640:805306367]	94	1			T2	1		T25	2		T77	1
auto[805306368:939524095]	120	1			T44	1		T25	3		T77	1
auto[939524096:1073741823]	106	1			T16	1		T25	2		T27	1
auto[1073741824:1207959551]	110	1			T3	1		T25	1		T26	1
auto[1207959552:1342177279]	119	1			T44	1		T77	1		T88	1
auto[1342177280:1476395007]	100	1			T11	1		T13	1		T25	1
auto[1476395008:1610612735]	98	1			T13	1		T25	1		T37	1
auto[1610612736:1744830463]	106	1			T67	1		T4	1		T119	1
auto[1744830464:1879048191]	97	1			T3	1		T34	1		T25	1
auto[1879048192:2013265919]	99	1			T15	1		T25	1		T4	1
auto[2013265920:2147483647]	77	1			T16	1		T25	2		T67	1
auto[2147483648:2281701375]	115	1			T1	1		T34	1		T44	1
auto[2281701376:2415919103]	118	1			T44	1		T25	1		T17	1
auto[2415919104:2550136831]	108	1			T1	1		T10	1		T13	1
auto[2550136832:2684354559]	119	1			T2	1		T4	1		T37	1
auto[2684354560:2818572287]	122	1			T1	1		T2	1		T10	1
auto[2818572288:2952790015]	109	1			T16	1		T25	2		T26	1
auto[2952790016:3087007743]	98	1			T2	1		T34	1		T25	1
auto[3087007744:3221225471]	104	1			T3	1		T37	1		T54	1
auto[3221225472:3355443199]	86	1			T1	1		T44	1		T4	1
auto[3355443200:3489660927]	115	1			T16	1		T25	1		T27	1
auto[3489660928:3623878655]	113	1			T15	1		T25	1		T67	1
auto[3623878656:3758096383]	110	1			T1	1		T26	1		T64	1
auto[3758096384:3892314111]	104	1			T15	1		T16	1		T44	1
auto[3892314112:4026531839]	108	1			T1	1		T10	1		T25	1
auto[4026531840:4160749567]	94	1			T93	1		T4	1		T54	2
auto[4160749568:4294967295]	112	1			T15	1		T25	1		T4	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	45	1			T13	1		T4	1		T5	1
auto[0:134217727]	auto[1]	43	1			T13	1		T54	1		T55	1
auto[134217728:268435455]	auto[0]	45	1			T44	1		T4	1		T5	1
auto[134217728:268435455]	auto[1]	48	1			T15	1		T37	1		T52	1
auto[268435456:402653183]	auto[0]	69	1			T15	1		T4	2		T28	1
auto[268435456:402653183]	auto[1]	46	1			T4	1		T45	1		T86	1
auto[402653184:536870911]	auto[0]	48	1			T3	1		T67	1		T257	1
auto[402653184:536870911]	auto[1]	58	1			T25	2		T64	1		T37	1
auto[536870912:671088639]	auto[0]	40	1			T2	1		T25	1		T4	1
auto[536870912:671088639]	auto[1]	48	1			T77	1		T54	1		T346	1
auto[671088640:805306367]	auto[0]	39	1			T52	1		T5	2		T45	2
auto[671088640:805306367]	auto[1]	55	1			T2	1		T25	2		T77	1
auto[805306368:939524095]	auto[0]	50	1			T77	1		T4	3		T54	2
auto[805306368:939524095]	auto[1]	70	1			T44	1		T25	3		T5	1
auto[939524096:1073741823]	auto[0]	51	1			T16	1		T25	1		T27	1
auto[939524096:1073741823]	auto[1]	55	1			T25	1		T5	1		T244	1
auto[1073741824:1207959551]	auto[0]	55	1			T3	1		T4	1		T5	2
auto[1073741824:1207959551]	auto[1]	55	1			T25	1		T26	1		T27	1
auto[1207959552:1342177279]	auto[0]	59	1			T44	1		T88	1		T37	1
auto[1207959552:1342177279]	auto[1]	60	1			T77	1		T5	1		T81	1
auto[1342177280:1476395007]	auto[0]	43	1			T11	1		T25	1		T67	1
auto[1342177280:1476395007]	auto[1]	57	1			T13	1		T64	1		T5	1
auto[1476395008:1610612735]	auto[0]	50	1			T25	1		T37	1		T235	1
auto[1476395008:1610612735]	auto[1]	48	1			T13	1		T297	1		T192	1
auto[1610612736:1744830463]	auto[0]	51	1			T67	1		T4	1		T54	1
auto[1610612736:1744830463]	auto[1]	55	1			T119	1		T54	1		T5	3
auto[1744830464:1879048191]	auto[0]	41	1			T34	1		T64	1		T28	1
auto[1744830464:1879048191]	auto[1]	56	1			T3	1		T25	1		T238	1
auto[1879048192:2013265919]	auto[0]	38	1			T235	1		T6	1		T297	1
auto[1879048192:2013265919]	auto[1]	61	1			T15	1		T25	1		T4	1
auto[2013265920:2147483647]	auto[0]	37	1			T67	1		T133	1		T45	1
auto[2013265920:2147483647]	auto[1]	40	1			T16	1		T25	2		T5	1
auto[2147483648:2281701375]	auto[0]	59	1			T1	1		T34	1		T4	1
auto[2147483648:2281701375]	auto[1]	56	1			T44	1		T88	1		T55	1
auto[2281701376:2415919103]	auto[0]	55	1			T44	1		T25	1		T5	1
auto[2281701376:2415919103]	auto[1]	63	1			T17	1		T27	1		T4	1
auto[2415919104:2550136831]	auto[0]	46	1			T1	1		T4	1		T5	3
auto[2415919104:2550136831]	auto[1]	62	1			T10	1		T13	1		T44	1
auto[2550136832:2684354559]	auto[0]	48	1			T2	1		T4	1		T45	3
auto[2550136832:2684354559]	auto[1]	71	1			T37	1		T80	1		T297	1
auto[2684354560:2818572287]	auto[0]	57	1			T1	1		T25	1		T26	1
auto[2684354560:2818572287]	auto[1]	65	1			T2	1		T10	1		T54	1
auto[2818572288:2952790015]	auto[0]	51	1			T16	1		T47	1		T18	1
auto[2818572288:2952790015]	auto[1]	58	1			T25	2		T26	1		T4	1
auto[2952790016:3087007743]	auto[0]	45	1			T34	1		T26	1		T88	1
auto[2952790016:3087007743]	auto[1]	53	1			T2	1		T25	1		T46	1
auto[3087007744:3221225471]	auto[0]	44	1			T3	1		T37	1		T5	1
auto[3087007744:3221225471]	auto[1]	60	1			T54	1		T45	2		T237	1
auto[3221225472:3355443199]	auto[0]	37	1			T1	1		T44	1		T4	1
auto[3221225472:3355443199]	auto[1]	49	1			T133	1		T269	1		T238	1
auto[3355443200:3489660927]	auto[0]	55	1			T93	1		T4	1		T54	1
auto[3355443200:3489660927]	auto[1]	60	1			T16	1		T25	1		T27	1
auto[3489660928:3623878655]	auto[0]	54	1			T15	1		T4	1		T5	2
auto[3489660928:3623878655]	auto[1]	59	1			T25	1		T67	1		T5	1
auto[3623878656:3758096383]	auto[0]	61	1			T1	1		T64	1		T4	1
auto[3623878656:3758096383]	auto[1]	49	1			T26	1		T5	1		T230	1
auto[3758096384:3892314111]	auto[0]	45	1			T15	1		T4	1		T54	1
auto[3758096384:3892314111]	auto[1]	59	1			T16	1		T44	1		T64	1
auto[3892314112:4026531839]	auto[0]	51	1			T1	1		T67	1		T37	1
auto[3892314112:4026531839]	auto[1]	57	1			T10	1		T25	1		T4	2
auto[4026531840:4160749567]	auto[0]	48	1			T54	1		T5	1		T45	1
auto[4026531840:4160749567]	auto[1]	46	1			T93	1		T4	1		T54	1
auto[4160749568:4294967295]	auto[0]	64	1			T15	1		T25	1		T5	1
auto[4160749568:4294967295]	auto[1]	48	1			T4	1		T68	1		T18	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1543

1

T1

4

T2

2

T3

3

auto[1]

1808

1

T1

2

T2

3

T3

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	112	1			T13	1		T4	1		T5	1
auto[134217728:268435455]	96	1			T25	2		T67	2		T4	1
auto[268435456:402653183]	103	1			T16	1		T25	1		T77	1
auto[402653184:536870911]	97	1			T15	1		T34	2		T44	1
auto[536870912:671088639]	120	1			T2	1		T10	1		T16	2
auto[671088640:805306367]	103	1			T2	1		T13	1		T54	1
auto[805306368:939524095]	104	1			T2	1		T34	1		T25	1
auto[939524096:1073741823]	98	1			T2	1		T16	1		T25	1
auto[1073741824:1207959551]	111	1			T25	1		T26	1		T88	1
auto[1207959552:1342177279]	113	1			T25	1		T27	1		T93	1
auto[1342177280:1476395007]	101	1			T1	1		T27	1		T4	1
auto[1476395008:1610612735]	109	1			T3	2		T13	1		T25	2
auto[1610612736:1744830463]	101	1			T4	1		T5	2		T235	1
auto[1744830464:1879048191]	117	1			T44	1		T25	1		T4	2
auto[1879048192:2013265919]	111	1			T1	1		T15	1		T4	1
auto[2013265920:2147483647]	104	1			T10	1		T25	2		T64	2
auto[2147483648:2281701375]	104	1			T3	1		T25	1		T27	1
auto[2281701376:2415919103]	89	1			T44	1		T93	1		T4	1
auto[2415919104:2550136831]	93	1			T10	1		T25	1		T77	1
auto[2550136832:2684354559]	119	1			T25	2		T77	1		T5	2
auto[2684354560:2818572287]	93	1			T1	1		T15	1		T4	2
auto[2818572288:2952790015]	104	1			T44	1		T4	1		T5	3
auto[2952790016:3087007743]	107	1			T44	1		T25	2		T5	2
auto[3087007744:3221225471]	105	1			T13	1		T44	2		T25	3
auto[3221225472:3355443199]	96	1			T1	1		T3	1		T4	1
auto[3355443200:3489660927]	110	1			T1	1		T25	1		T64	1
auto[3489660928:3623878655]	97	1			T13	1		T77	1		T26	1
auto[3623878656:3758096383]	109	1			T26	1		T4	1		T5	1
auto[3758096384:3892314111]	118	1			T15	1		T26	1		T93	1
auto[3892314112:4026531839]	94	1			T2	1		T15	2		T25	2
auto[4026531840:4160749567]	90	1			T16	1		T4	1		T48	1
auto[4160749568:4294967295]	123	1			T1	1		T11	1		T44	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	61	1			T4	1		T5	1		T235	1
auto[0:134217727]	auto[1]	51	1			T13	1		T269	1		T241	1
auto[134217728:268435455]	auto[0]	37	1			T25	1		T67	2		T4	1
auto[134217728:268435455]	auto[1]	59	1			T25	1		T5	1		T297	1
auto[268435456:402653183]	auto[0]	50	1			T16	1		T25	1		T77	1
auto[268435456:402653183]	auto[1]	53	1			T30	1		T269	1		T46	1
auto[402653184:536870911]	auto[0]	41	1			T34	1		T52	1		T45	2
auto[402653184:536870911]	auto[1]	56	1			T15	1		T34	1		T44	1
auto[536870912:671088639]	auto[0]	54	1			T4	1		T52	1		T54	2
auto[536870912:671088639]	auto[1]	66	1			T2	1		T10	1		T16	2
auto[671088640:805306367]	auto[0]	42	1			T5	2		T48	1		T6	1
auto[671088640:805306367]	auto[1]	61	1			T2	1		T13	1		T54	1
auto[805306368:939524095]	auto[0]	57	1			T2	1		T34	1		T67	1
auto[805306368:939524095]	auto[1]	47	1			T25	1		T119	1		T81	1
auto[939524096:1073741823]	auto[0]	45	1			T2	1		T16	1		T88	1
auto[939524096:1073741823]	auto[1]	53	1			T25	1		T5	2		T235	1
auto[1073741824:1207959551]	auto[0]	42	1			T4	1		T54	2		T287	1
auto[1073741824:1207959551]	auto[1]	69	1			T25	1		T26	1		T88	1
auto[1207959552:1342177279]	auto[0]	54	1			T67	1		T4	1		T411	1
auto[1207959552:1342177279]	auto[1]	59	1			T25	1		T27	1		T93	1
auto[1342177280:1476395007]	auto[0]	42	1			T4	1		T37	1		T45	2
auto[1342177280:1476395007]	auto[1]	59	1			T1	1		T27	1		T37	1
auto[1476395008:1610612735]	auto[0]	43	1			T3	1		T25	1		T64	1
auto[1476395008:1610612735]	auto[1]	66	1			T3	1		T13	1		T25	1
auto[1610612736:1744830463]	auto[0]	50	1			T5	2		T46	1		T60	2
auto[1610612736:1744830463]	auto[1]	51	1			T4	1		T235	1		T230	1
auto[1744830464:1879048191]	auto[0]	44	1			T44	1		T25	1		T4	1
auto[1744830464:1879048191]	auto[1]	73	1			T4	1		T54	1		T5	1
auto[1879048192:2013265919]	auto[0]	56	1			T4	1		T28	1		T5	1
auto[1879048192:2013265919]	auto[1]	55	1			T1	1		T15	1		T52	2
auto[2013265920:2147483647]	auto[0]	49	1			T25	1		T4	1		T37	2
auto[2013265920:2147483647]	auto[1]	55	1			T10	1		T25	1		T64	2
auto[2147483648:2281701375]	auto[0]	46	1			T3	1		T4	1		T344	1
auto[2147483648:2281701375]	auto[1]	58	1			T25	1		T27	1		T121	1
auto[2281701376:2415919103]	auto[0]	36	1			T4	1		T5	1		T46	1
auto[2281701376:2415919103]	auto[1]	53	1			T44	1		T93	1		T55	2
auto[2415919104:2550136831]	auto[0]	39	1			T4	1		T37	1		T47	1
auto[2415919104:2550136831]	auto[1]	54	1			T10	1		T25	1		T77	1
auto[2550136832:2684354559]	auto[0]	57	1			T5	2		T47	2		T230	1
auto[2550136832:2684354559]	auto[1]	62	1			T25	2		T77	1		T421	1
auto[2684354560:2818572287]	auto[0]	41	1			T1	1		T15	1		T4	2
auto[2684354560:2818572287]	auto[1]	52	1			T5	1		T56	1		T60	2
auto[2818572288:2952790015]	auto[0]	57	1			T44	1		T5	3		T18	1
auto[2818572288:2952790015]	auto[1]	47	1			T4	1		T86	1		T46	1
auto[2952790016:3087007743]	auto[0]	53	1			T44	1		T25	2		T5	1
auto[2952790016:3087007743]	auto[1]	54	1			T5	1		T45	1		T297	1
auto[3087007744:3221225471]	auto[0]	51	1			T44	1		T25	2		T119	1
auto[3087007744:3221225471]	auto[1]	54	1			T13	1		T44	1		T25	1
auto[3221225472:3355443199]	auto[0]	49	1			T1	1		T3	1		T37	1
auto[3221225472:3355443199]	auto[1]	47	1			T4	1		T45	1		T53	1
auto[3355443200:3489660927]	auto[0]	54	1			T1	1		T25	1		T88	1
auto[3355443200:3489660927]	auto[1]	56	1			T64	1		T5	2		T421	1
auto[3489660928:3623878655]	auto[0]	42	1			T77	1		T26	1		T5	1
auto[3489660928:3623878655]	auto[1]	55	1			T13	1		T67	1		T18	1
auto[3623878656:3758096383]	auto[0]	48	1			T5	1		T53	1		T46	2
auto[3623878656:3758096383]	auto[1]	61	1			T26	1		T4	1		T45	1
auto[3758096384:3892314111]	auto[0]	60	1			T15	1		T26	1		T93	1
auto[3758096384:3892314111]	auto[1]	58	1			T81	1		T45	1		T237	1
auto[3892314112:4026531839]	auto[0]	44	1			T15	2		T25	1		T54	1
auto[3892314112:4026531839]	auto[1]	50	1			T2	1		T25	1		T5	1
auto[4026531840:4160749567]	auto[0]	39	1			T4	1		T48	1		T269	1
auto[4026531840:4160749567]	auto[1]	51	1			T16	1		T82	1		T237	1
auto[4160749568:4294967295]	auto[0]	60	1			T1	1		T11	1		T4	2
auto[4160749568:4294967295]	auto[1]	63	1			T44	1		T25	1		T17	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1571

1

T1

4

T2

2

T3

3

auto[1]

1780

1

T1

2

T2

3

T3

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	95	1			T34	1		T25	1		T4	1
auto[134217728:268435455]	108	1			T3	1		T44	2		T26	1
auto[268435456:402653183]	121	1			T3	1		T25	1		T64	1
auto[402653184:536870911]	77	1			T44	1		T77	1		T4	1
auto[536870912:671088639]	103	1			T13	1		T4	1		T5	1
auto[671088640:805306367]	86	1			T25	1		T17	1		T4	1
auto[805306368:939524095]	103	1			T2	1		T15	1		T34	1
auto[939524096:1073741823]	96	1			T25	1		T37	1		T54	3
auto[1073741824:1207959551]	119	1			T25	1		T67	1		T37	1
auto[1207959552:1342177279]	95	1			T64	1		T88	1		T4	1
auto[1342177280:1476395007]	94	1			T2	1		T34	1		T44	1
auto[1476395008:1610612735]	108	1			T1	1		T15	1		T88	1
auto[1610612736:1744830463]	113	1			T10	1		T25	2		T4	1
auto[1744830464:1879048191]	98	1			T2	1		T25	1		T27	1
auto[1879048192:2013265919]	106	1			T1	1		T16	1		T25	1
auto[2013265920:2147483647]	111	1			T2	1		T3	1		T25	1
auto[2147483648:2281701375]	126	1			T10	2		T25	1		T27	1
auto[2281701376:2415919103]	112	1			T1	1		T15	1		T25	1
auto[2415919104:2550136831]	111	1			T2	1		T15	1		T44	1
auto[2550136832:2684354559]	96	1			T1	1		T25	2		T64	1
auto[2684354560:2818572287]	95	1			T16	1		T52	1		T5	3
auto[2818572288:2952790015]	99	1			T25	1		T27	1		T45	2
auto[2952790016:3087007743]	95	1			T13	2		T15	1		T44	1
auto[3087007744:3221225471]	98	1			T16	1		T77	1		T64	2
auto[3221225472:3355443199]	127	1			T16	1		T4	3		T68	1
auto[3355443200:3489660927]	96	1			T25	1		T26	1		T4	1
auto[3489660928:3623878655]	108	1			T3	1		T11	1		T4	1
auto[3623878656:3758096383]	125	1			T13	1		T25	1		T77	1
auto[3758096384:3892314111]	106	1			T1	1		T15	1		T44	1
auto[3892314112:4026531839]	117	1			T13	1		T25	2		T5	1
auto[4026531840:4160749567]	110	1			T1	1		T16	1		T44	1
auto[4160749568:4294967295]	97	1			T25	2		T4	2		T54	1