Unified Coverage Report :: Group Instance : salt_4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2932

1

T1

6

T2

5

T3

4

auto[1]

295

1

T2

5

T133

4

T225

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	79	1			T54	1		T48	1		T133	2
auto[134217728:268435455]	101	1			T44	1		T25	1		T77	1
auto[268435456:402653183]	88	1			T2	1		T44	1		T26	1
auto[402653184:536870911]	94	1			T15	1		T16	1		T34	1
auto[536870912:671088639]	113	1			T44	1		T25	1		T88	1
auto[671088640:805306367]	97	1			T25	1		T54	1		T5	2
auto[805306368:939524095]	91	1			T1	1		T3	1		T25	1
auto[939524096:1073741823]	118	1			T25	1		T88	1		T54	1
auto[1073741824:1207959551]	85	1			T11	1		T25	1		T67	1
auto[1207959552:1342177279]	94	1			T34	1		T54	1		T133	2
auto[1342177280:1476395007]	90	1			T1	1		T3	1		T25	1
auto[1476395008:1610612735]	110	1			T1	1		T2	1		T3	1
auto[1610612736:1744830463]	106	1			T15	1		T77	1		T27	1
auto[1744830464:1879048191]	97	1			T2	1		T15	1		T16	1
auto[1879048192:2013265919]	89	1			T44	1		T25	1		T93	1
auto[2013265920:2147483647]	108	1			T2	1		T13	1		T25	1
auto[2147483648:2281701375]	96	1			T10	1		T13	1		T44	1
auto[2281701376:2415919103]	112	1			T1	1		T3	1		T15	1
auto[2415919104:2550136831]	95	1			T1	1		T2	2		T25	1
auto[2550136832:2684354559]	109	1			T4	1		T37	1		T54	1
auto[2684354560:2818572287]	110	1			T34	1		T44	1		T47	1
auto[2818572288:2952790015]	107	1			T2	1		T25	1		T67	2
auto[2952790016:3087007743]	112	1			T2	1		T13	1		T25	1
auto[3087007744:3221225471]	94	1			T13	1		T15	2		T26	1
auto[3221225472:3355443199]	122	1			T10	1		T25	1		T64	1
auto[3355443200:3489660927]	98	1			T2	1		T44	1		T25	1
auto[3489660928:3623878655]	101	1			T25	1		T26	1		T93	1
auto[3623878656:3758096383]	81	1			T2	1		T54	2		T230	1
auto[3758096384:3892314111]	116	1			T1	1		T25	3		T77	1
auto[3892314112:4026531839]	116	1			T25	1		T77	1		T67	1
auto[4026531840:4160749567]	102	1			T25	1		T37	1		T5	1
auto[4160749568:4294967295]	96	1			T10	1		T44	1		T25	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	69	1			T54	1		T48	1		T133	1
auto[0:134217727]	auto[1]	10	1			T133	1		T226	1		T420	1
auto[134217728:268435455]	auto[0]	95	1			T44	1		T25	1		T77	1
auto[134217728:268435455]	auto[1]	6	1			T127	1		T249	2		T418	1
auto[268435456:402653183]	auto[0]	78	1			T44	1		T26	1		T37	2
auto[268435456:402653183]	auto[1]	10	1			T2	1		T328	2		T226	1
auto[402653184:536870911]	auto[0]	86	1			T15	1		T16	1		T34	1
auto[402653184:536870911]	auto[1]	8	1			T225	1		T328	1		T420	1
auto[536870912:671088639]	auto[0]	100	1			T44	1		T25	1		T88	1
auto[536870912:671088639]	auto[1]	13	1			T123	1		T226	1		T127	1
auto[671088640:805306367]	auto[0]	93	1			T25	1		T54	1		T5	2
auto[671088640:805306367]	auto[1]	4	1			T123	1		T315	1		T426	1
auto[805306368:939524095]	auto[0]	83	1			T1	1		T3	1		T25	1
auto[805306368:939524095]	auto[1]	8	1			T126	1		T420	1		T247	2
auto[939524096:1073741823]	auto[0]	106	1			T25	1		T88	1		T54	1
auto[939524096:1073741823]	auto[1]	12	1			T225	1		T123	1		T226	1
auto[1073741824:1207959551]	auto[0]	77	1			T11	1		T25	1		T67	1
auto[1073741824:1207959551]	auto[1]	8	1			T125	1		T127	1		T227	1
auto[1207959552:1342177279]	auto[0]	83	1			T34	1		T54	1		T133	1
auto[1207959552:1342177279]	auto[1]	11	1			T133	1		T123	1		T125	2
auto[1342177280:1476395007]	auto[0]	85	1			T1	1		T3	1		T25	1
auto[1342177280:1476395007]	auto[1]	5	1			T360	1		T419	1		T248	1
auto[1476395008:1610612735]	auto[0]	104	1			T1	1		T3	1		T13	1
auto[1476395008:1610612735]	auto[1]	6	1			T2	1		T226	1		T417	1
auto[1610612736:1744830463]	auto[0]	95	1			T15	1		T77	1		T27	1
auto[1610612736:1744830463]	auto[1]	11	1			T126	1		T127	1		T249	2
auto[1744830464:1879048191]	auto[0]	89	1			T2	1		T15	1		T16	1
auto[1744830464:1879048191]	auto[1]	8	1			T225	1		T249	1		T420	1
auto[1879048192:2013265919]	auto[0]	83	1			T44	1		T25	1		T93	1
auto[1879048192:2013265919]	auto[1]	6	1			T125	1		T270	1		T337	1
auto[2013265920:2147483647]	auto[0]	94	1			T2	1		T13	1		T25	1
auto[2013265920:2147483647]	auto[1]	14	1			T126	2		T249	1		T227	1
auto[2147483648:2281701375]	auto[0]	81	1			T10	1		T13	1		T44	1
auto[2147483648:2281701375]	auto[1]	15	1			T328	2		T226	1		T417	1
auto[2281701376:2415919103]	auto[0]	102	1			T1	1		T3	1		T15	1
auto[2281701376:2415919103]	auto[1]	10	1			T125	1		T418	1		T273	1
auto[2415919104:2550136831]	auto[0]	81	1			T1	1		T2	1		T25	1
auto[2415919104:2550136831]	auto[1]	14	1			T2	1		T225	1		T123	2
auto[2550136832:2684354559]	auto[0]	106	1			T4	1		T37	1		T54	1
auto[2550136832:2684354559]	auto[1]	3	1			T226	1		T270	1		T423	1
auto[2684354560:2818572287]	auto[0]	101	1			T34	1		T44	1		T47	1
auto[2684354560:2818572287]	auto[1]	9	1			T249	1		T415	1		T98	1
auto[2818572288:2952790015]	auto[0]	99	1			T25	1		T67	2		T4	1
auto[2818572288:2952790015]	auto[1]	8	1			T2	1		T227	1		T323	2
auto[2952790016:3087007743]	auto[0]	100	1			T2	1		T13	1		T25	1
auto[2952790016:3087007743]	auto[1]	12	1			T328	1		T125	1		T249	2
auto[3087007744:3221225471]	auto[0]	87	1			T13	1		T15	2		T26	1
auto[3087007744:3221225471]	auto[1]	7	1			T124	1		T360	1		T270	1
auto[3221225472:3355443199]	auto[0]	110	1			T10	1		T25	1		T64	1
auto[3221225472:3355443199]	auto[1]	12	1			T133	1		T123	1		T226	1
auto[3355443200:3489660927]	auto[0]	89	1			T44	1		T25	1		T4	1
auto[3355443200:3489660927]	auto[1]	9	1			T2	1		T127	1		T418	2
auto[3489660928:3623878655]	auto[0]	93	1			T25	1		T26	1		T93	1
auto[3489660928:3623878655]	auto[1]	8	1			T227	1		T273	2		T399	2
auto[3623878656:3758096383]	auto[0]	76	1			T2	1		T54	2		T230	1
auto[3623878656:3758096383]	auto[1]	5	1			T126	1		T417	1		T399	2
auto[3758096384:3892314111]	auto[0]	105	1			T1	1		T25	3		T77	1
auto[3758096384:3892314111]	auto[1]	11	1			T127	1		T420	1		T419	1
auto[3892314112:4026531839]	auto[0]	101	1			T25	1		T77	1		T67	1
auto[3892314112:4026531839]	auto[1]	15	1			T328	2		T126	1		T127	1
auto[4026531840:4160749567]	auto[0]	93	1			T25	1		T37	1		T5	1
auto[4026531840:4160749567]	auto[1]	9	1			T133	1		T127	1		T418	1
auto[4160749568:4294967295]	auto[0]	88	1			T10	1		T44	1		T25	2
auto[4160749568:4294967295]	auto[1]	8	1			T127	1		T360	1		T227	1