Unified Coverage Report :: Group Instance : sealing_sw_binding_6

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1578

1

T1

6

T2

2

T3

3

auto[1]

1773

1

T2

3

T3

1

T10

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T1	1		T34	1		T25	2
auto[134217728:268435455]	106	1			T88	1		T4	1		T230	2
auto[268435456:402653183]	92	1			T34	1		T25	1		T67	1
auto[402653184:536870911]	103	1			T25	4		T119	1		T5	1
auto[536870912:671088639]	105	1			T26	1		T93	1		T67	1
auto[671088640:805306367]	117	1			T2	1		T3	1		T13	1
auto[805306368:939524095]	100	1			T44	1		T25	1		T4	1
auto[939524096:1073741823]	119	1			T1	1		T15	1		T119	1
auto[1073741824:1207959551]	116	1			T44	1		T25	2		T64	1
auto[1207959552:1342177279]	108	1			T44	2		T77	1		T4	3
auto[1342177280:1476395007]	110	1			T15	2		T25	1		T4	3
auto[1476395008:1610612735]	106	1			T93	1		T67	1		T4	1
auto[1610612736:1744830463]	111	1			T1	1		T2	1		T13	1
auto[1744830464:1879048191]	95	1			T13	1		T26	1		T52	1
auto[1879048192:2013265919]	102	1			T44	1		T77	1		T48	1
auto[2013265920:2147483647]	96	1			T1	1		T25	1		T55	1
auto[2147483648:2281701375]	101	1			T1	1		T13	1		T25	1
auto[2281701376:2415919103]	116	1			T1	1		T10	1		T25	3
auto[2415919104:2550136831]	116	1			T3	1		T16	1		T44	1
auto[2550136832:2684354559]	97	1			T3	1		T10	1		T13	1
auto[2684354560:2818572287]	105	1			T2	1		T3	1		T25	1
auto[2818572288:2952790015]	92	1			T27	1		T67	1		T37	1
auto[2952790016:3087007743]	81	1			T11	1		T16	2		T67	1
auto[3087007744:3221225471]	103	1			T15	1		T25	1		T77	1
auto[3221225472:3355443199]	98	1			T25	1		T88	1		T4	4
auto[3355443200:3489660927]	110	1			T25	1		T4	3		T54	1
auto[3489660928:3623878655]	105	1			T64	2		T27	1		T54	1
auto[3623878656:3758096383]	112	1			T15	1		T34	1		T88	1
auto[3758096384:3892314111]	125	1			T10	1		T25	2		T4	2
auto[3892314112:4026531839]	109	1			T16	1		T37	1		T55	1
auto[4026531840:4160749567]	93	1			T15	1		T44	1		T5	2
auto[4160749568:4294967295]	94	1			T2	2		T25	2		T64	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	45	1			T1	1		T34	1		T25	2
auto[0:134217727]	auto[1]	63	1			T55	1		T45	4		T269	1
auto[134217728:268435455]	auto[0]	56	1			T88	1		T4	1		T230	2
auto[134217728:268435455]	auto[1]	50	1			T53	1		T421	1		T46	1
auto[268435456:402653183]	auto[0]	42	1			T34	1		T67	1		T241	1
auto[268435456:402653183]	auto[1]	50	1			T25	1		T37	2		T54	1
auto[402653184:536870911]	auto[0]	41	1			T25	2		T235	1		T244	2
auto[402653184:536870911]	auto[1]	62	1			T25	2		T119	1		T5	1
auto[536870912:671088639]	auto[0]	46	1			T26	1		T67	1		T47	1
auto[536870912:671088639]	auto[1]	59	1			T93	1		T5	1		T45	1
auto[671088640:805306367]	auto[0]	48	1			T3	1		T4	1		T45	2
auto[671088640:805306367]	auto[1]	69	1			T2	1		T13	1		T16	1
auto[805306368:939524095]	auto[0]	53	1			T4	1		T54	2		T5	2
auto[805306368:939524095]	auto[1]	47	1			T44	1		T25	1		T373	1
auto[939524096:1073741823]	auto[0]	62	1			T1	1		T15	1		T119	1
auto[939524096:1073741823]	auto[1]	57	1			T237	1		T244	1		T53	1
auto[1073741824:1207959551]	auto[0]	51	1			T54	1		T5	3		T46	1
auto[1073741824:1207959551]	auto[1]	65	1			T44	1		T25	2		T64	1
auto[1207959552:1342177279]	auto[0]	49	1			T44	1		T77	1		T4	3
auto[1207959552:1342177279]	auto[1]	59	1			T44	1		T54	1		T28	1
auto[1342177280:1476395007]	auto[0]	47	1			T15	1		T4	2		T54	1
auto[1342177280:1476395007]	auto[1]	63	1			T15	1		T25	1		T4	1
auto[1476395008:1610612735]	auto[0]	44	1			T67	1		T4	1		T5	2
auto[1476395008:1610612735]	auto[1]	62	1			T93	1		T5	1		T45	1
auto[1610612736:1744830463]	auto[0]	48	1			T1	1		T4	1		T54	1
auto[1610612736:1744830463]	auto[1]	63	1			T2	1		T13	1		T25	2
auto[1744830464:1879048191]	auto[0]	43	1			T235	1		T244	1		T6	1
auto[1744830464:1879048191]	auto[1]	52	1			T13	1		T26	1		T52	1
auto[1879048192:2013265919]	auto[0]	52	1			T44	1		T48	1		T269	1
auto[1879048192:2013265919]	auto[1]	50	1			T77	1		T80	2		T350	1
auto[2013265920:2147483647]	auto[0]	42	1			T1	1		T5	1		T257	1
auto[2013265920:2147483647]	auto[1]	54	1			T25	1		T55	1		T46	1
auto[2147483648:2281701375]	auto[0]	45	1			T1	1		T13	1		T25	1
auto[2147483648:2281701375]	auto[1]	56	1			T26	1		T4	1		T54	1
auto[2281701376:2415919103]	auto[0]	58	1			T1	1		T5	1		T45	1
auto[2281701376:2415919103]	auto[1]	58	1			T10	1		T25	3		T4	1
auto[2415919104:2550136831]	auto[0]	53	1			T44	1		T26	1		T86	1
auto[2415919104:2550136831]	auto[1]	63	1			T3	1		T16	1		T54	1
auto[2550136832:2684354559]	auto[0]	56	1			T3	1		T27	1		T37	1
auto[2550136832:2684354559]	auto[1]	41	1			T10	1		T13	1		T77	1
auto[2684354560:2818572287]	auto[0]	53	1			T2	1		T3	1		T67	1
auto[2684354560:2818572287]	auto[1]	52	1			T25	1		T26	1		T4	1
auto[2818572288:2952790015]	auto[0]	50	1			T67	1		T37	1		T5	1
auto[2818572288:2952790015]	auto[1]	42	1			T27	1		T121	1		T5	1
auto[2952790016:3087007743]	auto[0]	39	1			T16	1		T67	1		T4	1
auto[2952790016:3087007743]	auto[1]	42	1			T11	1		T16	1		T421	2
auto[3087007744:3221225471]	auto[0]	52	1			T15	1		T4	1		T37	1
auto[3087007744:3221225471]	auto[1]	51	1			T25	1		T77	1		T4	1
auto[3221225472:3355443199]	auto[0]	50	1			T4	3		T37	1		T47	1
auto[3221225472:3355443199]	auto[1]	48	1			T25	1		T88	1		T4	1
auto[3355443200:3489660927]	auto[0]	49	1			T4	3		T5	2		T46	1
auto[3355443200:3489660927]	auto[1]	61	1			T25	1		T54	1		T5	1
auto[3489660928:3623878655]	auto[0]	47	1			T54	1		T5	2		T47	2
auto[3489660928:3623878655]	auto[1]	58	1			T64	2		T27	1		T5	1
auto[3623878656:3758096383]	auto[0]	46	1			T82	1		T269	1		T234	1
auto[3623878656:3758096383]	auto[1]	66	1			T15	1		T34	1		T88	1
auto[3758096384:3892314111]	auto[0]	59	1			T25	1		T4	2		T37	1
auto[3758096384:3892314111]	auto[1]	66	1			T10	1		T25	1		T37	1
auto[3892314112:4026531839]	auto[0]	54	1			T16	1		T37	1		T5	1
auto[3892314112:4026531839]	auto[1]	55	1			T55	1		T5	1		T30	1
auto[4026531840:4160749567]	auto[0]	47	1			T15	1		T45	1		T346	1
auto[4026531840:4160749567]	auto[1]	46	1			T44	1		T5	2		T68	1
auto[4160749568:4294967295]	auto[0]	51	1			T2	1		T25	2		T54	1
auto[4160749568:4294967295]	auto[1]	43	1			T2	1		T64	1		T17	1