Unified Coverage Report :: Group Instance : attest_sw_binding_6

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1573

1

T1

5

T2

2

T3

3

auto[1]

1778

1

T1

1

T2

3

T3

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	107	1			T34	1		T26	1		T4	1
auto[134217728:268435455]	110	1			T16	1		T25	1		T64	2
auto[268435456:402653183]	101	1			T15	1		T25	2		T26	1
auto[402653184:536870911]	103	1			T1	1		T16	1		T34	1
auto[536870912:671088639]	90	1			T16	1		T4	1		T5	2
auto[671088640:805306367]	113	1			T3	1		T10	1		T34	1
auto[805306368:939524095]	112	1			T67	1		T88	1		T4	1
auto[939524096:1073741823]	111	1			T15	1		T44	2		T25	1
auto[1073741824:1207959551]	107	1			T1	1		T3	1		T93	2
auto[1207959552:1342177279]	95	1			T25	1		T5	3		T235	1
auto[1342177280:1476395007]	92	1			T1	1		T11	1		T16	1
auto[1476395008:1610612735]	98	1			T25	1		T26	1		T54	1
auto[1610612736:1744830463]	121	1			T44	1		T25	1		T67	1
auto[1744830464:1879048191]	87	1			T25	1		T37	1		T54	1
auto[1879048192:2013265919]	104	1			T25	2		T88	1		T4	2
auto[2013265920:2147483647]	93	1			T13	1		T4	2		T52	1
auto[2147483648:2281701375]	99	1			T1	1		T16	1		T25	1
auto[2281701376:2415919103]	87	1			T15	1		T44	1		T25	1
auto[2415919104:2550136831]	121	1			T2	1		T25	2		T4	1
auto[2550136832:2684354559]	100	1			T25	2		T27	1		T37	2
auto[2684354560:2818572287]	101	1			T1	1		T27	1		T4	1
auto[2818572288:2952790015]	99	1			T2	1		T13	1		T25	1
auto[2952790016:3087007743]	114	1			T88	1		T28	1		T5	4
auto[3087007744:3221225471]	108	1			T13	1		T4	3		T54	1
auto[3221225472:3355443199]	122	1			T1	1		T2	2		T15	1
auto[3355443200:3489660927]	125	1			T2	1		T44	2		T25	1
auto[3489660928:3623878655]	110	1			T15	1		T44	1		T25	2
auto[3623878656:3758096383]	107	1			T10	1		T15	1		T44	1
auto[3758096384:3892314111]	106	1			T25	1		T77	1		T64	1
auto[3892314112:4026531839]	94	1			T3	1		T10	1		T13	1
auto[4026531840:4160749567]	106	1			T3	1		T27	1		T37	1
auto[4160749568:4294967295]	108	1			T13	1		T25	1		T93	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T26	1		T4	1		T47	1
auto[0:134217727]	auto[1]	54	1			T34	1		T54	1		T5	1
auto[134217728:268435455]	auto[0]	57	1			T25	1		T64	1		T4	1
auto[134217728:268435455]	auto[1]	53	1			T16	1		T64	1		T52	1
auto[268435456:402653183]	auto[0]	46	1			T15	1		T25	1		T5	3
auto[268435456:402653183]	auto[1]	55	1			T25	1		T26	1		T119	1
auto[402653184:536870911]	auto[0]	48	1			T1	1		T34	1		T25	1
auto[402653184:536870911]	auto[1]	55	1			T16	1		T25	1		T54	1
auto[536870912:671088639]	auto[0]	44	1			T16	1		T4	1		T5	2
auto[536870912:671088639]	auto[1]	46	1			T45	1		T421	1		T276	1
auto[671088640:805306367]	auto[0]	53	1			T3	1		T34	1		T37	1
auto[671088640:805306367]	auto[1]	60	1			T10	1		T67	1		T5	1
auto[805306368:939524095]	auto[0]	51	1			T67	1		T4	1		T45	1
auto[805306368:939524095]	auto[1]	61	1			T88	1		T52	1		T55	1
auto[939524096:1073741823]	auto[0]	58	1			T15	1		T44	1		T25	1
auto[939524096:1073741823]	auto[1]	53	1			T44	1		T27	1		T4	1
auto[1073741824:1207959551]	auto[0]	48	1			T1	1		T3	1		T54	1
auto[1073741824:1207959551]	auto[1]	59	1			T93	2		T55	1		T5	1
auto[1207959552:1342177279]	auto[0]	51	1			T5	2		T235	1		T45	2
auto[1207959552:1342177279]	auto[1]	44	1			T25	1		T5	1		T269	1
auto[1342177280:1476395007]	auto[0]	43	1			T1	1		T11	1		T45	1
auto[1342177280:1476395007]	auto[1]	49	1			T16	1		T4	1		T5	1
auto[1476395008:1610612735]	auto[0]	41	1			T26	1		T133	1		T234	1
auto[1476395008:1610612735]	auto[1]	57	1			T25	1		T54	1		T5	1
auto[1610612736:1744830463]	auto[0]	57	1			T67	1		T5	1		T47	2
auto[1610612736:1744830463]	auto[1]	64	1			T44	1		T25	1		T4	1
auto[1744830464:1879048191]	auto[0]	38	1			T37	1		T133	1		T45	1
auto[1744830464:1879048191]	auto[1]	49	1			T25	1		T54	1		T82	1
auto[1879048192:2013265919]	auto[0]	47	1			T88	1		T4	1		T37	1
auto[1879048192:2013265919]	auto[1]	57	1			T25	2		T4	1		T81	1
auto[2013265920:2147483647]	auto[0]	53	1			T4	2		T28	1		T5	1
auto[2013265920:2147483647]	auto[1]	40	1			T13	1		T52	1		T54	1
auto[2147483648:2281701375]	auto[0]	49	1			T25	1		T4	2		T68	1
auto[2147483648:2281701375]	auto[1]	50	1			T1	1		T16	1		T133	1
auto[2281701376:2415919103]	auto[0]	33	1			T15	1		T44	1		T4	1
auto[2281701376:2415919103]	auto[1]	54	1			T25	1		T54	1		T45	1
auto[2415919104:2550136831]	auto[0]	49	1			T4	1		T5	1		T53	1
auto[2415919104:2550136831]	auto[1]	72	1			T2	1		T25	2		T54	1
auto[2550136832:2684354559]	auto[0]	48	1			T25	1		T37	2		T5	2
auto[2550136832:2684354559]	auto[1]	52	1			T25	1		T27	1		T5	1
auto[2684354560:2818572287]	auto[0]	42	1			T1	1		T27	1		T4	1
auto[2684354560:2818572287]	auto[1]	59	1			T5	1		T45	2		T287	1
auto[2818572288:2952790015]	auto[0]	51	1			T77	1		T4	1		T37	1
auto[2818572288:2952790015]	auto[1]	48	1			T2	1		T13	1		T25	1
auto[2952790016:3087007743]	auto[0]	57	1			T28	1		T5	3		T47	1
auto[2952790016:3087007743]	auto[1]	57	1			T88	1		T5	1		T235	1
auto[3087007744:3221225471]	auto[0]	45	1			T4	3		T45	1		T46	1
auto[3087007744:3221225471]	auto[1]	63	1			T13	1		T54	1		T235	1
auto[3221225472:3355443199]	auto[0]	58	1			T1	1		T2	2		T15	1
auto[3221225472:3355443199]	auto[1]	64	1			T25	1		T54	1		T45	1
auto[3355443200:3489660927]	auto[0]	57	1			T88	1		T4	1		T86	1
auto[3355443200:3489660927]	auto[1]	68	1			T2	1		T44	2		T25	1
auto[3489660928:3623878655]	auto[0]	59	1			T44	1		T25	1		T4	1
auto[3489660928:3623878655]	auto[1]	51	1			T15	1		T25	1		T64	1
auto[3623878656:3758096383]	auto[0]	48	1			T44	1		T54	1		T5	1
auto[3623878656:3758096383]	auto[1]	59	1			T10	1		T15	1		T77	1
auto[3758096384:3892314111]	auto[0]	54	1			T54	1		T48	1		T45	2
auto[3758096384:3892314111]	auto[1]	52	1			T25	1		T77	1		T64	1
auto[3892314112:4026531839]	auto[0]	43	1			T3	1		T13	1		T25	1
auto[3892314112:4026531839]	auto[1]	51	1			T10	1		T64	1		T67	1
auto[4026531840:4160749567]	auto[0]	55	1			T5	4		T45	1		T225	1
auto[4026531840:4160749567]	auto[1]	51	1			T3	1		T27	1		T37	1
auto[4160749568:4294967295]	auto[0]	37	1			T230	1		T133	1		T46	2
auto[4160749568:4294967295]	auto[1]	71	1			T13	1		T25	1		T93	1