Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6867

1

T1

13

T2

8

T3

8

auto[1]

268

1

T2

7

T133

3

T225

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2922	1			T1	5		T2	3		T3	4
auto[134217728:268435455]	167	1			T44	2		T25	1		T88	1
auto[268435456:402653183]	152	1			T2	1		T3	1		T25	3
auto[402653184:536870911]	160	1			T1	1		T3	1		T77	1
auto[536870912:671088639]	165	1			T34	1		T25	3		T88	1
auto[671088640:805306367]	138	1			T1	1		T64	1		T67	1
auto[805306368:939524095]	117	1			T1	1		T44	2		T25	1
auto[939524096:1073741823]	152	1			T2	2		T13	1		T44	1
auto[1073741824:1207959551]	146	1			T2	1		T11	1		T15	1
auto[1207959552:1342177279]	133	1			T15	1		T34	1		T25	3
auto[1342177280:1476395007]	135	1			T10	1		T25	1		T67	1
auto[1476395008:1610612735]	126	1			T15	1		T44	2		T25	1
auto[1610612736:1744830463]	127	1			T1	1		T93	1		T88	2
auto[1744830464:1879048191]	106	1			T16	1		T25	2		T4	1
auto[1879048192:2013265919]	125	1			T15	1		T25	1		T5	1
auto[2013265920:2147483647]	117	1			T15	2		T44	1		T4	1
auto[2147483648:2281701375]	135	1			T1	1		T10	1		T5	1
auto[2281701376:2415919103]	133	1			T1	1		T15	1		T44	1
auto[2415919104:2550136831]	137	1			T13	1		T26	1		T93	1
auto[2550136832:2684354559]	140	1			T1	1		T2	1		T4	1
auto[2684354560:2818572287]	140	1			T3	1		T15	1		T16	1
auto[2818572288:2952790015]	122	1			T13	1		T25	1		T27	1
auto[2952790016:3087007743]	137	1			T1	1		T13	1		T15	1
auto[3087007744:3221225471]	121	1			T2	1		T28	1		T5	2
auto[3221225472:3355443199]	147	1			T2	1		T25	1		T77	1
auto[3355443200:3489660927]	136	1			T13	1		T15	1		T25	2
auto[3489660928:3623878655]	135	1			T2	2		T3	1		T16	1
auto[3623878656:3758096383]	134	1			T4	1		T54	1		T5	3
auto[3758096384:3892314111]	127	1			T15	1		T25	1		T26	1
auto[3892314112:4026531839]	141	1			T2	1		T15	1		T25	4
auto[4026531840:4160749567]	140	1			T2	2		T10	2		T25	1
auto[4160749568:4294967295]	122	1			T25	4		T26	2		T27	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2914	1			T1	5		T2	3		T3	4
auto[0:134217727]	auto[1]	8	1			T123	1		T420	1		T227	1
auto[134217728:268435455]	auto[0]	166	1			T44	2		T25	1		T88	1
auto[134217728:268435455]	auto[1]	1	1			T125	1		-	-		-	-
auto[268435456:402653183]	auto[0]	144	1			T3	1		T25	3		T26	2
auto[268435456:402653183]	auto[1]	8	1			T2	1		T226	1		T126	1
auto[402653184:536870911]	auto[0]	153	1			T1	1		T3	1		T77	1
auto[402653184:536870911]	auto[1]	7	1			T226	1		T360	2		T248	1
auto[536870912:671088639]	auto[0]	160	1			T34	1		T25	3		T88	1
auto[536870912:671088639]	auto[1]	5	1			T226	1		T417	1		T227	1
auto[671088640:805306367]	auto[0]	128	1			T1	1		T64	1		T67	1
auto[671088640:805306367]	auto[1]	10	1			T133	1		T226	1		T127	2
auto[805306368:939524095]	auto[0]	107	1			T1	1		T44	2		T25	1
auto[805306368:939524095]	auto[1]	10	1			T133	1		T328	1		T415	1
auto[939524096:1073741823]	auto[0]	134	1			T2	1		T13	1		T44	1
auto[939524096:1073741823]	auto[1]	18	1			T2	1		T225	1		T123	2
auto[1073741824:1207959551]	auto[0]	136	1			T11	1		T15	1		T27	1
auto[1073741824:1207959551]	auto[1]	10	1			T2	1		T226	2		T125	1
auto[1207959552:1342177279]	auto[0]	126	1			T15	1		T34	1		T25	3
auto[1207959552:1342177279]	auto[1]	7	1			T328	1		T338	2		T247	1
auto[1342177280:1476395007]	auto[0]	128	1			T10	1		T25	1		T67	1
auto[1342177280:1476395007]	auto[1]	7	1			T225	1		T328	1		T226	1
auto[1476395008:1610612735]	auto[0]	120	1			T15	1		T44	2		T25	1
auto[1476395008:1610612735]	auto[1]	6	1			T125	1		T415	1		T419	1
auto[1610612736:1744830463]	auto[0]	119	1			T1	1		T93	1		T88	2
auto[1610612736:1744830463]	auto[1]	8	1			T125	1		T249	1		T270	1
auto[1744830464:1879048191]	auto[0]	94	1			T16	1		T25	2		T4	1
auto[1744830464:1879048191]	auto[1]	12	1			T123	1		T328	1		T249	1
auto[1879048192:2013265919]	auto[0]	119	1			T15	1		T25	1		T5	1
auto[1879048192:2013265919]	auto[1]	6	1			T231	1		T249	1		T273	2
auto[2013265920:2147483647]	auto[0]	110	1			T15	2		T44	1		T4	1
auto[2013265920:2147483647]	auto[1]	7	1			T126	1		T417	1		T323	1
auto[2147483648:2281701375]	auto[0]	130	1			T1	1		T10	1		T5	1
auto[2147483648:2281701375]	auto[1]	5	1			T338	1		T399	1		T422	1
auto[2281701376:2415919103]	auto[0]	127	1			T1	1		T15	1		T44	1
auto[2281701376:2415919103]	auto[1]	6	1			T270	1		T247	1		T416	1
auto[2415919104:2550136831]	auto[0]	132	1			T13	1		T26	1		T93	1
auto[2415919104:2550136831]	auto[1]	5	1			T231	1		T127	1		T270	1
auto[2550136832:2684354559]	auto[0]	121	1			T1	1		T4	1		T54	1
auto[2550136832:2684354559]	auto[1]	19	1			T2	1		T328	2		T226	1
auto[2684354560:2818572287]	auto[0]	134	1			T3	1		T15	1		T16	1
auto[2684354560:2818572287]	auto[1]	6	1			T420	1		T227	1		T337	1
auto[2818572288:2952790015]	auto[0]	113	1			T13	1		T25	1		T27	1
auto[2818572288:2952790015]	auto[1]	9	1			T338	1		T417	1		T360	1
auto[2952790016:3087007743]	auto[0]	124	1			T1	1		T13	1		T15	1
auto[2952790016:3087007743]	auto[1]	13	1			T125	1		T126	1		T337	1
auto[3087007744:3221225471]	auto[0]	119	1			T2	1		T28	1		T5	2
auto[3087007744:3221225471]	auto[1]	2	1			T418	1		T248	1		-	-
auto[3221225472:3355443199]	auto[0]	139	1			T25	1		T77	1		T27	1
auto[3221225472:3355443199]	auto[1]	8	1			T2	1		T337	1		T398	1
auto[3355443200:3489660927]	auto[0]	128	1			T13	1		T15	1		T25	2
auto[3355443200:3489660927]	auto[1]	8	1			T133	1		T126	1		T423	1
auto[3489660928:3623878655]	auto[0]	128	1			T2	2		T3	1		T16	1
auto[3489660928:3623878655]	auto[1]	7	1			T225	1		T124	1		T125	1
auto[3623878656:3758096383]	auto[0]	126	1			T4	1		T54	1		T5	3
auto[3623878656:3758096383]	auto[1]	8	1			T417	1		T273	1		T423	1
auto[3758096384:3892314111]	auto[0]	122	1			T15	1		T25	1		T26	1
auto[3758096384:3892314111]	auto[1]	5	1			T126	1		T127	1		T420	1
auto[3892314112:4026531839]	auto[0]	128	1			T2	1		T15	1		T25	4
auto[3892314112:4026531839]	auto[1]	13	1			T123	1		T226	1		T126	1
auto[4026531840:4160749567]	auto[0]	127	1			T10	2		T25	1		T77	1
auto[4026531840:4160749567]	auto[1]	13	1			T2	2		T125	1		T126	1
auto[4160749568:4294967295]	auto[0]	111	1			T25	4		T26	2		T27	2
auto[4160749568:4294967295]	auto[1]	11	1			T225	1		T417	1		T270	1