Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.43 99.00 98.11 98.69 97.67 98.93 98.41 91.19


Total test records in report: 1081
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1003 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.4020219341 Aug 01 07:01:46 PM PDT 24 Aug 01 07:01:49 PM PDT 24 645323302 ps
T1004 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3818995265 Aug 01 07:01:59 PM PDT 24 Aug 01 07:02:01 PM PDT 24 262258553 ps
T1005 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.4200292715 Aug 01 07:02:01 PM PDT 24 Aug 01 07:02:05 PM PDT 24 85475643 ps
T1006 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1688766139 Aug 01 07:02:18 PM PDT 24 Aug 01 07:02:19 PM PDT 24 19549062 ps
T1007 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3294130840 Aug 01 07:02:06 PM PDT 24 Aug 01 07:02:07 PM PDT 24 12488723 ps
T1008 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2056573447 Aug 01 07:02:01 PM PDT 24 Aug 01 07:02:05 PM PDT 24 924980455 ps
T1009 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3240330649 Aug 01 07:02:16 PM PDT 24 Aug 01 07:02:16 PM PDT 24 12961293 ps
T1010 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.804847058 Aug 01 07:02:15 PM PDT 24 Aug 01 07:02:18 PM PDT 24 319259581 ps
T1011 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1710439363 Aug 01 07:02:24 PM PDT 24 Aug 01 07:02:28 PM PDT 24 139069041 ps
T1012 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3068229979 Aug 01 07:01:42 PM PDT 24 Aug 01 07:01:45 PM PDT 24 326091985 ps
T1013 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1031370887 Aug 01 07:02:01 PM PDT 24 Aug 01 07:02:03 PM PDT 24 146102560 ps
T1014 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.824884062 Aug 01 07:02:15 PM PDT 24 Aug 01 07:02:16 PM PDT 24 182212292 ps
T1015 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1866865544 Aug 01 07:02:19 PM PDT 24 Aug 01 07:02:20 PM PDT 24 40887404 ps
T1016 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.475210393 Aug 01 07:02:16 PM PDT 24 Aug 01 07:02:21 PM PDT 24 124903682 ps
T1017 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1967840573 Aug 01 07:02:05 PM PDT 24 Aug 01 07:02:05 PM PDT 24 17154718 ps
T1018 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.512663812 Aug 01 07:01:46 PM PDT 24 Aug 01 07:01:53 PM PDT 24 420264686 ps
T1019 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2572692577 Aug 01 07:01:51 PM PDT 24 Aug 01 07:01:53 PM PDT 24 175643454 ps
T1020 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.351480590 Aug 01 07:02:17 PM PDT 24 Aug 01 07:02:18 PM PDT 24 14711992 ps
T1021 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2138717011 Aug 01 07:02:12 PM PDT 24 Aug 01 07:02:13 PM PDT 24 24293999 ps
T1022 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1368161118 Aug 01 07:01:52 PM PDT 24 Aug 01 07:01:57 PM PDT 24 690529859 ps
T1023 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3733410968 Aug 01 07:01:56 PM PDT 24 Aug 01 07:01:58 PM PDT 24 115775590 ps
T1024 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1003738775 Aug 01 07:02:01 PM PDT 24 Aug 01 07:02:03 PM PDT 24 49567260 ps
T1025 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.4273195339 Aug 01 07:01:54 PM PDT 24 Aug 01 07:01:55 PM PDT 24 72382838 ps
T1026 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2022604665 Aug 01 07:01:47 PM PDT 24 Aug 01 07:02:12 PM PDT 24 3424374686 ps
T1027 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1093056775 Aug 01 07:02:04 PM PDT 24 Aug 01 07:02:05 PM PDT 24 102570299 ps
T1028 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2080599173 Aug 01 07:02:00 PM PDT 24 Aug 01 07:02:01 PM PDT 24 13876420 ps
T1029 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3531039370 Aug 01 07:02:12 PM PDT 24 Aug 01 07:02:15 PM PDT 24 277801186 ps
T1030 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.304084361 Aug 01 07:02:13 PM PDT 24 Aug 01 07:02:14 PM PDT 24 82937487 ps
T1031 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1595916570 Aug 01 07:02:01 PM PDT 24 Aug 01 07:02:05 PM PDT 24 424343175 ps
T1032 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1925266176 Aug 01 07:01:47 PM PDT 24 Aug 01 07:01:49 PM PDT 24 270267859 ps
T1033 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.708428778 Aug 01 07:01:51 PM PDT 24 Aug 01 07:02:00 PM PDT 24 246060909 ps
T1034 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3856335236 Aug 01 07:01:48 PM PDT 24 Aug 01 07:01:52 PM PDT 24 273841001 ps
T1035 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3407744152 Aug 01 07:02:15 PM PDT 24 Aug 01 07:02:16 PM PDT 24 8857872 ps
T1036 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1891163557 Aug 01 07:02:19 PM PDT 24 Aug 01 07:02:20 PM PDT 24 25849363 ps
T1037 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3550154890 Aug 01 07:01:55 PM PDT 24 Aug 01 07:01:56 PM PDT 24 14826941 ps
T1038 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2378149868 Aug 01 07:02:10 PM PDT 24 Aug 01 07:02:13 PM PDT 24 111959609 ps
T1039 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3650732033 Aug 01 07:01:47 PM PDT 24 Aug 01 07:01:52 PM PDT 24 253440276 ps
T1040 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2226307805 Aug 01 07:01:49 PM PDT 24 Aug 01 07:01:52 PM PDT 24 46177287 ps
T1041 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1718491203 Aug 01 07:01:40 PM PDT 24 Aug 01 07:01:48 PM PDT 24 176825898 ps
T1042 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.403905400 Aug 01 07:02:03 PM PDT 24 Aug 01 07:02:09 PM PDT 24 216420344 ps
T1043 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1514336712 Aug 01 07:02:14 PM PDT 24 Aug 01 07:02:15 PM PDT 24 24934416 ps
T1044 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.510353786 Aug 01 07:01:40 PM PDT 24 Aug 01 07:01:41 PM PDT 24 188730791 ps
T1045 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.815805027 Aug 01 07:02:07 PM PDT 24 Aug 01 07:02:08 PM PDT 24 42113187 ps
T1046 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2989981940 Aug 01 07:02:07 PM PDT 24 Aug 01 07:02:09 PM PDT 24 15435342 ps
T1047 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2908334582 Aug 01 07:02:03 PM PDT 24 Aug 01 07:02:06 PM PDT 24 143649888 ps
T1048 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2843786638 Aug 01 07:01:43 PM PDT 24 Aug 01 07:01:55 PM PDT 24 464130231 ps
T1049 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.608216538 Aug 01 07:01:52 PM PDT 24 Aug 01 07:02:00 PM PDT 24 451755214 ps
T159 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.948378803 Aug 01 07:02:11 PM PDT 24 Aug 01 07:02:16 PM PDT 24 238289693 ps
T1050 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1623061044 Aug 01 07:01:51 PM PDT 24 Aug 01 07:01:53 PM PDT 24 64084863 ps
T1051 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.529655060 Aug 01 07:01:59 PM PDT 24 Aug 01 07:02:01 PM PDT 24 76354531 ps
T1052 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2117785423 Aug 01 07:02:19 PM PDT 24 Aug 01 07:02:20 PM PDT 24 27969492 ps
T1053 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2798589764 Aug 01 07:01:52 PM PDT 24 Aug 01 07:02:09 PM PDT 24 1295656851 ps
T1054 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2369381690 Aug 01 07:01:51 PM PDT 24 Aug 01 07:01:54 PM PDT 24 79754994 ps
T1055 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2676751197 Aug 01 07:01:52 PM PDT 24 Aug 01 07:01:53 PM PDT 24 112134715 ps
T1056 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2782332830 Aug 01 07:02:14 PM PDT 24 Aug 01 07:02:14 PM PDT 24 35263126 ps
T1057 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1278076381 Aug 01 07:01:49 PM PDT 24 Aug 01 07:01:52 PM PDT 24 65998116 ps
T1058 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1653450440 Aug 01 07:02:15 PM PDT 24 Aug 01 07:02:17 PM PDT 24 116141706 ps
T1059 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1699566519 Aug 01 07:02:19 PM PDT 24 Aug 01 07:02:20 PM PDT 24 51259506 ps
T1060 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2223917125 Aug 01 07:02:29 PM PDT 24 Aug 01 07:02:30 PM PDT 24 43916850 ps
T1061 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1190173168 Aug 01 07:02:14 PM PDT 24 Aug 01 07:02:15 PM PDT 24 10543809 ps
T171 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3689084116 Aug 01 07:01:52 PM PDT 24 Aug 01 07:01:59 PM PDT 24 274408067 ps
T1062 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.880814878 Aug 01 07:01:51 PM PDT 24 Aug 01 07:01:53 PM PDT 24 229348220 ps
T1063 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.112780008 Aug 01 07:02:21 PM PDT 24 Aug 01 07:02:22 PM PDT 24 38674497 ps
T1064 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.151896510 Aug 01 07:02:13 PM PDT 24 Aug 01 07:02:15 PM PDT 24 74678496 ps
T1065 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2043299154 Aug 01 07:01:49 PM PDT 24 Aug 01 07:01:51 PM PDT 24 21717032 ps
T1066 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3326049283 Aug 01 07:02:02 PM PDT 24 Aug 01 07:02:04 PM PDT 24 136617065 ps
T1067 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2333738579 Aug 01 07:02:27 PM PDT 24 Aug 01 07:02:28 PM PDT 24 12940858 ps
T1068 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3298503329 Aug 01 07:01:46 PM PDT 24 Aug 01 07:01:50 PM PDT 24 394142357 ps
T1069 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3159406913 Aug 01 07:01:52 PM PDT 24 Aug 01 07:01:53 PM PDT 24 119743982 ps
T1070 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2736076928 Aug 01 07:02:16 PM PDT 24 Aug 01 07:02:17 PM PDT 24 20927147 ps
T1071 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2730354347 Aug 01 07:02:15 PM PDT 24 Aug 01 07:02:17 PM PDT 24 19485239 ps
T1072 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3553153511 Aug 01 07:02:14 PM PDT 24 Aug 01 07:02:15 PM PDT 24 40170766 ps
T1073 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2706233875 Aug 01 07:02:05 PM PDT 24 Aug 01 07:02:06 PM PDT 24 13282102 ps
T1074 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2539645784 Aug 01 07:02:10 PM PDT 24 Aug 01 07:02:12 PM PDT 24 36034313 ps
T1075 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.4114150356 Aug 01 07:02:17 PM PDT 24 Aug 01 07:02:23 PM PDT 24 217745063 ps
T1076 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2743142237 Aug 01 07:02:00 PM PDT 24 Aug 01 07:02:02 PM PDT 24 40640346 ps
T1077 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3262438155 Aug 01 07:02:03 PM PDT 24 Aug 01 07:02:06 PM PDT 24 71913197 ps
T1078 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2749693301 Aug 01 07:01:54 PM PDT 24 Aug 01 07:02:05 PM PDT 24 267594628 ps
T1079 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1993787709 Aug 01 07:02:24 PM PDT 24 Aug 01 07:02:25 PM PDT 24 8238046 ps
T1080 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.4179232594 Aug 01 07:01:53 PM PDT 24 Aug 01 07:01:54 PM PDT 24 11343420 ps
T1081 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2227349706 Aug 01 07:02:23 PM PDT 24 Aug 01 07:02:24 PM PDT 24 57710108 ps

Test location /workspace/coverage/default/24.keymgr_lc_disable.594679244
Short name T13
Test name
Test status
Simulation time 179257886 ps
CPU time 3.48 seconds
Started Aug 01 07:00:34 PM PDT 24
Finished Aug 01 07:00:37 PM PDT 24
Peak memory 208832 kb
Host smart-055bbe99-f631-4528-af99-1028fd918520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594679244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.594679244
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3644097302
Short name T5
Test name
Test status
Simulation time 45233921534 ps
CPU time 265.42 seconds
Started Aug 01 07:00:05 PM PDT 24
Finished Aug 01 07:04:33 PM PDT 24
Peak memory 217176 kb
Host smart-76a17148-35c3-45f8-9ffb-dde23753ce1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644097302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3644097302
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2641500191
Short name T25
Test name
Test status
Simulation time 47158045255 ps
CPU time 118.73 seconds
Started Aug 01 07:00:19 PM PDT 24
Finished Aug 01 07:02:18 PM PDT 24
Peak memory 217252 kb
Host smart-7da85f8f-78ea-4f43-908b-194e7830b30e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641500191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2641500191
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.4127586283
Short name T46
Test name
Test status
Simulation time 1674154247 ps
CPU time 54.36 seconds
Started Aug 01 06:59:07 PM PDT 24
Finished Aug 01 07:00:01 PM PDT 24
Peak memory 222452 kb
Host smart-76b4db6f-f3ce-476f-97ba-65a6700e1a00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127586283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.4127586283
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2081590759
Short name T7
Test name
Test status
Simulation time 856826039 ps
CPU time 19.6 seconds
Started Aug 01 06:59:09 PM PDT 24
Finished Aug 01 06:59:29 PM PDT 24
Peak memory 237472 kb
Host smart-af22763f-3b15-4a4f-93dd-563e90afd475
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081590759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2081590759
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.961514792
Short name T93
Test name
Test status
Simulation time 335272315 ps
CPU time 8 seconds
Started Aug 01 07:01:06 PM PDT 24
Finished Aug 01 07:01:14 PM PDT 24
Peak memory 219948 kb
Host smart-781c2cc7-971a-4735-a8e9-18ce74954fbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961514792 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.961514792
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1929548443
Short name T110
Test name
Test status
Simulation time 85850579 ps
CPU time 2.55 seconds
Started Aug 01 07:01:48 PM PDT 24
Finished Aug 01 07:01:51 PM PDT 24
Peak memory 214732 kb
Host smart-d97ad80e-b3d7-4ae8-abc9-44ad247f63dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929548443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1929548443
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1697239130
Short name T60
Test name
Test status
Simulation time 402308519 ps
CPU time 21.89 seconds
Started Aug 01 07:00:31 PM PDT 24
Finished Aug 01 07:00:53 PM PDT 24
Peak memory 215908 kb
Host smart-727d16ca-0e59-4a5d-addc-25e73e3370d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697239130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1697239130
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2561358671
Short name T15
Test name
Test status
Simulation time 105066494 ps
CPU time 1.96 seconds
Started Aug 01 07:01:10 PM PDT 24
Finished Aug 01 07:01:12 PM PDT 24
Peak memory 215496 kb
Host smart-6f1a0342-ff6a-4f8e-8e78-527b25c42713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561358671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2561358671
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.345653285
Short name T4
Test name
Test status
Simulation time 1280318327 ps
CPU time 30.23 seconds
Started Aug 01 06:59:55 PM PDT 24
Finished Aug 01 07:00:26 PM PDT 24
Peak memory 216144 kb
Host smart-62b79777-09ed-4888-ade4-1513976604c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345653285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.345653285
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2814634545
Short name T126
Test name
Test status
Simulation time 372064842 ps
CPU time 10.12 seconds
Started Aug 01 06:59:33 PM PDT 24
Finished Aug 01 06:59:43 PM PDT 24
Peak memory 215588 kb
Host smart-98c1b098-fe5b-4ca4-b45d-5d88e11f972a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2814634545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2814634545
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2196828139
Short name T108
Test name
Test status
Simulation time 404418001 ps
CPU time 8.87 seconds
Started Aug 01 07:01:51 PM PDT 24
Finished Aug 01 07:02:00 PM PDT 24
Peak memory 214612 kb
Host smart-5c721afe-5a2c-4d02-8aa3-e473a1aaaa36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196828139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2196828139
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1241940537
Short name T17
Test name
Test status
Simulation time 172602346 ps
CPU time 1.96 seconds
Started Aug 01 07:00:47 PM PDT 24
Finished Aug 01 07:00:50 PM PDT 24
Peak memory 216860 kb
Host smart-e69a8fa6-ec59-4e9f-95bc-d1e7ef5c56ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241940537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1241940537
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1039589266
Short name T328
Test name
Test status
Simulation time 1435380674 ps
CPU time 8.98 seconds
Started Aug 01 07:01:17 PM PDT 24
Finished Aug 01 07:01:26 PM PDT 24
Peak memory 215456 kb
Host smart-22c17657-6fb7-4299-9b33-8d0c09bed3d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1039589266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1039589266
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3090768758
Short name T226
Test name
Test status
Simulation time 3378498590 ps
CPU time 84.34 seconds
Started Aug 01 07:00:48 PM PDT 24
Finished Aug 01 07:02:13 PM PDT 24
Peak memory 214676 kb
Host smart-16358a40-88d9-4d13-b8b9-15cf44692099
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3090768758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3090768758
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.4224839051
Short name T36
Test name
Test status
Simulation time 2204138002 ps
CPU time 7.4 seconds
Started Aug 01 06:59:44 PM PDT 24
Finished Aug 01 06:59:51 PM PDT 24
Peak memory 210988 kb
Host smart-43b39fde-f098-4712-8140-8ac4a6a2d813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224839051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.4224839051
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3925348437
Short name T22
Test name
Test status
Simulation time 146839113 ps
CPU time 3.67 seconds
Started Aug 01 07:00:29 PM PDT 24
Finished Aug 01 07:00:33 PM PDT 24
Peak memory 214280 kb
Host smart-1173ff5e-d562-4f03-bd54-2e52a2311a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925348437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3925348437
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2542695224
Short name T424
Test name
Test status
Simulation time 161295066 ps
CPU time 7.98 seconds
Started Aug 01 06:59:08 PM PDT 24
Finished Aug 01 06:59:16 PM PDT 24
Peak memory 214240 kb
Host smart-a270a314-698a-44d7-809f-2b148cf60d37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2542695224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2542695224
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.579719153
Short name T69
Test name
Test status
Simulation time 6625686571 ps
CPU time 50.21 seconds
Started Aug 01 07:01:27 PM PDT 24
Finished Aug 01 07:02:18 PM PDT 24
Peak memory 222392 kb
Host smart-7a973700-267b-4e99-af14-2d37b2984708
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579719153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.579719153
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1716054036
Short name T418
Test name
Test status
Simulation time 923449116 ps
CPU time 11.95 seconds
Started Aug 01 07:01:37 PM PDT 24
Finished Aug 01 07:01:49 PM PDT 24
Peak memory 214288 kb
Host smart-81d968d5-3529-4e72-8e5e-12a7d7827e7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1716054036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1716054036
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.2480909443
Short name T54
Test name
Test status
Simulation time 5520665971 ps
CPU time 25.44 seconds
Started Aug 01 07:00:56 PM PDT 24
Finished Aug 01 07:01:21 PM PDT 24
Peak memory 222656 kb
Host smart-15bab690-30a5-4b2f-ae11-e624192a4c3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480909443 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.2480909443
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2514002541
Short name T24
Test name
Test status
Simulation time 138526561 ps
CPU time 3.88 seconds
Started Aug 01 07:00:43 PM PDT 24
Finished Aug 01 07:00:47 PM PDT 24
Peak memory 214300 kb
Host smart-d668e075-872e-4360-93c3-98c1f6b593ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514002541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2514002541
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3377241133
Short name T45
Test name
Test status
Simulation time 15181478756 ps
CPU time 85.12 seconds
Started Aug 01 07:01:17 PM PDT 24
Finished Aug 01 07:02:43 PM PDT 24
Peak memory 222520 kb
Host smart-4179704e-3858-4800-8bce-58e115665213
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377241133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3377241133
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.262827625
Short name T227
Test name
Test status
Simulation time 296818929 ps
CPU time 6.73 seconds
Started Aug 01 06:59:46 PM PDT 24
Finished Aug 01 06:59:53 PM PDT 24
Peak memory 214256 kb
Host smart-0821c9f8-d96f-46d7-9394-adb9cca9044c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=262827625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.262827625
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2324567663
Short name T270
Test name
Test status
Simulation time 746730097 ps
CPU time 10.52 seconds
Started Aug 01 07:00:44 PM PDT 24
Finished Aug 01 07:00:55 PM PDT 24
Peak memory 215288 kb
Host smart-0e4efb53-21b1-4d83-87c4-0337427d03c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2324567663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2324567663
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3295619232
Short name T139
Test name
Test status
Simulation time 136780808 ps
CPU time 2.24 seconds
Started Aug 01 06:59:57 PM PDT 24
Finished Aug 01 06:59:59 PM PDT 24
Peak memory 222588 kb
Host smart-f731d046-095b-4bff-899a-9a9233ce38a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295619232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3295619232
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1949968775
Short name T63
Test name
Test status
Simulation time 99369006 ps
CPU time 2.3 seconds
Started Aug 01 06:59:53 PM PDT 24
Finished Aug 01 06:59:56 PM PDT 24
Peak memory 208836 kb
Host smart-b33e8152-4e93-4fc8-90e2-89bbcd5352be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949968775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1949968775
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.569493405
Short name T31
Test name
Test status
Simulation time 54352390 ps
CPU time 2.15 seconds
Started Aug 01 06:59:09 PM PDT 24
Finished Aug 01 06:59:11 PM PDT 24
Peak memory 209756 kb
Host smart-f69f732d-bd37-4c6d-a215-e2ee51b21e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569493405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.569493405
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.920964226
Short name T49
Test name
Test status
Simulation time 818191742 ps
CPU time 18.47 seconds
Started Aug 01 06:59:10 PM PDT 24
Finished Aug 01 06:59:29 PM PDT 24
Peak memory 222472 kb
Host smart-903f1c01-6542-4f33-b4d3-f4d03038d941
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920964226 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.920964226
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3922568138
Short name T247
Test name
Test status
Simulation time 2882965313 ps
CPU time 37.37 seconds
Started Aug 01 06:59:20 PM PDT 24
Finished Aug 01 06:59:57 PM PDT 24
Peak memory 215384 kb
Host smart-6042e37b-ff8b-4762-8cbc-d0c6530d3892
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3922568138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3922568138
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3774225517
Short name T149
Test name
Test status
Simulation time 804082309 ps
CPU time 5.85 seconds
Started Aug 01 07:02:04 PM PDT 24
Finished Aug 01 07:02:10 PM PDT 24
Peak memory 215896 kb
Host smart-768cb715-6786-4b2d-aba1-1ea424f43467
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774225517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3774225517
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.588654583
Short name T109
Test name
Test status
Simulation time 710179065 ps
CPU time 13.91 seconds
Started Aug 01 07:00:34 PM PDT 24
Finished Aug 01 07:00:49 PM PDT 24
Peak memory 222536 kb
Host smart-a5bf37bb-0f48-48f1-b870-069d4445aaa7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588654583 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.588654583
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.4293926229
Short name T125
Test name
Test status
Simulation time 54526688 ps
CPU time 3.67 seconds
Started Aug 01 07:00:33 PM PDT 24
Finished Aug 01 07:00:37 PM PDT 24
Peak memory 214312 kb
Host smart-311da571-4459-416a-8e85-fcd0efc2854f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4293926229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.4293926229
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2735509025
Short name T213
Test name
Test status
Simulation time 1173442436 ps
CPU time 42.06 seconds
Started Aug 01 06:59:31 PM PDT 24
Finished Aug 01 07:00:13 PM PDT 24
Peak memory 222476 kb
Host smart-dc4e862f-f528-4924-af4f-7d5b84909ad6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735509025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2735509025
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2822386311
Short name T92
Test name
Test status
Simulation time 12802438 ps
CPU time 0.73 seconds
Started Aug 01 07:00:04 PM PDT 24
Finished Aug 01 07:00:08 PM PDT 24
Peak memory 205964 kb
Host smart-08b9a3e6-8381-4b50-87bb-f04b4ecf3892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822386311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2822386311
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2724108367
Short name T44
Test name
Test status
Simulation time 476641041 ps
CPU time 17.6 seconds
Started Aug 01 07:00:47 PM PDT 24
Finished Aug 01 07:01:05 PM PDT 24
Peak memory 215416 kb
Host smart-4bbaa7bd-240b-4202-8ac5-15e58b3adac2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724108367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2724108367
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2826745110
Short name T79
Test name
Test status
Simulation time 8586527319 ps
CPU time 27.87 seconds
Started Aug 01 07:01:30 PM PDT 24
Finished Aug 01 07:01:58 PM PDT 24
Peak memory 218136 kb
Host smart-d8eeb128-f509-48bc-88c9-5f502812caa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826745110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2826745110
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.352886551
Short name T370
Test name
Test status
Simulation time 362865898 ps
CPU time 5.58 seconds
Started Aug 01 06:59:35 PM PDT 24
Finished Aug 01 06:59:41 PM PDT 24
Peak memory 222404 kb
Host smart-e3053158-f191-4bb2-a47d-11970083e2de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=352886551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.352886551
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1309296908
Short name T18
Test name
Test status
Simulation time 167092003 ps
CPU time 3.79 seconds
Started Aug 01 07:00:32 PM PDT 24
Finished Aug 01 07:00:36 PM PDT 24
Peak memory 210000 kb
Host smart-f8d206fd-37da-409d-b102-d7e928f13dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309296908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1309296908
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2468935167
Short name T70
Test name
Test status
Simulation time 906251308 ps
CPU time 33 seconds
Started Aug 01 07:00:49 PM PDT 24
Finished Aug 01 07:01:22 PM PDT 24
Peak memory 222532 kb
Host smart-d3b35b38-6988-43af-b4f0-2742c6240773
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468935167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2468935167
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3834262158
Short name T143
Test name
Test status
Simulation time 498337833 ps
CPU time 4.26 seconds
Started Aug 01 07:01:28 PM PDT 24
Finished Aug 01 07:01:33 PM PDT 24
Peak memory 217940 kb
Host smart-d8aa8f62-160d-4648-9cc6-a31aa559cb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834262158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3834262158
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1427495465
Short name T140
Test name
Test status
Simulation time 65833228 ps
CPU time 3.14 seconds
Started Aug 01 07:01:31 PM PDT 24
Finished Aug 01 07:01:35 PM PDT 24
Peak memory 217848 kb
Host smart-cf760606-7b4b-4d63-ad9d-f77ebea80c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427495465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1427495465
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.66801923
Short name T625
Test name
Test status
Simulation time 56643950 ps
CPU time 2.56 seconds
Started Aug 01 06:59:53 PM PDT 24
Finished Aug 01 06:59:56 PM PDT 24
Peak memory 214260 kb
Host smart-6a660059-86ff-42cb-9704-7d394d531ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66801923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.66801923
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3455551376
Short name T138
Test name
Test status
Simulation time 85053375 ps
CPU time 3.34 seconds
Started Aug 01 07:00:43 PM PDT 24
Finished Aug 01 07:00:47 PM PDT 24
Peak memory 217248 kb
Host smart-4c792887-430e-47b0-846d-5f70b89bad73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455551376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3455551376
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.4044545621
Short name T275
Test name
Test status
Simulation time 2341832141 ps
CPU time 30.87 seconds
Started Aug 01 06:59:41 PM PDT 24
Finished Aug 01 07:00:12 PM PDT 24
Peak memory 216648 kb
Host smart-f55c27d5-68b1-4b60-8484-dccf3abf9193
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044545621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.4044545621
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.4017492608
Short name T399
Test name
Test status
Simulation time 135151001 ps
CPU time 7.53 seconds
Started Aug 01 06:59:48 PM PDT 24
Finished Aug 01 06:59:56 PM PDT 24
Peak memory 214292 kb
Host smart-56931719-b822-4925-99b6-2f282c4023d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4017492608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.4017492608
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.351828404
Short name T355
Test name
Test status
Simulation time 77612632 ps
CPU time 3.85 seconds
Started Aug 01 06:59:07 PM PDT 24
Finished Aug 01 06:59:11 PM PDT 24
Peak memory 214280 kb
Host smart-48819343-e6ff-4685-bb9b-f73f5a72e5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351828404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.351828404
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3935810157
Short name T42
Test name
Test status
Simulation time 112532687 ps
CPU time 1.41 seconds
Started Aug 01 07:01:31 PM PDT 24
Finished Aug 01 07:01:33 PM PDT 24
Peak memory 209984 kb
Host smart-2a48551a-9c3d-43c6-be5f-1a704aaea3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935810157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3935810157
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.701566790
Short name T152
Test name
Test status
Simulation time 1080381765 ps
CPU time 10.67 seconds
Started Aug 01 07:02:01 PM PDT 24
Finished Aug 01 07:02:12 PM PDT 24
Peak memory 206228 kb
Host smart-a271f813-4da7-43a7-8e9d-f053e13542c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701566790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.701566790
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1818994087
Short name T141
Test name
Test status
Simulation time 210756162 ps
CPU time 3.78 seconds
Started Aug 01 06:59:57 PM PDT 24
Finished Aug 01 07:00:00 PM PDT 24
Peak memory 222696 kb
Host smart-1f8eecbd-647c-4c6b-8a6e-b8b36ad8e4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818994087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1818994087
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3319987059
Short name T225
Test name
Test status
Simulation time 332078937 ps
CPU time 4.45 seconds
Started Aug 01 06:59:38 PM PDT 24
Finished Aug 01 06:59:43 PM PDT 24
Peak memory 215052 kb
Host smart-e8cb408e-ca6c-4b1b-9ad9-1547ffdc9e88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3319987059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3319987059
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.582914115
Short name T299
Test name
Test status
Simulation time 50932083 ps
CPU time 2.09 seconds
Started Aug 01 07:00:42 PM PDT 24
Finished Aug 01 07:00:45 PM PDT 24
Peak memory 206040 kb
Host smart-c7e6398e-a14e-4d3d-9cd4-9eb85d7f65a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582914115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.582914115
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2815471931
Short name T219
Test name
Test status
Simulation time 8402813874 ps
CPU time 142.82 seconds
Started Aug 01 06:59:22 PM PDT 24
Finished Aug 01 07:01:45 PM PDT 24
Peak memory 222524 kb
Host smart-6d5caba4-b36b-453e-bc9d-dc82a13181a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815471931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2815471931
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3244946392
Short name T160
Test name
Test status
Simulation time 448081817 ps
CPU time 5.93 seconds
Started Aug 01 07:01:54 PM PDT 24
Finished Aug 01 07:02:00 PM PDT 24
Peak memory 214396 kb
Host smart-9ea7e4c1-ab49-4e44-a3a9-bbe3f4d25678
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244946392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3244946392
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3949141933
Short name T168
Test name
Test status
Simulation time 171485383 ps
CPU time 4.69 seconds
Started Aug 01 07:02:05 PM PDT 24
Finished Aug 01 07:02:10 PM PDT 24
Peak memory 215760 kb
Host smart-85e64b78-ae08-481c-9561-00a0fec103db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949141933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3949141933
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2841446923
Short name T163
Test name
Test status
Simulation time 4664042338 ps
CPU time 9.96 seconds
Started Aug 01 07:02:20 PM PDT 24
Finished Aug 01 07:02:30 PM PDT 24
Peak memory 214364 kb
Host smart-62fc8b97-7586-486a-af9d-4d5c8ae15302
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841446923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2841446923
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2147772384
Short name T157
Test name
Test status
Simulation time 268388616 ps
CPU time 6.32 seconds
Started Aug 01 07:01:54 PM PDT 24
Finished Aug 01 07:02:01 PM PDT 24
Peak memory 214264 kb
Host smart-361524c4-6a28-48af-983a-7da73d278a0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147772384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2147772384
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1982999810
Short name T28
Test name
Test status
Simulation time 1813247466 ps
CPU time 3.37 seconds
Started Aug 01 06:59:07 PM PDT 24
Finished Aug 01 06:59:11 PM PDT 24
Peak memory 222576 kb
Host smart-4e88c12f-08c9-4893-bbb9-c7510e0c411a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982999810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1982999810
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.126803545
Short name T142
Test name
Test status
Simulation time 626065038 ps
CPU time 3.59 seconds
Started Aug 01 06:59:31 PM PDT 24
Finished Aug 01 06:59:35 PM PDT 24
Peak memory 222612 kb
Host smart-40919dd0-256b-466a-9bf1-a5fa4616e5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126803545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.126803545
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.158329610
Short name T37
Test name
Test status
Simulation time 200872082 ps
CPU time 4.84 seconds
Started Aug 01 06:59:10 PM PDT 24
Finished Aug 01 06:59:15 PM PDT 24
Peak memory 222480 kb
Host smart-b74aefe0-36c7-4512-b4ab-bbae0e0e0a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158329610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.158329610
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.2923282257
Short name T58
Test name
Test status
Simulation time 10310349460 ps
CPU time 19.95 seconds
Started Aug 01 07:00:20 PM PDT 24
Finished Aug 01 07:00:40 PM PDT 24
Peak memory 223696 kb
Host smart-03925a95-1534-4e07-80c2-ac5df8198da2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923282257 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.2923282257
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3823695628
Short name T341
Test name
Test status
Simulation time 80710638 ps
CPU time 2.19 seconds
Started Aug 01 07:00:47 PM PDT 24
Finished Aug 01 07:00:49 PM PDT 24
Peak memory 221268 kb
Host smart-ce149387-b063-4740-adee-cca5f86541ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823695628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3823695628
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.157095689
Short name T425
Test name
Test status
Simulation time 885928087 ps
CPU time 8.37 seconds
Started Aug 01 07:00:55 PM PDT 24
Finished Aug 01 07:01:03 PM PDT 24
Peak memory 215312 kb
Host smart-0bbfbc63-73b0-4fbd-8074-9459f3be011b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=157095689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.157095689
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3400483172
Short name T363
Test name
Test status
Simulation time 137740396 ps
CPU time 4.5 seconds
Started Aug 01 07:00:55 PM PDT 24
Finished Aug 01 07:01:00 PM PDT 24
Peak memory 208668 kb
Host smart-b01efc1f-cc62-48e8-b37f-64cd1950972e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400483172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3400483172
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1065712387
Short name T419
Test name
Test status
Simulation time 65929966 ps
CPU time 4.67 seconds
Started Aug 01 07:01:05 PM PDT 24
Finished Aug 01 07:01:10 PM PDT 24
Peak memory 222488 kb
Host smart-0d8e3285-4ac2-464e-8bec-e0eb132ea1a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1065712387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1065712387
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1329990775
Short name T135
Test name
Test status
Simulation time 376397780 ps
CPU time 4.53 seconds
Started Aug 01 07:00:35 PM PDT 24
Finished Aug 01 07:00:40 PM PDT 24
Peak memory 217992 kb
Host smart-f7fdc7df-6dcc-42ee-afef-32e2ebc9a6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329990775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1329990775
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1832519019
Short name T137
Test name
Test status
Simulation time 94827472 ps
CPU time 5.04 seconds
Started Aug 01 07:00:44 PM PDT 24
Finished Aug 01 07:00:49 PM PDT 24
Peak memory 222524 kb
Host smart-77006a93-d4bd-48b5-925f-58ca075fd535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832519019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1832519019
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_random.3407449636
Short name T316
Test name
Test status
Simulation time 78528010 ps
CPU time 3.92 seconds
Started Aug 01 06:59:09 PM PDT 24
Finished Aug 01 06:59:13 PM PDT 24
Peak memory 208356 kb
Host smart-dc946dbd-ad06-437b-8759-5b1915ce004e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407449636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3407449636
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1423675198
Short name T656
Test name
Test status
Simulation time 728474148 ps
CPU time 3.2 seconds
Started Aug 01 06:59:06 PM PDT 24
Finished Aug 01 06:59:09 PM PDT 24
Peak memory 208112 kb
Host smart-f851cce5-7252-4d37-a2ad-636f6d09a964
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423675198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1423675198
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.4107040937
Short name T358
Test name
Test status
Simulation time 103298110 ps
CPU time 3.23 seconds
Started Aug 01 06:59:48 PM PDT 24
Finished Aug 01 06:59:52 PM PDT 24
Peak memory 214352 kb
Host smart-6dc5cbbb-b6c4-41f1-ab4c-18d8214912fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107040937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.4107040937
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2018661532
Short name T353
Test name
Test status
Simulation time 45146792 ps
CPU time 1.71 seconds
Started Aug 01 06:59:57 PM PDT 24
Finished Aug 01 06:59:59 PM PDT 24
Peak memory 214244 kb
Host smart-4e90d9f5-442f-4944-8eac-6953b39c97a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018661532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2018661532
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3124009967
Short name T268
Test name
Test status
Simulation time 132709980 ps
CPU time 4.6 seconds
Started Aug 01 07:00:21 PM PDT 24
Finished Aug 01 07:00:26 PM PDT 24
Peak memory 215036 kb
Host smart-aa0e0e55-31cc-4d53-8411-624cc2d7cb95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3124009967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3124009967
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.984422382
Short name T23
Test name
Test status
Simulation time 52573110 ps
CPU time 3.15 seconds
Started Aug 01 07:00:36 PM PDT 24
Finished Aug 01 07:00:39 PM PDT 24
Peak memory 214264 kb
Host smart-7b19c420-ea37-4cef-99cc-97a0af3aa98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984422382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.984422382
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1223893964
Short name T311
Test name
Test status
Simulation time 172807498 ps
CPU time 2.02 seconds
Started Aug 01 07:00:43 PM PDT 24
Finished Aug 01 07:00:45 PM PDT 24
Peak memory 207252 kb
Host smart-133eba4b-fbb0-46f9-9115-e680d3a70975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223893964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1223893964
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3265442601
Short name T261
Test name
Test status
Simulation time 301774424 ps
CPU time 6.37 seconds
Started Aug 01 07:00:47 PM PDT 24
Finished Aug 01 07:00:54 PM PDT 24
Peak memory 222472 kb
Host smart-81abeaff-b3f8-4d04-9b0d-f400c5091af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265442601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3265442601
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2253041663
Short name T222
Test name
Test status
Simulation time 8144128342 ps
CPU time 44.61 seconds
Started Aug 01 07:01:04 PM PDT 24
Finished Aug 01 07:01:49 PM PDT 24
Peak memory 222488 kb
Host smart-69f9f35d-00df-49d6-bec7-0706ca808919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253041663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2253041663
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3617858599
Short name T321
Test name
Test status
Simulation time 144498409 ps
CPU time 2 seconds
Started Aug 01 07:01:18 PM PDT 24
Finished Aug 01 07:01:20 PM PDT 24
Peak memory 214168 kb
Host smart-35139bd4-bea8-48ad-b648-696779f2d4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617858599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3617858599
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.552783282
Short name T303
Test name
Test status
Simulation time 1595214079 ps
CPU time 10.48 seconds
Started Aug 01 06:59:22 PM PDT 24
Finished Aug 01 06:59:32 PM PDT 24
Peak memory 215576 kb
Host smart-765b65a1-6c6b-45b9-84f7-98d2df1c96f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=552783282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.552783282
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2402697530
Short name T167
Test name
Test status
Simulation time 144765070 ps
CPU time 2.85 seconds
Started Aug 01 07:02:00 PM PDT 24
Finished Aug 01 07:02:03 PM PDT 24
Peak memory 214348 kb
Host smart-4d0c7c66-c500-4c6a-88a7-aaac48ea3913
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402697530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2402697530
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.4244758427
Short name T170
Test name
Test status
Simulation time 300233187 ps
CPU time 2.49 seconds
Started Aug 01 07:02:19 PM PDT 24
Finished Aug 01 07:02:21 PM PDT 24
Peak memory 206152 kb
Host smart-63964cd2-ebf0-4dfa-975e-085c2de3dab9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244758427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.4244758427
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1711527494
Short name T155
Test name
Test status
Simulation time 427283973 ps
CPU time 8.76 seconds
Started Aug 01 07:02:13 PM PDT 24
Finished Aug 01 07:02:22 PM PDT 24
Peak memory 214316 kb
Host smart-237d709d-ccf8-45a3-b61e-d13ad3519b94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711527494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1711527494
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3677225734
Short name T154
Test name
Test status
Simulation time 301245469 ps
CPU time 6.59 seconds
Started Aug 01 07:01:48 PM PDT 24
Finished Aug 01 07:01:55 PM PDT 24
Peak memory 206148 kb
Host smart-6a7e37ab-301f-4719-94cc-10b479558fc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677225734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3677225734
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.1423864443
Short name T172
Test name
Test status
Simulation time 175359825 ps
CPU time 1.49 seconds
Started Aug 01 07:00:12 PM PDT 24
Finished Aug 01 07:00:13 PM PDT 24
Peak memory 210192 kb
Host smart-f7a615c0-993a-4ce6-a101-5edd82294949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423864443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1423864443
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.341258611
Short name T175
Test name
Test status
Simulation time 31189767 ps
CPU time 1.63 seconds
Started Aug 01 07:00:22 PM PDT 24
Finished Aug 01 07:00:24 PM PDT 24
Peak memory 215048 kb
Host smart-7aa10185-936c-453b-9100-dd4376ab9210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341258611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.341258611
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.61154308
Short name T134
Test name
Test status
Simulation time 638819180 ps
CPU time 7.76 seconds
Started Aug 01 07:01:29 PM PDT 24
Finished Aug 01 07:01:37 PM PDT 24
Peak memory 217600 kb
Host smart-114f0d80-7e19-494f-8a62-a976be8005ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61154308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.61154308
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.78735128
Short name T145
Test name
Test status
Simulation time 165922813 ps
CPU time 3.59 seconds
Started Aug 01 07:01:07 PM PDT 24
Finished Aug 01 07:01:11 PM PDT 24
Peak memory 217428 kb
Host smart-22bc98f5-98fb-4727-a40f-c7cef3abab22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78735128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.78735128
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1285745586
Short name T436
Test name
Test status
Simulation time 24515920 ps
CPU time 1.74 seconds
Started Aug 01 06:58:59 PM PDT 24
Finished Aug 01 06:59:01 PM PDT 24
Peak memory 206996 kb
Host smart-09177a83-c2b9-4268-be77-723b85022643
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285745586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1285745586
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1597775843
Short name T205
Test name
Test status
Simulation time 665143289 ps
CPU time 18.3 seconds
Started Aug 01 06:59:06 PM PDT 24
Finished Aug 01 06:59:24 PM PDT 24
Peak memory 220104 kb
Host smart-c1e40234-e5d7-49a8-a692-5769b0103d1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597775843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1597775843
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3888657508
Short name T304
Test name
Test status
Simulation time 186212773 ps
CPU time 3.47 seconds
Started Aug 01 06:59:37 PM PDT 24
Finished Aug 01 06:59:40 PM PDT 24
Peak memory 219980 kb
Host smart-893266eb-86a0-480c-8367-66eea885a48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888657508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3888657508
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3108864723
Short name T193
Test name
Test status
Simulation time 81825154 ps
CPU time 3.83 seconds
Started Aug 01 06:59:39 PM PDT 24
Finished Aug 01 06:59:43 PM PDT 24
Peak memory 208548 kb
Host smart-252888e1-f97f-47dc-a57d-14e45468fba6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108864723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3108864723
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3360106983
Short name T372
Test name
Test status
Simulation time 42631280 ps
CPU time 2.92 seconds
Started Aug 01 06:59:37 PM PDT 24
Finished Aug 01 06:59:40 PM PDT 24
Peak memory 214328 kb
Host smart-58845e4b-023c-4f67-af0a-19a497e26add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360106983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3360106983
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2002817200
Short name T741
Test name
Test status
Simulation time 218041611 ps
CPU time 3.59 seconds
Started Aug 01 06:59:41 PM PDT 24
Finished Aug 01 06:59:45 PM PDT 24
Peak memory 210288 kb
Host smart-3b099988-00fe-4553-b45b-982b6e8dd0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002817200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2002817200
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.2424264563
Short name T283
Test name
Test status
Simulation time 25885557 ps
CPU time 1.79 seconds
Started Aug 01 06:59:44 PM PDT 24
Finished Aug 01 06:59:46 PM PDT 24
Peak memory 207076 kb
Host smart-25f2df74-8392-41f2-a4de-8d5c3299eddc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424264563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2424264563
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.395150712
Short name T266
Test name
Test status
Simulation time 958370814 ps
CPU time 52.61 seconds
Started Aug 01 06:59:57 PM PDT 24
Finished Aug 01 07:00:50 PM PDT 24
Peak memory 215324 kb
Host smart-c989a629-8474-454c-9408-e6b80530ea1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=395150712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.395150712
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2809396290
Short name T317
Test name
Test status
Simulation time 54177561 ps
CPU time 1.37 seconds
Started Aug 01 07:00:08 PM PDT 24
Finished Aug 01 07:00:09 PM PDT 24
Peak memory 207372 kb
Host smart-85da1414-c82d-4dc0-9351-dc86d5cd4469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809396290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2809396290
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1886820363
Short name T320
Test name
Test status
Simulation time 277382900 ps
CPU time 2.68 seconds
Started Aug 01 06:59:09 PM PDT 24
Finished Aug 01 06:59:12 PM PDT 24
Peak memory 214280 kb
Host smart-d7895ccb-bf52-4d3d-9966-2bb09c08fb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886820363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1886820363
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3458421276
Short name T326
Test name
Test status
Simulation time 145714145 ps
CPU time 2.75 seconds
Started Aug 01 07:00:20 PM PDT 24
Finished Aug 01 07:00:23 PM PDT 24
Peak memory 210672 kb
Host smart-fd9274c7-39fb-415f-8476-f96a1d6dba4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458421276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3458421276
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1046592169
Short name T2
Test name
Test status
Simulation time 250509135 ps
CPU time 3.67 seconds
Started Aug 01 07:00:36 PM PDT 24
Finished Aug 01 07:00:40 PM PDT 24
Peak memory 214320 kb
Host smart-42ab767e-5d71-48ca-854b-65c35a24c2ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1046592169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1046592169
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.4275628211
Short name T30
Test name
Test status
Simulation time 51713348 ps
CPU time 1.68 seconds
Started Aug 01 07:00:45 PM PDT 24
Finished Aug 01 07:00:47 PM PDT 24
Peak memory 206944 kb
Host smart-757d3e04-0e6a-47e7-bf15-e23a0e6f5a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275628211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.4275628211
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1990213886
Short name T427
Test name
Test status
Simulation time 101866052 ps
CPU time 2.25 seconds
Started Aug 01 07:00:48 PM PDT 24
Finished Aug 01 07:00:51 PM PDT 24
Peak memory 214304 kb
Host smart-476134ae-7d7b-48ee-b553-048697eda5ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1990213886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1990213886
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2431423286
Short name T51
Test name
Test status
Simulation time 3359761215 ps
CPU time 31.27 seconds
Started Aug 01 07:01:29 PM PDT 24
Finished Aug 01 07:02:00 PM PDT 24
Peak memory 222528 kb
Host smart-25bf5bd3-4c7d-4fd5-8e3e-fb139bf4e6d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431423286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2431423286
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3258255690
Short name T206
Test name
Test status
Simulation time 88888993 ps
CPU time 2.92 seconds
Started Aug 01 07:01:29 PM PDT 24
Finished Aug 01 07:01:32 PM PDT 24
Peak memory 210432 kb
Host smart-86e5b0f4-51e0-4e1d-b831-75e87be811d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258255690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3258255690
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.4215694825
Short name T6
Test name
Test status
Simulation time 121511511 ps
CPU time 4.28 seconds
Started Aug 01 07:01:35 PM PDT 24
Finished Aug 01 07:01:40 PM PDT 24
Peak memory 220296 kb
Host smart-f54108b7-7a40-478c-8b10-3490e90abea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215694825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.4215694825
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3732904285
Short name T136
Test name
Test status
Simulation time 151381259 ps
CPU time 3.94 seconds
Started Aug 01 06:59:37 PM PDT 24
Finished Aug 01 06:59:41 PM PDT 24
Peak memory 217888 kb
Host smart-f556e95b-bf89-4a93-a3c4-9cfbcb44cbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732904285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3732904285
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.396466517
Short name T62
Test name
Test status
Simulation time 762069353 ps
CPU time 6.22 seconds
Started Aug 01 06:59:48 PM PDT 24
Finished Aug 01 06:59:55 PM PDT 24
Peak memory 222736 kb
Host smart-1f6a57f0-4688-4b28-a49a-d265a976502f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396466517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.396466517
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1643076061
Short name T979
Test name
Test status
Simulation time 987156723 ps
CPU time 18.26 seconds
Started Aug 01 07:01:50 PM PDT 24
Finished Aug 01 07:02:08 PM PDT 24
Peak memory 206244 kb
Host smart-9e328bfc-ec18-4a8c-bb19-39c865936f79
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643076061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
643076061
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2843786638
Short name T1048
Test name
Test status
Simulation time 464130231 ps
CPU time 12.28 seconds
Started Aug 01 07:01:43 PM PDT 24
Finished Aug 01 07:01:55 PM PDT 24
Peak memory 206212 kb
Host smart-e9d7e6bc-3050-4ee4-b78b-ebec9c30a3d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843786638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
843786638
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1925266176
Short name T1032
Test name
Test status
Simulation time 270267859 ps
CPU time 1.12 seconds
Started Aug 01 07:01:47 PM PDT 24
Finished Aug 01 07:01:49 PM PDT 24
Peak memory 206160 kb
Host smart-d90176e8-7acd-4ada-af33-efdb45de005f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925266176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
925266176
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.263678901
Short name T920
Test name
Test status
Simulation time 73711104 ps
CPU time 2.65 seconds
Started Aug 01 07:01:46 PM PDT 24
Finished Aug 01 07:01:48 PM PDT 24
Peak memory 214396 kb
Host smart-bd414014-1366-4907-a0e7-48395c1f8386
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263678901 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.263678901
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.808112766
Short name T980
Test name
Test status
Simulation time 111376225 ps
CPU time 1.12 seconds
Started Aug 01 07:01:40 PM PDT 24
Finished Aug 01 07:01:42 PM PDT 24
Peak memory 206044 kb
Host smart-0089876e-f63d-4030-b0c6-ad60be1bb618
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808112766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.808112766
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.510353786
Short name T1044
Test name
Test status
Simulation time 188730791 ps
CPU time 0.85 seconds
Started Aug 01 07:01:40 PM PDT 24
Finished Aug 01 07:01:41 PM PDT 24
Peak memory 205888 kb
Host smart-7eab66aa-ec7a-4a3d-809a-d9b5dcdcf45a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510353786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.510353786
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2369381690
Short name T1054
Test name
Test status
Simulation time 79754994 ps
CPU time 2.68 seconds
Started Aug 01 07:01:51 PM PDT 24
Finished Aug 01 07:01:54 PM PDT 24
Peak memory 206064 kb
Host smart-adfd3b76-baf1-4857-aa6e-754af4969777
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369381690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2369381690
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3068229979
Short name T1012
Test name
Test status
Simulation time 326091985 ps
CPU time 2.76 seconds
Started Aug 01 07:01:42 PM PDT 24
Finished Aug 01 07:01:45 PM PDT 24
Peak memory 214528 kb
Host smart-31009857-7215-4105-a0cb-7a9e51e4a1a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068229979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3068229979
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1718491203
Short name T1041
Test name
Test status
Simulation time 176825898 ps
CPU time 8.15 seconds
Started Aug 01 07:01:40 PM PDT 24
Finished Aug 01 07:01:48 PM PDT 24
Peak memory 214924 kb
Host smart-14f8c288-647a-4797-be6d-413c3649821e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718491203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1718491203
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2557296114
Short name T917
Test name
Test status
Simulation time 173096331 ps
CPU time 2.45 seconds
Started Aug 01 07:01:37 PM PDT 24
Finished Aug 01 07:01:40 PM PDT 24
Peak memory 214340 kb
Host smart-549ceea3-113c-4283-bda3-45439181343f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557296114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2557296114
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3298503329
Short name T1068
Test name
Test status
Simulation time 394142357 ps
CPU time 4.32 seconds
Started Aug 01 07:01:46 PM PDT 24
Finished Aug 01 07:01:50 PM PDT 24
Peak memory 214272 kb
Host smart-1501e8ba-a13c-479f-a2e0-094504bd6a40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298503329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3298503329
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2013935116
Short name T932
Test name
Test status
Simulation time 1903069239 ps
CPU time 10.97 seconds
Started Aug 01 07:01:51 PM PDT 24
Finished Aug 01 07:02:02 PM PDT 24
Peak memory 206220 kb
Host smart-c96c22f2-7c3f-4c4b-888d-e935e4d7050c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013935116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
013935116
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1000711243
Short name T996
Test name
Test status
Simulation time 2575538863 ps
CPU time 8.72 seconds
Started Aug 01 07:01:49 PM PDT 24
Finished Aug 01 07:01:58 PM PDT 24
Peak memory 206244 kb
Host smart-35fd4110-c372-48d9-99b3-570a822f910b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000711243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1
000711243
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1221504377
Short name T147
Test name
Test status
Simulation time 34541399 ps
CPU time 1.15 seconds
Started Aug 01 07:01:55 PM PDT 24
Finished Aug 01 07:01:56 PM PDT 24
Peak memory 206292 kb
Host smart-24bd8ac9-7b77-4276-942c-a0c67c71518b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221504377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
221504377
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.581733275
Short name T148
Test name
Test status
Simulation time 59670368 ps
CPU time 2.19 seconds
Started Aug 01 07:01:49 PM PDT 24
Finished Aug 01 07:01:52 PM PDT 24
Peak memory 214404 kb
Host smart-7588ee92-7f50-444a-a11b-49f4be88e405
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581733275 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.581733275
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2104033432
Short name T396
Test name
Test status
Simulation time 58397077 ps
CPU time 1.42 seconds
Started Aug 01 07:01:46 PM PDT 24
Finished Aug 01 07:01:47 PM PDT 24
Peak memory 206116 kb
Host smart-e6733c9b-26bb-4fa6-ac18-3ea3322267d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104033432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2104033432
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.4179232594
Short name T1080
Test name
Test status
Simulation time 11343420 ps
CPU time 0.71 seconds
Started Aug 01 07:01:53 PM PDT 24
Finished Aug 01 07:01:54 PM PDT 24
Peak memory 205912 kb
Host smart-84caa495-1d0e-414b-bea2-5c244d3ba783
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179232594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.4179232594
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1183716727
Short name T984
Test name
Test status
Simulation time 34035331 ps
CPU time 2.06 seconds
Started Aug 01 07:01:49 PM PDT 24
Finished Aug 01 07:01:51 PM PDT 24
Peak memory 206156 kb
Host smart-aeeeb01a-72fb-430f-867a-79512bea997e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183716727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1183716727
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.4020219341
Short name T1003
Test name
Test status
Simulation time 645323302 ps
CPU time 2.56 seconds
Started Aug 01 07:01:46 PM PDT 24
Finished Aug 01 07:01:49 PM PDT 24
Peak memory 214652 kb
Host smart-dac63348-9658-4a75-a8a8-46c0d7f4f420
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020219341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.4020219341
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3846717288
Short name T959
Test name
Test status
Simulation time 375063944 ps
CPU time 7.67 seconds
Started Aug 01 07:01:47 PM PDT 24
Finished Aug 01 07:01:55 PM PDT 24
Peak memory 214644 kb
Host smart-b61ba3fe-f9df-4a45-bca4-96c0dc7d5a2f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846717288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3846717288
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2226307805
Short name T1040
Test name
Test status
Simulation time 46177287 ps
CPU time 3.04 seconds
Started Aug 01 07:01:49 PM PDT 24
Finished Aug 01 07:01:52 PM PDT 24
Peak memory 214308 kb
Host smart-e068a977-c7e0-4b9e-b20b-44177f7e1028
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226307805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2226307805
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.802196551
Short name T935
Test name
Test status
Simulation time 61889294 ps
CPU time 1.25 seconds
Started Aug 01 07:02:01 PM PDT 24
Finished Aug 01 07:02:03 PM PDT 24
Peak memory 214472 kb
Host smart-faf2507a-c108-4a2a-876f-91a7950b9f68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802196551 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.802196551
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2138717011
Short name T1021
Test name
Test status
Simulation time 24293999 ps
CPU time 0.92 seconds
Started Aug 01 07:02:12 PM PDT 24
Finished Aug 01 07:02:13 PM PDT 24
Peak memory 206008 kb
Host smart-3104045e-fe58-478b-adcc-2c0631623bf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138717011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2138717011
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2706233875
Short name T1073
Test name
Test status
Simulation time 13282102 ps
CPU time 0.7 seconds
Started Aug 01 07:02:05 PM PDT 24
Finished Aug 01 07:02:06 PM PDT 24
Peak memory 205952 kb
Host smart-7f6b99f6-7f2e-4652-b1f8-b4dbc5f6d5d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706233875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2706233875
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3293920050
Short name T925
Test name
Test status
Simulation time 246076581 ps
CPU time 1.45 seconds
Started Aug 01 07:02:10 PM PDT 24
Finished Aug 01 07:02:12 PM PDT 24
Peak memory 206256 kb
Host smart-5065a011-d96c-4b1d-8f6f-33b5b285002d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293920050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3293920050
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.313715759
Short name T945
Test name
Test status
Simulation time 396701902 ps
CPU time 4.22 seconds
Started Aug 01 07:02:04 PM PDT 24
Finished Aug 01 07:02:08 PM PDT 24
Peak memory 214704 kb
Host smart-f651aee7-4c7b-4cce-9c39-ab78e177c792
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313715759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.313715759
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.4199898376
Short name T106
Test name
Test status
Simulation time 557973505 ps
CPU time 6.64 seconds
Started Aug 01 07:02:09 PM PDT 24
Finished Aug 01 07:02:16 PM PDT 24
Peak memory 214628 kb
Host smart-ff3961c1-df45-4526-b7f5-136cdf616f67
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199898376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.4199898376
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2056573447
Short name T1008
Test name
Test status
Simulation time 924980455 ps
CPU time 3.34 seconds
Started Aug 01 07:02:01 PM PDT 24
Finished Aug 01 07:02:05 PM PDT 24
Peak memory 214364 kb
Host smart-6b077567-0381-43b9-866b-5a22ee21da56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056573447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2056573447
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1505444626
Short name T930
Test name
Test status
Simulation time 23664956 ps
CPU time 1.9 seconds
Started Aug 01 07:02:00 PM PDT 24
Finished Aug 01 07:02:03 PM PDT 24
Peak memory 214404 kb
Host smart-3b90ad28-64f9-44b5-a6ed-8249c6fd2e25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505444626 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1505444626
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2989981940
Short name T1046
Test name
Test status
Simulation time 15435342 ps
CPU time 1.06 seconds
Started Aug 01 07:02:07 PM PDT 24
Finished Aug 01 07:02:09 PM PDT 24
Peak memory 206112 kb
Host smart-dee536a9-65c3-4a21-ae79-47956e9a7822
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989981940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2989981940
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1967840573
Short name T1017
Test name
Test status
Simulation time 17154718 ps
CPU time 0.77 seconds
Started Aug 01 07:02:05 PM PDT 24
Finished Aug 01 07:02:05 PM PDT 24
Peak memory 205940 kb
Host smart-e34bb0bc-4ada-4031-b397-dea71b96a78a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967840573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1967840573
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.4270788691
Short name T990
Test name
Test status
Simulation time 96280383 ps
CPU time 1.69 seconds
Started Aug 01 07:02:07 PM PDT 24
Finished Aug 01 07:02:09 PM PDT 24
Peak memory 206268 kb
Host smart-400fe875-d0de-4e55-b16d-1fc6811e5ecb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270788691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.4270788691
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1031370887
Short name T1013
Test name
Test status
Simulation time 146102560 ps
CPU time 1.72 seconds
Started Aug 01 07:02:01 PM PDT 24
Finished Aug 01 07:02:03 PM PDT 24
Peak memory 214656 kb
Host smart-fdef5045-4874-4945-be44-07007afda7cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031370887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1031370887
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2488161375
Short name T985
Test name
Test status
Simulation time 281747394 ps
CPU time 8.06 seconds
Started Aug 01 07:02:01 PM PDT 24
Finished Aug 01 07:02:09 PM PDT 24
Peak memory 220588 kb
Host smart-80db5df0-16e8-43fa-8a69-e53932c678a9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488161375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2488161375
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2944290944
Short name T934
Test name
Test status
Simulation time 1477517614 ps
CPU time 3.43 seconds
Started Aug 01 07:01:59 PM PDT 24
Finished Aug 01 07:02:02 PM PDT 24
Peak memory 214420 kb
Host smart-0c7d95bd-21c5-4be1-b02b-0d6cf1abc40a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944290944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2944290944
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3326049283
Short name T1066
Test name
Test status
Simulation time 136617065 ps
CPU time 1.59 seconds
Started Aug 01 07:02:02 PM PDT 24
Finished Aug 01 07:02:04 PM PDT 24
Peak memory 214500 kb
Host smart-b1f4f37e-9806-4fd5-9706-24d26d4c34ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326049283 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3326049283
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2608864690
Short name T965
Test name
Test status
Simulation time 71638562 ps
CPU time 0.97 seconds
Started Aug 01 07:02:12 PM PDT 24
Finished Aug 01 07:02:13 PM PDT 24
Peak memory 206008 kb
Host smart-f2a8849a-ab43-4d6b-acb2-b2517482b6b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608864690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2608864690
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.815805027
Short name T1045
Test name
Test status
Simulation time 42113187 ps
CPU time 0.77 seconds
Started Aug 01 07:02:07 PM PDT 24
Finished Aug 01 07:02:08 PM PDT 24
Peak memory 205860 kb
Host smart-e9e19c26-e064-4c51-820f-cd2a2f63f6fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815805027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.815805027
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3213200828
Short name T987
Test name
Test status
Simulation time 130841682 ps
CPU time 2.75 seconds
Started Aug 01 07:02:10 PM PDT 24
Finished Aug 01 07:02:13 PM PDT 24
Peak memory 206092 kb
Host smart-a3320b3b-48d4-4e29-8457-a07dd0e3afbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213200828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3213200828
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1648430659
Short name T939
Test name
Test status
Simulation time 416017067 ps
CPU time 2.52 seconds
Started Aug 01 07:02:02 PM PDT 24
Finished Aug 01 07:02:04 PM PDT 24
Peak memory 214676 kb
Host smart-bd7c27c3-29bd-40c6-bbe3-9d44b46d0c42
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648430659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1648430659
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1595916570
Short name T1031
Test name
Test status
Simulation time 424343175 ps
CPU time 3.32 seconds
Started Aug 01 07:02:01 PM PDT 24
Finished Aug 01 07:02:05 PM PDT 24
Peak memory 214656 kb
Host smart-3162d8f5-0e00-40f0-9bfb-49dc779a723f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595916570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1595916570
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1977947011
Short name T969
Test name
Test status
Simulation time 201026378 ps
CPU time 1.61 seconds
Started Aug 01 07:02:01 PM PDT 24
Finished Aug 01 07:02:03 PM PDT 24
Peak memory 214388 kb
Host smart-626042f5-e6e4-4e8a-ab33-c3ff9b7e0db9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977947011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1977947011
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.948378803
Short name T159
Test name
Test status
Simulation time 238289693 ps
CPU time 4.66 seconds
Started Aug 01 07:02:11 PM PDT 24
Finished Aug 01 07:02:16 PM PDT 24
Peak memory 206308 kb
Host smart-206ed8ff-d59b-4ece-b300-43dc463931a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948378803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err
.948378803
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2664519786
Short name T928
Test name
Test status
Simulation time 111231167 ps
CPU time 1.48 seconds
Started Aug 01 07:02:11 PM PDT 24
Finished Aug 01 07:02:13 PM PDT 24
Peak memory 214496 kb
Host smart-0d3249a9-355e-4e4f-9886-b7ce89e828aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664519786 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2664519786
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.758124528
Short name T129
Test name
Test status
Simulation time 42480896 ps
CPU time 1.02 seconds
Started Aug 01 07:02:11 PM PDT 24
Finished Aug 01 07:02:12 PM PDT 24
Peak memory 205984 kb
Host smart-d1ae27b7-fd69-497e-af28-617f2055bd2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758124528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.758124528
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3640847021
Short name T942
Test name
Test status
Simulation time 15794958 ps
CPU time 0.8 seconds
Started Aug 01 07:02:02 PM PDT 24
Finished Aug 01 07:02:03 PM PDT 24
Peak memory 205888 kb
Host smart-aeda1ce0-b906-4f81-8273-6c8aa146ad79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640847021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3640847021
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2539645784
Short name T1074
Test name
Test status
Simulation time 36034313 ps
CPU time 2.28 seconds
Started Aug 01 07:02:10 PM PDT 24
Finished Aug 01 07:02:12 PM PDT 24
Peak memory 206192 kb
Host smart-61b45322-8e61-4659-9f5c-e86f1d95cb5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539645784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2539645784
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2908334582
Short name T1047
Test name
Test status
Simulation time 143649888 ps
CPU time 2.92 seconds
Started Aug 01 07:02:03 PM PDT 24
Finished Aug 01 07:02:06 PM PDT 24
Peak memory 214576 kb
Host smart-7787e469-81c2-4893-a94b-52e0b3554191
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908334582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2908334582
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1195675350
Short name T111
Test name
Test status
Simulation time 281209382 ps
CPU time 8.44 seconds
Started Aug 01 07:02:02 PM PDT 24
Finished Aug 01 07:02:10 PM PDT 24
Peak memory 214584 kb
Host smart-3ed1edba-8d52-4b6b-b217-21a81f02cb81
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195675350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1195675350
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3262438155
Short name T1077
Test name
Test status
Simulation time 71913197 ps
CPU time 2.51 seconds
Started Aug 01 07:02:03 PM PDT 24
Finished Aug 01 07:02:06 PM PDT 24
Peak memory 214420 kb
Host smart-4eeaae23-9c36-4286-8323-b7e093260103
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262438155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3262438155
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3536308430
Short name T967
Test name
Test status
Simulation time 39385455 ps
CPU time 1.36 seconds
Started Aug 01 07:02:16 PM PDT 24
Finished Aug 01 07:02:17 PM PDT 24
Peak memory 214552 kb
Host smart-7d0b169c-1abf-433e-8459-dae05486a592
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536308430 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3536308430
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1866865544
Short name T1015
Test name
Test status
Simulation time 40887404 ps
CPU time 1.08 seconds
Started Aug 01 07:02:19 PM PDT 24
Finished Aug 01 07:02:20 PM PDT 24
Peak memory 206008 kb
Host smart-6a8f2e5d-9efe-4371-b487-999b08a28ea3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866865544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1866865544
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1514336712
Short name T1043
Test name
Test status
Simulation time 24934416 ps
CPU time 0.71 seconds
Started Aug 01 07:02:14 PM PDT 24
Finished Aug 01 07:02:15 PM PDT 24
Peak memory 205964 kb
Host smart-bcf3b4dd-7406-465d-8998-59c789ce2fda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514336712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1514336712
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.388078473
Short name T128
Test name
Test status
Simulation time 904403873 ps
CPU time 3.21 seconds
Started Aug 01 07:02:20 PM PDT 24
Finished Aug 01 07:02:24 PM PDT 24
Peak memory 206116 kb
Host smart-9ff74159-0002-4e8d-a901-9d79ecabf160
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388078473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.388078473
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.403905400
Short name T1042
Test name
Test status
Simulation time 216420344 ps
CPU time 5.71 seconds
Started Aug 01 07:02:03 PM PDT 24
Finished Aug 01 07:02:09 PM PDT 24
Peak memory 214532 kb
Host smart-98b26dbe-62f8-4d9b-96de-be859c733950
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403905400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.403905400
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.4158513622
Short name T113
Test name
Test status
Simulation time 170562169 ps
CPU time 8.48 seconds
Started Aug 01 07:02:03 PM PDT 24
Finished Aug 01 07:02:11 PM PDT 24
Peak memory 214672 kb
Host smart-6c3ac8d0-e2e3-4e8a-a5d5-dd06a1ddd661
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158513622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.4158513622
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3144743468
Short name T949
Test name
Test status
Simulation time 34393026 ps
CPU time 2.48 seconds
Started Aug 01 07:02:03 PM PDT 24
Finished Aug 01 07:02:06 PM PDT 24
Peak memory 214332 kb
Host smart-b6fca0d0-7c9c-4114-9b96-68c3eccdc327
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144743468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3144743468
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.271356471
Short name T158
Test name
Test status
Simulation time 112565189 ps
CPU time 5.59 seconds
Started Aug 01 07:02:12 PM PDT 24
Finished Aug 01 07:02:18 PM PDT 24
Peak memory 214264 kb
Host smart-f64fc70a-19f7-4e0b-9a8f-19c079adc36a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271356471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err
.271356471
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2730354347
Short name T1071
Test name
Test status
Simulation time 19485239 ps
CPU time 1.46 seconds
Started Aug 01 07:02:15 PM PDT 24
Finished Aug 01 07:02:17 PM PDT 24
Peak memory 206180 kb
Host smart-a7d97d1e-8f6a-4b36-9e3e-1e167a9ff735
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730354347 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2730354347
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.304084361
Short name T1030
Test name
Test status
Simulation time 82937487 ps
CPU time 0.99 seconds
Started Aug 01 07:02:13 PM PDT 24
Finished Aug 01 07:02:14 PM PDT 24
Peak memory 206132 kb
Host smart-f449be4c-ca87-4b71-a3c3-2c468c789460
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304084361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.304084361
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.4201779064
Short name T927
Test name
Test status
Simulation time 16208433 ps
CPU time 0.76 seconds
Started Aug 01 07:02:14 PM PDT 24
Finished Aug 01 07:02:15 PM PDT 24
Peak memory 205940 kb
Host smart-f654bf8f-3b6d-4baa-b31b-fc14d3b57a02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201779064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.4201779064
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1609539183
Short name T982
Test name
Test status
Simulation time 34520449 ps
CPU time 2.46 seconds
Started Aug 01 07:02:14 PM PDT 24
Finished Aug 01 07:02:17 PM PDT 24
Peak memory 206268 kb
Host smart-528e1bdf-5ab8-45b1-8bbd-bea44b8e3c7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609539183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1609539183
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.4273823534
Short name T986
Test name
Test status
Simulation time 157396473 ps
CPU time 2.4 seconds
Started Aug 01 07:02:11 PM PDT 24
Finished Aug 01 07:02:14 PM PDT 24
Peak memory 214604 kb
Host smart-2c04418c-04c9-4b84-8a93-df30a6401f23
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273823534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.4273823534
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.247381271
Short name T1002
Test name
Test status
Simulation time 381072739 ps
CPU time 7.49 seconds
Started Aug 01 07:02:17 PM PDT 24
Finished Aug 01 07:02:25 PM PDT 24
Peak memory 214612 kb
Host smart-bb630817-d464-45d9-af0d-69a00a8d1fc9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247381271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_shadow_reg_errors_with_csr_rw.247381271
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.783757967
Short name T992
Test name
Test status
Simulation time 89968603 ps
CPU time 1.62 seconds
Started Aug 01 07:02:17 PM PDT 24
Finished Aug 01 07:02:19 PM PDT 24
Peak memory 214456 kb
Host smart-25d40c66-4658-4e60-bb0f-e6c4db33ffed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783757967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.783757967
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2539339534
Short name T954
Test name
Test status
Simulation time 81908725 ps
CPU time 1.39 seconds
Started Aug 01 07:02:15 PM PDT 24
Finished Aug 01 07:02:16 PM PDT 24
Peak memory 206280 kb
Host smart-b6e2bb95-4e3c-4535-b9c0-2262d479c3ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539339534 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2539339534
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2223917125
Short name T1060
Test name
Test status
Simulation time 43916850 ps
CPU time 0.93 seconds
Started Aug 01 07:02:29 PM PDT 24
Finished Aug 01 07:02:30 PM PDT 24
Peak memory 205896 kb
Host smart-3cdcf72c-5709-47ad-8229-94cb4079f977
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223917125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2223917125
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1699566519
Short name T1059
Test name
Test status
Simulation time 51259506 ps
CPU time 0.79 seconds
Started Aug 01 07:02:19 PM PDT 24
Finished Aug 01 07:02:20 PM PDT 24
Peak memory 205956 kb
Host smart-8a9ab95e-cef9-44af-9eb1-501bb660cecf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699566519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1699566519
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.35890268
Short name T958
Test name
Test status
Simulation time 431993967 ps
CPU time 2.77 seconds
Started Aug 01 07:02:22 PM PDT 24
Finished Aug 01 07:02:25 PM PDT 24
Peak memory 214376 kb
Host smart-d9d9a3cc-6602-41cc-adac-04c294acaeb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35890268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sam
e_csr_outstanding.35890268
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3110723861
Short name T948
Test name
Test status
Simulation time 70279399 ps
CPU time 1.66 seconds
Started Aug 01 07:02:20 PM PDT 24
Finished Aug 01 07:02:22 PM PDT 24
Peak memory 214608 kb
Host smart-3659668b-f564-488b-b387-ff356c86ab6f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110723861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3110723861
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2325775106
Short name T933
Test name
Test status
Simulation time 1342986991 ps
CPU time 8.89 seconds
Started Aug 01 07:02:14 PM PDT 24
Finished Aug 01 07:02:24 PM PDT 24
Peak memory 214652 kb
Host smart-810bb8d0-ea31-4aac-a866-afbf5374e1c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325775106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.2325775106
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2378149868
Short name T1038
Test name
Test status
Simulation time 111959609 ps
CPU time 2.74 seconds
Started Aug 01 07:02:10 PM PDT 24
Finished Aug 01 07:02:13 PM PDT 24
Peak memory 216840 kb
Host smart-9634838d-76e2-4654-a33c-f94c5c185d61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378149868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2378149868
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.151896510
Short name T1064
Test name
Test status
Simulation time 74678496 ps
CPU time 1.39 seconds
Started Aug 01 07:02:13 PM PDT 24
Finished Aug 01 07:02:15 PM PDT 24
Peak memory 214392 kb
Host smart-06740876-0699-4520-b2df-79bee7b95ef3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151896510 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.151896510
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1393173713
Short name T961
Test name
Test status
Simulation time 29998409 ps
CPU time 1.63 seconds
Started Aug 01 07:02:20 PM PDT 24
Finished Aug 01 07:02:22 PM PDT 24
Peak memory 206068 kb
Host smart-2ffeef1f-7102-462d-a524-c8fe312ac6eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393173713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1393173713
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2782332830
Short name T1056
Test name
Test status
Simulation time 35263126 ps
CPU time 0.74 seconds
Started Aug 01 07:02:14 PM PDT 24
Finished Aug 01 07:02:14 PM PDT 24
Peak memory 205916 kb
Host smart-2fbf74a0-71d7-4732-911a-1909827ca8cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782332830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2782332830
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.475210393
Short name T1016
Test name
Test status
Simulation time 124903682 ps
CPU time 4.18 seconds
Started Aug 01 07:02:16 PM PDT 24
Finished Aug 01 07:02:21 PM PDT 24
Peak memory 206076 kb
Host smart-39303983-b88f-4178-9b9a-47dfcccf5dc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475210393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.475210393
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3728397857
Short name T981
Test name
Test status
Simulation time 90940766 ps
CPU time 2.46 seconds
Started Aug 01 07:02:16 PM PDT 24
Finished Aug 01 07:02:19 PM PDT 24
Peak memory 214592 kb
Host smart-7b74c0c2-a289-4b6a-a7f9-8531f96e64d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728397857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3728397857
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.904475046
Short name T951
Test name
Test status
Simulation time 1308796164 ps
CPU time 11.95 seconds
Started Aug 01 07:02:12 PM PDT 24
Finished Aug 01 07:02:24 PM PDT 24
Peak memory 214624 kb
Host smart-1dac37cc-37da-4ddf-9d32-938b11ee9e9d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904475046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.904475046
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2518976329
Short name T963
Test name
Test status
Simulation time 83335322 ps
CPU time 1.81 seconds
Started Aug 01 07:02:15 PM PDT 24
Finished Aug 01 07:02:17 PM PDT 24
Peak memory 214672 kb
Host smart-bfe78578-fab5-46c6-a6e5-25e2afe3faed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518976329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2518976329
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1412286718
Short name T918
Test name
Test status
Simulation time 37438599 ps
CPU time 2.63 seconds
Started Aug 01 07:02:16 PM PDT 24
Finished Aug 01 07:02:19 PM PDT 24
Peak memory 214508 kb
Host smart-0f23d49f-4f5e-445e-995c-3248d15e979e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412286718 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1412286718
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2227349706
Short name T1081
Test name
Test status
Simulation time 57710108 ps
CPU time 1.64 seconds
Started Aug 01 07:02:23 PM PDT 24
Finished Aug 01 07:02:24 PM PDT 24
Peak memory 206160 kb
Host smart-16eaff6e-9171-497a-af2d-e65ab1ff3ad2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227349706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2227349706
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.4002385347
Short name T915
Test name
Test status
Simulation time 17906989 ps
CPU time 0.75 seconds
Started Aug 01 07:02:22 PM PDT 24
Finished Aug 01 07:02:23 PM PDT 24
Peak memory 205952 kb
Host smart-ee7fa2c5-0c12-4555-83fb-a53210ec1573
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002385347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.4002385347
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1653450440
Short name T1058
Test name
Test status
Simulation time 116141706 ps
CPU time 2.12 seconds
Started Aug 01 07:02:15 PM PDT 24
Finished Aug 01 07:02:17 PM PDT 24
Peak memory 206140 kb
Host smart-5489338c-c189-4ed1-a78a-6bcefdf08165
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653450440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1653450440
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3531039370
Short name T1029
Test name
Test status
Simulation time 277801186 ps
CPU time 2.65 seconds
Started Aug 01 07:02:12 PM PDT 24
Finished Aug 01 07:02:15 PM PDT 24
Peak memory 214688 kb
Host smart-259d3870-b12f-4bb4-b8d8-404375c8b08c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531039370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3531039370
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.878057290
Short name T962
Test name
Test status
Simulation time 317461167 ps
CPU time 7.09 seconds
Started Aug 01 07:02:13 PM PDT 24
Finished Aug 01 07:02:20 PM PDT 24
Peak memory 214648 kb
Host smart-9dbc0865-cbef-4caf-8e5d-8384f3f7a2da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878057290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_shadow_reg_errors_with_csr_rw.878057290
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.899955578
Short name T960
Test name
Test status
Simulation time 21135124 ps
CPU time 1.62 seconds
Started Aug 01 07:02:25 PM PDT 24
Finished Aug 01 07:02:26 PM PDT 24
Peak memory 214496 kb
Host smart-71c33a27-026d-4a3c-94fd-3835f2896069
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899955578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.899955578
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1710439363
Short name T1011
Test name
Test status
Simulation time 139069041 ps
CPU time 3.86 seconds
Started Aug 01 07:02:24 PM PDT 24
Finished Aug 01 07:02:28 PM PDT 24
Peak memory 214392 kb
Host smart-870349b9-c29f-40b8-a53c-0ff44df4dc27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710439363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1710439363
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3036155367
Short name T153
Test name
Test status
Simulation time 113355974 ps
CPU time 1.27 seconds
Started Aug 01 07:02:12 PM PDT 24
Finished Aug 01 07:02:13 PM PDT 24
Peak memory 214380 kb
Host smart-60116138-dd8e-47d9-b4dd-a5f0f215a0bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036155367 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3036155367
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2736076928
Short name T1070
Test name
Test status
Simulation time 20927147 ps
CPU time 1.04 seconds
Started Aug 01 07:02:16 PM PDT 24
Finished Aug 01 07:02:17 PM PDT 24
Peak memory 206148 kb
Host smart-46f14318-db15-480e-a8a3-638bc675a1d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736076928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2736076928
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.112780008
Short name T1063
Test name
Test status
Simulation time 38674497 ps
CPU time 0.75 seconds
Started Aug 01 07:02:21 PM PDT 24
Finished Aug 01 07:02:22 PM PDT 24
Peak memory 205932 kb
Host smart-e672057c-f1eb-4df6-85f3-28b033efa037
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112780008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.112780008
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1447473949
Short name T944
Test name
Test status
Simulation time 177714252 ps
CPU time 1.59 seconds
Started Aug 01 07:02:13 PM PDT 24
Finished Aug 01 07:02:15 PM PDT 24
Peak memory 206180 kb
Host smart-a08c2420-9643-4a70-8bf0-9f529ae95b82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447473949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1447473949
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.804847058
Short name T1010
Test name
Test status
Simulation time 319259581 ps
CPU time 2.71 seconds
Started Aug 01 07:02:15 PM PDT 24
Finished Aug 01 07:02:18 PM PDT 24
Peak memory 214588 kb
Host smart-cbae0962-2a1e-4293-8296-894484c9f651
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804847058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.804847058
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3586906538
Short name T112
Test name
Test status
Simulation time 626484633 ps
CPU time 4.52 seconds
Started Aug 01 07:02:14 PM PDT 24
Finished Aug 01 07:02:19 PM PDT 24
Peak memory 221152 kb
Host smart-46116748-2e70-472c-a140-87ea7d5af695
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586906538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3586906538
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.4114150356
Short name T1075
Test name
Test status
Simulation time 217745063 ps
CPU time 5.91 seconds
Started Aug 01 07:02:17 PM PDT 24
Finished Aug 01 07:02:23 PM PDT 24
Peak memory 217592 kb
Host smart-eff3b926-d8a8-4be2-be63-c57e49fbaab4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114150356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.4114150356
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2913393073
Short name T150
Test name
Test status
Simulation time 194093597 ps
CPU time 3.02 seconds
Started Aug 01 07:02:10 PM PDT 24
Finished Aug 01 07:02:13 PM PDT 24
Peak memory 214368 kb
Host smart-ab00fde7-218f-4d72-90a2-6268956a3012
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913393073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2913393073
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3650732033
Short name T1039
Test name
Test status
Simulation time 253440276 ps
CPU time 5.41 seconds
Started Aug 01 07:01:47 PM PDT 24
Finished Aug 01 07:01:52 PM PDT 24
Peak memory 206096 kb
Host smart-3968a01b-1007-4bcf-83ec-eb002be51e83
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650732033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
650732033
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2749693301
Short name T1078
Test name
Test status
Simulation time 267594628 ps
CPU time 11.63 seconds
Started Aug 01 07:01:54 PM PDT 24
Finished Aug 01 07:02:05 PM PDT 24
Peak memory 206196 kb
Host smart-b3f2ab41-e97c-49a6-ae45-9e1bb4728b27
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749693301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
749693301
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1890227328
Short name T974
Test name
Test status
Simulation time 22080013 ps
CPU time 1.09 seconds
Started Aug 01 07:01:50 PM PDT 24
Finished Aug 01 07:01:51 PM PDT 24
Peak memory 206088 kb
Host smart-431bbd74-65ab-4965-8cfa-0fd317241f27
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890227328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
890227328
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3442962872
Short name T923
Test name
Test status
Simulation time 23685331 ps
CPU time 1.48 seconds
Started Aug 01 07:01:49 PM PDT 24
Finished Aug 01 07:01:50 PM PDT 24
Peak memory 214384 kb
Host smart-fb1ac887-8073-4e98-b75d-822609e84fad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442962872 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3442962872
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3159406913
Short name T1069
Test name
Test status
Simulation time 119743982 ps
CPU time 1.05 seconds
Started Aug 01 07:01:52 PM PDT 24
Finished Aug 01 07:01:53 PM PDT 24
Peak memory 206008 kb
Host smart-b968bd98-b061-4321-b30a-124755864af7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159406913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3159406913
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2685385177
Short name T964
Test name
Test status
Simulation time 26811886 ps
CPU time 0.73 seconds
Started Aug 01 07:01:49 PM PDT 24
Finished Aug 01 07:01:50 PM PDT 24
Peak memory 205880 kb
Host smart-d2c13bfd-bbb6-43cc-8a82-c8bc93fa3a5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685385177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2685385177
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2043299154
Short name T1065
Test name
Test status
Simulation time 21717032 ps
CPU time 1.7 seconds
Started Aug 01 07:01:49 PM PDT 24
Finished Aug 01 07:01:51 PM PDT 24
Peak memory 206168 kb
Host smart-66695326-205a-4470-b9cd-29c245a094a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043299154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2043299154
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3856335236
Short name T1034
Test name
Test status
Simulation time 273841001 ps
CPU time 4.11 seconds
Started Aug 01 07:01:48 PM PDT 24
Finished Aug 01 07:01:52 PM PDT 24
Peak memory 214628 kb
Host smart-b30a99f6-c5d1-47ea-a60a-c04b57b3a7fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856335236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3856335236
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1994857829
Short name T131
Test name
Test status
Simulation time 455289267 ps
CPU time 8.58 seconds
Started Aug 01 07:01:52 PM PDT 24
Finished Aug 01 07:02:00 PM PDT 24
Peak memory 214692 kb
Host smart-048edf92-497d-4de6-9b4e-c304aa401c05
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994857829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1994857829
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1172363221
Short name T997
Test name
Test status
Simulation time 92464720 ps
CPU time 3.47 seconds
Started Aug 01 07:01:51 PM PDT 24
Finished Aug 01 07:01:54 PM PDT 24
Peak memory 214316 kb
Host smart-be7ebd2c-7d46-4b70-91e8-cba1f3528e36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172363221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1172363221
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1190173168
Short name T1061
Test name
Test status
Simulation time 10543809 ps
CPU time 0.73 seconds
Started Aug 01 07:02:14 PM PDT 24
Finished Aug 01 07:02:15 PM PDT 24
Peak memory 205836 kb
Host smart-d2d8602d-2845-4262-bbbf-1c9868cf3a4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190173168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1190173168
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2786384229
Short name T988
Test name
Test status
Simulation time 54198789 ps
CPU time 0.81 seconds
Started Aug 01 07:02:15 PM PDT 24
Finished Aug 01 07:02:16 PM PDT 24
Peak memory 205928 kb
Host smart-b478a8be-f9e0-4184-aef8-75c0b7997e50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786384229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2786384229
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2272637519
Short name T941
Test name
Test status
Simulation time 38807573 ps
CPU time 0.81 seconds
Started Aug 01 07:02:16 PM PDT 24
Finished Aug 01 07:02:17 PM PDT 24
Peak memory 205940 kb
Host smart-3f948913-dae3-4279-bbdc-b2aabae73e19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272637519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2272637519
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1792269288
Short name T926
Test name
Test status
Simulation time 41942153 ps
CPU time 0.73 seconds
Started Aug 01 07:02:14 PM PDT 24
Finished Aug 01 07:02:15 PM PDT 24
Peak memory 205912 kb
Host smart-b71ef901-34ad-4a50-bc50-d1fdbe0848ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792269288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1792269288
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1218548286
Short name T914
Test name
Test status
Simulation time 7659976 ps
CPU time 0.78 seconds
Started Aug 01 07:02:16 PM PDT 24
Finished Aug 01 07:02:17 PM PDT 24
Peak memory 205868 kb
Host smart-25937f2f-dae5-4b8c-807c-6a65a4677d26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218548286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1218548286
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.406346656
Short name T977
Test name
Test status
Simulation time 10209695 ps
CPU time 0.86 seconds
Started Aug 01 07:02:19 PM PDT 24
Finished Aug 01 07:02:20 PM PDT 24
Peak memory 205916 kb
Host smart-4381a4b7-d0c4-4ae8-b339-892672a0cf9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406346656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.406346656
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2197048334
Short name T983
Test name
Test status
Simulation time 16603668 ps
CPU time 0.7 seconds
Started Aug 01 07:02:24 PM PDT 24
Finished Aug 01 07:02:25 PM PDT 24
Peak memory 205964 kb
Host smart-af2759ed-af05-4a8f-81ee-4c7d00635eb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197048334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2197048334
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3526967364
Short name T946
Test name
Test status
Simulation time 9486200 ps
CPU time 0.82 seconds
Started Aug 01 07:02:13 PM PDT 24
Finished Aug 01 07:02:14 PM PDT 24
Peak memory 205968 kb
Host smart-a2eb4f43-fbdf-4ba7-a2e0-4bb699825327
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526967364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3526967364
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.158252773
Short name T956
Test name
Test status
Simulation time 43026984 ps
CPU time 0.73 seconds
Started Aug 01 07:02:16 PM PDT 24
Finished Aug 01 07:02:17 PM PDT 24
Peak memory 205900 kb
Host smart-647dea3a-4702-4bc8-ab3f-5f8fb550664a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158252773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.158252773
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1993787709
Short name T1079
Test name
Test status
Simulation time 8238046 ps
CPU time 0.69 seconds
Started Aug 01 07:02:24 PM PDT 24
Finished Aug 01 07:02:25 PM PDT 24
Peak memory 205940 kb
Host smart-446ce550-aeec-4246-a5c1-4724d81ac255
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993787709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1993787709
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2798589764
Short name T1053
Test name
Test status
Simulation time 1295656851 ps
CPU time 16.97 seconds
Started Aug 01 07:01:52 PM PDT 24
Finished Aug 01 07:02:09 PM PDT 24
Peak memory 206220 kb
Host smart-6e951453-2e2d-4072-8aa0-d8f2ab273232
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798589764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
798589764
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2022604665
Short name T1026
Test name
Test status
Simulation time 3424374686 ps
CPU time 24.88 seconds
Started Aug 01 07:01:47 PM PDT 24
Finished Aug 01 07:02:12 PM PDT 24
Peak memory 206248 kb
Host smart-3e0d775e-f218-4d77-bcc8-8b1cea3e82c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022604665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
022604665
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3733410968
Short name T1023
Test name
Test status
Simulation time 115775590 ps
CPU time 1.11 seconds
Started Aug 01 07:01:56 PM PDT 24
Finished Aug 01 07:01:58 PM PDT 24
Peak memory 206200 kb
Host smart-baf4ea13-d6f8-4c28-a9c3-1180b861f561
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733410968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
733410968
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.197882979
Short name T952
Test name
Test status
Simulation time 50092035 ps
CPU time 2.11 seconds
Started Aug 01 07:01:53 PM PDT 24
Finished Aug 01 07:01:56 PM PDT 24
Peak memory 214376 kb
Host smart-e3146c88-5f1e-4779-b98b-2159742210b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197882979 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.197882979
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2676751197
Short name T1055
Test name
Test status
Simulation time 112134715 ps
CPU time 1.6 seconds
Started Aug 01 07:01:52 PM PDT 24
Finished Aug 01 07:01:53 PM PDT 24
Peak memory 206160 kb
Host smart-9e2ffc55-2d58-494b-8044-f681d1b5918d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676751197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2676751197
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3320606071
Short name T971
Test name
Test status
Simulation time 25627684 ps
CPU time 0.83 seconds
Started Aug 01 07:01:49 PM PDT 24
Finished Aug 01 07:01:50 PM PDT 24
Peak memory 206172 kb
Host smart-e52af41b-6e79-4954-9834-42fa0103a25e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320606071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3320606071
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.4203915908
Short name T955
Test name
Test status
Simulation time 811018776 ps
CPU time 1.96 seconds
Started Aug 01 07:01:47 PM PDT 24
Finished Aug 01 07:01:49 PM PDT 24
Peak memory 206116 kb
Host smart-699ef093-32d6-4412-9571-f8d879e1c64c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203915908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.4203915908
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.985909199
Short name T107
Test name
Test status
Simulation time 133503057 ps
CPU time 1.85 seconds
Started Aug 01 07:01:52 PM PDT 24
Finished Aug 01 07:01:54 PM PDT 24
Peak memory 214576 kb
Host smart-8e303bcb-1106-43e3-9ca4-aa904b1d3b20
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985909199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.985909199
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.708428778
Short name T1033
Test name
Test status
Simulation time 246060909 ps
CPU time 8.74 seconds
Started Aug 01 07:01:51 PM PDT 24
Finished Aug 01 07:02:00 PM PDT 24
Peak memory 214564 kb
Host smart-5019b100-0f55-4d20-af63-149e02cb5b46
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708428778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_shadow_reg_errors_with_csr_rw.708428778
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.72089007
Short name T184
Test name
Test status
Simulation time 770298226 ps
CPU time 2.48 seconds
Started Aug 01 07:01:51 PM PDT 24
Finished Aug 01 07:01:54 PM PDT 24
Peak memory 216784 kb
Host smart-a53bdf11-a7d5-4904-b0dd-b1fc8d697ca9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72089007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.72089007
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.736411484
Short name T156
Test name
Test status
Simulation time 108599790 ps
CPU time 3.26 seconds
Started Aug 01 07:01:51 PM PDT 24
Finished Aug 01 07:01:55 PM PDT 24
Peak memory 214428 kb
Host smart-9166c45e-9278-45dd-b2d6-265a52d4911d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736411484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
736411484
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2984728722
Short name T978
Test name
Test status
Simulation time 36491648 ps
CPU time 0.79 seconds
Started Aug 01 07:02:23 PM PDT 24
Finished Aug 01 07:02:24 PM PDT 24
Peak memory 205968 kb
Host smart-a08c4353-5e17-4775-81db-b05f0cd26d3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984728722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2984728722
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1268103161
Short name T913
Test name
Test status
Simulation time 42384171 ps
CPU time 0.71 seconds
Started Aug 01 07:02:14 PM PDT 24
Finished Aug 01 07:02:15 PM PDT 24
Peak memory 205928 kb
Host smart-722a2a19-01e6-4cf5-a0ae-deeef4c18461
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268103161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1268103161
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2117785423
Short name T1052
Test name
Test status
Simulation time 27969492 ps
CPU time 0.7 seconds
Started Aug 01 07:02:19 PM PDT 24
Finished Aug 01 07:02:20 PM PDT 24
Peak memory 205916 kb
Host smart-69050eca-1e21-4672-92db-9465d4d024b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117785423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2117785423
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3553153511
Short name T1072
Test name
Test status
Simulation time 40170766 ps
CPU time 0.81 seconds
Started Aug 01 07:02:14 PM PDT 24
Finished Aug 01 07:02:15 PM PDT 24
Peak memory 205960 kb
Host smart-97c2555f-f8f5-481c-a005-7eaedf3318a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553153511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3553153511
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3644927450
Short name T937
Test name
Test status
Simulation time 85716942 ps
CPU time 0.73 seconds
Started Aug 01 07:02:19 PM PDT 24
Finished Aug 01 07:02:20 PM PDT 24
Peak memory 205952 kb
Host smart-d6bc087f-0281-43ba-b608-3dc6c8593e1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644927450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3644927450
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.351480590
Short name T1020
Test name
Test status
Simulation time 14711992 ps
CPU time 0.87 seconds
Started Aug 01 07:02:17 PM PDT 24
Finished Aug 01 07:02:18 PM PDT 24
Peak memory 206064 kb
Host smart-8087f20b-7ec3-4072-89af-b02e0d9bd3d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351480590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.351480590
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.824884062
Short name T1014
Test name
Test status
Simulation time 182212292 ps
CPU time 0.9 seconds
Started Aug 01 07:02:15 PM PDT 24
Finished Aug 01 07:02:16 PM PDT 24
Peak memory 205932 kb
Host smart-3da5c193-4462-42b9-8319-95db6e7a15b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824884062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.824884062
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.771756400
Short name T943
Test name
Test status
Simulation time 31562827 ps
CPU time 0.75 seconds
Started Aug 01 07:02:17 PM PDT 24
Finished Aug 01 07:02:18 PM PDT 24
Peak memory 205936 kb
Host smart-51257bd9-03a8-493f-83b7-c4e3d21a34e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771756400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.771756400
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3407744152
Short name T1035
Test name
Test status
Simulation time 8857872 ps
CPU time 0.81 seconds
Started Aug 01 07:02:15 PM PDT 24
Finished Aug 01 07:02:16 PM PDT 24
Peak memory 205992 kb
Host smart-80693adb-f11b-46f7-99f7-95feca33545f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407744152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3407744152
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3240330649
Short name T1009
Test name
Test status
Simulation time 12961293 ps
CPU time 0.74 seconds
Started Aug 01 07:02:16 PM PDT 24
Finished Aug 01 07:02:16 PM PDT 24
Peak memory 205836 kb
Host smart-13138790-22ab-4405-aeaf-cf3490ebaf85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240330649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3240330649
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1673785112
Short name T972
Test name
Test status
Simulation time 67317525 ps
CPU time 5.01 seconds
Started Aug 01 07:01:49 PM PDT 24
Finished Aug 01 07:01:54 PM PDT 24
Peak memory 206116 kb
Host smart-7d0ce319-73aa-4114-8112-d415d9688ac5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673785112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
673785112
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2591198141
Short name T940
Test name
Test status
Simulation time 275380601 ps
CPU time 14.18 seconds
Started Aug 01 07:01:50 PM PDT 24
Finished Aug 01 07:02:05 PM PDT 24
Peak memory 206092 kb
Host smart-412768a9-541e-442d-9c25-2b8eb4f53042
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591198141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
591198141
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1098906782
Short name T919
Test name
Test status
Simulation time 14542003 ps
CPU time 0.99 seconds
Started Aug 01 07:01:49 PM PDT 24
Finished Aug 01 07:01:50 PM PDT 24
Peak memory 205992 kb
Host smart-19dc0270-9561-4cda-bbb2-1e63d7ac4f02
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098906782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
098906782
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2657823388
Short name T999
Test name
Test status
Simulation time 62379114 ps
CPU time 1.23 seconds
Started Aug 01 07:01:49 PM PDT 24
Finished Aug 01 07:01:51 PM PDT 24
Peak memory 206336 kb
Host smart-a54768b1-fe3e-4270-a192-4d528626dee4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657823388 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2657823388
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.303984112
Short name T947
Test name
Test status
Simulation time 31799655 ps
CPU time 0.96 seconds
Started Aug 01 07:01:48 PM PDT 24
Finished Aug 01 07:01:49 PM PDT 24
Peak memory 206028 kb
Host smart-fec68879-fa73-4552-af15-bfb98582826d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303984112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.303984112
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3550154890
Short name T1037
Test name
Test status
Simulation time 14826941 ps
CPU time 0.9 seconds
Started Aug 01 07:01:55 PM PDT 24
Finished Aug 01 07:01:56 PM PDT 24
Peak memory 206124 kb
Host smart-5426e612-63c8-4201-ad29-26ee9aa958ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550154890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3550154890
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1623061044
Short name T1050
Test name
Test status
Simulation time 64084863 ps
CPU time 2.12 seconds
Started Aug 01 07:01:51 PM PDT 24
Finished Aug 01 07:01:53 PM PDT 24
Peak memory 206164 kb
Host smart-c003eb49-79bb-49c9-8f86-93263954cc68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623061044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1623061044
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1107416492
Short name T936
Test name
Test status
Simulation time 60043245 ps
CPU time 2.25 seconds
Started Aug 01 07:01:49 PM PDT 24
Finished Aug 01 07:01:52 PM PDT 24
Peak memory 214544 kb
Host smart-0c2c7f99-c4ee-4a44-a8a5-9fadf8e74d83
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107416492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1107416492
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.512663812
Short name T1018
Test name
Test status
Simulation time 420264686 ps
CPU time 6.47 seconds
Started Aug 01 07:01:46 PM PDT 24
Finished Aug 01 07:01:53 PM PDT 24
Peak memory 214672 kb
Host smart-dfa94f99-dcf5-4308-898a-9d2cf2361eb3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512663812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.512663812
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1278076381
Short name T1057
Test name
Test status
Simulation time 65998116 ps
CPU time 2.62 seconds
Started Aug 01 07:01:49 PM PDT 24
Finished Aug 01 07:01:52 PM PDT 24
Peak memory 214444 kb
Host smart-319fb176-0587-49e6-8f7d-c8e67b542f52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278076381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1278076381
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3868540898
Short name T976
Test name
Test status
Simulation time 2354413120 ps
CPU time 4.11 seconds
Started Aug 01 07:01:48 PM PDT 24
Finished Aug 01 07:01:52 PM PDT 24
Peak memory 215868 kb
Host smart-c89db652-a6b6-44a5-9788-1159b4964922
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868540898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3868540898
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3414124264
Short name T973
Test name
Test status
Simulation time 33980518 ps
CPU time 0.83 seconds
Started Aug 01 07:02:17 PM PDT 24
Finished Aug 01 07:02:18 PM PDT 24
Peak memory 205768 kb
Host smart-795ffa55-7926-4c8e-9e1d-18f7bc51fd1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414124264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3414124264
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1891163557
Short name T1036
Test name
Test status
Simulation time 25849363 ps
CPU time 0.93 seconds
Started Aug 01 07:02:19 PM PDT 24
Finished Aug 01 07:02:20 PM PDT 24
Peak memory 205884 kb
Host smart-b2a319b9-7037-4912-b9f2-cf1739abf49a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891163557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1891163557
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1688766139
Short name T1006
Test name
Test status
Simulation time 19549062 ps
CPU time 0.74 seconds
Started Aug 01 07:02:18 PM PDT 24
Finished Aug 01 07:02:19 PM PDT 24
Peak memory 205944 kb
Host smart-19188dd1-0ac6-4c32-a328-de66dfb4b298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688766139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1688766139
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1916987688
Short name T970
Test name
Test status
Simulation time 13171028 ps
CPU time 0.77 seconds
Started Aug 01 07:02:18 PM PDT 24
Finished Aug 01 07:02:19 PM PDT 24
Peak memory 205944 kb
Host smart-a66e389e-1578-4aa5-8168-cb01aa05265e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916987688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1916987688
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2299009999
Short name T966
Test name
Test status
Simulation time 13023204 ps
CPU time 0.84 seconds
Started Aug 01 07:02:15 PM PDT 24
Finished Aug 01 07:02:16 PM PDT 24
Peak memory 205908 kb
Host smart-2bdf7d09-df3f-4296-965f-af7955506e2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299009999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2299009999
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2346814034
Short name T991
Test name
Test status
Simulation time 50540771 ps
CPU time 0.79 seconds
Started Aug 01 07:02:19 PM PDT 24
Finished Aug 01 07:02:20 PM PDT 24
Peak memory 205960 kb
Host smart-80b79a52-872a-4dc0-b11d-af942768e1cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346814034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2346814034
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3956260327
Short name T995
Test name
Test status
Simulation time 8709505 ps
CPU time 0.81 seconds
Started Aug 01 07:02:17 PM PDT 24
Finished Aug 01 07:02:18 PM PDT 24
Peak memory 205772 kb
Host smart-1b860221-babc-4af9-b452-c5fbe8a8ae4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956260327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3956260327
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3013891279
Short name T912
Test name
Test status
Simulation time 10956900 ps
CPU time 0.73 seconds
Started Aug 01 07:02:28 PM PDT 24
Finished Aug 01 07:02:29 PM PDT 24
Peak memory 205832 kb
Host smart-e33e49bb-5c01-4a22-b7d4-600e4988d22f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013891279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3013891279
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1518875410
Short name T968
Test name
Test status
Simulation time 116525499 ps
CPU time 0.89 seconds
Started Aug 01 07:02:33 PM PDT 24
Finished Aug 01 07:02:34 PM PDT 24
Peak memory 205952 kb
Host smart-5166c9fb-8c00-42f7-b1e1-91d1c8e83b74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518875410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1518875410
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2333738579
Short name T1067
Test name
Test status
Simulation time 12940858 ps
CPU time 0.72 seconds
Started Aug 01 07:02:27 PM PDT 24
Finished Aug 01 07:02:28 PM PDT 24
Peak memory 205912 kb
Host smart-3496e780-6c37-4136-b35f-fe00134f39fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333738579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2333738579
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2687901037
Short name T924
Test name
Test status
Simulation time 31698112 ps
CPU time 2.12 seconds
Started Aug 01 07:01:50 PM PDT 24
Finished Aug 01 07:01:52 PM PDT 24
Peak memory 214408 kb
Host smart-c90dafb0-b259-4efe-99a8-08832fca319b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687901037 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2687901037
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3573332634
Short name T931
Test name
Test status
Simulation time 48960072 ps
CPU time 1.02 seconds
Started Aug 01 07:01:50 PM PDT 24
Finished Aug 01 07:01:51 PM PDT 24
Peak memory 205924 kb
Host smart-3a96c69f-3148-4a18-a760-aa9b7b5f0eeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573332634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3573332634
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.4273195339
Short name T1025
Test name
Test status
Simulation time 72382838 ps
CPU time 0.81 seconds
Started Aug 01 07:01:54 PM PDT 24
Finished Aug 01 07:01:55 PM PDT 24
Peak memory 205896 kb
Host smart-9e012f47-e43a-496d-9475-10d6e81e9cd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273195339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.4273195339
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.819601416
Short name T1000
Test name
Test status
Simulation time 356601787 ps
CPU time 3.57 seconds
Started Aug 01 07:01:52 PM PDT 24
Finished Aug 01 07:01:56 PM PDT 24
Peak memory 206096 kb
Host smart-1f025266-44d6-44a9-ba65-671ff364f493
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819601416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.819601416
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.608216538
Short name T1049
Test name
Test status
Simulation time 451755214 ps
CPU time 7.97 seconds
Started Aug 01 07:01:52 PM PDT 24
Finished Aug 01 07:02:00 PM PDT 24
Peak memory 214680 kb
Host smart-9b790025-6984-490c-b601-609358ca741e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608216538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.608216538
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.880814878
Short name T1062
Test name
Test status
Simulation time 229348220 ps
CPU time 2.49 seconds
Started Aug 01 07:01:51 PM PDT 24
Finished Aug 01 07:01:53 PM PDT 24
Peak memory 217460 kb
Host smart-e0facc20-8c10-454d-8350-9219887121d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880814878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.880814878
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.4253586294
Short name T953
Test name
Test status
Simulation time 70145950 ps
CPU time 1.47 seconds
Started Aug 01 07:01:52 PM PDT 24
Finished Aug 01 07:01:54 PM PDT 24
Peak memory 214300 kb
Host smart-b4464d2d-b875-432c-b59f-cf64fbd45318
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253586294 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.4253586294
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.672970589
Short name T998
Test name
Test status
Simulation time 25415979 ps
CPU time 0.87 seconds
Started Aug 01 07:01:49 PM PDT 24
Finished Aug 01 07:01:50 PM PDT 24
Peak memory 205992 kb
Host smart-6bf0961e-dcd9-4a69-abf6-ae2a031c717e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672970589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.672970589
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3830389774
Short name T989
Test name
Test status
Simulation time 138175133 ps
CPU time 0.75 seconds
Started Aug 01 07:01:52 PM PDT 24
Finished Aug 01 07:01:53 PM PDT 24
Peak memory 205860 kb
Host smart-9c0b7a55-f858-4134-b337-748396e57685
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830389774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3830389774
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1422619449
Short name T130
Test name
Test status
Simulation time 145568119 ps
CPU time 3.39 seconds
Started Aug 01 07:01:51 PM PDT 24
Finished Aug 01 07:01:54 PM PDT 24
Peak memory 206156 kb
Host smart-bc4f9b4a-24c6-4d5b-9cc1-c4dd97974d8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422619449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1422619449
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1368161118
Short name T1022
Test name
Test status
Simulation time 690529859 ps
CPU time 4.95 seconds
Started Aug 01 07:01:52 PM PDT 24
Finished Aug 01 07:01:57 PM PDT 24
Peak memory 219820 kb
Host smart-1cf6fefd-2977-4522-bff4-aaff5ad2e9c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368161118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1368161118
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2219101605
Short name T938
Test name
Test status
Simulation time 357441040 ps
CPU time 9.21 seconds
Started Aug 01 07:01:52 PM PDT 24
Finished Aug 01 07:02:01 PM PDT 24
Peak memory 214604 kb
Host smart-4fa8fcd6-f59a-4b48-9647-dbcefb3ebe5a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219101605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2219101605
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.860268575
Short name T922
Test name
Test status
Simulation time 91567347 ps
CPU time 2.22 seconds
Started Aug 01 07:01:48 PM PDT 24
Finished Aug 01 07:01:50 PM PDT 24
Peak memory 214532 kb
Host smart-53c9ba52-459f-4c0c-b114-273b4a710b5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860268575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.860268575
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3689084116
Short name T171
Test name
Test status
Simulation time 274408067 ps
CPU time 7.05 seconds
Started Aug 01 07:01:52 PM PDT 24
Finished Aug 01 07:01:59 PM PDT 24
Peak memory 216696 kb
Host smart-0a9b15b2-9807-49d7-bad5-2b2927c4718a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689084116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3689084116
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3301034722
Short name T975
Test name
Test status
Simulation time 28550057 ps
CPU time 1.36 seconds
Started Aug 01 07:02:07 PM PDT 24
Finished Aug 01 07:02:08 PM PDT 24
Peak memory 206200 kb
Host smart-05892ec0-f647-43f8-90ca-2fb20453537e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301034722 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3301034722
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1003738775
Short name T1024
Test name
Test status
Simulation time 49567260 ps
CPU time 1.18 seconds
Started Aug 01 07:02:01 PM PDT 24
Finished Aug 01 07:02:03 PM PDT 24
Peak memory 206048 kb
Host smart-0d70ff60-2555-4187-adef-3daac95c2121
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003738775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1003738775
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3294130840
Short name T1007
Test name
Test status
Simulation time 12488723 ps
CPU time 0.73 seconds
Started Aug 01 07:02:06 PM PDT 24
Finished Aug 01 07:02:07 PM PDT 24
Peak memory 205932 kb
Host smart-0b6bef38-9664-44fe-add9-3cf8db2b9469
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294130840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3294130840
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1325273103
Short name T1001
Test name
Test status
Simulation time 748797395 ps
CPU time 3.52 seconds
Started Aug 01 07:02:07 PM PDT 24
Finished Aug 01 07:02:10 PM PDT 24
Peak memory 206216 kb
Host smart-a1469d73-a678-452b-a488-fcf65d8c855f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325273103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1325273103
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2572692577
Short name T1019
Test name
Test status
Simulation time 175643454 ps
CPU time 1.59 seconds
Started Aug 01 07:01:51 PM PDT 24
Finished Aug 01 07:01:53 PM PDT 24
Peak memory 214668 kb
Host smart-09c9cb45-223e-4b97-87fc-58980dc8a1d6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572692577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2572692577
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.755166288
Short name T950
Test name
Test status
Simulation time 594467349 ps
CPU time 1.7 seconds
Started Aug 01 07:01:51 PM PDT 24
Finished Aug 01 07:01:53 PM PDT 24
Peak memory 216156 kb
Host smart-e7b2093e-edba-4a5a-b7d7-dd64cd50d64b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755166288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.755166288
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.969435956
Short name T161
Test name
Test status
Simulation time 423636928 ps
CPU time 4.61 seconds
Started Aug 01 07:02:06 PM PDT 24
Finished Aug 01 07:02:10 PM PDT 24
Peak memory 214260 kb
Host smart-1f306037-75dd-4cab-b02c-9a691f8f382a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969435956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
969435956
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.529655060
Short name T1051
Test name
Test status
Simulation time 76354531 ps
CPU time 1.57 seconds
Started Aug 01 07:01:59 PM PDT 24
Finished Aug 01 07:02:01 PM PDT 24
Peak memory 214384 kb
Host smart-5cdf05bc-9086-40d3-abf4-f5d2647d014a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529655060 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.529655060
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1339270367
Short name T921
Test name
Test status
Simulation time 17788551 ps
CPU time 1.18 seconds
Started Aug 01 07:02:03 PM PDT 24
Finished Aug 01 07:02:04 PM PDT 24
Peak memory 206160 kb
Host smart-f85b9850-b646-4811-a61d-79eaafc55d7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339270367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1339270367
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2054978107
Short name T916
Test name
Test status
Simulation time 55968997 ps
CPU time 0.72 seconds
Started Aug 01 07:02:10 PM PDT 24
Finished Aug 01 07:02:11 PM PDT 24
Peak memory 205832 kb
Host smart-b0d621f0-15a9-4083-8cab-5c02a05195c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054978107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2054978107
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2743142237
Short name T1076
Test name
Test status
Simulation time 40640346 ps
CPU time 2.14 seconds
Started Aug 01 07:02:00 PM PDT 24
Finished Aug 01 07:02:02 PM PDT 24
Peak memory 206112 kb
Host smart-3d554ab0-8163-44fe-9ab6-107731af30c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743142237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2743142237
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3818995265
Short name T1004
Test name
Test status
Simulation time 262258553 ps
CPU time 1.49 seconds
Started Aug 01 07:01:59 PM PDT 24
Finished Aug 01 07:02:01 PM PDT 24
Peak memory 214736 kb
Host smart-3a93469b-aca2-4306-a0e6-d9b5924ae475
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818995265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3818995265
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.284751041
Short name T132
Test name
Test status
Simulation time 161338469 ps
CPU time 6.14 seconds
Started Aug 01 07:02:00 PM PDT 24
Finished Aug 01 07:02:07 PM PDT 24
Peak memory 214696 kb
Host smart-02938686-a6d4-4422-8edd-921635dc3af5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284751041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.284751041
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.371990068
Short name T993
Test name
Test status
Simulation time 118009827 ps
CPU time 2.76 seconds
Started Aug 01 07:01:59 PM PDT 24
Finished Aug 01 07:02:02 PM PDT 24
Peak memory 217000 kb
Host smart-7c5aba39-9b34-42ee-86d5-2ae562dfcb63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371990068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.371990068
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2036460071
Short name T151
Test name
Test status
Simulation time 178906789 ps
CPU time 3.16 seconds
Started Aug 01 07:02:00 PM PDT 24
Finished Aug 01 07:02:03 PM PDT 24
Peak memory 214456 kb
Host smart-a0d924e7-f8ca-4744-a368-610c10460f8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036460071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2036460071
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1962688246
Short name T397
Test name
Test status
Simulation time 377876738 ps
CPU time 2.1 seconds
Started Aug 01 07:02:00 PM PDT 24
Finished Aug 01 07:02:02 PM PDT 24
Peak memory 206212 kb
Host smart-4bc925a9-87e5-426e-b6be-8f18bab5d67f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962688246 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1962688246
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1093056775
Short name T1027
Test name
Test status
Simulation time 102570299 ps
CPU time 0.89 seconds
Started Aug 01 07:02:04 PM PDT 24
Finished Aug 01 07:02:05 PM PDT 24
Peak memory 205988 kb
Host smart-721aad04-c0e3-4357-9adb-b75e83330fec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093056775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1093056775
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2080599173
Short name T1028
Test name
Test status
Simulation time 13876420 ps
CPU time 0.84 seconds
Started Aug 01 07:02:00 PM PDT 24
Finished Aug 01 07:02:01 PM PDT 24
Peak memory 205880 kb
Host smart-c3a6de83-9975-4a3e-862f-7a01cc20be7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080599173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2080599173
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2990527500
Short name T994
Test name
Test status
Simulation time 92459243 ps
CPU time 1.5 seconds
Started Aug 01 07:02:00 PM PDT 24
Finished Aug 01 07:02:03 PM PDT 24
Peak memory 206092 kb
Host smart-89c27519-7366-4bee-a94b-1efc73e25d6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990527500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.2990527500
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2838996733
Short name T929
Test name
Test status
Simulation time 193777996 ps
CPU time 2.64 seconds
Started Aug 01 07:02:01 PM PDT 24
Finished Aug 01 07:02:04 PM PDT 24
Peak memory 214664 kb
Host smart-8f27bb4c-6e92-4b1e-81d9-118b509a54c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838996733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2838996733
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.4200292715
Short name T1005
Test name
Test status
Simulation time 85475643 ps
CPU time 3.83 seconds
Started Aug 01 07:02:01 PM PDT 24
Finished Aug 01 07:02:05 PM PDT 24
Peak memory 214596 kb
Host smart-63508cc6-3574-444b-b555-8c346a1b375c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200292715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.4200292715
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3843178439
Short name T957
Test name
Test status
Simulation time 200786381 ps
CPU time 2.77 seconds
Started Aug 01 07:02:02 PM PDT 24
Finished Aug 01 07:02:05 PM PDT 24
Peak memory 214444 kb
Host smart-5ea2cec6-6980-41cc-af56-c503d8cb742a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843178439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3843178439
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3264096081
Short name T787
Test name
Test status
Simulation time 11674259 ps
CPU time 0.89 seconds
Started Aug 01 06:59:10 PM PDT 24
Finished Aug 01 06:59:11 PM PDT 24
Peak memory 205952 kb
Host smart-8bb72f76-4012-480c-87ed-f95ed4d3aa88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264096081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3264096081
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2749481244
Short name T430
Test name
Test status
Simulation time 121635645 ps
CPU time 2.63 seconds
Started Aug 01 06:59:00 PM PDT 24
Finished Aug 01 06:59:03 PM PDT 24
Peak memory 222448 kb
Host smart-122751c3-44db-4a16-990a-f4f50e7e8702
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2749481244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2749481244
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1142464737
Short name T824
Test name
Test status
Simulation time 62729271 ps
CPU time 3.61 seconds
Started Aug 01 06:59:07 PM PDT 24
Finished Aug 01 06:59:11 PM PDT 24
Peak memory 214496 kb
Host smart-eb275f8a-4bea-44d1-9c5a-711f157fbe03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142464737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1142464737
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1815169872
Short name T733
Test name
Test status
Simulation time 35572484 ps
CPU time 2.22 seconds
Started Aug 01 06:59:03 PM PDT 24
Finished Aug 01 06:59:06 PM PDT 24
Peak memory 219888 kb
Host smart-5b2e06a6-b9b8-4b33-8348-d6a38f1de13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815169872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1815169872
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3897995487
Short name T383
Test name
Test status
Simulation time 289278845 ps
CPU time 3.71 seconds
Started Aug 01 06:59:04 PM PDT 24
Finished Aug 01 06:59:08 PM PDT 24
Peak memory 209368 kb
Host smart-5bd12a9f-732c-43b2-86fa-fa7a5c1c0c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897995487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3897995487
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3892541557
Short name T357
Test name
Test status
Simulation time 454872972 ps
CPU time 4.43 seconds
Started Aug 01 06:59:01 PM PDT 24
Finished Aug 01 06:59:05 PM PDT 24
Peak memory 222316 kb
Host smart-038d6dfe-3155-48e2-b643-30b6fa23b08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892541557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3892541557
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2828548607
Short name T529
Test name
Test status
Simulation time 159627576 ps
CPU time 3.76 seconds
Started Aug 01 06:58:58 PM PDT 24
Finished Aug 01 06:59:02 PM PDT 24
Peak memory 219908 kb
Host smart-e172c866-3793-4839-8963-9f608ee76589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828548607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2828548607
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.171325301
Short name T736
Test name
Test status
Simulation time 126294495 ps
CPU time 3.43 seconds
Started Aug 01 06:59:00 PM PDT 24
Finished Aug 01 06:59:03 PM PDT 24
Peak memory 218504 kb
Host smart-73706b3a-c327-46d6-8945-e3763ba5fc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171325301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.171325301
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3252184699
Short name T9
Test name
Test status
Simulation time 1124097330 ps
CPU time 7.3 seconds
Started Aug 01 06:59:07 PM PDT 24
Finished Aug 01 06:59:15 PM PDT 24
Peak memory 229624 kb
Host smart-2d556328-938c-4d9b-b595-0fe9149eb326
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252184699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3252184699
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2393678535
Short name T252
Test name
Test status
Simulation time 129096110 ps
CPU time 2.54 seconds
Started Aug 01 06:58:59 PM PDT 24
Finished Aug 01 06:59:02 PM PDT 24
Peak memory 208476 kb
Host smart-f6288ad8-64cb-4c99-98e7-7e32efee201f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393678535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2393678535
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.4059945626
Short name T579
Test name
Test status
Simulation time 5635702537 ps
CPU time 14.9 seconds
Started Aug 01 06:58:59 PM PDT 24
Finished Aug 01 06:59:14 PM PDT 24
Peak memory 209048 kb
Host smart-f57aaf58-8702-4801-a902-01fa41210112
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059945626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.4059945626
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2395658613
Short name T506
Test name
Test status
Simulation time 881737248 ps
CPU time 6.33 seconds
Started Aug 01 06:59:01 PM PDT 24
Finished Aug 01 06:59:08 PM PDT 24
Peak memory 207988 kb
Host smart-349de99b-9d3e-41f3-a15c-23ad31d8fa0f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395658613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2395658613
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2943759971
Short name T251
Test name
Test status
Simulation time 79690475 ps
CPU time 3.6 seconds
Started Aug 01 06:59:08 PM PDT 24
Finished Aug 01 06:59:12 PM PDT 24
Peak memory 214264 kb
Host smart-91b7be00-857e-4c73-8c2b-31780de145da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943759971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2943759971
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2303144217
Short name T541
Test name
Test status
Simulation time 29131238 ps
CPU time 1.84 seconds
Started Aug 01 06:58:59 PM PDT 24
Finished Aug 01 06:59:01 PM PDT 24
Peak memory 206780 kb
Host smart-420edc28-e849-43a5-855e-c9fdc412f68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303144217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2303144217
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1809349841
Short name T468
Test name
Test status
Simulation time 1568923708 ps
CPU time 16.05 seconds
Started Aug 01 06:59:00 PM PDT 24
Finished Aug 01 06:59:16 PM PDT 24
Peak memory 210632 kb
Host smart-b004a180-63bf-4d35-b8e7-f1eb72e38413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809349841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1809349841
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.671599090
Short name T104
Test name
Test status
Simulation time 80171129 ps
CPU time 2.39 seconds
Started Aug 01 06:59:10 PM PDT 24
Finished Aug 01 06:59:12 PM PDT 24
Peak memory 210104 kb
Host smart-0f387b15-54ed-45c7-a907-ce4990e64f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671599090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.671599090
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1029305293
Short name T866
Test name
Test status
Simulation time 43563465 ps
CPU time 0.79 seconds
Started Aug 01 06:59:09 PM PDT 24
Finished Aug 01 06:59:10 PM PDT 24
Peak memory 205936 kb
Host smart-6e599784-f0bd-4045-bf99-fd6ad1c897df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029305293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1029305293
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1811140236
Short name T249
Test name
Test status
Simulation time 180353406 ps
CPU time 9.58 seconds
Started Aug 01 06:59:08 PM PDT 24
Finished Aug 01 06:59:18 PM PDT 24
Peak memory 214328 kb
Host smart-f93f2ab9-4620-4711-8259-10c729665a3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1811140236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1811140236
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.441485000
Short name T789
Test name
Test status
Simulation time 87735916 ps
CPU time 2.46 seconds
Started Aug 01 06:59:07 PM PDT 24
Finished Aug 01 06:59:10 PM PDT 24
Peak memory 218384 kb
Host smart-cc3b04b0-d7a3-4113-89e7-083359453909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441485000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.441485000
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.499748822
Short name T747
Test name
Test status
Simulation time 4837596252 ps
CPU time 45.84 seconds
Started Aug 01 06:59:08 PM PDT 24
Finished Aug 01 06:59:55 PM PDT 24
Peak memory 222476 kb
Host smart-8e68f31e-1d48-47ba-bb27-52c6e4c2c9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499748822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.499748822
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1357235061
Short name T533
Test name
Test status
Simulation time 255999587 ps
CPU time 3.46 seconds
Started Aug 01 06:59:08 PM PDT 24
Finished Aug 01 06:59:12 PM PDT 24
Peak memory 214220 kb
Host smart-500468b7-c6a5-4a6b-9fdd-786817736a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357235061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1357235061
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2179976497
Short name T209
Test name
Test status
Simulation time 184875683 ps
CPU time 3.06 seconds
Started Aug 01 06:59:09 PM PDT 24
Finished Aug 01 06:59:12 PM PDT 24
Peak memory 214420 kb
Host smart-c76514db-02b9-4fe5-9892-33d0c0bff562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179976497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2179976497
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1235646216
Short name T726
Test name
Test status
Simulation time 462372830 ps
CPU time 10.43 seconds
Started Aug 01 06:59:11 PM PDT 24
Finished Aug 01 06:59:22 PM PDT 24
Peak memory 208200 kb
Host smart-183630e2-1154-40ee-8de0-cdfa5145c843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235646216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1235646216
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.570605980
Short name T534
Test name
Test status
Simulation time 40100120 ps
CPU time 1.75 seconds
Started Aug 01 06:59:10 PM PDT 24
Finished Aug 01 06:59:12 PM PDT 24
Peak memory 206892 kb
Host smart-5873687a-ea8e-4684-9e78-749b171cb2d9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570605980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.570605980
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3471685377
Short name T753
Test name
Test status
Simulation time 177898741 ps
CPU time 3.91 seconds
Started Aug 01 06:59:09 PM PDT 24
Finished Aug 01 06:59:13 PM PDT 24
Peak memory 208468 kb
Host smart-fb5abb26-4cb9-46e2-9af8-eade7e890f78
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471685377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3471685377
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3495568822
Short name T279
Test name
Test status
Simulation time 102212864 ps
CPU time 2.49 seconds
Started Aug 01 06:59:10 PM PDT 24
Finished Aug 01 06:59:13 PM PDT 24
Peak memory 209624 kb
Host smart-b2331c19-c4ca-4bc3-8810-0cd6a69bcdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495568822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3495568822
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.157073459
Short name T855
Test name
Test status
Simulation time 70827225 ps
CPU time 2.56 seconds
Started Aug 01 06:59:07 PM PDT 24
Finished Aug 01 06:59:10 PM PDT 24
Peak memory 207012 kb
Host smart-3e625cf9-882c-48d6-9059-5bcaf9f519ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157073459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.157073459
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.174366416
Short name T342
Test name
Test status
Simulation time 7832140906 ps
CPU time 50.69 seconds
Started Aug 01 06:59:10 PM PDT 24
Finished Aug 01 07:00:00 PM PDT 24
Peak memory 220024 kb
Host smart-c58b8630-aec7-4f58-b2fd-86fa0178eaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174366416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.174366416
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3082481638
Short name T389
Test name
Test status
Simulation time 166221648 ps
CPU time 4.64 seconds
Started Aug 01 06:59:08 PM PDT 24
Finished Aug 01 06:59:13 PM PDT 24
Peak memory 210468 kb
Host smart-6a527a05-2286-4e1b-93ad-d707f20a1f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082481638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3082481638
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.4016067429
Short name T857
Test name
Test status
Simulation time 19677412 ps
CPU time 0.85 seconds
Started Aug 01 06:59:41 PM PDT 24
Finished Aug 01 06:59:42 PM PDT 24
Peak memory 205864 kb
Host smart-18463f1c-2224-4f3a-af82-fee5f5420a96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016067429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.4016067429
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1330492015
Short name T490
Test name
Test status
Simulation time 110057348 ps
CPU time 4.44 seconds
Started Aug 01 06:59:39 PM PDT 24
Finished Aug 01 06:59:44 PM PDT 24
Peak memory 214248 kb
Host smart-1462515f-5eaf-48c8-8425-48640df333b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330492015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1330492015
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3897652924
Short name T83
Test name
Test status
Simulation time 615990058 ps
CPU time 14.72 seconds
Started Aug 01 06:59:33 PM PDT 24
Finished Aug 01 06:59:48 PM PDT 24
Peak memory 222428 kb
Host smart-50f51008-78ac-4b2e-8b68-0e087e8a022a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897652924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3897652924
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1549057119
Short name T720
Test name
Test status
Simulation time 435814294 ps
CPU time 4.65 seconds
Started Aug 01 06:59:37 PM PDT 24
Finished Aug 01 06:59:42 PM PDT 24
Peak memory 222452 kb
Host smart-7f9b1127-1011-444e-baf2-753c88d56977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549057119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1549057119
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_random.3701587495
Short name T458
Test name
Test status
Simulation time 503735072 ps
CPU time 5.57 seconds
Started Aug 01 06:59:39 PM PDT 24
Finished Aug 01 06:59:44 PM PDT 24
Peak memory 218156 kb
Host smart-86d556b9-606b-47cc-b299-b980d5076db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701587495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3701587495
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2966445207
Short name T678
Test name
Test status
Simulation time 324816911 ps
CPU time 6.14 seconds
Started Aug 01 06:59:37 PM PDT 24
Finished Aug 01 06:59:43 PM PDT 24
Peak memory 206976 kb
Host smart-142911ee-6f70-4ba0-bb67-f0625fbd1b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966445207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2966445207
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.124177016
Short name T573
Test name
Test status
Simulation time 46627607 ps
CPU time 2.52 seconds
Started Aug 01 06:59:38 PM PDT 24
Finished Aug 01 06:59:40 PM PDT 24
Peak memory 206532 kb
Host smart-43d63365-a443-491b-a843-33cb04b75568
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124177016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.124177016
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1263163354
Short name T476
Test name
Test status
Simulation time 241150695 ps
CPU time 4.88 seconds
Started Aug 01 06:59:37 PM PDT 24
Finished Aug 01 06:59:42 PM PDT 24
Peak memory 206976 kb
Host smart-2c2ab4f1-5b8d-4052-90ce-64f69d9b45b3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263163354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1263163354
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.1749434209
Short name T850
Test name
Test status
Simulation time 124526605 ps
CPU time 2.55 seconds
Started Aug 01 06:59:41 PM PDT 24
Finished Aug 01 06:59:44 PM PDT 24
Peak memory 209480 kb
Host smart-ee08095e-4727-4a3c-a488-abc7ed6b00d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749434209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1749434209
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.904946437
Short name T412
Test name
Test status
Simulation time 71745005 ps
CPU time 2.35 seconds
Started Aug 01 06:59:39 PM PDT 24
Finished Aug 01 06:59:41 PM PDT 24
Peak memory 208228 kb
Host smart-9406f319-4a18-4715-afbe-ab6f5919433e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904946437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.904946437
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.368065761
Short name T475
Test name
Test status
Simulation time 22775688 ps
CPU time 0.88 seconds
Started Aug 01 06:59:47 PM PDT 24
Finished Aug 01 06:59:48 PM PDT 24
Peak memory 205960 kb
Host smart-66895091-f4ff-4b9c-8656-f59d760630b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368065761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.368065761
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2367552455
Short name T765
Test name
Test status
Simulation time 47059736 ps
CPU time 2.41 seconds
Started Aug 01 06:59:44 PM PDT 24
Finished Aug 01 06:59:46 PM PDT 24
Peak memory 209904 kb
Host smart-c6e9c55d-ecff-4b78-8827-e2591ab954e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367552455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2367552455
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1691102667
Short name T242
Test name
Test status
Simulation time 85357259 ps
CPU time 2.98 seconds
Started Aug 01 06:59:46 PM PDT 24
Finished Aug 01 06:59:49 PM PDT 24
Peak memory 214304 kb
Host smart-2c4c7f25-2952-41df-b6bd-4ca34d2e971f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691102667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1691102667
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3798915198
Short name T287
Test name
Test status
Simulation time 43502841 ps
CPU time 2.34 seconds
Started Aug 01 06:59:43 PM PDT 24
Finished Aug 01 06:59:46 PM PDT 24
Peak memory 222304 kb
Host smart-d1ef4018-de23-4280-9167-d1b90a3eab7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798915198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3798915198
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.4049662595
Short name T623
Test name
Test status
Simulation time 202609499 ps
CPU time 8.62 seconds
Started Aug 01 06:59:46 PM PDT 24
Finished Aug 01 06:59:55 PM PDT 24
Peak memory 220704 kb
Host smart-3fddd002-a03c-43ba-8392-f3b98b2002bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049662595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.4049662595
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.2772222974
Short name T255
Test name
Test status
Simulation time 443184270 ps
CPU time 6.57 seconds
Started Aug 01 06:59:48 PM PDT 24
Finished Aug 01 06:59:55 PM PDT 24
Peak memory 208096 kb
Host smart-fabb6180-10e8-48d1-a884-4fd875fd8ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772222974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2772222974
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2089238705
Short name T637
Test name
Test status
Simulation time 338701902 ps
CPU time 4.73 seconds
Started Aug 01 06:59:36 PM PDT 24
Finished Aug 01 06:59:41 PM PDT 24
Peak memory 207036 kb
Host smart-b0bd9a3f-53b4-4b07-bfa2-8a5f31be386e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089238705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2089238705
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2493371430
Short name T889
Test name
Test status
Simulation time 166053596 ps
CPU time 1.83 seconds
Started Aug 01 06:59:53 PM PDT 24
Finished Aug 01 06:59:55 PM PDT 24
Peak memory 207020 kb
Host smart-69ad860f-c21e-4038-aa82-82b6e8e796c6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493371430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2493371430
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.825758649
Short name T566
Test name
Test status
Simulation time 142916703 ps
CPU time 4.4 seconds
Started Aug 01 06:59:37 PM PDT 24
Finished Aug 01 06:59:41 PM PDT 24
Peak memory 206824 kb
Host smart-21f2b446-75e6-4e91-9556-83763f95e8a4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825758649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.825758649
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1707067015
Short name T465
Test name
Test status
Simulation time 123258116 ps
CPU time 2.34 seconds
Started Aug 01 06:59:48 PM PDT 24
Finished Aug 01 06:59:50 PM PDT 24
Peak memory 207660 kb
Host smart-a7e8583a-b097-4bd9-8f1f-2f66808de007
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707067015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1707067015
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1293379006
Short name T545
Test name
Test status
Simulation time 24020669 ps
CPU time 1.83 seconds
Started Aug 01 06:59:43 PM PDT 24
Finished Aug 01 06:59:45 PM PDT 24
Peak memory 214304 kb
Host smart-9b311960-93cb-4bed-adfe-a4e0834f0661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293379006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1293379006
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1682586652
Short name T456
Test name
Test status
Simulation time 74275673 ps
CPU time 3.15 seconds
Started Aug 01 06:59:41 PM PDT 24
Finished Aug 01 06:59:44 PM PDT 24
Peak memory 208660 kb
Host smart-c2b76bf5-5649-4857-baf1-d865ad15829f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682586652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1682586652
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3336896496
Short name T301
Test name
Test status
Simulation time 2269101425 ps
CPU time 65.39 seconds
Started Aug 01 06:59:53 PM PDT 24
Finished Aug 01 07:00:59 PM PDT 24
Peak memory 222528 kb
Host smart-0cb4331d-88d3-4544-90f8-6780e40a0eec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336896496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3336896496
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.436025026
Short name T105
Test name
Test status
Simulation time 1275485234 ps
CPU time 6.54 seconds
Started Aug 01 06:59:48 PM PDT 24
Finished Aug 01 06:59:55 PM PDT 24
Peak memory 222640 kb
Host smart-667aa3f6-d28c-460a-b323-c5949a1b3b48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436025026 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.436025026
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2550000995
Short name T368
Test name
Test status
Simulation time 759982727 ps
CPU time 17.43 seconds
Started Aug 01 06:59:43 PM PDT 24
Finished Aug 01 07:00:00 PM PDT 24
Peak memory 209180 kb
Host smart-2a956d73-31eb-4aef-bdac-9789ff66df77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550000995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2550000995
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.342866229
Short name T894
Test name
Test status
Simulation time 359737932 ps
CPU time 2.53 seconds
Started Aug 01 06:59:53 PM PDT 24
Finished Aug 01 06:59:56 PM PDT 24
Peak memory 210172 kb
Host smart-218c0f99-110f-4b87-bd02-f8973aac78a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342866229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.342866229
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.873886065
Short name T819
Test name
Test status
Simulation time 36202570 ps
CPU time 0.73 seconds
Started Aug 01 06:59:50 PM PDT 24
Finished Aug 01 06:59:51 PM PDT 24
Peak memory 205952 kb
Host smart-e39f0848-ca3c-4afc-8635-d9c3df39d956
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873886065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.873886065
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1770039598
Short name T101
Test name
Test status
Simulation time 75256922 ps
CPU time 2.11 seconds
Started Aug 01 06:59:48 PM PDT 24
Finished Aug 01 06:59:50 PM PDT 24
Peak memory 207092 kb
Host smart-f2110ae5-c50f-4739-8e49-03a9d970697f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770039598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1770039598
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1644916620
Short name T218
Test name
Test status
Simulation time 1223868122 ps
CPU time 4.68 seconds
Started Aug 01 06:59:48 PM PDT 24
Finished Aug 01 06:59:52 PM PDT 24
Peak memory 210644 kb
Host smart-a8305345-c746-45d3-98c0-e5b78c121525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644916620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1644916620
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3939142820
Short name T235
Test name
Test status
Simulation time 4217375588 ps
CPU time 26.29 seconds
Started Aug 01 06:59:42 PM PDT 24
Finished Aug 01 07:00:09 PM PDT 24
Peak memory 218360 kb
Host smart-848ec76b-c363-420d-b090-c3e93faca672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939142820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3939142820
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3207336332
Short name T622
Test name
Test status
Simulation time 510318319 ps
CPU time 6.52 seconds
Started Aug 01 06:59:46 PM PDT 24
Finished Aug 01 06:59:53 PM PDT 24
Peak memory 208328 kb
Host smart-e4d20194-44a4-4f6a-87fe-58e609a02af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207336332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3207336332
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.4104878123
Short name T911
Test name
Test status
Simulation time 19989989 ps
CPU time 1.82 seconds
Started Aug 01 06:59:44 PM PDT 24
Finished Aug 01 06:59:46 PM PDT 24
Peak memory 207016 kb
Host smart-42121731-e277-462b-b461-3f89067ed3f6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104878123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.4104878123
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.4101390630
Short name T725
Test name
Test status
Simulation time 51350989 ps
CPU time 2.53 seconds
Started Aug 01 06:59:46 PM PDT 24
Finished Aug 01 06:59:49 PM PDT 24
Peak memory 206856 kb
Host smart-c3ee651a-3e84-4a68-b144-d67ad1690ee4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101390630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.4101390630
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2181613596
Short name T811
Test name
Test status
Simulation time 87535606 ps
CPU time 1.34 seconds
Started Aug 01 06:59:50 PM PDT 24
Finished Aug 01 06:59:52 PM PDT 24
Peak memory 207520 kb
Host smart-be5ca7dc-fdd4-4b9e-87b7-eafe15b9524e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181613596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2181613596
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2531133721
Short name T885
Test name
Test status
Simulation time 682469432 ps
CPU time 3.25 seconds
Started Aug 01 06:59:42 PM PDT 24
Finished Aug 01 06:59:45 PM PDT 24
Peak memory 208732 kb
Host smart-a4bd23fe-5a0c-45da-b22e-8209652d5276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531133721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2531133721
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3774412972
Short name T371
Test name
Test status
Simulation time 821279719 ps
CPU time 28.34 seconds
Started Aug 01 06:59:51 PM PDT 24
Finished Aug 01 07:00:19 PM PDT 24
Peak memory 216516 kb
Host smart-361b340a-1835-4988-a7f2-003bf364fdd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774412972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3774412972
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.125620548
Short name T289
Test name
Test status
Simulation time 3492113830 ps
CPU time 10.17 seconds
Started Aug 01 06:59:50 PM PDT 24
Finished Aug 01 07:00:00 PM PDT 24
Peak memory 220052 kb
Host smart-85ab58fd-d4cb-43f4-ba90-eb51ac81bb56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125620548 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.125620548
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1268512565
Short name T119
Test name
Test status
Simulation time 1899748398 ps
CPU time 4.45 seconds
Started Aug 01 06:59:46 PM PDT 24
Finished Aug 01 06:59:50 PM PDT 24
Peak memory 209240 kb
Host smart-3fef1257-e576-4b50-a9a4-1772916f4f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268512565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1268512565
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1953546216
Short name T563
Test name
Test status
Simulation time 47146774 ps
CPU time 0.76 seconds
Started Aug 01 06:59:56 PM PDT 24
Finished Aug 01 06:59:57 PM PDT 24
Peak memory 205940 kb
Host smart-e2c224ac-d8f4-475e-ba1f-40b47a754dce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953546216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1953546216
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.1029689363
Short name T428
Test name
Test status
Simulation time 364860745 ps
CPU time 6.91 seconds
Started Aug 01 06:59:45 PM PDT 24
Finished Aug 01 06:59:52 PM PDT 24
Peak memory 215372 kb
Host smart-a2afe4e9-7b81-401b-b527-8b7eeb35e313
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1029689363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1029689363
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.875596357
Short name T749
Test name
Test status
Simulation time 163087985 ps
CPU time 3.44 seconds
Started Aug 01 06:59:57 PM PDT 24
Finished Aug 01 07:00:00 PM PDT 24
Peak memory 214476 kb
Host smart-7996b9fb-b24b-4d34-b9e3-1b7a81a368ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875596357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.875596357
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3684020254
Short name T640
Test name
Test status
Simulation time 43666959 ps
CPU time 1.68 seconds
Started Aug 01 06:59:48 PM PDT 24
Finished Aug 01 06:59:50 PM PDT 24
Peak memory 207272 kb
Host smart-706e1a0a-42d9-49a7-8d7a-ce905979e5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684020254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3684020254
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2506741535
Short name T750
Test name
Test status
Simulation time 56721169 ps
CPU time 2.26 seconds
Started Aug 01 06:59:45 PM PDT 24
Finished Aug 01 06:59:47 PM PDT 24
Peak memory 214280 kb
Host smart-27e1ee87-151f-4902-aa74-f8d42a68e7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506741535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2506741535
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2284831277
Short name T237
Test name
Test status
Simulation time 132509766 ps
CPU time 2.76 seconds
Started Aug 01 06:59:42 PM PDT 24
Finished Aug 01 06:59:45 PM PDT 24
Peak memory 214280 kb
Host smart-5cb438da-e79b-4259-aa5a-431c7f404270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284831277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2284831277
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.3271740217
Short name T907
Test name
Test status
Simulation time 106512736 ps
CPU time 3.1 seconds
Started Aug 01 06:59:45 PM PDT 24
Finished Aug 01 06:59:48 PM PDT 24
Peak memory 215848 kb
Host smart-ea38d051-1d86-4394-a592-f4e06329dea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271740217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3271740217
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3905640566
Short name T781
Test name
Test status
Simulation time 624811975 ps
CPU time 5.6 seconds
Started Aug 01 06:59:44 PM PDT 24
Finished Aug 01 06:59:50 PM PDT 24
Peak memory 207344 kb
Host smart-15f96de3-1de7-4f7d-bbe3-2ad763ebd5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905640566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3905640566
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3701682239
Short name T677
Test name
Test status
Simulation time 1726293840 ps
CPU time 33.88 seconds
Started Aug 01 06:59:42 PM PDT 24
Finished Aug 01 07:00:16 PM PDT 24
Peak memory 208516 kb
Host smart-390fd031-a636-47c7-9a9f-b6601b683b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701682239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3701682239
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3338328319
Short name T607
Test name
Test status
Simulation time 103915237 ps
CPU time 3.31 seconds
Started Aug 01 06:59:42 PM PDT 24
Finished Aug 01 06:59:46 PM PDT 24
Peak memory 208588 kb
Host smart-864c744d-3e24-42bf-92df-23e0b3c273ad
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338328319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3338328319
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1962248802
Short name T847
Test name
Test status
Simulation time 321753595 ps
CPU time 7.62 seconds
Started Aug 01 06:59:50 PM PDT 24
Finished Aug 01 06:59:58 PM PDT 24
Peak memory 207952 kb
Host smart-956cd986-5de6-4996-9f27-bd591748224f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962248802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1962248802
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1165165457
Short name T512
Test name
Test status
Simulation time 45822344 ps
CPU time 2.5 seconds
Started Aug 01 06:59:50 PM PDT 24
Finished Aug 01 06:59:53 PM PDT 24
Peak memory 208080 kb
Host smart-c3f8bc11-69dc-49fa-a3eb-04cf11df3e13
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165165457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1165165457
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.1432861669
Short name T292
Test name
Test status
Simulation time 100869785 ps
CPU time 3.18 seconds
Started Aug 01 06:59:55 PM PDT 24
Finished Aug 01 06:59:58 PM PDT 24
Peak memory 208092 kb
Host smart-3a614470-1924-428e-ab03-e9b2b7034f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432861669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1432861669
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.467921660
Short name T667
Test name
Test status
Simulation time 189011290 ps
CPU time 4.41 seconds
Started Aug 01 06:59:44 PM PDT 24
Finished Aug 01 06:59:49 PM PDT 24
Peak memory 208704 kb
Host smart-e39ad988-afaf-47f0-a1d5-cc5c0487c7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467921660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.467921660
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2866195492
Short name T663
Test name
Test status
Simulation time 1914437805 ps
CPU time 58.71 seconds
Started Aug 01 07:00:01 PM PDT 24
Finished Aug 01 07:00:59 PM PDT 24
Peak memory 218376 kb
Host smart-5c88808e-b26c-4980-96fc-fe06f771923a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866195492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2866195492
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.443691100
Short name T699
Test name
Test status
Simulation time 189268203 ps
CPU time 3.16 seconds
Started Aug 01 06:59:43 PM PDT 24
Finished Aug 01 06:59:46 PM PDT 24
Peak memory 207504 kb
Host smart-e6eaf94b-42cb-4b74-961c-116cf36af67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443691100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.443691100
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1671006072
Short name T394
Test name
Test status
Simulation time 32933741 ps
CPU time 1.54 seconds
Started Aug 01 06:59:55 PM PDT 24
Finished Aug 01 06:59:57 PM PDT 24
Peak memory 209716 kb
Host smart-4ca8fa78-4902-4fb5-b3dc-bb370539cb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671006072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1671006072
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.603559169
Short name T829
Test name
Test status
Simulation time 8214087 ps
CPU time 0.91 seconds
Started Aug 01 06:59:56 PM PDT 24
Finished Aug 01 06:59:58 PM PDT 24
Peak memory 205952 kb
Host smart-96d11f93-702e-45c0-a62b-a748bfa7536e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603559169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.603559169
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1126783424
Short name T315
Test name
Test status
Simulation time 963138208 ps
CPU time 7.01 seconds
Started Aug 01 06:59:55 PM PDT 24
Finished Aug 01 07:00:02 PM PDT 24
Peak memory 215132 kb
Host smart-ba791888-31dc-4c02-9315-cb3df74d470d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1126783424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1126783424
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3288600983
Short name T508
Test name
Test status
Simulation time 90136202 ps
CPU time 4.78 seconds
Started Aug 01 06:59:56 PM PDT 24
Finished Aug 01 07:00:01 PM PDT 24
Peak memory 222616 kb
Host smart-b086e145-71f2-4d13-85fa-9826d291129b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288600983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3288600983
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1221423358
Short name T769
Test name
Test status
Simulation time 153179609 ps
CPU time 2.21 seconds
Started Aug 01 06:59:56 PM PDT 24
Finished Aug 01 06:59:59 PM PDT 24
Peak memory 208976 kb
Host smart-906ededd-2559-4f66-a2ab-045b730f7094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221423358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1221423358
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3027129424
Short name T90
Test name
Test status
Simulation time 164908835 ps
CPU time 4.02 seconds
Started Aug 01 06:59:57 PM PDT 24
Finished Aug 01 07:00:01 PM PDT 24
Peak memory 208636 kb
Host smart-49c61849-581d-4eff-8708-1ae7e8d7e4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027129424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3027129424
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.1583135793
Short name T265
Test name
Test status
Simulation time 453969105 ps
CPU time 4.79 seconds
Started Aug 01 06:59:58 PM PDT 24
Finished Aug 01 07:00:03 PM PDT 24
Peak memory 214292 kb
Host smart-90b6f6fe-72f4-4df7-8bb0-de5f156223f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583135793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1583135793
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1086025814
Short name T540
Test name
Test status
Simulation time 452596726 ps
CPU time 3.23 seconds
Started Aug 01 06:59:55 PM PDT 24
Finished Aug 01 06:59:59 PM PDT 24
Peak memory 220332 kb
Host smart-f64a6ab3-65f1-4a96-ba0f-ee9abc38edf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086025814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1086025814
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3398561087
Short name T478
Test name
Test status
Simulation time 318081763 ps
CPU time 5.38 seconds
Started Aug 01 06:59:53 PM PDT 24
Finished Aug 01 06:59:59 PM PDT 24
Peak memory 208200 kb
Host smart-da1f4427-7ae1-4acf-a281-6b4dfb295463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398561087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3398561087
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2582686672
Short name T846
Test name
Test status
Simulation time 284876298 ps
CPU time 3.12 seconds
Started Aug 01 06:59:55 PM PDT 24
Finished Aug 01 06:59:59 PM PDT 24
Peak memory 208528 kb
Host smart-13247ca6-d9d0-47c5-b3ea-af0d2cf9bd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582686672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2582686672
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2491802007
Short name T413
Test name
Test status
Simulation time 223206008 ps
CPU time 5.57 seconds
Started Aug 01 06:59:55 PM PDT 24
Finished Aug 01 07:00:01 PM PDT 24
Peak memory 207908 kb
Host smart-7461e01e-bc20-4dce-9d3b-bbd0e82828d7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491802007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2491802007
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.868079836
Short name T272
Test name
Test status
Simulation time 234764377 ps
CPU time 4.5 seconds
Started Aug 01 06:59:54 PM PDT 24
Finished Aug 01 06:59:58 PM PDT 24
Peak memory 208400 kb
Host smart-b5c5e7a5-49d6-4cd4-8802-8d20a9d71e9e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868079836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.868079836
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.4045199127
Short name T632
Test name
Test status
Simulation time 24604608 ps
CPU time 1.84 seconds
Started Aug 01 06:59:56 PM PDT 24
Finished Aug 01 06:59:58 PM PDT 24
Peak memory 206968 kb
Host smart-b1c722cb-c83b-4fb1-bf04-5fc53c864526
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045199127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.4045199127
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3357426924
Short name T604
Test name
Test status
Simulation time 182933709 ps
CPU time 2.51 seconds
Started Aug 01 06:59:55 PM PDT 24
Finished Aug 01 06:59:58 PM PDT 24
Peak memory 215548 kb
Host smart-a1c275c4-7e91-474b-8dc4-f7c0db81217f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357426924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3357426924
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3762952314
Short name T453
Test name
Test status
Simulation time 306115656 ps
CPU time 3.3 seconds
Started Aug 01 06:59:55 PM PDT 24
Finished Aug 01 06:59:59 PM PDT 24
Peak memory 208316 kb
Host smart-1685d58b-d735-4ab2-99f3-7a1599f882f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762952314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3762952314
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.21249013
Short name T74
Test name
Test status
Simulation time 3422187358 ps
CPU time 29.24 seconds
Started Aug 01 06:59:54 PM PDT 24
Finished Aug 01 07:00:23 PM PDT 24
Peak memory 217404 kb
Host smart-76a15876-8998-4be3-90b0-1509bce8af90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21249013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.21249013
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.4081728239
Short name T532
Test name
Test status
Simulation time 134367751 ps
CPU time 4.2 seconds
Started Aug 01 06:59:57 PM PDT 24
Finished Aug 01 07:00:02 PM PDT 24
Peak memory 208040 kb
Host smart-3d68405d-6de2-4b85-b466-dfe089b715dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081728239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.4081728239
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.883951077
Short name T162
Test name
Test status
Simulation time 48748607 ps
CPU time 1.55 seconds
Started Aug 01 06:59:56 PM PDT 24
Finished Aug 01 06:59:58 PM PDT 24
Peak memory 209808 kb
Host smart-8ab04272-5c7d-42a9-8c5d-8ef6a92a9808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883951077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.883951077
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.562147320
Short name T682
Test name
Test status
Simulation time 43466689 ps
CPU time 0.89 seconds
Started Aug 01 06:59:55 PM PDT 24
Finished Aug 01 06:59:56 PM PDT 24
Peak memory 205972 kb
Host smart-8c68cf97-77ba-4019-ab36-ca56edf3b4e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562147320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.562147320
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3200405723
Short name T422
Test name
Test status
Simulation time 6542152479 ps
CPU time 85.96 seconds
Started Aug 01 06:59:57 PM PDT 24
Finished Aug 01 07:01:23 PM PDT 24
Peak memory 215132 kb
Host smart-bdac6bc9-43f5-4325-bfd4-33aed5a435a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3200405723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3200405723
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3903615279
Short name T639
Test name
Test status
Simulation time 104834653 ps
CPU time 3.2 seconds
Started Aug 01 06:59:59 PM PDT 24
Finished Aug 01 07:00:02 PM PDT 24
Peak memory 218520 kb
Host smart-58d73bdd-48fb-4ad9-b105-962e1ad4b35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903615279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3903615279
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3934076145
Short name T84
Test name
Test status
Simulation time 100161970 ps
CPU time 4.59 seconds
Started Aug 01 06:59:54 PM PDT 24
Finished Aug 01 06:59:59 PM PDT 24
Peak memory 222552 kb
Host smart-bad020b4-5dc0-470b-8e84-e81c5e7d38b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934076145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3934076145
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2819468978
Short name T890
Test name
Test status
Simulation time 205297756 ps
CPU time 2.95 seconds
Started Aug 01 06:59:55 PM PDT 24
Finished Aug 01 06:59:59 PM PDT 24
Peak memory 214572 kb
Host smart-e94b190b-efd3-406c-aea2-31bf67b20f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819468978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2819468978
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.848098037
Short name T210
Test name
Test status
Simulation time 61376396 ps
CPU time 2.93 seconds
Started Aug 01 06:59:54 PM PDT 24
Finished Aug 01 06:59:57 PM PDT 24
Peak memory 222476 kb
Host smart-d7d53150-2acb-4a2e-be63-0947629ea0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848098037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.848098037
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1870151071
Short name T501
Test name
Test status
Simulation time 144823317 ps
CPU time 5.51 seconds
Started Aug 01 06:59:57 PM PDT 24
Finished Aug 01 07:00:03 PM PDT 24
Peak memory 214268 kb
Host smart-db1da585-6004-49a0-a9ae-91d5bf905112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870151071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1870151071
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.4203396638
Short name T878
Test name
Test status
Simulation time 95595367 ps
CPU time 2.63 seconds
Started Aug 01 06:59:54 PM PDT 24
Finished Aug 01 06:59:57 PM PDT 24
Peak memory 208668 kb
Host smart-f37bda93-1d06-4a2e-a94e-7f3980be1c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203396638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.4203396638
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2927877428
Short name T763
Test name
Test status
Simulation time 149140112 ps
CPU time 3.89 seconds
Started Aug 01 06:59:53 PM PDT 24
Finished Aug 01 06:59:57 PM PDT 24
Peak memory 207040 kb
Host smart-1de595c6-16e0-481d-bfa5-345fc77c8aeb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927877428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2927877428
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3796877346
Short name T793
Test name
Test status
Simulation time 107072515 ps
CPU time 3.15 seconds
Started Aug 01 06:59:55 PM PDT 24
Finished Aug 01 06:59:59 PM PDT 24
Peak memory 206932 kb
Host smart-0e903acc-f922-40ab-ad31-3fd8584a647e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796877346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3796877346
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.97484050
Short name T683
Test name
Test status
Simulation time 52503505 ps
CPU time 2.82 seconds
Started Aug 01 06:59:55 PM PDT 24
Finished Aug 01 06:59:59 PM PDT 24
Peak memory 206904 kb
Host smart-a6ea808e-9f35-453e-8e7b-24ff9b44b8d9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97484050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.97484050
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3748554786
Short name T437
Test name
Test status
Simulation time 269981746 ps
CPU time 1.89 seconds
Started Aug 01 06:59:57 PM PDT 24
Finished Aug 01 06:59:59 PM PDT 24
Peak memory 207160 kb
Host smart-e2c3bed6-505c-4617-aa05-d97319fbfce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748554786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3748554786
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3295692278
Short name T199
Test name
Test status
Simulation time 1791091802 ps
CPU time 5.39 seconds
Started Aug 01 06:59:54 PM PDT 24
Finished Aug 01 07:00:00 PM PDT 24
Peak memory 208916 kb
Host smart-cf9d52af-17a3-42f2-acf5-a92d97b7a52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295692278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3295692278
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3904021292
Short name T488
Test name
Test status
Simulation time 47208943 ps
CPU time 3.12 seconds
Started Aug 01 07:00:01 PM PDT 24
Finished Aug 01 07:00:04 PM PDT 24
Peak memory 214324 kb
Host smart-253be93a-3d17-4205-9997-8713babc789a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904021292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3904021292
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1075769619
Short name T535
Test name
Test status
Simulation time 45202582 ps
CPU time 2.11 seconds
Started Aug 01 06:59:55 PM PDT 24
Finished Aug 01 06:59:58 PM PDT 24
Peak memory 209784 kb
Host smart-16b794b0-adeb-48d4-b5db-59e2d520140c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075769619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1075769619
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3216070347
Short name T636
Test name
Test status
Simulation time 16415802 ps
CPU time 0.89 seconds
Started Aug 01 07:00:06 PM PDT 24
Finished Aug 01 07:00:08 PM PDT 24
Peak memory 206072 kb
Host smart-75676427-9f54-4cd7-a627-51c2849f095e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216070347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3216070347
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3523527853
Short name T757
Test name
Test status
Simulation time 54453945 ps
CPU time 2.41 seconds
Started Aug 01 06:59:55 PM PDT 24
Finished Aug 01 06:59:58 PM PDT 24
Peak memory 209336 kb
Host smart-9af04c72-99e6-4d45-9d5a-96ae09056d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523527853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3523527853
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1271811411
Short name T322
Test name
Test status
Simulation time 909606558 ps
CPU time 3.24 seconds
Started Aug 01 06:59:57 PM PDT 24
Finished Aug 01 07:00:00 PM PDT 24
Peak memory 214312 kb
Host smart-d5e8d12a-3fcb-480f-a2db-ab39d1413980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271811411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1271811411
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2317927687
Short name T797
Test name
Test status
Simulation time 31895730 ps
CPU time 2.17 seconds
Started Aug 01 06:59:59 PM PDT 24
Finished Aug 01 07:00:01 PM PDT 24
Peak memory 209360 kb
Host smart-5f562cf6-c936-4879-883c-7ccfab82cf51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317927687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2317927687
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2026335432
Short name T182
Test name
Test status
Simulation time 287308940 ps
CPU time 9.68 seconds
Started Aug 01 06:59:55 PM PDT 24
Finished Aug 01 07:00:06 PM PDT 24
Peak memory 206952 kb
Host smart-483d68a4-9f86-4562-9f0d-7487bd85dd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026335432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2026335432
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1012594416
Short name T908
Test name
Test status
Simulation time 148791415 ps
CPU time 4.49 seconds
Started Aug 01 06:59:54 PM PDT 24
Finished Aug 01 06:59:58 PM PDT 24
Peak memory 206700 kb
Host smart-54813d73-f4c2-417f-8d4d-a7c9725e641d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012594416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1012594416
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3250740767
Short name T452
Test name
Test status
Simulation time 3393129855 ps
CPU time 39.93 seconds
Started Aug 01 06:59:55 PM PDT 24
Finished Aug 01 07:00:35 PM PDT 24
Peak memory 208984 kb
Host smart-3909bf1c-548c-4d33-b184-02fd0c9b7480
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250740767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3250740767
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3710976402
Short name T680
Test name
Test status
Simulation time 147162337 ps
CPU time 2.85 seconds
Started Aug 01 06:59:56 PM PDT 24
Finished Aug 01 06:59:59 PM PDT 24
Peak memory 208904 kb
Host smart-f9dbab15-5d31-49b6-b99c-7836ecca4aab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710976402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3710976402
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3154978725
Short name T517
Test name
Test status
Simulation time 134283852 ps
CPU time 3.8 seconds
Started Aug 01 07:00:00 PM PDT 24
Finished Aug 01 07:00:04 PM PDT 24
Peak memory 208024 kb
Host smart-50376ad3-095d-4e03-b526-da467c89c686
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154978725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3154978725
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.4140188476
Short name T659
Test name
Test status
Simulation time 154856896 ps
CPU time 3.32 seconds
Started Aug 01 06:59:57 PM PDT 24
Finished Aug 01 07:00:00 PM PDT 24
Peak memory 214276 kb
Host smart-2292f2a1-9c3e-4b79-878e-79db07f7a97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140188476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.4140188476
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2094341991
Short name T118
Test name
Test status
Simulation time 129440253 ps
CPU time 2.33 seconds
Started Aug 01 06:59:58 PM PDT 24
Finished Aug 01 07:00:00 PM PDT 24
Peak memory 207276 kb
Host smart-676c0ecd-1be4-4e34-89c6-8b3e391b8eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094341991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2094341991
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.1145140092
Short name T775
Test name
Test status
Simulation time 502769633 ps
CPU time 11.52 seconds
Started Aug 01 07:00:04 PM PDT 24
Finished Aug 01 07:00:19 PM PDT 24
Peak memory 220592 kb
Host smart-e9c33ea6-6db2-4668-bb29-19e0112882cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145140092 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.1145140092
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3324292041
Short name T349
Test name
Test status
Simulation time 88086529 ps
CPU time 3.71 seconds
Started Aug 01 06:59:55 PM PDT 24
Finished Aug 01 06:59:59 PM PDT 24
Peak memory 214328 kb
Host smart-b1e051f1-bccd-490e-bbaf-042794688324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324292041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3324292041
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3996312633
Short name T518
Test name
Test status
Simulation time 58513069 ps
CPU time 2.57 seconds
Started Aug 01 06:59:57 PM PDT 24
Finished Aug 01 06:59:59 PM PDT 24
Peak memory 210052 kb
Host smart-08292d11-1633-414f-ba7a-e35a924635e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996312633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3996312633
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3656769280
Short name T248
Test name
Test status
Simulation time 9140231509 ps
CPU time 118.56 seconds
Started Aug 01 07:00:05 PM PDT 24
Finished Aug 01 07:02:06 PM PDT 24
Peak memory 215924 kb
Host smart-0f0a6405-f40f-46bd-b345-c69bd996bb74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3656769280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3656769280
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.4094857344
Short name T767
Test name
Test status
Simulation time 73308734 ps
CPU time 2.97 seconds
Started Aug 01 07:00:09 PM PDT 24
Finished Aug 01 07:00:12 PM PDT 24
Peak memory 214572 kb
Host smart-3129d1da-9dbb-4bf0-8d2d-ea6567adcf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094857344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.4094857344
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3282725645
Short name T298
Test name
Test status
Simulation time 56381591 ps
CPU time 2.09 seconds
Started Aug 01 07:00:06 PM PDT 24
Finished Aug 01 07:00:10 PM PDT 24
Peak memory 214304 kb
Host smart-e7658621-7ff0-4567-842d-a697c6aeebd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282725645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3282725645
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2451434397
Short name T634
Test name
Test status
Simulation time 60198151 ps
CPU time 3.21 seconds
Started Aug 01 07:00:07 PM PDT 24
Finished Aug 01 07:00:11 PM PDT 24
Peak memory 214348 kb
Host smart-f67f01c6-8554-438e-924e-f1f4751214b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451434397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2451434397
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2810077713
Short name T375
Test name
Test status
Simulation time 236639694 ps
CPU time 1.98 seconds
Started Aug 01 07:00:12 PM PDT 24
Finished Aug 01 07:00:14 PM PDT 24
Peak memory 214236 kb
Host smart-f5c80950-c2c6-4fb8-be79-fe3dafc78f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810077713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2810077713
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1460717718
Short name T537
Test name
Test status
Simulation time 104493176 ps
CPU time 2.78 seconds
Started Aug 01 07:00:05 PM PDT 24
Finished Aug 01 07:00:10 PM PDT 24
Peak memory 215136 kb
Host smart-fe17ba51-de14-4854-8442-bcc718437788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460717718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1460717718
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.183761042
Short name T407
Test name
Test status
Simulation time 650741996 ps
CPU time 5.19 seconds
Started Aug 01 07:00:13 PM PDT 24
Finished Aug 01 07:00:18 PM PDT 24
Peak memory 209736 kb
Host smart-22222b52-a710-4315-a5d3-cac0bcc60f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183761042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.183761042
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1319543412
Short name T187
Test name
Test status
Simulation time 102224621 ps
CPU time 2.79 seconds
Started Aug 01 07:00:06 PM PDT 24
Finished Aug 01 07:00:10 PM PDT 24
Peak memory 206892 kb
Host smart-9bd03fbc-a946-4757-a7bc-80c447b03393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319543412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1319543412
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.2847227630
Short name T351
Test name
Test status
Simulation time 161005608 ps
CPU time 4.22 seconds
Started Aug 01 07:00:05 PM PDT 24
Finished Aug 01 07:00:12 PM PDT 24
Peak memory 208856 kb
Host smart-84a897a4-4fc8-4be9-b8ea-04841bfae93e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847227630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2847227630
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.66768961
Short name T414
Test name
Test status
Simulation time 163683280 ps
CPU time 2.58 seconds
Started Aug 01 07:00:07 PM PDT 24
Finished Aug 01 07:00:11 PM PDT 24
Peak memory 207016 kb
Host smart-dd95d414-bc3f-4166-93ee-cbc36eec5a7c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66768961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.66768961
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1653552300
Short name T809
Test name
Test status
Simulation time 134441716 ps
CPU time 2.73 seconds
Started Aug 01 07:00:06 PM PDT 24
Finished Aug 01 07:00:10 PM PDT 24
Peak memory 206976 kb
Host smart-0d9b5a02-bbef-4025-b953-d19242306770
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653552300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1653552300
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1183711245
Short name T818
Test name
Test status
Simulation time 2623931389 ps
CPU time 20.6 seconds
Started Aug 01 07:00:04 PM PDT 24
Finished Aug 01 07:00:28 PM PDT 24
Peak memory 218608 kb
Host smart-a90ea196-c574-46c0-adf7-f30bc5890393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183711245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1183711245
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2279358126
Short name T606
Test name
Test status
Simulation time 46523612 ps
CPU time 2.08 seconds
Started Aug 01 07:00:07 PM PDT 24
Finished Aug 01 07:00:10 PM PDT 24
Peak memory 206088 kb
Host smart-117b5868-5eae-4d46-88d6-d529365d947a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279358126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2279358126
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2346730141
Short name T229
Test name
Test status
Simulation time 494904215 ps
CPU time 4.09 seconds
Started Aug 01 07:00:07 PM PDT 24
Finished Aug 01 07:00:12 PM PDT 24
Peak memory 214352 kb
Host smart-8568d053-4c22-4582-b165-422cebd8305b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346730141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2346730141
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2928146449
Short name T901
Test name
Test status
Simulation time 1268077724 ps
CPU time 3.72 seconds
Started Aug 01 07:00:06 PM PDT 24
Finished Aug 01 07:00:11 PM PDT 24
Peak memory 210720 kb
Host smart-fad533c2-d255-48a7-88ef-4f53b31402fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928146449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2928146449
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.551625148
Short name T668
Test name
Test status
Simulation time 85720003 ps
CPU time 0.86 seconds
Started Aug 01 07:00:06 PM PDT 24
Finished Aug 01 07:00:08 PM PDT 24
Peak memory 205948 kb
Host smart-5fdb1c27-5c53-4835-8402-b69126947662
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551625148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.551625148
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3347699695
Short name T231
Test name
Test status
Simulation time 118551789 ps
CPU time 3.75 seconds
Started Aug 01 07:00:07 PM PDT 24
Finished Aug 01 07:00:11 PM PDT 24
Peak memory 215588 kb
Host smart-567ff18e-2146-4517-9fbd-3528e01b5c3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3347699695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3347699695
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3388608429
Short name T144
Test name
Test status
Simulation time 238701820 ps
CPU time 4.53 seconds
Started Aug 01 07:00:08 PM PDT 24
Finished Aug 01 07:00:13 PM PDT 24
Peak memory 222524 kb
Host smart-5d086a1d-775a-42c1-b7d2-d832fc8abb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388608429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3388608429
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2628355988
Short name T100
Test name
Test status
Simulation time 164969430 ps
CPU time 1.56 seconds
Started Aug 01 07:00:06 PM PDT 24
Finished Aug 01 07:00:09 PM PDT 24
Peak memory 209812 kb
Host smart-b3896218-a1ef-4813-9f08-0f2b0bf8098a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628355988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2628355988
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1588237912
Short name T82
Test name
Test status
Simulation time 28963649 ps
CPU time 2.45 seconds
Started Aug 01 07:00:07 PM PDT 24
Finished Aug 01 07:00:10 PM PDT 24
Peak memory 214316 kb
Host smart-25e86b85-6170-4349-8561-8fe1dff3edf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588237912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1588237912
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.1703523410
Short name T378
Test name
Test status
Simulation time 241936747 ps
CPU time 5.29 seconds
Started Aug 01 07:00:09 PM PDT 24
Finished Aug 01 07:00:15 PM PDT 24
Peak memory 222312 kb
Host smart-f550218e-7489-4c6f-85af-49dc2a24251d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703523410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1703523410
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2036671445
Short name T780
Test name
Test status
Simulation time 48458804 ps
CPU time 1.42 seconds
Started Aug 01 07:00:09 PM PDT 24
Finished Aug 01 07:00:11 PM PDT 24
Peak memory 214360 kb
Host smart-1b9fc9e5-73ba-4f4c-8171-0eb9a66f2739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036671445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2036671445
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1354914616
Short name T766
Test name
Test status
Simulation time 209747428 ps
CPU time 5.48 seconds
Started Aug 01 07:00:05 PM PDT 24
Finished Aug 01 07:00:13 PM PDT 24
Peak memory 208680 kb
Host smart-34a8c47a-b9ff-40fd-973f-525d06604296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354914616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1354914616
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3219008216
Short name T444
Test name
Test status
Simulation time 67153577 ps
CPU time 2.92 seconds
Started Aug 01 07:00:07 PM PDT 24
Finished Aug 01 07:00:11 PM PDT 24
Peak memory 206816 kb
Host smart-9346edaf-8221-4c30-aeea-f0a78503d4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219008216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3219008216
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3597589649
Short name T618
Test name
Test status
Simulation time 310405525 ps
CPU time 4.79 seconds
Started Aug 01 07:00:11 PM PDT 24
Finished Aug 01 07:00:16 PM PDT 24
Peak memory 208136 kb
Host smart-5d25f95c-c3fc-42d8-93c8-a8bb4e07ebd7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597589649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3597589649
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1607308607
Short name T450
Test name
Test status
Simulation time 65499769 ps
CPU time 2.39 seconds
Started Aug 01 07:00:09 PM PDT 24
Finished Aug 01 07:00:12 PM PDT 24
Peak memory 206936 kb
Host smart-8a8e4043-99f4-4300-85be-b8850c20c1a8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607308607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1607308607
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3227963231
Short name T756
Test name
Test status
Simulation time 64536751 ps
CPU time 3.41 seconds
Started Aug 01 07:00:08 PM PDT 24
Finished Aug 01 07:00:11 PM PDT 24
Peak memory 206956 kb
Host smart-f70dfe80-1eef-4ad0-a3d2-6beaf6b447bf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227963231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3227963231
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.531261327
Short name T564
Test name
Test status
Simulation time 124293147 ps
CPU time 4.69 seconds
Started Aug 01 07:00:07 PM PDT 24
Finished Aug 01 07:00:13 PM PDT 24
Peak memory 210124 kb
Host smart-11ad8a8d-005e-4ec8-8dde-93bfd35ab8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531261327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.531261327
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2093348135
Short name T449
Test name
Test status
Simulation time 87652723 ps
CPU time 2.5 seconds
Started Aug 01 07:00:06 PM PDT 24
Finished Aug 01 07:00:10 PM PDT 24
Peak memory 208388 kb
Host smart-d886301d-21de-4887-974b-671ad98d453b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093348135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2093348135
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2966047897
Short name T278
Test name
Test status
Simulation time 869830284 ps
CPU time 20.94 seconds
Started Aug 01 07:00:08 PM PDT 24
Finished Aug 01 07:00:29 PM PDT 24
Peak memory 222388 kb
Host smart-55465d73-536e-4e2e-941c-aeec8ba7ddd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966047897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2966047897
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1602640914
Short name T729
Test name
Test status
Simulation time 974579859 ps
CPU time 10.2 seconds
Started Aug 01 07:00:10 PM PDT 24
Finished Aug 01 07:00:20 PM PDT 24
Peak memory 208984 kb
Host smart-2ff49c6f-8a31-42ff-a968-c8a99fdfc2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602640914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1602640914
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.160760571
Short name T647
Test name
Test status
Simulation time 89289880 ps
CPU time 1.62 seconds
Started Aug 01 07:00:07 PM PDT 24
Finished Aug 01 07:00:09 PM PDT 24
Peak memory 209704 kb
Host smart-a7b96804-335c-4a8d-af48-f4f5029544d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160760571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.160760571
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1565437665
Short name T443
Test name
Test status
Simulation time 15630878 ps
CPU time 0.73 seconds
Started Aug 01 07:00:08 PM PDT 24
Finished Aug 01 07:00:09 PM PDT 24
Peak memory 205928 kb
Host smart-e3f74571-98a2-4d90-b93d-8b308a08457e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565437665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1565437665
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3264671440
Short name T415
Test name
Test status
Simulation time 51905769 ps
CPU time 3.61 seconds
Started Aug 01 07:00:07 PM PDT 24
Finished Aug 01 07:00:11 PM PDT 24
Peak memory 214324 kb
Host smart-e8c0c2e6-4d6e-4eb1-854c-97169e101601
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3264671440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3264671440
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1975483673
Short name T786
Test name
Test status
Simulation time 95822995 ps
CPU time 3.31 seconds
Started Aug 01 07:00:11 PM PDT 24
Finished Aug 01 07:00:14 PM PDT 24
Peak memory 222616 kb
Host smart-6896d781-e2fc-4804-be2a-7b739acbcfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975483673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1975483673
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1000408928
Short name T880
Test name
Test status
Simulation time 140491331 ps
CPU time 3.39 seconds
Started Aug 01 07:00:07 PM PDT 24
Finished Aug 01 07:00:11 PM PDT 24
Peak memory 222392 kb
Host smart-d49ae54c-c42a-4f81-8d7d-0840d42c7bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000408928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1000408928
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1439241555
Short name T669
Test name
Test status
Simulation time 420234258 ps
CPU time 3.43 seconds
Started Aug 01 07:00:14 PM PDT 24
Finished Aug 01 07:00:17 PM PDT 24
Peak memory 214304 kb
Host smart-c0094bf8-c0db-4f3c-8f68-f569e5e12367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439241555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1439241555
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2522696108
Short name T256
Test name
Test status
Simulation time 445588025 ps
CPU time 2.57 seconds
Started Aug 01 07:00:06 PM PDT 24
Finished Aug 01 07:00:10 PM PDT 24
Peak memory 220600 kb
Host smart-5872a3f7-e146-443d-a0da-c42b26a032a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522696108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2522696108
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.177616403
Short name T577
Test name
Test status
Simulation time 277917911 ps
CPU time 3.34 seconds
Started Aug 01 07:00:13 PM PDT 24
Finished Aug 01 07:00:16 PM PDT 24
Peak memory 207664 kb
Host smart-f17ba862-cd68-4f90-9c84-5b056ba46cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177616403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.177616403
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3816102406
Short name T815
Test name
Test status
Simulation time 150818310 ps
CPU time 3.08 seconds
Started Aug 01 07:00:09 PM PDT 24
Finished Aug 01 07:00:12 PM PDT 24
Peak memory 206700 kb
Host smart-5db4c5c9-3f59-4224-a682-54e4289e3ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816102406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3816102406
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2480403246
Short name T485
Test name
Test status
Simulation time 281410253 ps
CPU time 3.68 seconds
Started Aug 01 07:00:09 PM PDT 24
Finished Aug 01 07:00:13 PM PDT 24
Peak memory 208812 kb
Host smart-e2691ac5-169c-447a-9aaf-c41ddf281e7e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480403246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2480403246
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.2701886631
Short name T451
Test name
Test status
Simulation time 55991241 ps
CPU time 2.28 seconds
Started Aug 01 07:00:09 PM PDT 24
Finished Aug 01 07:00:12 PM PDT 24
Peak memory 206820 kb
Host smart-3e6334f9-4743-4682-9fe6-7c00b01dde71
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701886631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2701886631
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.457284652
Short name T233
Test name
Test status
Simulation time 447017059 ps
CPU time 4.37 seconds
Started Aug 01 07:00:05 PM PDT 24
Finished Aug 01 07:00:12 PM PDT 24
Peak memory 206872 kb
Host smart-ef2e6f71-afa7-47c2-899a-44182a64621f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457284652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.457284652
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.414989371
Short name T494
Test name
Test status
Simulation time 147695489 ps
CPU time 1.92 seconds
Started Aug 01 07:00:05 PM PDT 24
Finished Aug 01 07:00:09 PM PDT 24
Peak memory 208964 kb
Host smart-2db42ca6-5f5c-4cb1-994e-e7c9c0c9f934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414989371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.414989371
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3989792044
Short name T459
Test name
Test status
Simulation time 77892982 ps
CPU time 2.06 seconds
Started Aug 01 07:00:07 PM PDT 24
Finished Aug 01 07:00:10 PM PDT 24
Peak memory 207336 kb
Host smart-304d316a-c498-43f7-a3a2-4c4ca72627f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989792044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3989792044
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2118361082
Short name T738
Test name
Test status
Simulation time 1229933138 ps
CPU time 15.35 seconds
Started Aug 01 07:00:07 PM PDT 24
Finished Aug 01 07:00:23 PM PDT 24
Peak memory 208652 kb
Host smart-6e13c1a8-f58a-49b9-85f9-3682213106b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118361082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2118361082
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3760925895
Short name T496
Test name
Test status
Simulation time 38959696 ps
CPU time 0.7 seconds
Started Aug 01 06:59:09 PM PDT 24
Finished Aug 01 06:59:10 PM PDT 24
Peak memory 205900 kb
Host smart-b1fea82e-dd91-4c47-93f9-587682afc49d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760925895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3760925895
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.443273606
Short name T423
Test name
Test status
Simulation time 119814418 ps
CPU time 6.12 seconds
Started Aug 01 06:59:07 PM PDT 24
Finished Aug 01 06:59:13 PM PDT 24
Peak memory 213328 kb
Host smart-01a3afb5-8383-4a66-a93a-bfa2c1c6d0b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=443273606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.443273606
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.51172922
Short name T21
Test name
Test status
Simulation time 34097109 ps
CPU time 1.98 seconds
Started Aug 01 06:59:08 PM PDT 24
Finished Aug 01 06:59:10 PM PDT 24
Peak memory 219092 kb
Host smart-9b8a0094-826b-4ff5-8b86-cd511e3790b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51172922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.51172922
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3867771390
Short name T692
Test name
Test status
Simulation time 32378239 ps
CPU time 1.54 seconds
Started Aug 01 06:59:11 PM PDT 24
Finished Aug 01 06:59:12 PM PDT 24
Peak memory 207444 kb
Host smart-75516f6f-3e17-4ef4-9e28-0700dcdb5102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867771390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3867771390
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1747081953
Short name T783
Test name
Test status
Simulation time 115468976 ps
CPU time 3.39 seconds
Started Aug 01 06:59:10 PM PDT 24
Finished Aug 01 06:59:14 PM PDT 24
Peak memory 207320 kb
Host smart-55650e8b-7f77-4cb6-abd6-b671156251e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747081953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1747081953
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1428708549
Short name T373
Test name
Test status
Simulation time 138440881 ps
CPU time 4.79 seconds
Started Aug 01 06:59:07 PM PDT 24
Finished Aug 01 06:59:12 PM PDT 24
Peak memory 207452 kb
Host smart-49ce6b60-b9aa-4f81-8ffb-9988d202a990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428708549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1428708549
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.1449531134
Short name T43
Test name
Test status
Simulation time 1182717588 ps
CPU time 19.34 seconds
Started Aug 01 06:59:09 PM PDT 24
Finished Aug 01 06:59:29 PM PDT 24
Peak memory 240360 kb
Host smart-04171b57-e491-4d8b-b98e-70a534118751
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449531134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1449531134
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1073009282
Short name T502
Test name
Test status
Simulation time 90656268 ps
CPU time 2.55 seconds
Started Aug 01 06:59:09 PM PDT 24
Finished Aug 01 06:59:12 PM PDT 24
Peak memory 206716 kb
Host smart-7d3148fd-57be-4502-a303-d3cd27e4942e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073009282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1073009282
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3630179678
Short name T334
Test name
Test status
Simulation time 59309978 ps
CPU time 2.33 seconds
Started Aug 01 06:59:08 PM PDT 24
Finished Aug 01 06:59:11 PM PDT 24
Peak memory 206924 kb
Host smart-63c74309-6e08-4f25-a7a9-fb4807268091
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630179678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3630179678
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.826174112
Short name T516
Test name
Test status
Simulation time 278212974 ps
CPU time 3.01 seconds
Started Aug 01 06:59:08 PM PDT 24
Finished Aug 01 06:59:11 PM PDT 24
Peak memory 208700 kb
Host smart-5ccc979f-4a13-45cf-b5ff-4d1f07854b9f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826174112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.826174112
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.4024813987
Short name T591
Test name
Test status
Simulation time 1203437673 ps
CPU time 7.96 seconds
Started Aug 01 06:59:10 PM PDT 24
Finished Aug 01 06:59:18 PM PDT 24
Peak memory 208912 kb
Host smart-aa55a12b-bcd8-420c-8f9a-c97b169308e4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024813987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.4024813987
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2458443566
Short name T633
Test name
Test status
Simulation time 153030550 ps
CPU time 4.57 seconds
Started Aug 01 06:59:09 PM PDT 24
Finished Aug 01 06:59:13 PM PDT 24
Peak memory 208784 kb
Host smart-18faf95c-cf06-4821-8313-f3a8fac4b486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458443566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2458443566
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3323788294
Short name T714
Test name
Test status
Simulation time 50103528 ps
CPU time 1.95 seconds
Started Aug 01 06:59:07 PM PDT 24
Finished Aug 01 06:59:09 PM PDT 24
Peak memory 208232 kb
Host smart-2b0a6b26-37e9-491b-a8fb-2969f99e7a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323788294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3323788294
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2727069272
Short name T892
Test name
Test status
Simulation time 5261540283 ps
CPU time 32.7 seconds
Started Aug 01 06:59:13 PM PDT 24
Finished Aug 01 06:59:45 PM PDT 24
Peak memory 222544 kb
Host smart-09f73f21-935a-4dfe-a957-fda63aef6e75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727069272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2727069272
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.3601220772
Short name T759
Test name
Test status
Simulation time 1085058366 ps
CPU time 10.06 seconds
Started Aug 01 06:59:08 PM PDT 24
Finished Aug 01 06:59:18 PM PDT 24
Peak memory 219288 kb
Host smart-4d975169-e725-4665-a981-72445fc125f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601220772 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.3601220772
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.427410695
Short name T367
Test name
Test status
Simulation time 1298777716 ps
CPU time 30.37 seconds
Started Aug 01 06:59:10 PM PDT 24
Finished Aug 01 06:59:40 PM PDT 24
Peak memory 208920 kb
Host smart-786962b0-e88d-4925-b889-6eb46158dbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427410695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.427410695
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.427497804
Short name T839
Test name
Test status
Simulation time 461644035 ps
CPU time 3.63 seconds
Started Aug 01 06:59:10 PM PDT 24
Finished Aug 01 06:59:14 PM PDT 24
Peak memory 210320 kb
Host smart-b068d28d-c272-4257-bccf-fab6085dd5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427497804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.427497804
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.957078288
Short name T709
Test name
Test status
Simulation time 45688671 ps
CPU time 0.74 seconds
Started Aug 01 07:00:22 PM PDT 24
Finished Aug 01 07:00:23 PM PDT 24
Peak memory 205948 kb
Host smart-a19c87e6-ff0f-4e92-aaa0-1f300d1fd9e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957078288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.957078288
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1866968439
Short name T295
Test name
Test status
Simulation time 35956988 ps
CPU time 2.83 seconds
Started Aug 01 07:00:10 PM PDT 24
Finished Aug 01 07:00:13 PM PDT 24
Peak memory 214268 kb
Host smart-dca323b4-1cce-448f-abb2-927098367934
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1866968439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1866968439
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.924289210
Short name T593
Test name
Test status
Simulation time 139056009 ps
CPU time 2.86 seconds
Started Aug 01 07:00:22 PM PDT 24
Finished Aug 01 07:00:25 PM PDT 24
Peak memory 220828 kb
Host smart-cc2dad41-2e47-4ff2-9a7f-9618daf83b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924289210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.924289210
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.861736144
Short name T71
Test name
Test status
Simulation time 67836881 ps
CPU time 3 seconds
Started Aug 01 07:00:10 PM PDT 24
Finished Aug 01 07:00:13 PM PDT 24
Peak memory 209724 kb
Host smart-d5d6ff57-a6e0-42cc-a14c-e7a34694ca81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861736144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.861736144
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3113291328
Short name T510
Test name
Test status
Simulation time 409463454 ps
CPU time 6.61 seconds
Started Aug 01 07:00:14 PM PDT 24
Finished Aug 01 07:00:20 PM PDT 24
Peak memory 222508 kb
Host smart-55065487-03f7-46cf-b3ec-b028d24d09b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113291328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3113291328
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3351466591
Short name T354
Test name
Test status
Simulation time 200285937 ps
CPU time 3.1 seconds
Started Aug 01 07:00:18 PM PDT 24
Finished Aug 01 07:00:22 PM PDT 24
Peak memory 221968 kb
Host smart-4d13fc4c-3591-43c1-a1c6-1820631579a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351466591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3351466591
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3533696105
Short name T208
Test name
Test status
Simulation time 232112006 ps
CPU time 2.03 seconds
Started Aug 01 07:00:07 PM PDT 24
Finished Aug 01 07:00:10 PM PDT 24
Peak memory 222480 kb
Host smart-a5dd559b-a922-47ac-b71b-d66743746b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533696105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3533696105
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1852088749
Short name T379
Test name
Test status
Simulation time 306480278 ps
CPU time 3.62 seconds
Started Aug 01 07:00:09 PM PDT 24
Finished Aug 01 07:00:13 PM PDT 24
Peak memory 207532 kb
Host smart-188d5679-281e-4568-b101-1dc3553c863d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852088749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1852088749
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2362442419
Short name T642
Test name
Test status
Simulation time 600489383 ps
CPU time 3.98 seconds
Started Aug 01 07:00:15 PM PDT 24
Finished Aug 01 07:00:19 PM PDT 24
Peak memory 208412 kb
Host smart-c68ebf3c-5891-463a-9a6f-e81ff41b8b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362442419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2362442419
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3766312922
Short name T838
Test name
Test status
Simulation time 461206347 ps
CPU time 4.11 seconds
Started Aug 01 07:00:09 PM PDT 24
Finished Aug 01 07:00:14 PM PDT 24
Peak memory 206996 kb
Host smart-ce137dfb-9909-445c-8c88-06696403303c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766312922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3766312922
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2562514133
Short name T745
Test name
Test status
Simulation time 361750286 ps
CPU time 7.45 seconds
Started Aug 01 07:00:10 PM PDT 24
Finished Aug 01 07:00:17 PM PDT 24
Peak memory 206944 kb
Host smart-cd745aeb-3050-489c-a948-2947fb339820
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562514133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2562514133
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1804364511
Short name T614
Test name
Test status
Simulation time 139457517 ps
CPU time 3.42 seconds
Started Aug 01 07:00:13 PM PDT 24
Finished Aug 01 07:00:17 PM PDT 24
Peak memory 208900 kb
Host smart-1721ae86-1b16-4362-9db5-9f8081fc3906
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804364511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1804364511
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2116312588
Short name T760
Test name
Test status
Simulation time 127159546 ps
CPU time 2.93 seconds
Started Aug 01 07:00:20 PM PDT 24
Finished Aug 01 07:00:23 PM PDT 24
Peak memory 209064 kb
Host smart-13cc7c85-6126-4f88-824c-aef7036a6ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116312588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2116312588
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3821088950
Short name T808
Test name
Test status
Simulation time 125968793 ps
CPU time 2.15 seconds
Started Aug 01 07:00:13 PM PDT 24
Finished Aug 01 07:00:15 PM PDT 24
Peak memory 206780 kb
Host smart-7588631c-3360-47bf-a4f6-e4e3378a01ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821088950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3821088950
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.313413250
Short name T228
Test name
Test status
Simulation time 696344648 ps
CPU time 9.72 seconds
Started Aug 01 07:00:20 PM PDT 24
Finished Aug 01 07:00:30 PM PDT 24
Peak memory 216884 kb
Host smart-f0f8b84c-627a-4bb0-b51e-bcbae5923151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313413250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.313413250
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2104105205
Short name T277
Test name
Test status
Simulation time 722444750 ps
CPU time 24.5 seconds
Started Aug 01 07:00:16 PM PDT 24
Finished Aug 01 07:00:40 PM PDT 24
Peak memory 209200 kb
Host smart-7858d883-5fa0-4f5a-8b70-dc0d7aa576e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104105205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2104105205
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.180618136
Short name T122
Test name
Test status
Simulation time 251626642 ps
CPU time 2.08 seconds
Started Aug 01 07:00:20 PM PDT 24
Finished Aug 01 07:00:22 PM PDT 24
Peak memory 210028 kb
Host smart-432a92ba-c97d-4ad8-938d-ee1239996392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180618136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.180618136
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2308651864
Short name T434
Test name
Test status
Simulation time 50515943 ps
CPU time 0.71 seconds
Started Aug 01 07:00:26 PM PDT 24
Finished Aug 01 07:00:27 PM PDT 24
Peak memory 205956 kb
Host smart-db1735dc-7eef-417e-a960-ef379f720a72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308651864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2308651864
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3119104879
Short name T398
Test name
Test status
Simulation time 86074053 ps
CPU time 5.05 seconds
Started Aug 01 07:00:17 PM PDT 24
Finished Aug 01 07:00:22 PM PDT 24
Peak memory 214728 kb
Host smart-444777ef-f382-409f-8005-dfeaf68d8932
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3119104879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3119104879
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2155080645
Short name T215
Test name
Test status
Simulation time 78392118 ps
CPU time 3.23 seconds
Started Aug 01 07:00:21 PM PDT 24
Finished Aug 01 07:00:25 PM PDT 24
Peak memory 208500 kb
Host smart-f5496e94-7010-46ff-af9d-794abf18f315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155080645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2155080645
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2347584032
Short name T684
Test name
Test status
Simulation time 110447351 ps
CPU time 3 seconds
Started Aug 01 07:00:21 PM PDT 24
Finished Aug 01 07:00:24 PM PDT 24
Peak memory 209244 kb
Host smart-22038184-aa46-4e79-91cd-a0b02a8bbb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347584032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2347584032
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.313882657
Short name T250
Test name
Test status
Simulation time 154317410 ps
CPU time 3.82 seconds
Started Aug 01 07:00:20 PM PDT 24
Finished Aug 01 07:00:24 PM PDT 24
Peak memory 214316 kb
Host smart-18ec09cc-df46-4660-85b1-5dfd60bb8fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313882657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.313882657
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3403920465
Short name T183
Test name
Test status
Simulation time 457048556 ps
CPU time 2.85 seconds
Started Aug 01 07:00:20 PM PDT 24
Finished Aug 01 07:00:23 PM PDT 24
Peak memory 214224 kb
Host smart-f4642f97-453a-47fc-ab12-25c9af9c5bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403920465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3403920465
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3724380396
Short name T812
Test name
Test status
Simulation time 321966562 ps
CPU time 2.48 seconds
Started Aug 01 07:00:17 PM PDT 24
Finished Aug 01 07:00:20 PM PDT 24
Peak memory 208796 kb
Host smart-74f1de46-91cb-4e85-8cc3-992368d8e9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724380396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3724380396
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3312527381
Short name T402
Test name
Test status
Simulation time 485918976 ps
CPU time 4.97 seconds
Started Aug 01 07:00:22 PM PDT 24
Finished Aug 01 07:00:27 PM PDT 24
Peak memory 222452 kb
Host smart-ea9a14e6-2499-4f42-94af-35725b685458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312527381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3312527381
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3228597712
Short name T538
Test name
Test status
Simulation time 515599376 ps
CPU time 4.33 seconds
Started Aug 01 07:00:18 PM PDT 24
Finished Aug 01 07:00:23 PM PDT 24
Peak memory 208600 kb
Host smart-5e73eebb-67b2-4cbd-b0f4-996660ac5fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228597712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3228597712
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2113800762
Short name T831
Test name
Test status
Simulation time 823285232 ps
CPU time 22.96 seconds
Started Aug 01 07:00:19 PM PDT 24
Finished Aug 01 07:00:42 PM PDT 24
Peak memory 208844 kb
Host smart-534c4f54-e696-47de-ad9d-97cb149e2862
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113800762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2113800762
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.519600677
Short name T12
Test name
Test status
Simulation time 211918564 ps
CPU time 3.09 seconds
Started Aug 01 07:00:20 PM PDT 24
Finished Aug 01 07:00:24 PM PDT 24
Peak memory 207156 kb
Host smart-d522db67-bd38-49c0-81f5-c905c86383ba
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519600677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.519600677
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1769126681
Short name T755
Test name
Test status
Simulation time 201971417 ps
CPU time 2.84 seconds
Started Aug 01 07:00:20 PM PDT 24
Finished Aug 01 07:00:23 PM PDT 24
Peak memory 206916 kb
Host smart-fafae141-1a21-456a-a63d-c5e98cf8a381
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769126681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1769126681
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.796162276
Short name T365
Test name
Test status
Simulation time 37004077 ps
CPU time 2.53 seconds
Started Aug 01 07:00:21 PM PDT 24
Finished Aug 01 07:00:23 PM PDT 24
Peak memory 210148 kb
Host smart-621d5347-df52-43ef-80d4-5226bc6fe11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796162276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.796162276
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.720855380
Short name T587
Test name
Test status
Simulation time 2781286049 ps
CPU time 4.92 seconds
Started Aug 01 07:00:27 PM PDT 24
Finished Aug 01 07:00:32 PM PDT 24
Peak memory 208096 kb
Host smart-aef24a68-6da6-42bb-9172-eefd3b51a814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720855380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.720855380
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.422226413
Short name T875
Test name
Test status
Simulation time 1509385834 ps
CPU time 19.1 seconds
Started Aug 01 07:00:21 PM PDT 24
Finished Aug 01 07:00:41 PM PDT 24
Peak memory 216536 kb
Host smart-8f39d245-0c7c-4575-8262-7159e99493b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422226413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.422226413
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.2093317055
Short name T116
Test name
Test status
Simulation time 261193377 ps
CPU time 5.58 seconds
Started Aug 01 07:00:19 PM PDT 24
Finished Aug 01 07:00:25 PM PDT 24
Peak memory 222560 kb
Host smart-d595de6e-4edb-4cbf-b6b3-38f6cfefa9f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093317055 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.2093317055
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.794972992
Short name T612
Test name
Test status
Simulation time 107804434 ps
CPU time 4.64 seconds
Started Aug 01 07:00:19 PM PDT 24
Finished Aug 01 07:00:24 PM PDT 24
Peak memory 207412 kb
Host smart-14b37405-fa0b-4f5e-8527-7fc8a3b30fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794972992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.794972992
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.621956866
Short name T390
Test name
Test status
Simulation time 72090192 ps
CPU time 3.05 seconds
Started Aug 01 07:00:22 PM PDT 24
Finished Aug 01 07:00:26 PM PDT 24
Peak memory 210232 kb
Host smart-d9121c5b-7bf7-421c-a107-8b377f672367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621956866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.621956866
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1401512804
Short name T520
Test name
Test status
Simulation time 10620534 ps
CPU time 0.72 seconds
Started Aug 01 07:00:21 PM PDT 24
Finished Aug 01 07:00:22 PM PDT 24
Peak memory 205960 kb
Host smart-2d4ffd49-d0a0-4803-9566-d3b4af669f8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401512804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1401512804
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.3470913176
Short name T426
Test name
Test status
Simulation time 180164081 ps
CPU time 3.5 seconds
Started Aug 01 07:00:21 PM PDT 24
Finished Aug 01 07:00:25 PM PDT 24
Peak memory 214316 kb
Host smart-b42c9dda-f6b1-47f8-9020-07af24d48901
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3470913176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3470913176
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3778599929
Short name T504
Test name
Test status
Simulation time 275008223 ps
CPU time 3.66 seconds
Started Aug 01 07:00:17 PM PDT 24
Finished Aug 01 07:00:21 PM PDT 24
Peak memory 209304 kb
Host smart-3d269112-d6d1-4001-bdd2-57ab7a0bef77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778599929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3778599929
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3463915560
Short name T80
Test name
Test status
Simulation time 1277980748 ps
CPU time 3.94 seconds
Started Aug 01 07:00:19 PM PDT 24
Finished Aug 01 07:00:23 PM PDT 24
Peak memory 220468 kb
Host smart-72203a48-0fc5-4149-8c30-36af7ab66b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463915560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3463915560
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2652494973
Short name T546
Test name
Test status
Simulation time 30557898 ps
CPU time 2.27 seconds
Started Aug 01 07:00:19 PM PDT 24
Finished Aug 01 07:00:21 PM PDT 24
Peak memory 211444 kb
Host smart-200574db-2cc6-4ae8-bfb1-e988d169f5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652494973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2652494973
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_random.4007500475
Short name T514
Test name
Test status
Simulation time 121999337 ps
CPU time 5.51 seconds
Started Aug 01 07:00:22 PM PDT 24
Finished Aug 01 07:00:27 PM PDT 24
Peak memory 209416 kb
Host smart-53237bc7-e8a6-44f5-b340-43bf1798b304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007500475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.4007500475
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1910975544
Short name T120
Test name
Test status
Simulation time 1888516441 ps
CPU time 25.67 seconds
Started Aug 01 07:00:22 PM PDT 24
Finished Aug 01 07:00:48 PM PDT 24
Peak memory 208232 kb
Host smart-ba718825-ef68-4bf2-8e40-4e485d77a043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910975544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1910975544
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1106070783
Short name T259
Test name
Test status
Simulation time 78171658 ps
CPU time 1.83 seconds
Started Aug 01 07:00:21 PM PDT 24
Finished Aug 01 07:00:23 PM PDT 24
Peak memory 206812 kb
Host smart-7369a9b4-df3e-4289-90b8-acf515e63cf5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106070783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1106070783
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.1283226892
Short name T715
Test name
Test status
Simulation time 221748383 ps
CPU time 3.24 seconds
Started Aug 01 07:00:23 PM PDT 24
Finished Aug 01 07:00:27 PM PDT 24
Peak memory 206764 kb
Host smart-7b2d19e0-04a2-453e-b600-15efe3484d87
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283226892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1283226892
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3634128701
Short name T302
Test name
Test status
Simulation time 228270623 ps
CPU time 3.08 seconds
Started Aug 01 07:00:22 PM PDT 24
Finished Aug 01 07:00:25 PM PDT 24
Peak memory 208960 kb
Host smart-46a53b06-6a1e-4998-bef3-6c2aa05cd4b0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634128701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3634128701
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3903908281
Short name T325
Test name
Test status
Simulation time 152996994 ps
CPU time 3.92 seconds
Started Aug 01 07:00:23 PM PDT 24
Finished Aug 01 07:00:27 PM PDT 24
Peak memory 214264 kb
Host smart-e96c7556-5c05-4d7d-b5c4-ba5ff0eff4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903908281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3903908281
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.961198898
Short name T872
Test name
Test status
Simulation time 212481761 ps
CPU time 2.58 seconds
Started Aug 01 07:00:20 PM PDT 24
Finished Aug 01 07:00:22 PM PDT 24
Peak memory 208628 kb
Host smart-4e433367-4c81-4e25-b0cc-f4b9f9f1101e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961198898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.961198898
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2810788907
Short name T192
Test name
Test status
Simulation time 93221655 ps
CPU time 3.1 seconds
Started Aug 01 07:00:19 PM PDT 24
Finished Aug 01 07:00:22 PM PDT 24
Peak memory 207588 kb
Host smart-3b507849-6f31-4730-9596-2eff3f8219da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810788907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2810788907
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3481108420
Short name T833
Test name
Test status
Simulation time 258145458 ps
CPU time 1.85 seconds
Started Aug 01 07:00:23 PM PDT 24
Finished Aug 01 07:00:25 PM PDT 24
Peak memory 210152 kb
Host smart-6309c4bc-c2a9-407c-b6ac-329c15ae13e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481108420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3481108420
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.4023106796
Short name T433
Test name
Test status
Simulation time 37969393 ps
CPU time 0.72 seconds
Started Aug 01 07:00:32 PM PDT 24
Finished Aug 01 07:00:33 PM PDT 24
Peak memory 205956 kb
Host smart-14d52709-45fe-4757-884a-6f4f23e86d64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023106796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.4023106796
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1547619782
Short name T638
Test name
Test status
Simulation time 591765048 ps
CPU time 3 seconds
Started Aug 01 07:00:21 PM PDT 24
Finished Aug 01 07:00:25 PM PDT 24
Peak memory 210496 kb
Host smart-a954a68e-5a29-434c-b470-e83e36d34619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547619782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1547619782
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2988392035
Short name T565
Test name
Test status
Simulation time 112440917 ps
CPU time 3.79 seconds
Started Aug 01 07:00:33 PM PDT 24
Finished Aug 01 07:00:37 PM PDT 24
Peak memory 214320 kb
Host smart-78b4fec2-d909-4d6e-9829-64baf43a4b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988392035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2988392035
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2851745826
Short name T599
Test name
Test status
Simulation time 252114987 ps
CPU time 2.41 seconds
Started Aug 01 07:00:31 PM PDT 24
Finished Aug 01 07:00:34 PM PDT 24
Peak memory 214340 kb
Host smart-426686cb-0996-4d96-8fbb-1488056679e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851745826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2851745826
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.925238236
Short name T52
Test name
Test status
Simulation time 302392726 ps
CPU time 3.39 seconds
Started Aug 01 07:00:33 PM PDT 24
Finished Aug 01 07:00:36 PM PDT 24
Peak memory 209708 kb
Host smart-a3e6baba-d0f9-4422-be17-e6e09c2dcc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925238236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.925238236
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.366145845
Short name T693
Test name
Test status
Simulation time 12462926704 ps
CPU time 61.37 seconds
Started Aug 01 07:00:23 PM PDT 24
Finished Aug 01 07:01:25 PM PDT 24
Peak memory 218280 kb
Host smart-63297371-1403-495f-89d4-a4fb2c8c8103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366145845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.366145845
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1217550834
Short name T629
Test name
Test status
Simulation time 406036876 ps
CPU time 3.2 seconds
Started Aug 01 07:00:25 PM PDT 24
Finished Aug 01 07:00:28 PM PDT 24
Peak memory 206948 kb
Host smart-d2146a4d-278c-4cf7-876e-a5bd87d68d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217550834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1217550834
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.2044325160
Short name T679
Test name
Test status
Simulation time 569646317 ps
CPU time 4.11 seconds
Started Aug 01 07:00:20 PM PDT 24
Finished Aug 01 07:00:25 PM PDT 24
Peak memory 207216 kb
Host smart-7fb356d7-03f1-4444-ae39-5a80f847c0ee
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044325160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2044325160
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2949109857
Short name T551
Test name
Test status
Simulation time 435288681 ps
CPU time 2.93 seconds
Started Aug 01 07:00:22 PM PDT 24
Finished Aug 01 07:00:25 PM PDT 24
Peak memory 207300 kb
Host smart-cb23f82f-198d-4572-b1b2-dd0f81909eee
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949109857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2949109857
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.121079082
Short name T758
Test name
Test status
Simulation time 539028642 ps
CPU time 4.01 seconds
Started Aug 01 07:00:23 PM PDT 24
Finished Aug 01 07:00:27 PM PDT 24
Peak memory 206984 kb
Host smart-7ceba193-c87a-4c6a-b658-640753a7ed02
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121079082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.121079082
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.815050101
Short name T774
Test name
Test status
Simulation time 50546274 ps
CPU time 1.82 seconds
Started Aug 01 07:00:34 PM PDT 24
Finished Aug 01 07:00:36 PM PDT 24
Peak memory 215464 kb
Host smart-9b64e6bf-92e1-4656-a413-9af00be53565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815050101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.815050101
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2469250620
Short name T772
Test name
Test status
Simulation time 313555328 ps
CPU time 2.54 seconds
Started Aug 01 07:00:25 PM PDT 24
Finished Aug 01 07:00:28 PM PDT 24
Peak memory 206812 kb
Host smart-6210b98f-1cfd-4f33-840f-7d21be88be80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469250620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2469250620
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3697860103
Short name T269
Test name
Test status
Simulation time 83269389 ps
CPU time 3.26 seconds
Started Aug 01 07:00:32 PM PDT 24
Finished Aug 01 07:00:35 PM PDT 24
Peak memory 218428 kb
Host smart-6db4dcbb-364d-4bed-bdb1-8e1cc7918b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697860103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3697860103
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2264155921
Short name T146
Test name
Test status
Simulation time 77764862 ps
CPU time 2.79 seconds
Started Aug 01 07:00:32 PM PDT 24
Finished Aug 01 07:00:35 PM PDT 24
Peak memory 210212 kb
Host smart-1e7707af-289f-43eb-83b6-41b6996e100d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264155921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2264155921
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.422009776
Short name T446
Test name
Test status
Simulation time 21375717 ps
CPU time 0.81 seconds
Started Aug 01 07:00:34 PM PDT 24
Finished Aug 01 07:00:35 PM PDT 24
Peak memory 205952 kb
Host smart-79528979-7eb6-49e9-9386-02dbd3e883f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422009776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.422009776
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3176401190
Short name T369
Test name
Test status
Simulation time 2014616982 ps
CPU time 25.88 seconds
Started Aug 01 07:00:31 PM PDT 24
Finished Aug 01 07:00:57 PM PDT 24
Peak memory 214500 kb
Host smart-a4aa0f1e-4d31-40d1-b96c-c0b631b98724
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3176401190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3176401190
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3049490313
Short name T66
Test name
Test status
Simulation time 64058529 ps
CPU time 2.2 seconds
Started Aug 01 07:00:33 PM PDT 24
Finished Aug 01 07:00:36 PM PDT 24
Peak memory 220968 kb
Host smart-40647351-b605-45fa-81a9-0f5df156fc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049490313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3049490313
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3024926744
Short name T59
Test name
Test status
Simulation time 66281714 ps
CPU time 3.2 seconds
Started Aug 01 07:00:36 PM PDT 24
Finished Aug 01 07:00:39 PM PDT 24
Peak memory 210560 kb
Host smart-c3343cdf-87fa-40bb-bc03-0d96ee54ec22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024926744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3024926744
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.218385193
Short name T795
Test name
Test status
Simulation time 77084406 ps
CPU time 3.5 seconds
Started Aug 01 07:00:33 PM PDT 24
Finished Aug 01 07:00:36 PM PDT 24
Peak memory 221428 kb
Host smart-218e2a76-d508-4f37-8f2a-67e18d9cf1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218385193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.218385193
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_random.384230637
Short name T471
Test name
Test status
Simulation time 7713700891 ps
CPU time 65.42 seconds
Started Aug 01 07:00:35 PM PDT 24
Finished Aug 01 07:01:41 PM PDT 24
Peak memory 209060 kb
Host smart-3d718cb8-f80c-496e-a686-4f223d241dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384230637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.384230637
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1790163994
Short name T743
Test name
Test status
Simulation time 533250916 ps
CPU time 2.4 seconds
Started Aug 01 07:00:33 PM PDT 24
Finished Aug 01 07:00:35 PM PDT 24
Peak memory 206896 kb
Host smart-5a5c3c87-bc5a-490c-9854-6950d17d2e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790163994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1790163994
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2150836378
Short name T879
Test name
Test status
Simulation time 280503250 ps
CPU time 2.8 seconds
Started Aug 01 07:00:41 PM PDT 24
Finished Aug 01 07:00:44 PM PDT 24
Peak memory 207308 kb
Host smart-c3df466b-a566-4535-b329-d108e0e01c17
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150836378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2150836378
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2494296469
Short name T102
Test name
Test status
Simulation time 113210775 ps
CPU time 3.17 seconds
Started Aug 01 07:00:33 PM PDT 24
Finished Aug 01 07:00:37 PM PDT 24
Peak memory 208156 kb
Host smart-35864308-4ce3-4eb6-86df-8f26b8e58c85
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494296469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2494296469
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3872684461
Short name T307
Test name
Test status
Simulation time 855529306 ps
CPU time 6.24 seconds
Started Aug 01 07:00:29 PM PDT 24
Finished Aug 01 07:00:36 PM PDT 24
Peak memory 207844 kb
Host smart-9c3242cf-3ea7-46a4-8db8-9223ebe3df9e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872684461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3872684461
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.4249343614
Short name T581
Test name
Test status
Simulation time 318730299 ps
CPU time 3.22 seconds
Started Aug 01 07:00:35 PM PDT 24
Finished Aug 01 07:00:38 PM PDT 24
Peak memory 217824 kb
Host smart-0967b427-38ee-4813-bcca-888f509f1574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249343614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.4249343614
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3512617656
Short name T482
Test name
Test status
Simulation time 702873254 ps
CPU time 4.59 seconds
Started Aug 01 07:00:29 PM PDT 24
Finished Aug 01 07:00:34 PM PDT 24
Peak memory 208100 kb
Host smart-1e680b33-d39a-43b6-8974-af8b2c38d145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512617656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3512617656
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1320439991
Short name T189
Test name
Test status
Simulation time 1776494257 ps
CPU time 33.58 seconds
Started Aug 01 07:00:32 PM PDT 24
Finished Aug 01 07:01:06 PM PDT 24
Peak memory 215168 kb
Host smart-42b524fc-9ece-49c7-95a8-b95ef38bb67d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320439991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1320439991
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2558334121
Short name T570
Test name
Test status
Simulation time 417412941 ps
CPU time 4.86 seconds
Started Aug 01 07:00:30 PM PDT 24
Finished Aug 01 07:00:35 PM PDT 24
Peak memory 214304 kb
Host smart-c872054d-b311-4ced-ad71-d2e0249e91cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558334121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2558334121
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.405324497
Short name T41
Test name
Test status
Simulation time 245402564 ps
CPU time 1.95 seconds
Started Aug 01 07:00:36 PM PDT 24
Finished Aug 01 07:00:38 PM PDT 24
Peak memory 209864 kb
Host smart-9bbb39a9-08be-4af3-b769-eb46e5faed3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405324497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.405324497
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1750761898
Short name T440
Test name
Test status
Simulation time 15134768 ps
CPU time 0.83 seconds
Started Aug 01 07:00:32 PM PDT 24
Finished Aug 01 07:00:33 PM PDT 24
Peak memory 206004 kb
Host smart-e55c7a6c-b796-4832-b5ad-5c88d3950fe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750761898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1750761898
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1379788481
Short name T39
Test name
Test status
Simulation time 128696878 ps
CPU time 2.46 seconds
Started Aug 01 07:00:32 PM PDT 24
Finished Aug 01 07:00:35 PM PDT 24
Peak memory 214244 kb
Host smart-0f50e034-1e8e-449d-bac1-1a2cce32ac9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379788481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1379788481
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3091690569
Short name T582
Test name
Test status
Simulation time 89422706 ps
CPU time 1.64 seconds
Started Aug 01 07:00:32 PM PDT 24
Finished Aug 01 07:00:34 PM PDT 24
Peak memory 207656 kb
Host smart-a9fc3a23-e55b-4d0e-bd88-5bc525b1fe65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091690569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3091690569
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1077996380
Short name T263
Test name
Test status
Simulation time 332421319 ps
CPU time 5.75 seconds
Started Aug 01 07:00:36 PM PDT 24
Finished Aug 01 07:00:42 PM PDT 24
Peak memory 211436 kb
Host smart-3b503ba2-0c87-4d12-9aed-89956f4643bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077996380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1077996380
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.4087181954
Short name T860
Test name
Test status
Simulation time 195521993 ps
CPU time 2.58 seconds
Started Aug 01 07:00:31 PM PDT 24
Finished Aug 01 07:00:34 PM PDT 24
Peak memory 214320 kb
Host smart-d45d24d0-aecc-4f8a-a7db-b15c7a142a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087181954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.4087181954
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2939662767
Short name T234
Test name
Test status
Simulation time 1331946601 ps
CPU time 9.76 seconds
Started Aug 01 07:00:32 PM PDT 24
Finished Aug 01 07:00:42 PM PDT 24
Peak memory 222600 kb
Host smart-59476a43-7f59-48e7-848d-20de0cb25125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939662767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2939662767
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2263846521
Short name T191
Test name
Test status
Simulation time 183118039 ps
CPU time 5.6 seconds
Started Aug 01 07:00:36 PM PDT 24
Finished Aug 01 07:00:42 PM PDT 24
Peak memory 207396 kb
Host smart-f36bef32-05f8-4c83-864d-efeaa6746b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263846521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2263846521
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.4094441410
Short name T195
Test name
Test status
Simulation time 1294545972 ps
CPU time 9.53 seconds
Started Aug 01 07:00:36 PM PDT 24
Finished Aug 01 07:00:46 PM PDT 24
Peak memory 208260 kb
Host smart-60557d3b-e87c-4aad-a924-93488e730785
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094441410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.4094441410
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.93467778
Short name T674
Test name
Test status
Simulation time 200764955 ps
CPU time 3.83 seconds
Started Aug 01 07:00:35 PM PDT 24
Finished Aug 01 07:00:39 PM PDT 24
Peak memory 206684 kb
Host smart-5f0171c0-0dc3-437d-8d68-1a171e4eb466
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93467778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.93467778
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2803649696
Short name T689
Test name
Test status
Simulation time 368104512 ps
CPU time 2.63 seconds
Started Aug 01 07:01:15 PM PDT 24
Finished Aug 01 07:01:18 PM PDT 24
Peak memory 208044 kb
Host smart-098ecd34-fa24-400c-b8d4-439826ed4e9a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803649696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2803649696
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.692946082
Short name T498
Test name
Test status
Simulation time 119442000 ps
CPU time 5.13 seconds
Started Aug 01 07:00:34 PM PDT 24
Finished Aug 01 07:00:39 PM PDT 24
Peak memory 209236 kb
Host smart-50bf4722-917a-4383-b6c8-c4656ee7c38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692946082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.692946082
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3432335667
Short name T447
Test name
Test status
Simulation time 67486751 ps
CPU time 2.63 seconds
Started Aug 01 07:00:35 PM PDT 24
Finished Aug 01 07:00:38 PM PDT 24
Peak memory 208148 kb
Host smart-3044cdc0-66aa-4d7c-bac7-07fe688e1ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432335667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3432335667
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3282822378
Short name T50
Test name
Test status
Simulation time 12669855947 ps
CPU time 74.04 seconds
Started Aug 01 07:00:38 PM PDT 24
Finished Aug 01 07:01:53 PM PDT 24
Peak memory 214972 kb
Host smart-cf8c2ec0-08a2-4822-be99-7b066b28b23d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282822378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3282822378
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3399913085
Short name T649
Test name
Test status
Simulation time 114307948 ps
CPU time 2.33 seconds
Started Aug 01 07:00:32 PM PDT 24
Finished Aug 01 07:00:34 PM PDT 24
Peak memory 209668 kb
Host smart-7564e51a-d701-4fcd-aa5e-8da6aa35f52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399913085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3399913085
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2635000689
Short name T393
Test name
Test status
Simulation time 35135604 ps
CPU time 1.92 seconds
Started Aug 01 07:00:37 PM PDT 24
Finished Aug 01 07:00:39 PM PDT 24
Peak memory 209924 kb
Host smart-63b5dee5-bcdf-4d70-8959-ababc3377759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635000689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2635000689
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2681304421
Short name T867
Test name
Test status
Simulation time 47024982 ps
CPU time 0.87 seconds
Started Aug 01 07:00:33 PM PDT 24
Finished Aug 01 07:00:34 PM PDT 24
Peak memory 205996 kb
Host smart-c78f9a51-e1e4-4bfa-bd16-ff3c015e33a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681304421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2681304421
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2646145150
Short name T312
Test name
Test status
Simulation time 70799988 ps
CPU time 2.7 seconds
Started Aug 01 07:00:37 PM PDT 24
Finished Aug 01 07:00:40 PM PDT 24
Peak memory 215212 kb
Host smart-2b2b395e-9047-4bb1-bc9c-ce740e00530d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2646145150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2646145150
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.577317680
Short name T55
Test name
Test status
Simulation time 68565832 ps
CPU time 2.69 seconds
Started Aug 01 07:00:35 PM PDT 24
Finished Aug 01 07:00:38 PM PDT 24
Peak memory 214292 kb
Host smart-7081eeb6-be17-4e95-b770-01b3c5124cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577317680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.577317680
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3828005722
Short name T877
Test name
Test status
Simulation time 89559806 ps
CPU time 1.82 seconds
Started Aug 01 07:00:37 PM PDT 24
Finished Aug 01 07:00:39 PM PDT 24
Peak memory 214360 kb
Host smart-ce6e77a5-ac5c-4c12-bd95-d9915c37c670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828005722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3828005722
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1630151571
Short name T896
Test name
Test status
Simulation time 67614085 ps
CPU time 2.59 seconds
Started Aug 01 07:00:34 PM PDT 24
Finished Aug 01 07:00:37 PM PDT 24
Peak memory 214256 kb
Host smart-262dec36-1a5c-43d6-8699-71768e120075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630151571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1630151571
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3895199826
Short name T173
Test name
Test status
Simulation time 133594662 ps
CPU time 2.91 seconds
Started Aug 01 07:00:35 PM PDT 24
Finished Aug 01 07:00:38 PM PDT 24
Peak memory 214300 kb
Host smart-fdb0b1ac-58e0-4e6e-a91e-34514541d22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895199826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3895199826
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3472027691
Short name T346
Test name
Test status
Simulation time 83103700 ps
CPU time 4.1 seconds
Started Aug 01 07:00:34 PM PDT 24
Finished Aug 01 07:00:38 PM PDT 24
Peak memory 207576 kb
Host smart-6bd5b687-e807-472c-bf4e-5f5216e264e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472027691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3472027691
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1081167875
Short name T258
Test name
Test status
Simulation time 518233094 ps
CPU time 6.62 seconds
Started Aug 01 07:00:35 PM PDT 24
Finished Aug 01 07:00:42 PM PDT 24
Peak memory 208064 kb
Host smart-20640b91-0efa-4b39-8750-084db588a95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081167875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1081167875
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.798757133
Short name T870
Test name
Test status
Simulation time 75237711 ps
CPU time 3.49 seconds
Started Aug 01 07:00:36 PM PDT 24
Finished Aug 01 07:00:40 PM PDT 24
Peak memory 208592 kb
Host smart-8bbfbd8f-2ee4-41a3-ae14-962a42bb85d5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798757133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.798757133
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1974203075
Short name T557
Test name
Test status
Simulation time 929413314 ps
CPU time 4.15 seconds
Started Aug 01 07:00:36 PM PDT 24
Finished Aug 01 07:00:40 PM PDT 24
Peak memory 208520 kb
Host smart-0fad93ff-38b9-45d8-a355-ac1763e79d0a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974203075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1974203075
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1970365282
Short name T486
Test name
Test status
Simulation time 126521350 ps
CPU time 2.38 seconds
Started Aug 01 07:00:36 PM PDT 24
Finished Aug 01 07:00:39 PM PDT 24
Peak memory 206884 kb
Host smart-627d746d-4758-4b43-94b8-4b4a5e771309
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970365282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1970365282
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.4270124722
Short name T121
Test name
Test status
Simulation time 203395948 ps
CPU time 3.79 seconds
Started Aug 01 07:00:34 PM PDT 24
Finished Aug 01 07:00:39 PM PDT 24
Peak memory 215868 kb
Host smart-8596b7ed-e458-48d7-b959-42a60fbb288e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270124722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.4270124722
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.425561150
Short name T560
Test name
Test status
Simulation time 128514444 ps
CPU time 3.84 seconds
Started Aug 01 07:00:34 PM PDT 24
Finished Aug 01 07:00:37 PM PDT 24
Peak memory 206940 kb
Host smart-1cc5541a-22d8-418c-916f-eaa54c64624a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425561150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.425561150
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.144537019
Short name T290
Test name
Test status
Simulation time 1605019480 ps
CPU time 41.1 seconds
Started Aug 01 07:00:34 PM PDT 24
Finished Aug 01 07:01:15 PM PDT 24
Peak memory 222460 kb
Host smart-8978f52f-6c8a-477d-a2fa-1ac720b44945
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144537019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.144537019
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.585731763
Short name T340
Test name
Test status
Simulation time 220060718 ps
CPU time 10.74 seconds
Started Aug 01 07:00:35 PM PDT 24
Finished Aug 01 07:00:46 PM PDT 24
Peak memory 222552 kb
Host smart-1b64c96f-0a35-45aa-83c0-63f3158ff02a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585731763 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.585731763
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2673675384
Short name T27
Test name
Test status
Simulation time 91675770 ps
CPU time 3.89 seconds
Started Aug 01 07:00:34 PM PDT 24
Finished Aug 01 07:00:38 PM PDT 24
Peak memory 214324 kb
Host smart-10a74878-d362-4c75-8c00-7b1b63ed10ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673675384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2673675384
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3553923253
Short name T803
Test name
Test status
Simulation time 69098142 ps
CPU time 1.37 seconds
Started Aug 01 07:00:37 PM PDT 24
Finished Aug 01 07:00:39 PM PDT 24
Peak memory 209616 kb
Host smart-52ce7dbe-025f-4bb3-a6b2-c33e9ae76625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553923253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3553923253
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.1701898566
Short name T675
Test name
Test status
Simulation time 87698831 ps
CPU time 0.74 seconds
Started Aug 01 07:00:41 PM PDT 24
Finished Aug 01 07:00:42 PM PDT 24
Peak memory 205940 kb
Host smart-8b63d6f2-c206-40c4-a3c6-f626869bbf6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701898566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1701898566
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2691432378
Short name T40
Test name
Test status
Simulation time 278186368 ps
CPU time 2.24 seconds
Started Aug 01 07:00:43 PM PDT 24
Finished Aug 01 07:00:46 PM PDT 24
Peak memory 214268 kb
Host smart-efff4adf-7f93-4b3f-a02a-58d5444d1891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691432378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2691432378
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.2529455098
Short name T666
Test name
Test status
Simulation time 290145138 ps
CPU time 2.34 seconds
Started Aug 01 07:00:34 PM PDT 24
Finished Aug 01 07:00:37 PM PDT 24
Peak memory 209104 kb
Host smart-daa4d399-9286-4c28-8ddb-3fa68dfcd2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529455098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2529455098
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.35750935
Short name T569
Test name
Test status
Simulation time 119477075 ps
CPU time 2.31 seconds
Started Aug 01 07:00:48 PM PDT 24
Finished Aug 01 07:00:50 PM PDT 24
Peak memory 214288 kb
Host smart-7ed22f4b-9940-41af-9947-33e99f00bb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35750935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.35750935
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.4015167877
Short name T220
Test name
Test status
Simulation time 477923146 ps
CPU time 6 seconds
Started Aug 01 07:00:35 PM PDT 24
Finished Aug 01 07:00:41 PM PDT 24
Peak memory 220456 kb
Host smart-3566aaee-7dd3-431e-983e-4a81a3cc0149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015167877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.4015167877
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.3507177874
Short name T455
Test name
Test status
Simulation time 801818401 ps
CPU time 6.54 seconds
Started Aug 01 07:00:33 PM PDT 24
Finished Aug 01 07:00:40 PM PDT 24
Peak memory 207868 kb
Host smart-1aad8b78-aa50-41ad-b4f2-19515bfb0cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507177874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3507177874
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2293205813
Short name T796
Test name
Test status
Simulation time 47800160 ps
CPU time 1.74 seconds
Started Aug 01 07:00:35 PM PDT 24
Finished Aug 01 07:00:37 PM PDT 24
Peak memory 206920 kb
Host smart-956b564c-fc88-4346-9d9b-234b1239a46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293205813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2293205813
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1941273395
Short name T549
Test name
Test status
Simulation time 35197716 ps
CPU time 2.46 seconds
Started Aug 01 07:00:35 PM PDT 24
Finished Aug 01 07:00:38 PM PDT 24
Peak memory 208624 kb
Host smart-92256466-8ab0-44c8-a4ab-7f40c5e6a9e1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941273395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1941273395
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.919882746
Short name T260
Test name
Test status
Simulation time 278647524 ps
CPU time 2.95 seconds
Started Aug 01 07:00:35 PM PDT 24
Finished Aug 01 07:00:38 PM PDT 24
Peak memory 206960 kb
Host smart-f9c09384-7571-49dc-b4d0-f55a1d73b25b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919882746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.919882746
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2671832614
Short name T526
Test name
Test status
Simulation time 74584722 ps
CPU time 3.51 seconds
Started Aug 01 07:00:34 PM PDT 24
Finished Aug 01 07:00:38 PM PDT 24
Peak memory 208604 kb
Host smart-e959c69a-7188-4c65-a179-664ca1ed5cf5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671832614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2671832614
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1913464402
Short name T461
Test name
Test status
Simulation time 94316038 ps
CPU time 3.01 seconds
Started Aug 01 07:00:46 PM PDT 24
Finished Aug 01 07:00:50 PM PDT 24
Peak memory 208480 kb
Host smart-678e76b6-2bfc-43ee-9246-90767f91e865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913464402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1913464402
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.1796424118
Short name T561
Test name
Test status
Simulation time 1301101551 ps
CPU time 19.73 seconds
Started Aug 01 07:00:35 PM PDT 24
Finished Aug 01 07:00:55 PM PDT 24
Peak memory 208088 kb
Host smart-2b2e43d3-250e-4732-bc49-2cafd2044f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796424118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1796424118
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2052014102
Short name T280
Test name
Test status
Simulation time 1091633623 ps
CPU time 37.41 seconds
Started Aug 01 07:00:42 PM PDT 24
Finished Aug 01 07:01:19 PM PDT 24
Peak memory 209236 kb
Host smart-29b665a9-bc56-422f-a68b-ba79b784834f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052014102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2052014102
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.813494565
Short name T746
Test name
Test status
Simulation time 94712957 ps
CPU time 1.33 seconds
Started Aug 01 07:00:45 PM PDT 24
Finished Aug 01 07:00:47 PM PDT 24
Peak memory 210020 kb
Host smart-4b1e63c3-6101-43f4-b122-84eb924266a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813494565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.813494565
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2368141983
Short name T595
Test name
Test status
Simulation time 15681038 ps
CPU time 0.79 seconds
Started Aug 01 07:00:47 PM PDT 24
Finished Aug 01 07:00:48 PM PDT 24
Peak memory 205964 kb
Host smart-2ede8238-feae-4132-8e0c-d041fa633738
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368141983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2368141983
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3280032962
Short name T253
Test name
Test status
Simulation time 142494491 ps
CPU time 2.12 seconds
Started Aug 01 07:00:46 PM PDT 24
Finished Aug 01 07:00:48 PM PDT 24
Peak memory 208072 kb
Host smart-f6a67411-c1e1-425a-9e1d-e5bf6516cd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280032962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3280032962
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1047412701
Short name T240
Test name
Test status
Simulation time 123067285 ps
CPU time 5 seconds
Started Aug 01 07:00:47 PM PDT 24
Finished Aug 01 07:00:53 PM PDT 24
Peak memory 214332 kb
Host smart-d41f2d20-21e7-4ea8-9096-0815dd313421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047412701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1047412701
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1194527925
Short name T801
Test name
Test status
Simulation time 326267447 ps
CPU time 2.94 seconds
Started Aug 01 07:00:44 PM PDT 24
Finished Aug 01 07:00:47 PM PDT 24
Peak memory 209196 kb
Host smart-667591e6-b94f-4048-9182-8280b048fd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194527925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1194527925
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.443232930
Short name T843
Test name
Test status
Simulation time 341447519 ps
CPU time 8.45 seconds
Started Aug 01 07:00:46 PM PDT 24
Finished Aug 01 07:00:54 PM PDT 24
Peak memory 207624 kb
Host smart-c0b425f4-5c71-4af2-85d1-05f7664f966d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443232930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.443232930
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.775606141
Short name T305
Test name
Test status
Simulation time 1341933290 ps
CPU time 39.8 seconds
Started Aug 01 07:00:45 PM PDT 24
Finished Aug 01 07:01:25 PM PDT 24
Peak memory 208252 kb
Host smart-dd31b38e-550a-43f2-9543-01ae5a1123e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775606141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.775606141
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.4058510412
Short name T704
Test name
Test status
Simulation time 186369859 ps
CPU time 2.69 seconds
Started Aug 01 07:00:49 PM PDT 24
Finished Aug 01 07:00:52 PM PDT 24
Peak memory 208704 kb
Host smart-5f3393a2-769d-4559-9b1c-72453dc4cba1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058510412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.4058510412
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1709420
Short name T548
Test name
Test status
Simulation time 39007817 ps
CPU time 1.75 seconds
Started Aug 01 07:00:43 PM PDT 24
Finished Aug 01 07:00:45 PM PDT 24
Peak memory 207468 kb
Host smart-48e02046-94e5-4765-a897-d5e16312ed0d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1709420
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.48729983
Short name T574
Test name
Test status
Simulation time 570136699 ps
CPU time 5.64 seconds
Started Aug 01 07:00:48 PM PDT 24
Finished Aug 01 07:00:54 PM PDT 24
Peak memory 208144 kb
Host smart-1e4de731-0b7d-4673-a991-178f27cefa8a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48729983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.48729983
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.892053181
Short name T359
Test name
Test status
Simulation time 143995185 ps
CPU time 3.25 seconds
Started Aug 01 07:00:43 PM PDT 24
Finished Aug 01 07:00:47 PM PDT 24
Peak memory 214316 kb
Host smart-e4022e4c-417b-4703-8042-64e1af127b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892053181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.892053181
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1704931406
Short name T673
Test name
Test status
Simulation time 67689059 ps
CPU time 2.24 seconds
Started Aug 01 07:00:49 PM PDT 24
Finished Aug 01 07:00:51 PM PDT 24
Peak memory 206936 kb
Host smart-19acb6c6-706c-4eef-8466-67a41c71a54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704931406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1704931406
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.477180932
Short name T388
Test name
Test status
Simulation time 1282611675 ps
CPU time 7.33 seconds
Started Aug 01 07:00:49 PM PDT 24
Finished Aug 01 07:00:56 PM PDT 24
Peak memory 210280 kb
Host smart-418dcda8-94c6-46a3-866f-754dee50af51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477180932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.477180932
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.393945965
Short name T849
Test name
Test status
Simulation time 15937718 ps
CPU time 0.9 seconds
Started Aug 01 07:00:46 PM PDT 24
Finished Aug 01 07:00:47 PM PDT 24
Peak memory 205924 kb
Host smart-26bd3c42-6b78-4f74-9e6c-71414fb2a98e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393945965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.393945965
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1788076197
Short name T11
Test name
Test status
Simulation time 122972330 ps
CPU time 2.66 seconds
Started Aug 01 07:00:43 PM PDT 24
Finished Aug 01 07:00:46 PM PDT 24
Peak memory 218396 kb
Host smart-c9da7732-8741-4a4d-931e-349aa8a7aceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788076197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1788076197
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1762982486
Short name T542
Test name
Test status
Simulation time 1891671772 ps
CPU time 5.02 seconds
Started Aug 01 07:00:44 PM PDT 24
Finished Aug 01 07:00:49 PM PDT 24
Peak memory 208724 kb
Host smart-6a5d6d63-e2cc-44a4-8d7c-01391df60f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762982486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1762982486
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2375693016
Short name T481
Test name
Test status
Simulation time 667128751 ps
CPU time 6.37 seconds
Started Aug 01 07:00:50 PM PDT 24
Finished Aug 01 07:00:56 PM PDT 24
Peak memory 222536 kb
Host smart-05204315-ebbc-4698-b3ab-1f6f8b94ce2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375693016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2375693016
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1202219878
Short name T500
Test name
Test status
Simulation time 77707024 ps
CPU time 3.53 seconds
Started Aug 01 07:00:48 PM PDT 24
Finished Aug 01 07:00:52 PM PDT 24
Peak memory 210416 kb
Host smart-76f7d489-991d-43c2-b1e5-ef458c15c1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202219878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1202219878
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3020782574
Short name T695
Test name
Test status
Simulation time 132599886 ps
CPU time 3.31 seconds
Started Aug 01 07:00:43 PM PDT 24
Finished Aug 01 07:00:46 PM PDT 24
Peak memory 208992 kb
Host smart-e1abfdf8-f93f-46b2-9cd7-ec8b1eb52a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020782574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3020782574
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1454703024
Short name T281
Test name
Test status
Simulation time 2019992593 ps
CPU time 22.82 seconds
Started Aug 01 07:00:42 PM PDT 24
Finished Aug 01 07:01:05 PM PDT 24
Peak memory 208532 kb
Host smart-fa86d8d2-0f6d-4742-899a-ad55604add13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454703024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1454703024
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3449083535
Short name T613
Test name
Test status
Simulation time 77365089 ps
CPU time 2.53 seconds
Started Aug 01 07:00:42 PM PDT 24
Finished Aug 01 07:00:45 PM PDT 24
Peak memory 206948 kb
Host smart-f723f586-4684-4b8c-9156-e9102d4c7fc8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449083535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3449083535
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3014979364
Short name T716
Test name
Test status
Simulation time 378017503 ps
CPU time 7.06 seconds
Started Aug 01 07:00:48 PM PDT 24
Finished Aug 01 07:00:56 PM PDT 24
Peak memory 208044 kb
Host smart-ae1c826e-d2d2-4775-bcc5-c51f1ed2dd3a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014979364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3014979364
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1833121035
Short name T404
Test name
Test status
Simulation time 80019027 ps
CPU time 3.81 seconds
Started Aug 01 07:00:44 PM PDT 24
Finished Aug 01 07:00:48 PM PDT 24
Peak memory 208904 kb
Host smart-aee88b0b-8292-45aa-bcf3-a6f02906dae7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833121035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1833121035
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1176871062
Short name T531
Test name
Test status
Simulation time 97375724 ps
CPU time 1.79 seconds
Started Aug 01 07:00:46 PM PDT 24
Finished Aug 01 07:00:48 PM PDT 24
Peak memory 215660 kb
Host smart-c7ab2db5-e558-4918-8035-fa64ded39a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176871062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1176871062
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3077108266
Short name T75
Test name
Test status
Simulation time 68279079 ps
CPU time 3.31 seconds
Started Aug 01 07:00:48 PM PDT 24
Finished Aug 01 07:00:51 PM PDT 24
Peak memory 208004 kb
Host smart-e0d36e03-f8eb-4d8c-b6b9-15b5c22526b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077108266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3077108266
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2201588843
Short name T285
Test name
Test status
Simulation time 1980775496 ps
CPU time 52.62 seconds
Started Aug 01 07:00:49 PM PDT 24
Finished Aug 01 07:01:42 PM PDT 24
Peak memory 216892 kb
Host smart-ad5d3452-4b4b-4406-9cba-e08bce46e832
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201588843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2201588843
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.265115388
Short name T181
Test name
Test status
Simulation time 96468660 ps
CPU time 4.19 seconds
Started Aug 01 07:00:45 PM PDT 24
Finished Aug 01 07:00:49 PM PDT 24
Peak memory 209928 kb
Host smart-217420f3-d082-4de0-9a38-f22464241deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265115388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.265115388
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1756386840
Short name T395
Test name
Test status
Simulation time 42863072 ps
CPU time 1.93 seconds
Started Aug 01 07:00:47 PM PDT 24
Finished Aug 01 07:00:49 PM PDT 24
Peak memory 209760 kb
Host smart-2e8ebbe8-08b6-4313-8dfe-823b6ac4ea17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756386840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1756386840
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.4120444198
Short name T641
Test name
Test status
Simulation time 26997561 ps
CPU time 0.77 seconds
Started Aug 01 06:59:22 PM PDT 24
Finished Aug 01 06:59:23 PM PDT 24
Peak memory 205952 kb
Host smart-ce478255-28ff-4e7a-9483-ccfa667661d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120444198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.4120444198
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1266305340
Short name T3
Test name
Test status
Simulation time 50129849 ps
CPU time 2.57 seconds
Started Aug 01 06:59:09 PM PDT 24
Finished Aug 01 06:59:11 PM PDT 24
Peak memory 214372 kb
Host smart-a3aad74b-d00a-499b-881a-2de067764753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266305340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1266305340
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.257926763
Short name T655
Test name
Test status
Simulation time 143779722 ps
CPU time 3.68 seconds
Started Aug 01 06:59:09 PM PDT 24
Finished Aug 01 06:59:13 PM PDT 24
Peak memory 214224 kb
Host smart-5a2c7838-eaf0-408f-9e3c-7c2a922a0517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257926763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.257926763
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.474544594
Short name T212
Test name
Test status
Simulation time 361561399 ps
CPU time 3.81 seconds
Started Aug 01 06:59:09 PM PDT 24
Finished Aug 01 06:59:13 PM PDT 24
Peak memory 220660 kb
Host smart-ebe69f5f-e389-4e97-9a1e-57735eba7b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474544594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.474544594
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.662293963
Short name T257
Test name
Test status
Simulation time 98161762 ps
CPU time 3.33 seconds
Started Aug 01 06:59:10 PM PDT 24
Finished Aug 01 06:59:13 PM PDT 24
Peak memory 214284 kb
Host smart-b2a04ae3-d044-4997-93d2-860e19cfd50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662293963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.662293963
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3816436472
Short name T95
Test name
Test status
Simulation time 3083116628 ps
CPU time 5.7 seconds
Started Aug 01 06:59:08 PM PDT 24
Finished Aug 01 06:59:14 PM PDT 24
Peak memory 230396 kb
Host smart-43443101-9025-4ff3-9304-c0d6dd584216
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816436472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3816436472
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1167850042
Short name T479
Test name
Test status
Simulation time 210419685 ps
CPU time 2.82 seconds
Started Aug 01 06:59:11 PM PDT 24
Finished Aug 01 06:59:14 PM PDT 24
Peak memory 206568 kb
Host smart-3eeae7a2-4e3b-46b5-be0b-c8f1cbd49f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167850042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1167850042
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2094447764
Short name T200
Test name
Test status
Simulation time 48991243 ps
CPU time 2.4 seconds
Started Aug 01 06:59:07 PM PDT 24
Finished Aug 01 06:59:09 PM PDT 24
Peak memory 208516 kb
Host smart-5a3a7ca0-9241-4e41-9ecb-b012d031e044
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094447764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2094447764
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2903116926
Short name T364
Test name
Test status
Simulation time 599574570 ps
CPU time 5.89 seconds
Started Aug 01 06:59:15 PM PDT 24
Finished Aug 01 06:59:21 PM PDT 24
Peak memory 208712 kb
Host smart-59a22562-1a1b-4155-bba0-2dcf67a07826
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903116926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2903116926
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.122365403
Short name T584
Test name
Test status
Simulation time 6431071434 ps
CPU time 40.7 seconds
Started Aug 01 06:59:07 PM PDT 24
Finished Aug 01 06:59:48 PM PDT 24
Peak memory 208012 kb
Host smart-715e7517-84a8-4283-931c-c3b8bfd85005
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122365403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.122365403
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3409862804
Short name T899
Test name
Test status
Simulation time 594260791 ps
CPU time 6.57 seconds
Started Aug 01 06:59:08 PM PDT 24
Finished Aug 01 06:59:15 PM PDT 24
Peak memory 208332 kb
Host smart-752b3f60-3f9e-4d4f-b325-77c2e8e27d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409862804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3409862804
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.767514966
Short name T499
Test name
Test status
Simulation time 1486650070 ps
CPU time 16.18 seconds
Started Aug 01 06:59:08 PM PDT 24
Finished Aug 01 06:59:24 PM PDT 24
Peak memory 207952 kb
Host smart-57f4c18d-be1d-48de-8171-b7b8db204c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767514966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.767514966
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.67187294
Short name T221
Test name
Test status
Simulation time 684663093 ps
CPU time 15.97 seconds
Started Aug 01 06:59:07 PM PDT 24
Finished Aug 01 06:59:23 PM PDT 24
Peak memory 222536 kb
Host smart-85f1559f-09e9-4893-bb0a-5ced699b51e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67187294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.67187294
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3680767821
Short name T862
Test name
Test status
Simulation time 69693196 ps
CPU time 2.6 seconds
Started Aug 01 06:59:09 PM PDT 24
Finished Aug 01 06:59:12 PM PDT 24
Peak memory 208128 kb
Host smart-9a717cb8-2269-4c3a-b893-b08c1f7859df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680767821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3680767821
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1892018758
Short name T509
Test name
Test status
Simulation time 342114458 ps
CPU time 6.53 seconds
Started Aug 01 06:59:06 PM PDT 24
Finished Aug 01 06:59:13 PM PDT 24
Peak memory 210788 kb
Host smart-d791d63a-a1de-4973-bbaf-38dbaf859df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892018758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1892018758
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3040162375
Short name T748
Test name
Test status
Simulation time 11220322 ps
CPU time 0.84 seconds
Started Aug 01 07:00:43 PM PDT 24
Finished Aug 01 07:00:44 PM PDT 24
Peak memory 205944 kb
Host smart-36f56669-1daa-478b-810f-df0f630a7c37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040162375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3040162375
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1703339939
Short name T133
Test name
Test status
Simulation time 71952030 ps
CPU time 3.89 seconds
Started Aug 01 07:00:50 PM PDT 24
Finished Aug 01 07:00:55 PM PDT 24
Peak memory 215336 kb
Host smart-befff625-dd55-4938-8615-c08fb7b873ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1703339939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1703339939
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.701980423
Short name T722
Test name
Test status
Simulation time 71512955 ps
CPU time 1.81 seconds
Started Aug 01 07:00:48 PM PDT 24
Finished Aug 01 07:00:50 PM PDT 24
Peak memory 208712 kb
Host smart-d7c6b818-fac6-44e7-9e1d-3e24235ef173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701980423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.701980423
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.800594224
Short name T262
Test name
Test status
Simulation time 144114353 ps
CPU time 2.43 seconds
Started Aug 01 07:00:55 PM PDT 24
Finished Aug 01 07:00:58 PM PDT 24
Peak memory 214568 kb
Host smart-00a991d7-68cc-4006-86f9-7a961c408ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800594224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.800594224
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.250625700
Short name T16
Test name
Test status
Simulation time 575045593 ps
CPU time 4.96 seconds
Started Aug 01 07:00:51 PM PDT 24
Finished Aug 01 07:00:56 PM PDT 24
Peak memory 210168 kb
Host smart-5b6a1595-90f3-4db8-9f0e-b6815c45a7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250625700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.250625700
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.4178996773
Short name T597
Test name
Test status
Simulation time 175410539 ps
CPU time 4.39 seconds
Started Aug 01 07:00:49 PM PDT 24
Finished Aug 01 07:00:54 PM PDT 24
Peak memory 219684 kb
Host smart-2a2cb64e-3916-4016-adb0-6c88baa6b67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178996773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.4178996773
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3764178581
Short name T558
Test name
Test status
Simulation time 676630249 ps
CPU time 21.58 seconds
Started Aug 01 07:00:43 PM PDT 24
Finished Aug 01 07:01:05 PM PDT 24
Peak memory 207944 kb
Host smart-89f6a081-89a0-4cfe-9738-9e6e68f54d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764178581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3764178581
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3425803844
Short name T798
Test name
Test status
Simulation time 57492367 ps
CPU time 2.79 seconds
Started Aug 01 07:00:51 PM PDT 24
Finished Aug 01 07:00:54 PM PDT 24
Peak memory 206872 kb
Host smart-7c13633a-8293-4eb3-9cc4-34915d6695b2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425803844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3425803844
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.894961091
Short name T705
Test name
Test status
Simulation time 102075443 ps
CPU time 3.24 seconds
Started Aug 01 07:00:45 PM PDT 24
Finished Aug 01 07:00:48 PM PDT 24
Peak memory 206896 kb
Host smart-ac602cec-98b7-45bb-90b1-3f55df41ff45
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894961091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.894961091
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.362143675
Short name T823
Test name
Test status
Simulation time 424266446 ps
CPU time 3.35 seconds
Started Aug 01 07:00:48 PM PDT 24
Finished Aug 01 07:00:52 PM PDT 24
Peak memory 206900 kb
Host smart-cc0544de-e7d1-4bb6-8f73-54b4a1ddf052
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362143675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.362143675
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2789775395
Short name T652
Test name
Test status
Simulation time 776642303 ps
CPU time 2.42 seconds
Started Aug 01 07:00:50 PM PDT 24
Finished Aug 01 07:00:52 PM PDT 24
Peak memory 208352 kb
Host smart-87c3fbf1-1ecd-4870-a5b8-d9f525a3844f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789775395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2789775395
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1364267976
Short name T117
Test name
Test status
Simulation time 215784168 ps
CPU time 2.56 seconds
Started Aug 01 07:00:47 PM PDT 24
Finished Aug 01 07:00:50 PM PDT 24
Peak memory 206976 kb
Host smart-ef2a39d9-482f-4df0-81c8-8c171612d844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364267976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1364267976
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3263453449
Short name T820
Test name
Test status
Simulation time 498227287 ps
CPU time 11.41 seconds
Started Aug 01 07:00:52 PM PDT 24
Finished Aug 01 07:01:03 PM PDT 24
Peak memory 215596 kb
Host smart-29b75147-bb7c-4457-856d-86dbf334a875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263453449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3263453449
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2570826069
Short name T467
Test name
Test status
Simulation time 830689922 ps
CPU time 6.78 seconds
Started Aug 01 07:00:52 PM PDT 24
Finished Aug 01 07:00:59 PM PDT 24
Peak memory 207904 kb
Host smart-ab153d72-760e-482d-96ac-07ebfa80ca07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570826069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2570826069
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1395685917
Short name T562
Test name
Test status
Simulation time 199981174 ps
CPU time 2.89 seconds
Started Aug 01 07:00:50 PM PDT 24
Finished Aug 01 07:00:53 PM PDT 24
Peak memory 210772 kb
Host smart-b3fa4a21-4bb5-4e7a-a790-f04bda37768d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395685917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1395685917
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2126625845
Short name T462
Test name
Test status
Simulation time 12021562 ps
CPU time 0.7 seconds
Started Aug 01 07:00:54 PM PDT 24
Finished Aug 01 07:00:55 PM PDT 24
Peak memory 205948 kb
Host smart-8aea7a01-fb25-4325-b47b-45023668b992
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126625845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2126625845
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1431481077
Short name T732
Test name
Test status
Simulation time 28443672 ps
CPU time 1.64 seconds
Started Aug 01 07:00:57 PM PDT 24
Finished Aug 01 07:00:59 PM PDT 24
Peak memory 209120 kb
Host smart-0b824aea-cb0c-4e44-bdb9-1fadab27b72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431481077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1431481077
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.87897003
Short name T382
Test name
Test status
Simulation time 132185223 ps
CPU time 3.41 seconds
Started Aug 01 07:00:48 PM PDT 24
Finished Aug 01 07:00:51 PM PDT 24
Peak memory 208872 kb
Host smart-d3cc87e0-01ab-4be6-9cc9-5e982071163d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87897003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.87897003
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.187536019
Short name T330
Test name
Test status
Simulation time 71235417 ps
CPU time 3.23 seconds
Started Aug 01 07:00:43 PM PDT 24
Finished Aug 01 07:00:46 PM PDT 24
Peak memory 208976 kb
Host smart-c60eb0e0-0bef-42bc-9af0-d9e91bb73f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187536019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.187536019
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2231183247
Short name T484
Test name
Test status
Simulation time 254526493 ps
CPU time 6.32 seconds
Started Aug 01 07:00:51 PM PDT 24
Finished Aug 01 07:00:58 PM PDT 24
Peak memory 218176 kb
Host smart-3c362e0c-737c-4862-8785-ec5ac5447b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231183247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2231183247
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2681425235
Short name T493
Test name
Test status
Simulation time 73230346 ps
CPU time 2.55 seconds
Started Aug 01 07:00:45 PM PDT 24
Finished Aug 01 07:00:48 PM PDT 24
Peak memory 206812 kb
Host smart-fb7eb4a9-8432-4f34-b7dc-c2318e03c5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681425235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2681425235
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.387918010
Short name T469
Test name
Test status
Simulation time 106763782 ps
CPU time 4.38 seconds
Started Aug 01 07:00:43 PM PDT 24
Finished Aug 01 07:00:48 PM PDT 24
Peak memory 208644 kb
Host smart-ad354550-5ea1-4a55-b765-6e17f5897c59
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387918010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.387918010
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1306097550
Short name T826
Test name
Test status
Simulation time 329556518 ps
CPU time 3.96 seconds
Started Aug 01 07:00:47 PM PDT 24
Finished Aug 01 07:00:51 PM PDT 24
Peak memory 209092 kb
Host smart-3e688b58-c4cf-4967-9105-98e796a4a894
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306097550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1306097550
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2375270914
Short name T728
Test name
Test status
Simulation time 236735613 ps
CPU time 2.8 seconds
Started Aug 01 07:00:52 PM PDT 24
Finished Aug 01 07:00:55 PM PDT 24
Peak memory 206856 kb
Host smart-66d4a0bd-e1d0-4304-a2d3-8599c52e2b94
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375270914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2375270914
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.887454008
Short name T254
Test name
Test status
Simulation time 161809147 ps
CPU time 3.87 seconds
Started Aug 01 07:00:55 PM PDT 24
Finished Aug 01 07:00:59 PM PDT 24
Peak memory 214300 kb
Host smart-73a1f98b-0888-4f5e-a076-ceb30c78361f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887454008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.887454008
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3226631045
Short name T660
Test name
Test status
Simulation time 1438410083 ps
CPU time 3.84 seconds
Started Aug 01 07:00:51 PM PDT 24
Finished Aug 01 07:00:55 PM PDT 24
Peak memory 207448 kb
Host smart-7840a21e-988a-4679-9e3f-f2727e1df7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226631045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3226631045
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2613122471
Short name T698
Test name
Test status
Simulation time 10407597629 ps
CPU time 40.91 seconds
Started Aug 01 07:00:52 PM PDT 24
Finished Aug 01 07:01:33 PM PDT 24
Peak memory 216368 kb
Host smart-4b525aed-e702-42c7-8ce5-7d95edaebfff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613122471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2613122471
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2543483447
Short name T768
Test name
Test status
Simulation time 136494396 ps
CPU time 2.68 seconds
Started Aug 01 07:00:45 PM PDT 24
Finished Aug 01 07:00:48 PM PDT 24
Peak memory 222452 kb
Host smart-a4986610-2dce-4056-98be-7b05fd4cac2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543483447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2543483447
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3816538342
Short name T164
Test name
Test status
Simulation time 67145415 ps
CPU time 2.72 seconds
Started Aug 01 07:00:57 PM PDT 24
Finished Aug 01 07:01:00 PM PDT 24
Peak memory 209956 kb
Host smart-de3d6b4c-d96d-454f-b003-12f3710ca37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816538342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3816538342
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2986742635
Short name T448
Test name
Test status
Simulation time 57154572 ps
CPU time 0.81 seconds
Started Aug 01 07:00:55 PM PDT 24
Finished Aug 01 07:00:56 PM PDT 24
Peak memory 205940 kb
Host smart-6a09169c-b904-4e3d-8f2a-4fe89705ef4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986742635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2986742635
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.4127329286
Short name T605
Test name
Test status
Simulation time 226185269 ps
CPU time 2.33 seconds
Started Aug 01 07:00:54 PM PDT 24
Finished Aug 01 07:00:56 PM PDT 24
Peak memory 217908 kb
Host smart-d653797e-652c-4d8f-9d38-86fa6522114b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127329286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.4127329286
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1815454051
Short name T782
Test name
Test status
Simulation time 34607638 ps
CPU time 1.83 seconds
Started Aug 01 07:00:54 PM PDT 24
Finished Aug 01 07:00:56 PM PDT 24
Peak memory 214308 kb
Host smart-0a713e65-c1f8-425c-bf2b-7268753c8d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815454051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1815454051
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3794709570
Short name T81
Test name
Test status
Simulation time 31936742 ps
CPU time 2.43 seconds
Started Aug 01 07:01:06 PM PDT 24
Finished Aug 01 07:01:09 PM PDT 24
Peak memory 214312 kb
Host smart-4d2ea3a1-6f5a-422c-a3ba-7615744a5965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794709570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3794709570
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3649644761
Short name T197
Test name
Test status
Simulation time 57509323 ps
CPU time 3.31 seconds
Started Aug 01 07:00:55 PM PDT 24
Finished Aug 01 07:00:58 PM PDT 24
Peak memory 222388 kb
Host smart-cd3900e5-5fb8-441d-a2c4-d1525a09d282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649644761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3649644761
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_random.2897430079
Short name T898
Test name
Test status
Simulation time 242722245 ps
CPU time 4.98 seconds
Started Aug 01 07:00:55 PM PDT 24
Finished Aug 01 07:01:00 PM PDT 24
Peak memory 214292 kb
Host smart-ce2c3284-9220-4df9-aa3c-48348f459e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897430079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2897430079
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1954343801
Short name T525
Test name
Test status
Simulation time 333770301 ps
CPU time 2.6 seconds
Started Aug 01 07:00:53 PM PDT 24
Finished Aug 01 07:00:56 PM PDT 24
Peak memory 206808 kb
Host smart-4f178f28-ab6c-4bd7-a6ab-247fc2eae118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954343801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1954343801
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3881992728
Short name T347
Test name
Test status
Simulation time 67100563 ps
CPU time 3.3 seconds
Started Aug 01 07:00:56 PM PDT 24
Finished Aug 01 07:00:59 PM PDT 24
Peak memory 208628 kb
Host smart-2d4af49d-eea2-406a-9e87-ecd992df0a4f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881992728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3881992728
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2938599600
Short name T547
Test name
Test status
Simulation time 491264477 ps
CPU time 14.42 seconds
Started Aug 01 07:00:55 PM PDT 24
Finished Aug 01 07:01:10 PM PDT 24
Peak memory 208532 kb
Host smart-5f40eebd-6d72-4203-b8a3-089f775551a7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938599600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2938599600
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.507664898
Short name T521
Test name
Test status
Simulation time 707214134 ps
CPU time 2.95 seconds
Started Aug 01 07:01:03 PM PDT 24
Finished Aug 01 07:01:06 PM PDT 24
Peak memory 206840 kb
Host smart-807d14b6-b378-455b-8add-199029ac72d8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507664898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.507664898
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.365393787
Short name T503
Test name
Test status
Simulation time 161077985 ps
CPU time 2.29 seconds
Started Aug 01 07:00:59 PM PDT 24
Finished Aug 01 07:01:02 PM PDT 24
Peak memory 215708 kb
Host smart-4a07abc5-e558-4517-a011-3a224963510e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365393787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.365393787
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.695304730
Short name T854
Test name
Test status
Simulation time 66871173 ps
CPU time 3.1 seconds
Started Aug 01 07:00:52 PM PDT 24
Finished Aug 01 07:00:55 PM PDT 24
Peak memory 208168 kb
Host smart-0097a63d-4f46-4b7b-bbab-71e54cb3ed0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695304730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.695304730
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3191830473
Short name T188
Test name
Test status
Simulation time 35639548004 ps
CPU time 375.64 seconds
Started Aug 01 07:00:53 PM PDT 24
Finished Aug 01 07:07:09 PM PDT 24
Peak memory 222624 kb
Host smart-55ba02bc-01bb-4baf-899c-d856f72521de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191830473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3191830473
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.1726001818
Short name T381
Test name
Test status
Simulation time 606271780 ps
CPU time 8.34 seconds
Started Aug 01 07:00:54 PM PDT 24
Finished Aug 01 07:01:03 PM PDT 24
Peak memory 222576 kb
Host smart-0b892ba2-a246-4f05-ad86-7024771b1870
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726001818 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.1726001818
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.407222463
Short name T703
Test name
Test status
Simulation time 384890368 ps
CPU time 4.52 seconds
Started Aug 01 07:00:52 PM PDT 24
Finished Aug 01 07:00:57 PM PDT 24
Peak memory 207452 kb
Host smart-bce79241-f1a4-480b-839d-c3696d9d53aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407222463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.407222463
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3800404279
Short name T883
Test name
Test status
Simulation time 51961014 ps
CPU time 1.62 seconds
Started Aug 01 07:00:55 PM PDT 24
Finished Aug 01 07:00:57 PM PDT 24
Peak memory 209496 kb
Host smart-8ecec930-6d4e-4d07-a4e0-b1fcc657e3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800404279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3800404279
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2502729897
Short name T737
Test name
Test status
Simulation time 57091806 ps
CPU time 0.85 seconds
Started Aug 01 07:00:57 PM PDT 24
Finished Aug 01 07:00:58 PM PDT 24
Peak memory 205952 kb
Host smart-62192239-0c39-4003-8c77-3b6662da520c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502729897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2502729897
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1782156624
Short name T420
Test name
Test status
Simulation time 192205882 ps
CPU time 3.84 seconds
Started Aug 01 07:00:57 PM PDT 24
Finished Aug 01 07:01:01 PM PDT 24
Peak memory 214928 kb
Host smart-0e09c98d-97ac-448c-881e-0c158c06df26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1782156624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1782156624
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1635337283
Short name T713
Test name
Test status
Simulation time 266211136 ps
CPU time 3.42 seconds
Started Aug 01 07:00:55 PM PDT 24
Finished Aug 01 07:00:58 PM PDT 24
Peak memory 222736 kb
Host smart-f8908185-84ea-4047-a7c0-1b64f0c1031e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635337283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1635337283
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2853723460
Short name T744
Test name
Test status
Simulation time 928965917 ps
CPU time 18.5 seconds
Started Aug 01 07:00:54 PM PDT 24
Finished Aug 01 07:01:13 PM PDT 24
Peak memory 214288 kb
Host smart-e3c12427-30d8-4472-8056-1e08f3b2dd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853723460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2853723460
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2294277210
Short name T856
Test name
Test status
Simulation time 850860675 ps
CPU time 5.4 seconds
Started Aug 01 07:00:54 PM PDT 24
Finished Aug 01 07:01:00 PM PDT 24
Peak memory 214276 kb
Host smart-8a3a7108-b803-4d9a-8134-01adff43671d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294277210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2294277210
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1686420318
Short name T239
Test name
Test status
Simulation time 51613205 ps
CPU time 3.02 seconds
Started Aug 01 07:00:54 PM PDT 24
Finished Aug 01 07:00:57 PM PDT 24
Peak memory 206148 kb
Host smart-db9ddc26-cebe-42b1-b95a-7a1811d7585c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686420318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1686420318
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1460660850
Short name T864
Test name
Test status
Simulation time 319234439 ps
CPU time 2.3 seconds
Started Aug 01 07:00:53 PM PDT 24
Finished Aug 01 07:00:56 PM PDT 24
Peak memory 219960 kb
Host smart-d25d1e99-efd9-43c1-8f1d-00783ad947f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460660850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1460660850
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.776576700
Short name T785
Test name
Test status
Simulation time 158714769 ps
CPU time 6.38 seconds
Started Aug 01 07:00:56 PM PDT 24
Finished Aug 01 07:01:02 PM PDT 24
Peak memory 222364 kb
Host smart-0a2a9117-901d-4488-9de7-699a4f37fa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776576700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.776576700
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3804022966
Short name T288
Test name
Test status
Simulation time 133181730 ps
CPU time 2.53 seconds
Started Aug 01 07:00:53 PM PDT 24
Finished Aug 01 07:00:56 PM PDT 24
Peak memory 208720 kb
Host smart-b0f96840-712b-4e2b-bcb5-ff87cba2c60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804022966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3804022966
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3308286574
Short name T454
Test name
Test status
Simulation time 38439217 ps
CPU time 2.21 seconds
Started Aug 01 07:00:59 PM PDT 24
Finished Aug 01 07:01:01 PM PDT 24
Peak memory 207052 kb
Host smart-c0c81347-036f-4d16-bede-ea32837255c2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308286574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3308286574
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.4003169137
Short name T841
Test name
Test status
Simulation time 37475700 ps
CPU time 1.72 seconds
Started Aug 01 07:00:55 PM PDT 24
Finished Aug 01 07:00:57 PM PDT 24
Peak memory 206820 kb
Host smart-5d14369f-e75d-4dfa-9ff7-e50b7c5712a3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003169137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.4003169137
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.66599904
Short name T882
Test name
Test status
Simulation time 95398840 ps
CPU time 2.86 seconds
Started Aug 01 07:00:55 PM PDT 24
Finished Aug 01 07:00:58 PM PDT 24
Peak memory 208560 kb
Host smart-8a831eeb-990d-4bc7-8ea5-066a58a94af6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66599904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.66599904
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2879779685
Short name T598
Test name
Test status
Simulation time 457194426 ps
CPU time 2.31 seconds
Started Aug 01 07:00:57 PM PDT 24
Finished Aug 01 07:00:59 PM PDT 24
Peak memory 207988 kb
Host smart-8a43e052-3865-4cd9-90bd-6478b1026077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879779685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2879779685
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2110804674
Short name T792
Test name
Test status
Simulation time 141971209 ps
CPU time 2.71 seconds
Started Aug 01 07:00:54 PM PDT 24
Finished Aug 01 07:00:57 PM PDT 24
Peak memory 208200 kb
Host smart-35a64713-88f6-4625-a9f1-bd7c6af9fd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110804674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2110804674
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1276137246
Short name T865
Test name
Test status
Simulation time 13645149751 ps
CPU time 83 seconds
Started Aug 01 07:00:55 PM PDT 24
Finished Aug 01 07:02:18 PM PDT 24
Peak memory 215168 kb
Host smart-cdacdb0f-1ed4-44d8-978a-77ecffe3608d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276137246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1276137246
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.2148076540
Short name T771
Test name
Test status
Simulation time 604716419 ps
CPU time 8.29 seconds
Started Aug 01 07:00:53 PM PDT 24
Finished Aug 01 07:01:02 PM PDT 24
Peak memory 219568 kb
Host smart-ac38dc2c-663c-4405-a870-89b4ca07a152
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148076540 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.2148076540
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3281977416
Short name T806
Test name
Test status
Simulation time 816679958 ps
CPU time 6.34 seconds
Started Aug 01 07:00:53 PM PDT 24
Finished Aug 01 07:00:59 PM PDT 24
Peak memory 214468 kb
Host smart-e2d579c4-bc0b-4f14-b01b-7d3a30adbcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281977416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3281977416
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3061882699
Short name T708
Test name
Test status
Simulation time 102142062 ps
CPU time 1.74 seconds
Started Aug 01 07:00:56 PM PDT 24
Finished Aug 01 07:00:58 PM PDT 24
Peak memory 209548 kb
Host smart-eb9fc516-7a2b-495b-8296-3a017a5e014e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061882699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3061882699
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3126329539
Short name T609
Test name
Test status
Simulation time 11548058 ps
CPU time 0.79 seconds
Started Aug 01 07:01:01 PM PDT 24
Finished Aug 01 07:01:02 PM PDT 24
Peak memory 205936 kb
Host smart-834b512e-50af-42be-8460-1cb4b30b640b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126329539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3126329539
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1613414811
Short name T337
Test name
Test status
Simulation time 1275820280 ps
CPU time 12.68 seconds
Started Aug 01 07:00:57 PM PDT 24
Finished Aug 01 07:01:10 PM PDT 24
Peak memory 215628 kb
Host smart-cc451c17-fbff-4150-beb7-b8063fa51839
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1613414811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1613414811
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3267018458
Short name T20
Test name
Test status
Simulation time 899445175 ps
CPU time 6.75 seconds
Started Aug 01 07:00:59 PM PDT 24
Finished Aug 01 07:01:06 PM PDT 24
Peak memory 214500 kb
Host smart-ae9c3a1e-fda0-40ec-bc08-647da04304a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267018458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3267018458
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2323605592
Short name T895
Test name
Test status
Simulation time 158023428 ps
CPU time 3.88 seconds
Started Aug 01 07:00:53 PM PDT 24
Finished Aug 01 07:00:57 PM PDT 24
Peak memory 210380 kb
Host smart-5bda4abe-5321-4b3b-885f-f68b5f298ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323605592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2323605592
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.4052357215
Short name T752
Test name
Test status
Simulation time 661815488 ps
CPU time 6.54 seconds
Started Aug 01 07:00:59 PM PDT 24
Finished Aug 01 07:01:06 PM PDT 24
Peak memory 214316 kb
Host smart-06f65bcd-36f3-48e9-aafd-4bbd9b4bcce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052357215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.4052357215
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2565033470
Short name T515
Test name
Test status
Simulation time 261442170 ps
CPU time 3.83 seconds
Started Aug 01 07:00:56 PM PDT 24
Finished Aug 01 07:01:00 PM PDT 24
Peak memory 220400 kb
Host smart-1776235b-fcb0-4411-9ab2-f000c5d28e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565033470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2565033470
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2236914080
Short name T380
Test name
Test status
Simulation time 66901608 ps
CPU time 3.89 seconds
Started Aug 01 07:00:54 PM PDT 24
Finished Aug 01 07:00:58 PM PDT 24
Peak memory 210016 kb
Host smart-82105251-5226-4e08-b8a4-fbf2d7484e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236914080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2236914080
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2973224853
Short name T731
Test name
Test status
Simulation time 1573090717 ps
CPU time 36.78 seconds
Started Aug 01 07:00:54 PM PDT 24
Finished Aug 01 07:01:32 PM PDT 24
Peak memory 208024 kb
Host smart-03c75a90-d23b-499b-bf04-10a2c25c9df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973224853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2973224853
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2290549600
Short name T487
Test name
Test status
Simulation time 1436733171 ps
CPU time 46.21 seconds
Started Aug 01 07:00:57 PM PDT 24
Finished Aug 01 07:01:43 PM PDT 24
Peak memory 208640 kb
Host smart-6c435f79-8add-4ea3-a446-4c6097230013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290549600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2290549600
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3823354832
Short name T76
Test name
Test status
Simulation time 78211582 ps
CPU time 1.73 seconds
Started Aug 01 07:00:56 PM PDT 24
Finished Aug 01 07:00:58 PM PDT 24
Peak memory 207012 kb
Host smart-7c35e043-11a9-493e-8a61-2a1e10f318e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823354832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3823354832
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2481436631
Short name T472
Test name
Test status
Simulation time 65222994 ps
CPU time 2.32 seconds
Started Aug 01 07:01:00 PM PDT 24
Finished Aug 01 07:01:02 PM PDT 24
Peak memory 206952 kb
Host smart-b10c0080-893f-4931-a4ff-94defdd7bb87
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481436631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2481436631
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.158638443
Short name T761
Test name
Test status
Simulation time 55423382 ps
CPU time 2.39 seconds
Started Aug 01 07:01:00 PM PDT 24
Finished Aug 01 07:01:02 PM PDT 24
Peak memory 209080 kb
Host smart-cef359a8-2a24-40a5-9535-ec0dae45dff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158638443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.158638443
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2308521573
Short name T617
Test name
Test status
Simulation time 556308192 ps
CPU time 5.69 seconds
Started Aug 01 07:00:54 PM PDT 24
Finished Aug 01 07:01:00 PM PDT 24
Peak memory 208508 kb
Host smart-1845b8cf-0fc2-4d12-a48d-91b619d8899c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308521573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2308521573
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3485550321
Short name T681
Test name
Test status
Simulation time 3349400103 ps
CPU time 24.19 seconds
Started Aug 01 07:00:55 PM PDT 24
Finished Aug 01 07:01:19 PM PDT 24
Peak memory 219260 kb
Host smart-36f62a9c-3675-4693-bafe-e91faf3e46b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485550321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3485550321
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.4181657145
Short name T592
Test name
Test status
Simulation time 1275230806 ps
CPU time 12.46 seconds
Started Aug 01 07:01:00 PM PDT 24
Finished Aug 01 07:01:13 PM PDT 24
Peak memory 222612 kb
Host smart-a431f125-47db-43fd-aed7-173dcb6039c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181657145 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.4181657145
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3884344999
Short name T374
Test name
Test status
Simulation time 7880622763 ps
CPU time 39.93 seconds
Started Aug 01 07:00:57 PM PDT 24
Finished Aug 01 07:01:37 PM PDT 24
Peak memory 219120 kb
Host smart-4311bc0a-984e-40ca-96b2-f1cf64e0eec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884344999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3884344999
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1533602333
Short name T827
Test name
Test status
Simulation time 219776691 ps
CPU time 2.77 seconds
Started Aug 01 07:00:55 PM PDT 24
Finished Aug 01 07:00:58 PM PDT 24
Peak memory 210452 kb
Host smart-505709ea-40e2-4945-9cf3-b28c8df10c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533602333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1533602333
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.4282503401
Short name T834
Test name
Test status
Simulation time 20514995 ps
CPU time 0.83 seconds
Started Aug 01 07:01:04 PM PDT 24
Finished Aug 01 07:01:05 PM PDT 24
Peak memory 205944 kb
Host smart-463be042-87b2-455c-b0b4-921520acbac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282503401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.4282503401
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1770082352
Short name T429
Test name
Test status
Simulation time 2598546881 ps
CPU time 35.79 seconds
Started Aug 01 07:00:58 PM PDT 24
Finished Aug 01 07:01:34 PM PDT 24
Peak memory 222568 kb
Host smart-e19c79b6-e9a8-4f8c-9585-1e7507e2893c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1770082352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1770082352
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1011488291
Short name T556
Test name
Test status
Simulation time 102115548 ps
CPU time 2.13 seconds
Started Aug 01 07:00:58 PM PDT 24
Finished Aug 01 07:01:00 PM PDT 24
Peak memory 216736 kb
Host smart-0707cd49-000c-4ece-a4a2-db610f776fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011488291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1011488291
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1208193336
Short name T34
Test name
Test status
Simulation time 1387974755 ps
CPU time 3.4 seconds
Started Aug 01 07:01:01 PM PDT 24
Finished Aug 01 07:01:04 PM PDT 24
Peak memory 209444 kb
Host smart-a9f42638-3967-405b-b2b3-eccec352e63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208193336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1208193336
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3369665719
Short name T702
Test name
Test status
Simulation time 139218316 ps
CPU time 3.46 seconds
Started Aug 01 07:00:58 PM PDT 24
Finished Aug 01 07:01:02 PM PDT 24
Peak memory 214320 kb
Host smart-bde13b21-bf41-4689-9f78-438182a8fe93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369665719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3369665719
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.4246812749
Short name T900
Test name
Test status
Simulation time 428114407 ps
CPU time 2.98 seconds
Started Aug 01 07:00:57 PM PDT 24
Finished Aug 01 07:01:00 PM PDT 24
Peak memory 207276 kb
Host smart-70780b73-d8ed-43e2-bb15-fc893f3c99c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246812749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.4246812749
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1101337403
Short name T421
Test name
Test status
Simulation time 551232233 ps
CPU time 3.13 seconds
Started Aug 01 07:01:00 PM PDT 24
Finished Aug 01 07:01:03 PM PDT 24
Peak memory 207348 kb
Host smart-d61f72ee-202f-465c-8e83-27879931c6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101337403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1101337403
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.4249535992
Short name T435
Test name
Test status
Simulation time 308249696 ps
CPU time 8.5 seconds
Started Aug 01 07:01:00 PM PDT 24
Finished Aug 01 07:01:09 PM PDT 24
Peak memory 207964 kb
Host smart-34c6bb41-ed6e-4924-9559-79e307cb2a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249535992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.4249535992
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1096570998
Short name T600
Test name
Test status
Simulation time 61775929 ps
CPU time 3.09 seconds
Started Aug 01 07:00:55 PM PDT 24
Finished Aug 01 07:00:58 PM PDT 24
Peak memory 208812 kb
Host smart-77cb38a9-861f-4283-a74c-8e2a16af1300
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096570998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1096570998
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2724138461
Short name T902
Test name
Test status
Simulation time 283641492 ps
CPU time 4 seconds
Started Aug 01 07:01:00 PM PDT 24
Finished Aug 01 07:01:05 PM PDT 24
Peak memory 208820 kb
Host smart-7603cb5b-cf48-4dc4-874e-3087751d4591
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724138461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2724138461
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2762857014
Short name T308
Test name
Test status
Simulation time 321130042 ps
CPU time 8.73 seconds
Started Aug 01 07:01:01 PM PDT 24
Finished Aug 01 07:01:09 PM PDT 24
Peak memory 208048 kb
Host smart-4a1beb89-36f2-40dc-99b0-7aa2cbbec55e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762857014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2762857014
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1139919798
Short name T873
Test name
Test status
Simulation time 147052852 ps
CPU time 3.82 seconds
Started Aug 01 07:01:08 PM PDT 24
Finished Aug 01 07:01:12 PM PDT 24
Peak memory 208896 kb
Host smart-d987e549-fcbd-4055-a4fc-8850b53a2c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139919798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1139919798
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1772044209
Short name T432
Test name
Test status
Simulation time 687637639 ps
CPU time 11.5 seconds
Started Aug 01 07:01:02 PM PDT 24
Finished Aug 01 07:01:13 PM PDT 24
Peak memory 207852 kb
Host smart-82dc235d-d856-4706-86a7-2fc8306b5707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772044209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1772044209
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1149273513
Short name T876
Test name
Test status
Simulation time 1822788933 ps
CPU time 22.51 seconds
Started Aug 01 07:01:04 PM PDT 24
Finished Aug 01 07:01:26 PM PDT 24
Peak memory 221792 kb
Host smart-53fea1af-c32f-4abd-ad59-30d5c5ec0c63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149273513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1149273513
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.4246491670
Short name T296
Test name
Test status
Simulation time 213434975 ps
CPU time 3.59 seconds
Started Aug 01 07:00:57 PM PDT 24
Finished Aug 01 07:01:01 PM PDT 24
Peak memory 218492 kb
Host smart-b8567001-4de8-4ca2-ba09-e4e88b9d8dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246491670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.4246491670
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.848358645
Short name T784
Test name
Test status
Simulation time 113262622 ps
CPU time 1.98 seconds
Started Aug 01 07:01:05 PM PDT 24
Finished Aug 01 07:01:07 PM PDT 24
Peak memory 210076 kb
Host smart-887cb47b-039c-40f4-a6fc-0441c1a127f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848358645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.848358645
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.4244281222
Short name T706
Test name
Test status
Simulation time 16860491 ps
CPU time 0.77 seconds
Started Aug 01 07:01:06 PM PDT 24
Finished Aug 01 07:01:07 PM PDT 24
Peak memory 205964 kb
Host smart-5655a00f-cea6-4c4f-8cf9-fded8bb92e05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244281222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.4244281222
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.542540320
Short name T845
Test name
Test status
Simulation time 248583721 ps
CPU time 2.04 seconds
Started Aug 01 07:01:05 PM PDT 24
Finished Aug 01 07:01:07 PM PDT 24
Peak memory 207904 kb
Host smart-68000837-ee15-4824-9dd9-2e5c776654d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542540320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.542540320
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1024120743
Short name T87
Test name
Test status
Simulation time 740446386 ps
CPU time 26.11 seconds
Started Aug 01 07:01:09 PM PDT 24
Finished Aug 01 07:01:35 PM PDT 24
Peak memory 214320 kb
Host smart-45109ada-2eb6-488d-987d-f92cb73a577e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024120743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1024120743
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.3209474918
Short name T361
Test name
Test status
Simulation time 181204919 ps
CPU time 3.42 seconds
Started Aug 01 07:01:05 PM PDT 24
Finished Aug 01 07:01:09 PM PDT 24
Peak memory 222460 kb
Host smart-1ae29fc1-8866-4c05-8559-d5b49fa6b480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209474918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3209474918
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.712942359
Short name T688
Test name
Test status
Simulation time 74317584 ps
CPU time 3.63 seconds
Started Aug 01 07:01:05 PM PDT 24
Finished Aug 01 07:01:09 PM PDT 24
Peak memory 216124 kb
Host smart-5f5083fe-4e96-48e8-a4f9-432887ffb155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712942359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.712942359
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.2771246534
Short name T350
Test name
Test status
Simulation time 995894761 ps
CPU time 31.58 seconds
Started Aug 01 07:01:04 PM PDT 24
Finished Aug 01 07:01:35 PM PDT 24
Peak memory 214396 kb
Host smart-3203f7af-f62a-4630-a790-1e7078f07e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771246534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2771246534
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1880017318
Short name T740
Test name
Test status
Simulation time 297580970 ps
CPU time 6.21 seconds
Started Aug 01 07:01:03 PM PDT 24
Finished Aug 01 07:01:09 PM PDT 24
Peak memory 207100 kb
Host smart-a6b9041f-85a9-4036-a28f-906f6e1f43bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880017318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1880017318
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3902692610
Short name T332
Test name
Test status
Simulation time 508724879 ps
CPU time 4.49 seconds
Started Aug 01 07:01:04 PM PDT 24
Finished Aug 01 07:01:09 PM PDT 24
Peak memory 206812 kb
Host smart-df53b7c4-ddcf-46c5-a135-96c24bb55db6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902692610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3902692610
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1141697165
Short name T271
Test name
Test status
Simulation time 128895353 ps
CPU time 2.98 seconds
Started Aug 01 07:01:06 PM PDT 24
Finished Aug 01 07:01:09 PM PDT 24
Peak memory 208468 kb
Host smart-e8cc0cb4-b847-4557-a0cf-4ac2d697f144
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141697165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1141697165
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.4138976434
Short name T886
Test name
Test status
Simulation time 729452693 ps
CPU time 5.15 seconds
Started Aug 01 07:01:05 PM PDT 24
Finished Aug 01 07:01:10 PM PDT 24
Peak memory 208532 kb
Host smart-29840031-fdf5-4836-87f6-c30a1e80283e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138976434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.4138976434
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2047447471
Short name T186
Test name
Test status
Simulation time 61956723 ps
CPU time 2.2 seconds
Started Aug 01 07:01:06 PM PDT 24
Finished Aug 01 07:01:08 PM PDT 24
Peak memory 207236 kb
Host smart-f2e4e1a1-02e6-407b-8e4d-2c0804c15838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047447471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2047447471
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3983592288
Short name T739
Test name
Test status
Simulation time 656018307 ps
CPU time 10.87 seconds
Started Aug 01 07:01:05 PM PDT 24
Finished Aug 01 07:01:16 PM PDT 24
Peak memory 208324 kb
Host smart-be026a68-9e5a-46a0-93f3-b4d703cfe6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983592288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3983592288
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2123596455
Short name T670
Test name
Test status
Simulation time 578956604 ps
CPU time 5.24 seconds
Started Aug 01 07:01:08 PM PDT 24
Finished Aug 01 07:01:13 PM PDT 24
Peak memory 207324 kb
Host smart-7a5a29fb-46e8-4ef4-b934-9b5dfef8700c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123596455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2123596455
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2273381229
Short name T166
Test name
Test status
Simulation time 624100577 ps
CPU time 3.02 seconds
Started Aug 01 07:01:10 PM PDT 24
Finished Aug 01 07:01:13 PM PDT 24
Peak memory 210100 kb
Host smart-9e29a143-f387-485a-83b6-1313b8e07187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273381229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2273381229
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2233463819
Short name T438
Test name
Test status
Simulation time 20116524 ps
CPU time 0.96 seconds
Started Aug 01 07:01:09 PM PDT 24
Finished Aug 01 07:01:10 PM PDT 24
Peak memory 206064 kb
Host smart-18834919-121b-4698-9945-dc1fabf39e3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233463819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2233463819
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3405611399
Short name T828
Test name
Test status
Simulation time 80650239 ps
CPU time 3.09 seconds
Started Aug 01 07:01:09 PM PDT 24
Finished Aug 01 07:01:13 PM PDT 24
Peak memory 222444 kb
Host smart-6c3513ad-85d2-45b3-8e2c-5e9a2eb4ef1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3405611399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3405611399
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.184323758
Short name T19
Test name
Test status
Simulation time 514284103 ps
CPU time 4.94 seconds
Started Aug 01 07:01:04 PM PDT 24
Finished Aug 01 07:01:09 PM PDT 24
Peak memory 214608 kb
Host smart-3118f9dd-5092-493a-8c38-5159edddc464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184323758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.184323758
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.956874290
Short name T68
Test name
Test status
Simulation time 891038544 ps
CPU time 16.54 seconds
Started Aug 01 07:01:09 PM PDT 24
Finished Aug 01 07:01:25 PM PDT 24
Peak memory 208424 kb
Host smart-ddfeac7c-75c0-44d3-a89b-ba82bc80ae83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956874290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.956874290
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3795029225
Short name T238
Test name
Test status
Simulation time 34254092 ps
CPU time 2.08 seconds
Started Aug 01 07:01:06 PM PDT 24
Finished Aug 01 07:01:08 PM PDT 24
Peak memory 214572 kb
Host smart-6bb48256-1825-42d3-8806-265d398bb351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795029225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3795029225
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3196101628
Short name T776
Test name
Test status
Simulation time 373308283 ps
CPU time 3.64 seconds
Started Aug 01 07:01:07 PM PDT 24
Finished Aug 01 07:01:11 PM PDT 24
Peak memory 214252 kb
Host smart-caa82615-655b-4f0c-b390-13c05b7bcc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196101628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3196101628
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2442863275
Short name T464
Test name
Test status
Simulation time 493819741 ps
CPU time 3.96 seconds
Started Aug 01 07:01:04 PM PDT 24
Finished Aug 01 07:01:08 PM PDT 24
Peak memory 214448 kb
Host smart-e4f30079-acd8-4378-a4fd-adf38c2911d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442863275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2442863275
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.3272221762
Short name T408
Test name
Test status
Simulation time 536060062 ps
CPU time 6.69 seconds
Started Aug 01 07:01:08 PM PDT 24
Finished Aug 01 07:01:15 PM PDT 24
Peak memory 208724 kb
Host smart-bd9b12d3-ab4d-4741-915a-f6ab2713706c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272221762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3272221762
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1093237716
Short name T802
Test name
Test status
Simulation time 166156918 ps
CPU time 6.45 seconds
Started Aug 01 07:01:08 PM PDT 24
Finished Aug 01 07:01:15 PM PDT 24
Peak memory 207864 kb
Host smart-b73d1d1b-fed5-45c9-841c-d560e3c029f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093237716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1093237716
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1419227918
Short name T519
Test name
Test status
Simulation time 494943937 ps
CPU time 3.99 seconds
Started Aug 01 07:01:03 PM PDT 24
Finished Aug 01 07:01:08 PM PDT 24
Peak memory 208640 kb
Host smart-9b01bc9c-1d68-46a9-8286-4440683d9b75
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419227918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1419227918
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.941715458
Short name T585
Test name
Test status
Simulation time 1495351062 ps
CPU time 5.32 seconds
Started Aug 01 07:01:08 PM PDT 24
Finished Aug 01 07:01:14 PM PDT 24
Peak memory 208664 kb
Host smart-4c23af94-1b60-45f6-9ff4-903eeee715f9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941715458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.941715458
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3142726519
Short name T837
Test name
Test status
Simulation time 1643543500 ps
CPU time 22.62 seconds
Started Aug 01 07:01:04 PM PDT 24
Finished Aug 01 07:01:27 PM PDT 24
Peak memory 208132 kb
Host smart-89eb9ea7-c88d-4827-be1c-6b6b332ced32
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142726519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3142726519
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3303064374
Short name T97
Test name
Test status
Simulation time 476180633 ps
CPU time 5.87 seconds
Started Aug 01 07:01:09 PM PDT 24
Finished Aug 01 07:01:15 PM PDT 24
Peak memory 214412 kb
Host smart-4f7ae28a-a694-4a2d-b1c1-83c350789545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303064374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3303064374
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2083545276
Short name T696
Test name
Test status
Simulation time 317556247 ps
CPU time 4.86 seconds
Started Aug 01 07:01:10 PM PDT 24
Finished Aug 01 07:01:15 PM PDT 24
Peak memory 208804 kb
Host smart-be73c5a7-15be-46ce-9e59-981bbba49c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083545276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2083545276
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.1780863545
Short name T53
Test name
Test status
Simulation time 888837680 ps
CPU time 22.29 seconds
Started Aug 01 07:01:05 PM PDT 24
Finished Aug 01 07:01:27 PM PDT 24
Peak memory 221400 kb
Host smart-3245f4a1-0543-482b-8675-b37ed426e979
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780863545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.1780863545
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1558813215
Short name T176
Test name
Test status
Simulation time 1970431209 ps
CPU time 21.13 seconds
Started Aug 01 07:01:04 PM PDT 24
Finished Aug 01 07:01:25 PM PDT 24
Peak memory 222668 kb
Host smart-22391a21-a004-4716-b412-2c13dc82170f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558813215 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.1558813215
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.4026362010
Short name T26
Test name
Test status
Simulation time 101123124 ps
CPU time 3.32 seconds
Started Aug 01 07:01:08 PM PDT 24
Finished Aug 01 07:01:11 PM PDT 24
Peak memory 214296 kb
Host smart-2752eeb5-7561-446f-ac63-f4b59232aeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026362010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.4026362010
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.928995362
Short name T626
Test name
Test status
Simulation time 89410217 ps
CPU time 1.74 seconds
Started Aug 01 07:01:05 PM PDT 24
Finished Aug 01 07:01:07 PM PDT 24
Peak memory 210276 kb
Host smart-cdae9ebe-a54b-4f8a-b44a-562b2ab7653c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928995362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.928995362
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.750579678
Short name T893
Test name
Test status
Simulation time 15087353 ps
CPU time 0.88 seconds
Started Aug 01 07:01:06 PM PDT 24
Finished Aug 01 07:01:07 PM PDT 24
Peak memory 206124 kb
Host smart-2b45233f-bcf0-44d9-ba39-7b97b471da68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750579678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.750579678
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3616454273
Short name T127
Test name
Test status
Simulation time 1159356667 ps
CPU time 9.52 seconds
Started Aug 01 07:01:18 PM PDT 24
Finished Aug 01 07:01:28 PM PDT 24
Peak memory 215684 kb
Host smart-c15c549e-cd92-4c38-a6cb-839fac4c1480
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3616454273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3616454273
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3188108028
Short name T29
Test name
Test status
Simulation time 339516599 ps
CPU time 7.11 seconds
Started Aug 01 07:01:18 PM PDT 24
Finished Aug 01 07:01:25 PM PDT 24
Peak memory 210012 kb
Host smart-4205b40f-f91e-4ba2-a866-5d1926723225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188108028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3188108028
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3646741803
Short name T318
Test name
Test status
Simulation time 1145864645 ps
CPU time 10.83 seconds
Started Aug 01 07:01:07 PM PDT 24
Finished Aug 01 07:01:18 PM PDT 24
Peak memory 213316 kb
Host smart-52b8df30-7d45-411c-a250-5d04aa530563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646741803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3646741803
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3217586739
Short name T85
Test name
Test status
Simulation time 846442737 ps
CPU time 6.71 seconds
Started Aug 01 07:01:13 PM PDT 24
Finished Aug 01 07:01:20 PM PDT 24
Peak memory 214280 kb
Host smart-86a9acab-6a50-4b0c-b113-8a95ca4ff49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217586739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3217586739
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2216074342
Short name T814
Test name
Test status
Simulation time 160970415 ps
CPU time 1.68 seconds
Started Aug 01 07:01:18 PM PDT 24
Finished Aug 01 07:01:20 PM PDT 24
Peak memory 207280 kb
Host smart-e40b38af-37fe-4a12-a048-87c85f1d467b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216074342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2216074342
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3430806019
Short name T844
Test name
Test status
Simulation time 45253210 ps
CPU time 3.03 seconds
Started Aug 01 07:01:07 PM PDT 24
Finished Aug 01 07:01:10 PM PDT 24
Peak memory 207388 kb
Host smart-c57d449c-cbf5-4530-8eb5-66ec19618fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430806019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3430806019
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3536684172
Short name T813
Test name
Test status
Simulation time 102176824 ps
CPU time 2.14 seconds
Started Aug 01 07:01:09 PM PDT 24
Finished Aug 01 07:01:11 PM PDT 24
Peak memory 208680 kb
Host smart-c189f6c5-5c9d-4dc1-a654-7b1b847019a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536684172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3536684172
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.974903741
Short name T203
Test name
Test status
Simulation time 82651384 ps
CPU time 3.02 seconds
Started Aug 01 07:01:10 PM PDT 24
Finished Aug 01 07:01:13 PM PDT 24
Peak memory 206784 kb
Host smart-850665cb-bdb5-4955-890c-7e93065f2d0b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974903741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.974903741
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.80642405
Short name T881
Test name
Test status
Simulation time 185002764 ps
CPU time 2.67 seconds
Started Aug 01 07:01:18 PM PDT 24
Finished Aug 01 07:01:21 PM PDT 24
Peak memory 208768 kb
Host smart-8fcff941-6199-4457-931c-9193048a703d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80642405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.80642405
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1190556651
Short name T460
Test name
Test status
Simulation time 93986530 ps
CPU time 3.37 seconds
Started Aug 01 07:01:09 PM PDT 24
Finished Aug 01 07:01:12 PM PDT 24
Peak memory 206940 kb
Host smart-6ff27da9-b0a9-41ec-bdf2-61d4e0858622
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190556651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1190556651
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3690328137
Short name T463
Test name
Test status
Simulation time 494772640 ps
CPU time 6.49 seconds
Started Aug 01 07:01:18 PM PDT 24
Finished Aug 01 07:01:25 PM PDT 24
Peak memory 218376 kb
Host smart-a6bce50b-e1c4-4c1b-9228-6a9c561f2fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690328137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3690328137
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.4105334180
Short name T830
Test name
Test status
Simulation time 88212888 ps
CPU time 2.12 seconds
Started Aug 01 07:01:08 PM PDT 24
Finished Aug 01 07:01:11 PM PDT 24
Peak memory 206072 kb
Host smart-9c5d078c-a0c1-4749-8ff5-a965322b2e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105334180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.4105334180
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.2991867913
Short name T366
Test name
Test status
Simulation time 688019743 ps
CPU time 24.86 seconds
Started Aug 01 07:01:07 PM PDT 24
Finished Aug 01 07:01:32 PM PDT 24
Peak memory 222492 kb
Host smart-f84383ea-6e2c-4d2b-a043-45af3d810bff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991867913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2991867913
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2781566185
Short name T711
Test name
Test status
Simulation time 158646740 ps
CPU time 4.62 seconds
Started Aug 01 07:01:07 PM PDT 24
Finished Aug 01 07:01:12 PM PDT 24
Peak memory 209120 kb
Host smart-c4a7dccd-15ff-4336-83da-61c933cdbe9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781566185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2781566185
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1914542337
Short name T96
Test name
Test status
Simulation time 101214837 ps
CPU time 1.59 seconds
Started Aug 01 07:01:18 PM PDT 24
Finished Aug 01 07:01:20 PM PDT 24
Peak memory 208400 kb
Host smart-4d1a3f6e-9cad-4efc-99dd-1a38512c4526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914542337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1914542337
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2600368567
Short name T543
Test name
Test status
Simulation time 16439946 ps
CPU time 0.75 seconds
Started Aug 01 07:01:25 PM PDT 24
Finished Aug 01 07:01:26 PM PDT 24
Peak memory 205944 kb
Host smart-6e708224-3665-45a8-bc12-c4832cf06a2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600368567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2600368567
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2628979059
Short name T416
Test name
Test status
Simulation time 1204783916 ps
CPU time 6.9 seconds
Started Aug 01 07:01:07 PM PDT 24
Finished Aug 01 07:01:14 PM PDT 24
Peak memory 213616 kb
Host smart-ab0d49ff-da86-4d97-89c7-582165e1d03b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2628979059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2628979059
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.90852418
Short name T645
Test name
Test status
Simulation time 96988233 ps
CPU time 3.96 seconds
Started Aug 01 07:01:17 PM PDT 24
Finished Aug 01 07:01:21 PM PDT 24
Peak memory 214552 kb
Host smart-e27cc95e-f02f-4b8f-b11a-335f05813a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90852418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.90852418
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3417407520
Short name T352
Test name
Test status
Simulation time 115403295 ps
CPU time 2.3 seconds
Started Aug 01 07:01:13 PM PDT 24
Finished Aug 01 07:01:15 PM PDT 24
Peak memory 207376 kb
Host smart-1013b14d-d862-4abd-ac48-6419377b23bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417407520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3417407520
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.4276916758
Short name T48
Test name
Test status
Simulation time 640710469 ps
CPU time 3.51 seconds
Started Aug 01 07:01:20 PM PDT 24
Finished Aug 01 07:01:23 PM PDT 24
Peak memory 214360 kb
Host smart-8c6eb94e-da7a-4691-bfe4-7a75bd970919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276916758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.4276916758
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2414391172
Short name T707
Test name
Test status
Simulation time 86167581 ps
CPU time 2.89 seconds
Started Aug 01 07:01:30 PM PDT 24
Finished Aug 01 07:01:33 PM PDT 24
Peak memory 214276 kb
Host smart-62afad63-6a39-41a5-bfab-c564673fdded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414391172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2414391172
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.1942248441
Short name T624
Test name
Test status
Simulation time 472452324 ps
CPU time 4.46 seconds
Started Aug 01 07:01:20 PM PDT 24
Finished Aug 01 07:01:25 PM PDT 24
Peak memory 210796 kb
Host smart-2edcdc7b-30b0-4d60-8ea8-e4a0d5266995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942248441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1942248441
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1374963873
Short name T691
Test name
Test status
Simulation time 148673498 ps
CPU time 4.64 seconds
Started Aug 01 07:01:13 PM PDT 24
Finished Aug 01 07:01:17 PM PDT 24
Peak memory 214292 kb
Host smart-f7451e7d-14ba-4f59-92f3-06d48b05a058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374963873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1374963873
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1604884128
Short name T676
Test name
Test status
Simulation time 297240693 ps
CPU time 2.92 seconds
Started Aug 01 07:01:12 PM PDT 24
Finished Aug 01 07:01:15 PM PDT 24
Peak memory 208580 kb
Host smart-ff680698-15e9-47e0-ad46-75a575941251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604884128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1604884128
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1955898279
Short name T810
Test name
Test status
Simulation time 888324348 ps
CPU time 6.28 seconds
Started Aug 01 07:01:08 PM PDT 24
Finished Aug 01 07:01:15 PM PDT 24
Peak memory 207868 kb
Host smart-20d5f149-66a7-4201-be6c-001599a79103
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955898279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1955898279
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1761418136
Short name T727
Test name
Test status
Simulation time 492863142 ps
CPU time 5.81 seconds
Started Aug 01 07:01:12 PM PDT 24
Finished Aug 01 07:01:18 PM PDT 24
Peak memory 208320 kb
Host smart-24a4aad9-41be-4b27-8fef-a3927e6ef629
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761418136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1761418136
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1074001490
Short name T439
Test name
Test status
Simulation time 112903498 ps
CPU time 3.5 seconds
Started Aug 01 07:01:13 PM PDT 24
Finished Aug 01 07:01:16 PM PDT 24
Peak memory 208360 kb
Host smart-9be77b5b-eb6a-418f-ae1d-eff7dc39a626
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074001490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1074001490
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1727858119
Short name T615
Test name
Test status
Simulation time 338562014 ps
CPU time 4.05 seconds
Started Aug 01 07:01:17 PM PDT 24
Finished Aug 01 07:01:21 PM PDT 24
Peak memory 214320 kb
Host smart-7bc33534-6dba-4c78-8fb6-a81b1cef7325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727858119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1727858119
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3074294482
Short name T710
Test name
Test status
Simulation time 692014757 ps
CPU time 8.88 seconds
Started Aug 01 07:01:07 PM PDT 24
Finished Aug 01 07:01:16 PM PDT 24
Peak memory 207020 kb
Host smart-27bd381c-9560-44f3-95ea-eb42cc547494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074294482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3074294482
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.19825947
Short name T664
Test name
Test status
Simulation time 124532304 ps
CPU time 4.82 seconds
Started Aug 01 07:01:18 PM PDT 24
Finished Aug 01 07:01:23 PM PDT 24
Peak memory 214320 kb
Host smart-83ccc8de-707a-4c4a-8eb1-0ef955cbc50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19825947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.19825947
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.1354153494
Short name T169
Test name
Test status
Simulation time 562762372 ps
CPU time 3.42 seconds
Started Aug 01 07:01:16 PM PDT 24
Finished Aug 01 07:01:20 PM PDT 24
Peak memory 210248 kb
Host smart-d99c7c41-4b48-4e58-84ab-93ad30b00859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354153494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.1354153494
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.755832593
Short name T441
Test name
Test status
Simulation time 17335711 ps
CPU time 0.79 seconds
Started Aug 01 06:59:20 PM PDT 24
Finished Aug 01 06:59:21 PM PDT 24
Peak memory 205952 kb
Host smart-c9db023c-f6a8-4e9d-a575-4e6d1b42ee35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755832593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.755832593
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3588028299
Short name T174
Test name
Test status
Simulation time 358245560 ps
CPU time 3.89 seconds
Started Aug 01 06:59:19 PM PDT 24
Finished Aug 01 06:59:23 PM PDT 24
Peak memory 208556 kb
Host smart-0c8060a5-e662-4703-a20e-90b6058507fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588028299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3588028299
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.651807030
Short name T603
Test name
Test status
Simulation time 75216223 ps
CPU time 1.71 seconds
Started Aug 01 06:59:21 PM PDT 24
Finished Aug 01 06:59:23 PM PDT 24
Peak memory 214300 kb
Host smart-36e073ca-e477-4b9d-b48b-fd8d5b0b049f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651807030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.651807030
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.165962666
Short name T47
Test name
Test status
Simulation time 74048086 ps
CPU time 2.46 seconds
Started Aug 01 06:59:24 PM PDT 24
Finished Aug 01 06:59:26 PM PDT 24
Peak memory 215568 kb
Host smart-ee81111c-6633-4591-9ef5-62a2bd86102c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165962666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.165962666
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3280482271
Short name T906
Test name
Test status
Simulation time 140176502 ps
CPU time 2.75 seconds
Started Aug 01 06:59:20 PM PDT 24
Finished Aug 01 06:59:23 PM PDT 24
Peak memory 214248 kb
Host smart-0536ff4f-fdbc-49e5-b766-62666cdba48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280482271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3280482271
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3747578298
Short name T411
Test name
Test status
Simulation time 578018099 ps
CPU time 3.57 seconds
Started Aug 01 06:59:19 PM PDT 24
Finished Aug 01 06:59:22 PM PDT 24
Peak memory 209384 kb
Host smart-07404b72-a5bc-4b22-a98f-936895d7ea55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747578298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3747578298
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.101653692
Short name T345
Test name
Test status
Simulation time 1240935224 ps
CPU time 6.95 seconds
Started Aug 01 06:59:18 PM PDT 24
Finished Aug 01 06:59:25 PM PDT 24
Peak memory 214320 kb
Host smart-5030b236-1b73-4327-a082-f78031a4ac0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101653692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.101653692
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1910688030
Short name T8
Test name
Test status
Simulation time 766270315 ps
CPU time 6.62 seconds
Started Aug 01 06:59:23 PM PDT 24
Finished Aug 01 06:59:30 PM PDT 24
Peak memory 230516 kb
Host smart-f4142fd8-6ecd-4dcf-a39e-cffcafc359c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910688030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1910688030
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1538654589
Short name T887
Test name
Test status
Simulation time 164724744 ps
CPU time 3.75 seconds
Started Aug 01 06:59:20 PM PDT 24
Finished Aug 01 06:59:24 PM PDT 24
Peak memory 208848 kb
Host smart-3ffada50-c34d-4d61-9c7c-3cca645fdea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538654589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1538654589
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1759591465
Short name T611
Test name
Test status
Simulation time 244115635 ps
CPU time 3.26 seconds
Started Aug 01 06:59:21 PM PDT 24
Finished Aug 01 06:59:25 PM PDT 24
Peak memory 206984 kb
Host smart-efabe5a6-d3d6-404a-bbe6-9755542099e4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759591465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1759591465
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.98052439
Short name T589
Test name
Test status
Simulation time 90520718 ps
CPU time 3.77 seconds
Started Aug 01 06:59:21 PM PDT 24
Finished Aug 01 06:59:25 PM PDT 24
Peak memory 208504 kb
Host smart-eef9f447-15d2-4a6b-8cb0-edbbe4e1cc60
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98052439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.98052439
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.814789889
Short name T718
Test name
Test status
Simulation time 70758232 ps
CPU time 2.45 seconds
Started Aug 01 06:59:21 PM PDT 24
Finished Aug 01 06:59:24 PM PDT 24
Peak memory 207580 kb
Host smart-b23d09a4-1af0-4337-aa7a-1650ea7329b5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814789889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.814789889
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.4009934697
Short name T309
Test name
Test status
Simulation time 1149316698 ps
CPU time 20.72 seconds
Started Aug 01 06:59:21 PM PDT 24
Finished Aug 01 06:59:42 PM PDT 24
Peak memory 218604 kb
Host smart-fdaea613-3ddb-46ff-9f65-671f85618754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009934697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.4009934697
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3472985455
Short name T554
Test name
Test status
Simulation time 260482618 ps
CPU time 3.77 seconds
Started Aug 01 06:59:19 PM PDT 24
Finished Aug 01 06:59:23 PM PDT 24
Peak memory 208528 kb
Host smart-172ff219-0514-4ce5-8cce-442fb3da8232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472985455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3472985455
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.31090192
Short name T329
Test name
Test status
Simulation time 823286837 ps
CPU time 5.66 seconds
Started Aug 01 06:59:19 PM PDT 24
Finished Aug 01 06:59:25 PM PDT 24
Peak memory 209808 kb
Host smart-f19106e7-c62f-417b-a4fe-55ac7c16569a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31090192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.31090192
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2120067489
Short name T103
Test name
Test status
Simulation time 484572749 ps
CPU time 10.06 seconds
Started Aug 01 06:59:21 PM PDT 24
Finished Aug 01 06:59:32 PM PDT 24
Peak memory 210588 kb
Host smart-7628f0af-5f4d-4127-acad-014f03cf70ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120067489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2120067489
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1337698150
Short name T627
Test name
Test status
Simulation time 24136434 ps
CPU time 0.88 seconds
Started Aug 01 07:01:18 PM PDT 24
Finished Aug 01 07:01:19 PM PDT 24
Peak memory 205964 kb
Host smart-0b121d7a-8910-46a1-9389-e5714e66e278
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337698150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1337698150
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1695072023
Short name T360
Test name
Test status
Simulation time 171552228 ps
CPU time 9.45 seconds
Started Aug 01 07:01:20 PM PDT 24
Finished Aug 01 07:01:29 PM PDT 24
Peak memory 215456 kb
Host smart-b2cf673b-2a80-4518-8db2-e2c7b0587cbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1695072023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1695072023
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2975635262
Short name T724
Test name
Test status
Simulation time 78909695 ps
CPU time 3.11 seconds
Started Aug 01 07:01:30 PM PDT 24
Finished Aug 01 07:01:33 PM PDT 24
Peak memory 208732 kb
Host smart-abf6a124-be4a-446a-a197-2f88a07a399f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975635262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2975635262
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.754016454
Short name T72
Test name
Test status
Simulation time 100927804 ps
CPU time 2.54 seconds
Started Aug 01 07:01:19 PM PDT 24
Finished Aug 01 07:01:21 PM PDT 24
Peak memory 209756 kb
Host smart-db6f876c-c221-4989-9e88-fee418fd8f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754016454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.754016454
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1988717820
Short name T909
Test name
Test status
Simulation time 242887597 ps
CPU time 5.71 seconds
Started Aug 01 07:01:15 PM PDT 24
Finished Aug 01 07:01:21 PM PDT 24
Peak memory 214316 kb
Host smart-d58f436c-baed-4655-a827-ffa60d12b39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988717820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1988717820
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.928141140
Short name T319
Test name
Test status
Simulation time 262947925 ps
CPU time 2.53 seconds
Started Aug 01 07:01:19 PM PDT 24
Finished Aug 01 07:01:22 PM PDT 24
Peak memory 206260 kb
Host smart-c49f5ddd-0f8d-46ed-b25c-b229fea17b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928141140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.928141140
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.376362315
Short name T64
Test name
Test status
Simulation time 500185265 ps
CPU time 5.44 seconds
Started Aug 01 07:01:17 PM PDT 24
Finished Aug 01 07:01:22 PM PDT 24
Peak memory 214280 kb
Host smart-59558434-51fb-4296-b763-20c27d20f68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376362315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.376362315
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1108500902
Short name T477
Test name
Test status
Simulation time 195689469 ps
CPU time 3.14 seconds
Started Aug 01 07:01:25 PM PDT 24
Finished Aug 01 07:01:29 PM PDT 24
Peak memory 209084 kb
Host smart-5b4df9fe-2317-4e48-98e8-3c9a64b70732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108500902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1108500902
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1514245626
Short name T572
Test name
Test status
Simulation time 157353835 ps
CPU time 3.81 seconds
Started Aug 01 07:01:19 PM PDT 24
Finished Aug 01 07:01:23 PM PDT 24
Peak memory 208740 kb
Host smart-8ca5cc44-1250-4c7e-8315-be543fa25135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514245626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1514245626
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.878067745
Short name T848
Test name
Test status
Simulation time 122378835 ps
CPU time 3.77 seconds
Started Aug 01 07:01:18 PM PDT 24
Finished Aug 01 07:01:22 PM PDT 24
Peak memory 206760 kb
Host smart-e3c96f3a-9304-4ee2-9354-2eb6e546d6e5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878067745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.878067745
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.108945362
Short name T596
Test name
Test status
Simulation time 548386414 ps
CPU time 7.01 seconds
Started Aug 01 07:01:26 PM PDT 24
Finished Aug 01 07:01:33 PM PDT 24
Peak memory 208120 kb
Host smart-d69a0cc2-178c-4947-b61b-9e8312c44d31
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108945362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.108945362
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.3524318923
Short name T406
Test name
Test status
Simulation time 38922663 ps
CPU time 2.22 seconds
Started Aug 01 07:01:16 PM PDT 24
Finished Aug 01 07:01:18 PM PDT 24
Peak memory 206884 kb
Host smart-51fcdc41-ef76-4b16-840e-5f9dcc9bce64
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524318923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.3524318923
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2449021833
Short name T230
Test name
Test status
Simulation time 186510708 ps
CPU time 3.78 seconds
Started Aug 01 07:01:25 PM PDT 24
Finished Aug 01 07:01:29 PM PDT 24
Peak memory 209776 kb
Host smart-c12d0d38-fe70-4c36-a6a8-1f96302ded1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449021833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2449021833
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.607648731
Short name T185
Test name
Test status
Simulation time 125303361 ps
CPU time 2.16 seconds
Started Aug 01 07:01:18 PM PDT 24
Finished Aug 01 07:01:20 PM PDT 24
Peak memory 207424 kb
Host smart-faf89bac-3ff6-47b8-a907-c088eca2a179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607648731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.607648731
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3526498799
Short name T216
Test name
Test status
Simulation time 4774853076 ps
CPU time 49.62 seconds
Started Aug 01 07:01:15 PM PDT 24
Finished Aug 01 07:02:05 PM PDT 24
Peak memory 215184 kb
Host smart-647cbaad-5d84-4c8d-b092-6144ad38bb6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526498799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3526498799
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.3808637585
Short name T267
Test name
Test status
Simulation time 548192028 ps
CPU time 15.33 seconds
Started Aug 01 07:01:25 PM PDT 24
Finished Aug 01 07:01:41 PM PDT 24
Peak memory 222400 kb
Host smart-89626861-b244-4a26-b579-0c3c7b5985ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808637585 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.3808637585
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3772308354
Short name T807
Test name
Test status
Simulation time 1198804629 ps
CPU time 3.77 seconds
Started Aug 01 07:01:17 PM PDT 24
Finished Aug 01 07:01:21 PM PDT 24
Peak memory 208100 kb
Host smart-f56ec2e6-ab8b-4276-ad41-b05354f4d01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772308354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3772308354
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3842113979
Short name T386
Test name
Test status
Simulation time 297171507 ps
CPU time 3.07 seconds
Started Aug 01 07:01:19 PM PDT 24
Finished Aug 01 07:01:22 PM PDT 24
Peak memory 210340 kb
Host smart-ae595c68-36e6-4601-b58d-de2f9db541ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842113979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3842113979
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.1117059165
Short name T522
Test name
Test status
Simulation time 15532333 ps
CPU time 0.9 seconds
Started Aug 01 07:01:30 PM PDT 24
Finished Aug 01 07:01:31 PM PDT 24
Peak memory 206120 kb
Host smart-088f1625-2e76-49fc-9f8e-859cb984f648
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117059165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1117059165
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1834265293
Short name T822
Test name
Test status
Simulation time 258968812 ps
CPU time 3.37 seconds
Started Aug 01 07:01:17 PM PDT 24
Finished Aug 01 07:01:20 PM PDT 24
Peak memory 221520 kb
Host smart-f638cc9a-e0be-453d-861b-ec13db8627f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834265293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1834265293
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.341647474
Short name T67
Test name
Test status
Simulation time 720416323 ps
CPU time 5.54 seconds
Started Aug 01 07:01:29 PM PDT 24
Finished Aug 01 07:01:35 PM PDT 24
Peak memory 210392 kb
Host smart-c34acbc3-fdbb-4631-9a58-9fb95a796d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341647474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.341647474
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2319099425
Short name T356
Test name
Test status
Simulation time 60310598 ps
CPU time 1.96 seconds
Started Aug 01 07:01:31 PM PDT 24
Finished Aug 01 07:01:33 PM PDT 24
Peak memory 214336 kb
Host smart-2cae59f1-d8da-46df-a0c1-4d30c5ed81ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319099425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2319099425
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.431025502
Short name T1
Test name
Test status
Simulation time 66249282 ps
CPU time 3.18 seconds
Started Aug 01 07:01:17 PM PDT 24
Finished Aug 01 07:01:20 PM PDT 24
Peak memory 222340 kb
Host smart-95d60308-598c-4f73-931d-c29987197044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431025502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.431025502
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3300890990
Short name T910
Test name
Test status
Simulation time 70907561 ps
CPU time 3.79 seconds
Started Aug 01 07:01:18 PM PDT 24
Finished Aug 01 07:01:22 PM PDT 24
Peak memory 220120 kb
Host smart-1a39819a-fecd-43df-8b90-9352b56f58d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300890990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3300890990
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1991368941
Short name T671
Test name
Test status
Simulation time 322737351 ps
CPU time 6.73 seconds
Started Aug 01 07:01:17 PM PDT 24
Finished Aug 01 07:01:24 PM PDT 24
Peak memory 215188 kb
Host smart-3dd33fed-a7ef-46eb-952d-2ae9cd337330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991368941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1991368941
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.801052951
Short name T306
Test name
Test status
Simulation time 675936035 ps
CPU time 19 seconds
Started Aug 01 07:01:18 PM PDT 24
Finished Aug 01 07:01:37 PM PDT 24
Peak memory 208664 kb
Host smart-30d6cc4f-9fea-43b2-bc67-3b838f50ae33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801052951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.801052951
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.4071297216
Short name T544
Test name
Test status
Simulation time 774767176 ps
CPU time 13.88 seconds
Started Aug 01 07:01:17 PM PDT 24
Finished Aug 01 07:01:31 PM PDT 24
Peak memory 208384 kb
Host smart-435b1da5-6aa6-43bc-99cc-15f9ad10fec6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071297216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.4071297216
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.4161350343
Short name T871
Test name
Test status
Simulation time 120533038 ps
CPU time 2.24 seconds
Started Aug 01 07:01:31 PM PDT 24
Finished Aug 01 07:01:34 PM PDT 24
Peak memory 206984 kb
Host smart-ba4b37d8-6522-459e-a8ee-dbb98d393924
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161350343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.4161350343
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3958248090
Short name T580
Test name
Test status
Simulation time 85980098 ps
CPU time 2.55 seconds
Started Aug 01 07:01:17 PM PDT 24
Finished Aug 01 07:01:20 PM PDT 24
Peak memory 206796 kb
Host smart-87ca14fc-e2ab-42c8-a999-8e3bde889266
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958248090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3958248090
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2854391867
Short name T294
Test name
Test status
Simulation time 112421274 ps
CPU time 4.33 seconds
Started Aug 01 07:01:18 PM PDT 24
Finished Aug 01 07:01:23 PM PDT 24
Peak memory 209324 kb
Host smart-18c145ad-6a09-4a6b-bc32-e1a3b5c807ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854391867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2854391867
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2209846794
Short name T610
Test name
Test status
Simulation time 89900242 ps
CPU time 3.11 seconds
Started Aug 01 07:01:17 PM PDT 24
Finished Aug 01 07:01:20 PM PDT 24
Peak memory 208712 kb
Host smart-b198de79-6a0c-4e2a-965d-be302942ae58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209846794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2209846794
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.949441611
Short name T291
Test name
Test status
Simulation time 781624489 ps
CPU time 20.87 seconds
Started Aug 01 07:01:18 PM PDT 24
Finished Aug 01 07:01:39 PM PDT 24
Peak memory 216408 kb
Host smart-3ea20e0c-b941-4c67-ba83-6a71323157cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949441611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.949441611
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.4006012273
Short name T115
Test name
Test status
Simulation time 847303218 ps
CPU time 13.49 seconds
Started Aug 01 07:01:15 PM PDT 24
Finished Aug 01 07:01:29 PM PDT 24
Peak memory 220448 kb
Host smart-47f2848e-85e4-4f57-a689-dbbe6a53d037
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006012273 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.4006012273
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1666420531
Short name T762
Test name
Test status
Simulation time 116581815 ps
CPU time 5.15 seconds
Started Aug 01 07:01:31 PM PDT 24
Finished Aug 01 07:01:37 PM PDT 24
Peak memory 214304 kb
Host smart-cc2d8716-cd73-4cdd-bb48-50a770ca6d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666420531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1666420531
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2354998975
Short name T791
Test name
Test status
Simulation time 140249514 ps
CPU time 1.66 seconds
Started Aug 01 07:01:31 PM PDT 24
Finished Aug 01 07:01:33 PM PDT 24
Peak memory 209596 kb
Host smart-c22aef86-4a2a-4365-9aa8-d75a4daf3473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354998975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2354998975
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2751088179
Short name T891
Test name
Test status
Simulation time 27618394 ps
CPU time 0.79 seconds
Started Aug 01 07:01:31 PM PDT 24
Finished Aug 01 07:01:32 PM PDT 24
Peak memory 205976 kb
Host smart-2789ff7d-9297-4d0e-adc6-bbe5705dfdeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751088179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2751088179
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2425604357
Short name T124
Test name
Test status
Simulation time 130446562 ps
CPU time 2.68 seconds
Started Aug 01 07:01:30 PM PDT 24
Finished Aug 01 07:01:32 PM PDT 24
Peak memory 214316 kb
Host smart-bc8d488b-3147-4ee3-b700-05a970760a92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2425604357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2425604357
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.684410705
Short name T840
Test name
Test status
Simulation time 175022497 ps
CPU time 2.23 seconds
Started Aug 01 07:01:29 PM PDT 24
Finished Aug 01 07:01:32 PM PDT 24
Peak memory 206968 kb
Host smart-19962e68-012e-436c-a2b5-52a64518ad2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684410705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.684410705
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2846597849
Short name T88
Test name
Test status
Simulation time 1186272575 ps
CPU time 5.24 seconds
Started Aug 01 07:01:32 PM PDT 24
Finished Aug 01 07:01:37 PM PDT 24
Peak memory 214296 kb
Host smart-68f347d5-95d6-458e-94a2-aa0196ccfcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846597849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2846597849
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3425955467
Short name T376
Test name
Test status
Simulation time 118607546 ps
CPU time 2.02 seconds
Started Aug 01 07:01:27 PM PDT 24
Finished Aug 01 07:01:29 PM PDT 24
Peak memory 214248 kb
Host smart-baef64b3-167d-4b65-8507-54188bb8c4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425955467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3425955467
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1120732594
Short name T842
Test name
Test status
Simulation time 127671382 ps
CPU time 2.2 seconds
Started Aug 01 07:01:29 PM PDT 24
Finished Aug 01 07:01:31 PM PDT 24
Peak memory 206336 kb
Host smart-bbec6622-d74d-45d8-a8cd-708f3dfe7115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120732594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1120732594
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3926697938
Short name T232
Test name
Test status
Simulation time 332532961 ps
CPU time 4.43 seconds
Started Aug 01 07:01:28 PM PDT 24
Finished Aug 01 07:01:33 PM PDT 24
Peak memory 207376 kb
Host smart-a5ad4278-ff3c-480e-bb80-7cc3429b2d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926697938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3926697938
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3488217393
Short name T804
Test name
Test status
Simulation time 232588795 ps
CPU time 2.25 seconds
Started Aug 01 07:01:25 PM PDT 24
Finished Aug 01 07:01:28 PM PDT 24
Peak memory 206968 kb
Host smart-b6457194-826e-48ff-bfeb-201dce83b9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488217393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3488217393
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3013298958
Short name T685
Test name
Test status
Simulation time 186785932 ps
CPU time 2.74 seconds
Started Aug 01 07:01:28 PM PDT 24
Finished Aug 01 07:01:31 PM PDT 24
Peak memory 207096 kb
Host smart-99146072-fb99-443d-a0bd-2ff62bd7ff3e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013298958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3013298958
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2071478036
Short name T853
Test name
Test status
Simulation time 94077565 ps
CPU time 2.1 seconds
Started Aug 01 07:01:30 PM PDT 24
Finished Aug 01 07:01:33 PM PDT 24
Peak memory 208728 kb
Host smart-73599955-2dc4-498c-80fd-8b61ef9f3f20
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071478036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2071478036
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1589420572
Short name T555
Test name
Test status
Simulation time 28268478 ps
CPU time 2.09 seconds
Started Aug 01 07:01:26 PM PDT 24
Finished Aug 01 07:01:29 PM PDT 24
Peak memory 208840 kb
Host smart-cad2055a-c712-4625-a34f-956bc611971a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589420572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1589420572
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2412017991
Short name T179
Test name
Test status
Simulation time 187462222 ps
CPU time 4.19 seconds
Started Aug 01 07:01:27 PM PDT 24
Finished Aug 01 07:01:31 PM PDT 24
Peak memory 209724 kb
Host smart-2d23eb2b-ea21-429b-b274-d22942f6473f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412017991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2412017991
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3220631785
Short name T817
Test name
Test status
Simulation time 1161000808 ps
CPU time 2.73 seconds
Started Aug 01 07:01:31 PM PDT 24
Finished Aug 01 07:01:34 PM PDT 24
Peak memory 206828 kb
Host smart-231c36ad-9e58-451c-9c53-d1108c7ff480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220631785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3220631785
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.4017432889
Short name T601
Test name
Test status
Simulation time 288652750 ps
CPU time 10.56 seconds
Started Aug 01 07:01:27 PM PDT 24
Finished Aug 01 07:01:37 PM PDT 24
Peak memory 218700 kb
Host smart-a60d3048-996e-4588-8c8d-f9e92934bcb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017432889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.4017432889
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3940242193
Short name T244
Test name
Test status
Simulation time 1284169435 ps
CPU time 16.43 seconds
Started Aug 01 07:01:29 PM PDT 24
Finished Aug 01 07:01:46 PM PDT 24
Peak memory 214300 kb
Host smart-ad12c140-75b1-455a-ae17-4f441849b373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940242193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3940242193
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3077253392
Short name T165
Test name
Test status
Simulation time 147669798 ps
CPU time 1.86 seconds
Started Aug 01 07:01:31 PM PDT 24
Finished Aug 01 07:01:33 PM PDT 24
Peak memory 210036 kb
Host smart-bd29d911-0d03-428a-a195-a90171bd01c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077253392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3077253392
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.2603138547
Short name T869
Test name
Test status
Simulation time 18851092 ps
CPU time 0.69 seconds
Started Aug 01 07:01:26 PM PDT 24
Finished Aug 01 07:01:27 PM PDT 24
Peak memory 205924 kb
Host smart-9c0bf51e-a16f-4693-a7b7-55665a6ff2d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603138547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2603138547
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.59093319
Short name T123
Test name
Test status
Simulation time 859361893 ps
CPU time 11.46 seconds
Started Aug 01 07:01:30 PM PDT 24
Finished Aug 01 07:01:42 PM PDT 24
Peak memory 214344 kb
Host smart-606d6782-dc1c-48ab-a6cb-bac329b4f07e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=59093319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.59093319
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3361917006
Short name T832
Test name
Test status
Simulation time 35128320 ps
CPU time 2.56 seconds
Started Aug 01 07:01:27 PM PDT 24
Finished Aug 01 07:01:29 PM PDT 24
Peak memory 218320 kb
Host smart-2c573254-827e-4e0a-a117-5473fcb3c5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361917006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3361917006
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.902188254
Short name T779
Test name
Test status
Simulation time 240509494 ps
CPU time 3.14 seconds
Started Aug 01 07:01:30 PM PDT 24
Finished Aug 01 07:01:34 PM PDT 24
Peak memory 214268 kb
Host smart-9b0e3924-7f3e-4135-8cc8-c567ad7263c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902188254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.902188254
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3750106975
Short name T61
Test name
Test status
Simulation time 168227461 ps
CPU time 2.7 seconds
Started Aug 01 07:01:29 PM PDT 24
Finished Aug 01 07:01:32 PM PDT 24
Peak memory 209392 kb
Host smart-7a96c339-5455-4c7d-b2ee-2903de2f65ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750106975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3750106975
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.4199505211
Short name T314
Test name
Test status
Simulation time 361402188 ps
CPU time 3.92 seconds
Started Aug 01 07:01:30 PM PDT 24
Finished Aug 01 07:01:34 PM PDT 24
Peak memory 207420 kb
Host smart-b2715a75-7257-4e9b-8230-01806a35d8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199505211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.4199505211
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2951229051
Short name T559
Test name
Test status
Simulation time 255587617 ps
CPU time 2.75 seconds
Started Aug 01 07:01:34 PM PDT 24
Finished Aug 01 07:01:37 PM PDT 24
Peak memory 206904 kb
Host smart-592bd95b-f8cf-4973-a622-37156a78c270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951229051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2951229051
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1609259172
Short name T313
Test name
Test status
Simulation time 320367237 ps
CPU time 3.07 seconds
Started Aug 01 07:01:26 PM PDT 24
Finished Aug 01 07:01:30 PM PDT 24
Peak memory 208504 kb
Host smart-92cbed57-b045-4c42-9392-c52debea6fc7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609259172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1609259172
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.972885065
Short name T904
Test name
Test status
Simulation time 88277793 ps
CPU time 3.18 seconds
Started Aug 01 07:01:32 PM PDT 24
Finished Aug 01 07:01:35 PM PDT 24
Peak memory 206764 kb
Host smart-9e08a175-b0f3-4ab5-ae1c-9ed33e90e980
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972885065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.972885065
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.701585995
Short name T608
Test name
Test status
Simulation time 222478449 ps
CPU time 2.86 seconds
Started Aug 01 07:01:25 PM PDT 24
Finished Aug 01 07:01:28 PM PDT 24
Peak memory 208568 kb
Host smart-b7cbfe38-9a02-4426-af68-8b0aaabb5cbb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701585995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.701585995
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2307092727
Short name T690
Test name
Test status
Simulation time 17725134 ps
CPU time 1.42 seconds
Started Aug 01 07:01:27 PM PDT 24
Finished Aug 01 07:01:28 PM PDT 24
Peak memory 215388 kb
Host smart-7222b33f-8651-44f6-ab74-615c408c911e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307092727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2307092727
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1940086675
Short name T861
Test name
Test status
Simulation time 18817129 ps
CPU time 1.65 seconds
Started Aug 01 07:01:34 PM PDT 24
Finished Aug 01 07:01:36 PM PDT 24
Peak memory 207164 kb
Host smart-752f59f4-c678-4785-aff6-4be9e4d56351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940086675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1940086675
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2389512692
Short name T590
Test name
Test status
Simulation time 398210534 ps
CPU time 5.76 seconds
Started Aug 01 07:01:28 PM PDT 24
Finished Aug 01 07:01:34 PM PDT 24
Peak memory 219428 kb
Host smart-c4f98093-c1b2-4ab5-b296-d61858ed0b87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389512692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2389512692
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.1470153973
Short name T799
Test name
Test status
Simulation time 195657921 ps
CPU time 7.3 seconds
Started Aug 01 07:01:28 PM PDT 24
Finished Aug 01 07:01:36 PM PDT 24
Peak memory 208948 kb
Host smart-84e883de-c4a3-4877-bf51-e36cb88f1cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470153973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1470153973
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1752763473
Short name T650
Test name
Test status
Simulation time 148043137 ps
CPU time 3.11 seconds
Started Aug 01 07:01:31 PM PDT 24
Finished Aug 01 07:01:34 PM PDT 24
Peak memory 210276 kb
Host smart-4852b3cb-b494-4f6c-bb54-1da1bd69745b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752763473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1752763473
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.1167872536
Short name T701
Test name
Test status
Simulation time 12085441 ps
CPU time 0.7 seconds
Started Aug 01 07:01:32 PM PDT 24
Finished Aug 01 07:01:33 PM PDT 24
Peak memory 205948 kb
Host smart-8c283bd5-713a-4c8d-8afe-743ce7c07bb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167872536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1167872536
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1861095496
Short name T417
Test name
Test status
Simulation time 62362768 ps
CPU time 4.13 seconds
Started Aug 01 07:01:27 PM PDT 24
Finished Aug 01 07:01:41 PM PDT 24
Peak memory 215008 kb
Host smart-ed669a3a-678e-4f1f-ab19-ecd3c0cd1f1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1861095496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1861095496
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.808915678
Short name T400
Test name
Test status
Simulation time 424243662 ps
CPU time 4.7 seconds
Started Aug 01 07:01:28 PM PDT 24
Finished Aug 01 07:01:32 PM PDT 24
Peak memory 210516 kb
Host smart-971d6871-794c-4de4-8cb8-1732e45f68fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808915678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.808915678
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.4218864936
Short name T530
Test name
Test status
Simulation time 575196218 ps
CPU time 8.22 seconds
Started Aug 01 07:01:29 PM PDT 24
Finished Aug 01 07:01:37 PM PDT 24
Peak memory 208920 kb
Host smart-7d224a08-f0fc-40d5-8e36-30897363b8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218864936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.4218864936
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2433488044
Short name T78
Test name
Test status
Simulation time 200738140 ps
CPU time 5.4 seconds
Started Aug 01 07:01:27 PM PDT 24
Finished Aug 01 07:01:32 PM PDT 24
Peak memory 214328 kb
Host smart-7b921a7a-d673-4966-8ac0-1798a4923fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433488044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2433488044
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1300677101
Short name T241
Test name
Test status
Simulation time 194454262 ps
CPU time 2.93 seconds
Started Aug 01 07:01:29 PM PDT 24
Finished Aug 01 07:01:32 PM PDT 24
Peak memory 214216 kb
Host smart-0ff8c95a-b32f-46f0-b1b8-1214dafb1a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300677101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1300677101
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2972809678
Short name T343
Test name
Test status
Simulation time 468727409 ps
CPU time 3.72 seconds
Started Aug 01 07:01:26 PM PDT 24
Finished Aug 01 07:01:30 PM PDT 24
Peak memory 220196 kb
Host smart-70f2a518-3af1-40c7-9c99-b79c8c095931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972809678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2972809678
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2178333052
Short name T297
Test name
Test status
Simulation time 14612307377 ps
CPU time 29.8 seconds
Started Aug 01 07:01:28 PM PDT 24
Finished Aug 01 07:01:58 PM PDT 24
Peak memory 209784 kb
Host smart-b14d138a-f2b4-45d9-a2bc-fd536f9a4dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178333052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2178333052
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.4160935408
Short name T362
Test name
Test status
Simulation time 1674656197 ps
CPU time 17.33 seconds
Started Aug 01 07:01:28 PM PDT 24
Finished Aug 01 07:01:46 PM PDT 24
Peak memory 208192 kb
Host smart-6788dd35-8add-40c7-9674-2e4fa7b49204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160935408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.4160935408
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.63835924
Short name T575
Test name
Test status
Simulation time 156092006 ps
CPU time 2.57 seconds
Started Aug 01 07:01:26 PM PDT 24
Finished Aug 01 07:01:29 PM PDT 24
Peak memory 208888 kb
Host smart-9ad5eb1b-508d-4de7-a52c-c295671d69c2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63835924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.63835924
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3718331353
Short name T507
Test name
Test status
Simulation time 335663484 ps
CPU time 2.84 seconds
Started Aug 01 07:01:31 PM PDT 24
Finished Aug 01 07:01:34 PM PDT 24
Peak memory 206912 kb
Host smart-6121adaa-b958-40ec-9991-f1e7231c5410
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718331353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3718331353
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2560195556
Short name T202
Test name
Test status
Simulation time 70418396 ps
CPU time 3.37 seconds
Started Aug 01 07:01:28 PM PDT 24
Finished Aug 01 07:01:32 PM PDT 24
Peak memory 208740 kb
Host smart-c8f6ba1a-5cf5-434e-aafa-ad67dc058e22
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560195556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2560195556
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.917310005
Short name T821
Test name
Test status
Simulation time 1109140497 ps
CPU time 11.59 seconds
Started Aug 01 07:01:35 PM PDT 24
Finished Aug 01 07:01:47 PM PDT 24
Peak memory 208620 kb
Host smart-2d1e59ad-0d30-468d-bcb9-ac0e5b354151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917310005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.917310005
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2977904312
Short name T431
Test name
Test status
Simulation time 2867520594 ps
CPU time 13.31 seconds
Started Aug 01 07:01:31 PM PDT 24
Finished Aug 01 07:01:44 PM PDT 24
Peak memory 207896 kb
Host smart-335eb374-664a-4ea3-8bf1-568d8e11aee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977904312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2977904312
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3473802243
Short name T790
Test name
Test status
Simulation time 2349206872 ps
CPU time 6.88 seconds
Started Aug 01 07:01:31 PM PDT 24
Finished Aug 01 07:01:38 PM PDT 24
Peak memory 209144 kb
Host smart-788f6333-dc4c-4e18-9502-702072008ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473802243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3473802243
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.397725191
Short name T14
Test name
Test status
Simulation time 11523824 ps
CPU time 0.76 seconds
Started Aug 01 07:01:34 PM PDT 24
Finished Aug 01 07:01:35 PM PDT 24
Peak memory 205976 kb
Host smart-450533c1-b963-4d3c-82f4-8530438a09e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397725191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.397725191
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1634028545
Short name T324
Test name
Test status
Simulation time 66936788 ps
CPU time 2.71 seconds
Started Aug 01 07:01:31 PM PDT 24
Finished Aug 01 07:01:33 PM PDT 24
Peak memory 222496 kb
Host smart-19f82f75-57d1-4dba-b661-19bc8218e4c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1634028545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1634028545
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.503719501
Short name T734
Test name
Test status
Simulation time 137854387 ps
CPU time 1.81 seconds
Started Aug 01 07:01:32 PM PDT 24
Finished Aug 01 07:01:34 PM PDT 24
Peak memory 209136 kb
Host smart-9b8bb4b5-4cea-4cd3-bff1-400dd401e31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503719501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.503719501
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.804495303
Short name T723
Test name
Test status
Simulation time 305081543 ps
CPU time 3.77 seconds
Started Aug 01 07:01:30 PM PDT 24
Finished Aug 01 07:01:34 PM PDT 24
Peak memory 214460 kb
Host smart-ccaaa429-d012-45f4-ae32-48b6b07781f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804495303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.804495303
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1813061407
Short name T264
Test name
Test status
Simulation time 242537950 ps
CPU time 2.42 seconds
Started Aug 01 07:01:31 PM PDT 24
Finished Aug 01 07:01:33 PM PDT 24
Peak memory 214252 kb
Host smart-ca5a6d61-cd9f-41e8-883e-f7486434d607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813061407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1813061407
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_random.821868072
Short name T246
Test name
Test status
Simulation time 117067987 ps
CPU time 3.77 seconds
Started Aug 01 07:01:31 PM PDT 24
Finished Aug 01 07:01:35 PM PDT 24
Peak memory 214292 kb
Host smart-2b360fb7-a15e-4e0d-ac1e-fa8e1035873b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821868072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.821868072
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.426932143
Short name T310
Test name
Test status
Simulation time 19984168 ps
CPU time 1.71 seconds
Started Aug 01 07:01:31 PM PDT 24
Finished Aug 01 07:01:33 PM PDT 24
Peak memory 206968 kb
Host smart-4be712fb-2f5a-4ff0-bdbf-83b46fb9a254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426932143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.426932143
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2432529092
Short name T553
Test name
Test status
Simulation time 196872175 ps
CPU time 2.86 seconds
Started Aug 01 07:01:29 PM PDT 24
Finished Aug 01 07:01:32 PM PDT 24
Peak memory 206804 kb
Host smart-59bf1300-22e9-4175-a758-c2a0166939f7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432529092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2432529092
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.134913936
Short name T672
Test name
Test status
Simulation time 22535457 ps
CPU time 1.74 seconds
Started Aug 01 07:01:34 PM PDT 24
Finished Aug 01 07:01:36 PM PDT 24
Peak memory 207052 kb
Host smart-e8b117e3-83c9-4174-962a-84f8db298b81
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134913936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.134913936
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.733530065
Short name T483
Test name
Test status
Simulation time 26417714 ps
CPU time 2.03 seconds
Started Aug 01 07:01:31 PM PDT 24
Finished Aug 01 07:01:34 PM PDT 24
Peak memory 208676 kb
Host smart-332364c3-fee1-4197-8d68-d7edf20dd185
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733530065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.733530065
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2145329004
Short name T852
Test name
Test status
Simulation time 361832137 ps
CPU time 4.25 seconds
Started Aug 01 07:01:33 PM PDT 24
Finished Aug 01 07:01:37 PM PDT 24
Peak memory 209828 kb
Host smart-cdddfd64-fc1b-4879-b88e-deb5fb25bef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145329004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2145329004
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.528640937
Short name T524
Test name
Test status
Simulation time 791983343 ps
CPU time 4.65 seconds
Started Aug 01 07:01:37 PM PDT 24
Finished Aug 01 07:01:42 PM PDT 24
Peak memory 207776 kb
Host smart-7a0c00a5-f3ac-4620-86d7-99a10f166209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528640937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.528640937
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2808524747
Short name T114
Test name
Test status
Simulation time 401864243 ps
CPU time 14.95 seconds
Started Aug 01 07:01:29 PM PDT 24
Finished Aug 01 07:01:44 PM PDT 24
Peak memory 222536 kb
Host smart-da61551c-ad46-49a6-b549-392238d4fef7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808524747 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2808524747
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2490439339
Short name T825
Test name
Test status
Simulation time 525466019 ps
CPU time 15.57 seconds
Started Aug 01 07:01:31 PM PDT 24
Finished Aug 01 07:01:47 PM PDT 24
Peak memory 214168 kb
Host smart-e834ab43-c33f-421a-a759-a705e87eed3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490439339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2490439339
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.936597152
Short name T586
Test name
Test status
Simulation time 71629022 ps
CPU time 3.04 seconds
Started Aug 01 07:01:35 PM PDT 24
Finished Aug 01 07:01:38 PM PDT 24
Peak memory 210480 kb
Host smart-47c30533-dfca-484b-abf0-460877c67b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936597152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.936597152
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1708775728
Short name T539
Test name
Test status
Simulation time 57099063 ps
CPU time 0.74 seconds
Started Aug 01 07:01:44 PM PDT 24
Finished Aug 01 07:01:45 PM PDT 24
Peak memory 205932 kb
Host smart-95310aa7-14af-4409-8f04-9e93c1e41de8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708775728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1708775728
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1292570843
Short name T620
Test name
Test status
Simulation time 335982030 ps
CPU time 17.16 seconds
Started Aug 01 07:01:31 PM PDT 24
Finished Aug 01 07:01:49 PM PDT 24
Peak memory 214320 kb
Host smart-3b932d1c-ec1f-4ca0-8dc7-ec05205556a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1292570843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1292570843
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3886835743
Short name T491
Test name
Test status
Simulation time 132537919 ps
CPU time 2.34 seconds
Started Aug 01 07:01:37 PM PDT 24
Finished Aug 01 07:01:39 PM PDT 24
Peak memory 214304 kb
Host smart-40c0bb5b-3c5a-43aa-9e41-becfc82f3260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886835743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3886835743
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1402308118
Short name T635
Test name
Test status
Simulation time 1204239531 ps
CPU time 12.39 seconds
Started Aug 01 07:01:35 PM PDT 24
Finished Aug 01 07:01:47 PM PDT 24
Peak memory 219856 kb
Host smart-a436ccd7-71bb-4fba-8451-511ff9372730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402308118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1402308118
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2822595648
Short name T661
Test name
Test status
Simulation time 105176807 ps
CPU time 4.1 seconds
Started Aug 01 07:01:38 PM PDT 24
Finished Aug 01 07:01:42 PM PDT 24
Peak memory 214332 kb
Host smart-cbc1fde0-8ffc-45c9-b9a7-19738d643692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822595648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2822595648
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.880812234
Short name T194
Test name
Test status
Simulation time 87800650 ps
CPU time 4.32 seconds
Started Aug 01 07:01:35 PM PDT 24
Finished Aug 01 07:01:39 PM PDT 24
Peak memory 209792 kb
Host smart-bb983f54-674b-4826-aa98-e0577d716fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880812234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.880812234
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2729403051
Short name T800
Test name
Test status
Simulation time 98496068 ps
CPU time 4.22 seconds
Started Aug 01 07:01:35 PM PDT 24
Finished Aug 01 07:01:39 PM PDT 24
Peak memory 207524 kb
Host smart-5d34321a-2f4c-4202-b46b-46ffdd70df37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729403051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2729403051
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2703864168
Short name T282
Test name
Test status
Simulation time 188604427 ps
CPU time 6.42 seconds
Started Aug 01 07:01:32 PM PDT 24
Finished Aug 01 07:01:38 PM PDT 24
Peak memory 206776 kb
Host smart-112482be-d0b5-4516-913b-81955bf7d31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703864168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2703864168
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2685278611
Short name T445
Test name
Test status
Simulation time 100517634 ps
CPU time 3.32 seconds
Started Aug 01 07:01:31 PM PDT 24
Finished Aug 01 07:01:35 PM PDT 24
Peak memory 207456 kb
Host smart-a855e4a1-fcb3-4941-8d5a-6a951b499afb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685278611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2685278611
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3760686209
Short name T473
Test name
Test status
Simulation time 90968071 ps
CPU time 4.1 seconds
Started Aug 01 07:01:31 PM PDT 24
Finished Aug 01 07:01:35 PM PDT 24
Peak memory 208748 kb
Host smart-7f1b2c9c-64b2-4142-a8e3-1edadb55f09d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760686209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3760686209
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3820377760
Short name T619
Test name
Test status
Simulation time 107545000 ps
CPU time 3.37 seconds
Started Aug 01 07:01:39 PM PDT 24
Finished Aug 01 07:01:42 PM PDT 24
Peak memory 206804 kb
Host smart-06a5ce16-a446-4a51-9732-b10a4de29646
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820377760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3820377760
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.1410620418
Short name T274
Test name
Test status
Simulation time 776649261 ps
CPU time 5.35 seconds
Started Aug 01 07:01:35 PM PDT 24
Finished Aug 01 07:01:41 PM PDT 24
Peak memory 210436 kb
Host smart-bc30614d-9650-4b8f-a30b-2fb0fb47ceb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410620418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1410620418
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3747096495
Short name T409
Test name
Test status
Simulation time 796180958 ps
CPU time 5.44 seconds
Started Aug 01 07:01:31 PM PDT 24
Finished Aug 01 07:01:37 PM PDT 24
Peak memory 207516 kb
Host smart-8997edf1-8b03-45fa-bfa5-542194f07140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747096495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3747096495
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1364562010
Short name T903
Test name
Test status
Simulation time 1357853035 ps
CPU time 16.72 seconds
Started Aug 01 07:01:35 PM PDT 24
Finished Aug 01 07:01:52 PM PDT 24
Peak memory 214312 kb
Host smart-b2a3fe22-7494-4614-a208-4fb709ba5c54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364562010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1364562010
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.607813626
Short name T177
Test name
Test status
Simulation time 1705438336 ps
CPU time 15.01 seconds
Started Aug 01 07:01:46 PM PDT 24
Finished Aug 01 07:02:01 PM PDT 24
Peak memory 222540 kb
Host smart-708c5a17-1a32-41ec-882d-62a4f1237d2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607813626 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.607813626
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2053651607
Short name T344
Test name
Test status
Simulation time 119024214 ps
CPU time 3.8 seconds
Started Aug 01 07:01:34 PM PDT 24
Finished Aug 01 07:01:38 PM PDT 24
Peak memory 219780 kb
Host smart-792c48cc-21c6-417f-a898-8274fce3b571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053651607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2053651607
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3965482546
Short name T470
Test name
Test status
Simulation time 91938884 ps
CPU time 2.1 seconds
Started Aug 01 07:01:39 PM PDT 24
Finished Aug 01 07:01:41 PM PDT 24
Peak memory 209692 kb
Host smart-57e5b9f0-6cdf-431d-889f-39e50460288b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965482546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3965482546
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3067751977
Short name T550
Test name
Test status
Simulation time 8128563 ps
CPU time 0.72 seconds
Started Aug 01 07:01:35 PM PDT 24
Finished Aug 01 07:01:36 PM PDT 24
Peak memory 205960 kb
Host smart-fc319bf0-c3d5-439e-8fce-64f7bd8734cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067751977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3067751977
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2287073000
Short name T489
Test name
Test status
Simulation time 130344094 ps
CPU time 3.13 seconds
Started Aug 01 07:01:36 PM PDT 24
Finished Aug 01 07:01:39 PM PDT 24
Peak memory 208764 kb
Host smart-07cf06b2-29ec-4a63-b59f-3c15b9acfae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287073000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2287073000
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.2193351634
Short name T286
Test name
Test status
Simulation time 61827359 ps
CPU time 2.52 seconds
Started Aug 01 07:01:39 PM PDT 24
Finished Aug 01 07:01:42 PM PDT 24
Peak memory 214596 kb
Host smart-43d19aec-2c18-4854-9efe-1c060e2f235c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193351634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2193351634
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.687640265
Short name T721
Test name
Test status
Simulation time 476678931 ps
CPU time 4.14 seconds
Started Aug 01 07:01:37 PM PDT 24
Finished Aug 01 07:01:41 PM PDT 24
Peak memory 222436 kb
Host smart-ad1d2ec1-61c0-4092-b99b-f2a924a2c910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687640265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.687640265
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2616649215
Short name T211
Test name
Test status
Simulation time 29780243 ps
CPU time 1.9 seconds
Started Aug 01 07:01:44 PM PDT 24
Finished Aug 01 07:01:46 PM PDT 24
Peak memory 220124 kb
Host smart-4af278ef-98d8-4674-a2d0-99e14143adee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616649215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2616649215
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2629051897
Short name T243
Test name
Test status
Simulation time 100831361 ps
CPU time 4.77 seconds
Started Aug 01 07:01:37 PM PDT 24
Finished Aug 01 07:01:41 PM PDT 24
Peak memory 209596 kb
Host smart-8b618763-296f-43ef-879a-3ca4353227ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629051897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2629051897
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1576551021
Short name T712
Test name
Test status
Simulation time 352089194 ps
CPU time 2.87 seconds
Started Aug 01 07:01:44 PM PDT 24
Finished Aug 01 07:01:47 PM PDT 24
Peak memory 206760 kb
Host smart-32699c7b-b328-488f-b0de-e21b7a8ea895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576551021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1576551021
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2695591782
Short name T497
Test name
Test status
Simulation time 29482932 ps
CPU time 1.97 seconds
Started Aug 01 07:01:38 PM PDT 24
Finished Aug 01 07:01:40 PM PDT 24
Peak memory 207160 kb
Host smart-5c6d2c22-b20b-44c8-bdc9-5a5bf9f853b6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695591782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2695591782
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.4171397050
Short name T863
Test name
Test status
Simulation time 242775789 ps
CPU time 6.99 seconds
Started Aug 01 07:01:38 PM PDT 24
Finished Aug 01 07:01:45 PM PDT 24
Peak memory 208972 kb
Host smart-5b3dd00e-e3be-421b-9b3a-13c168f2aee8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171397050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.4171397050
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.3130467191
Short name T327
Test name
Test status
Simulation time 652643430 ps
CPU time 5 seconds
Started Aug 01 07:01:40 PM PDT 24
Finished Aug 01 07:01:45 PM PDT 24
Peak memory 208440 kb
Host smart-cc825ba2-6a9f-4a4a-bf66-0d7f0308c24c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130467191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3130467191
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3664176830
Short name T653
Test name
Test status
Simulation time 46876734 ps
CPU time 2.17 seconds
Started Aug 01 07:01:35 PM PDT 24
Finished Aug 01 07:01:37 PM PDT 24
Peak memory 208828 kb
Host smart-06c1c2e7-d38a-45a2-b262-b0b18144dd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664176830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3664176830
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2897474733
Short name T474
Test name
Test status
Simulation time 296436981 ps
CPU time 4.04 seconds
Started Aug 01 07:01:44 PM PDT 24
Finished Aug 01 07:01:48 PM PDT 24
Peak memory 206060 kb
Host smart-ecf15f4c-0b83-492d-8904-5158bc4d2c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897474733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2897474733
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.1729102870
Short name T223
Test name
Test status
Simulation time 640426668 ps
CPU time 29.05 seconds
Started Aug 01 07:01:44 PM PDT 24
Finished Aug 01 07:02:13 PM PDT 24
Peak memory 215004 kb
Host smart-f8ee8a58-3bfc-4a8d-a8c3-a6dd547deff8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729102870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1729102870
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.577435071
Short name T99
Test name
Test status
Simulation time 398017248 ps
CPU time 20.1 seconds
Started Aug 01 07:01:40 PM PDT 24
Finished Aug 01 07:02:01 PM PDT 24
Peak memory 222536 kb
Host smart-107b0972-ea0e-4b32-841a-ce68c396a755
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577435071 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.577435071
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.105750742
Short name T336
Test name
Test status
Simulation time 3627303096 ps
CPU time 36.02 seconds
Started Aug 01 07:01:43 PM PDT 24
Finished Aug 01 07:02:19 PM PDT 24
Peak memory 214348 kb
Host smart-d012d4c8-bca8-430e-be65-bcd24524c1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105750742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.105750742
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1404810244
Short name T583
Test name
Test status
Simulation time 100560413 ps
CPU time 2.91 seconds
Started Aug 01 07:01:36 PM PDT 24
Finished Aug 01 07:01:39 PM PDT 24
Peak memory 209964 kb
Host smart-3fc61ecb-c649-4147-a610-f8429809d641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404810244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1404810244
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2495726
Short name T858
Test name
Test status
Simulation time 13925382 ps
CPU time 0.75 seconds
Started Aug 01 07:01:42 PM PDT 24
Finished Aug 01 07:01:43 PM PDT 24
Peak memory 205948 kb
Host smart-781135df-754b-43bd-9fa2-3d187ef925ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2495726
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2024998179
Short name T323
Test name
Test status
Simulation time 132650312 ps
CPU time 6.22 seconds
Started Aug 01 07:01:43 PM PDT 24
Finished Aug 01 07:01:50 PM PDT 24
Peak memory 214892 kb
Host smart-3ffd49c1-628b-4ab0-bfdf-439bbc217b64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2024998179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2024998179
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.407353494
Short name T65
Test name
Test status
Simulation time 195622335 ps
CPU time 2.48 seconds
Started Aug 01 07:01:36 PM PDT 24
Finished Aug 01 07:01:39 PM PDT 24
Peak memory 220352 kb
Host smart-f529170c-a648-455b-9f77-4d92f7b390a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407353494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.407353494
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2251662041
Short name T236
Test name
Test status
Simulation time 135892874 ps
CPU time 1.48 seconds
Started Aug 01 07:01:38 PM PDT 24
Finished Aug 01 07:01:40 PM PDT 24
Peak memory 207504 kb
Host smart-9236300d-8d32-4c4f-8e3a-a819c03a9e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251662041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2251662041
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.12319590
Short name T528
Test name
Test status
Simulation time 745475079 ps
CPU time 20.56 seconds
Started Aug 01 07:01:51 PM PDT 24
Finished Aug 01 07:02:11 PM PDT 24
Peak memory 214292 kb
Host smart-4b5c34b6-b6a6-4865-a0d4-d15a84b8c430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12319590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.12319590
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.52117718
Short name T742
Test name
Test status
Simulation time 1422567265 ps
CPU time 3.97 seconds
Started Aug 01 07:01:42 PM PDT 24
Finished Aug 01 07:01:46 PM PDT 24
Peak memory 214244 kb
Host smart-04130be7-fc51-4d11-88df-015c06b3094a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52117718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.52117718
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.811839061
Short name T884
Test name
Test status
Simulation time 366701256 ps
CPU time 2.48 seconds
Started Aug 01 07:01:51 PM PDT 24
Finished Aug 01 07:01:53 PM PDT 24
Peak memory 222460 kb
Host smart-3e19eebd-1d39-4daa-ac58-e43fbe59b1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811839061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.811839061
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3936931848
Short name T77
Test name
Test status
Simulation time 451646020 ps
CPU time 6.8 seconds
Started Aug 01 07:01:46 PM PDT 24
Finished Aug 01 07:01:53 PM PDT 24
Peak memory 207132 kb
Host smart-8b0afe04-d72c-4aa2-a01d-1e89b1dee103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936931848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3936931848
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1129437126
Short name T505
Test name
Test status
Simulation time 144106740 ps
CPU time 3.4 seconds
Started Aug 01 07:01:39 PM PDT 24
Finished Aug 01 07:01:43 PM PDT 24
Peak memory 208820 kb
Host smart-09807502-a56a-473e-8ab3-1f3a10f6f746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129437126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1129437126
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1312161454
Short name T536
Test name
Test status
Simulation time 717640497 ps
CPU time 8.53 seconds
Started Aug 01 07:01:36 PM PDT 24
Finished Aug 01 07:01:44 PM PDT 24
Peak memory 208268 kb
Host smart-6e691f92-cbe9-49d5-a1a1-710d0e8af7d9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312161454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1312161454
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3445593969
Short name T665
Test name
Test status
Simulation time 234265884 ps
CPU time 3.02 seconds
Started Aug 01 07:01:43 PM PDT 24
Finished Aug 01 07:01:46 PM PDT 24
Peak memory 206944 kb
Host smart-54fa8672-2a64-40cd-b438-48794e4000a8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445593969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3445593969
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2492339147
Short name T643
Test name
Test status
Simulation time 36662596 ps
CPU time 1.72 seconds
Started Aug 01 07:01:37 PM PDT 24
Finished Aug 01 07:01:39 PM PDT 24
Peak memory 207180 kb
Host smart-cd22d3d1-c762-4bad-a69c-dca80d93a77b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492339147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2492339147
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.184091169
Short name T576
Test name
Test status
Simulation time 232753349 ps
CPU time 2.92 seconds
Started Aug 01 07:01:43 PM PDT 24
Finished Aug 01 07:01:47 PM PDT 24
Peak memory 214348 kb
Host smart-03685799-d78d-45a0-8aa3-f6676a296df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184091169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.184091169
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.1650167138
Short name T773
Test name
Test status
Simulation time 28815626 ps
CPU time 1.88 seconds
Started Aug 01 07:01:42 PM PDT 24
Finished Aug 01 07:01:44 PM PDT 24
Peak memory 208592 kb
Host smart-ba1f10e1-b3e5-4370-9eed-3b96fb27a3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650167138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1650167138
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.562278675
Short name T859
Test name
Test status
Simulation time 350819102 ps
CPU time 5.06 seconds
Started Aug 01 07:01:51 PM PDT 24
Finished Aug 01 07:01:56 PM PDT 24
Peak memory 207160 kb
Host smart-cb5f90d0-c143-4f47-86ea-a81ad6a5c5fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562278675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.562278675
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.1478388002
Short name T73
Test name
Test status
Simulation time 1599211232 ps
CPU time 25.39 seconds
Started Aug 01 07:01:39 PM PDT 24
Finished Aug 01 07:02:05 PM PDT 24
Peak memory 222476 kb
Host smart-2423c699-f80f-4bcd-8dcb-c0e67320d3b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478388002 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.1478388002
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.317219165
Short name T735
Test name
Test status
Simulation time 1080953360 ps
CPU time 12.36 seconds
Started Aug 01 07:01:50 PM PDT 24
Finished Aug 01 07:02:02 PM PDT 24
Peak memory 209232 kb
Host smart-37bc62a4-36a0-4475-a6b4-0035d7de3d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317219165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.317219165
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1572910877
Short name T387
Test name
Test status
Simulation time 747447554 ps
CPU time 11.56 seconds
Started Aug 01 07:01:38 PM PDT 24
Finished Aug 01 07:01:50 PM PDT 24
Peak memory 210452 kb
Host smart-95a2d002-83e7-478d-a3d9-30bc35314623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572910877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1572910877
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.683029699
Short name T805
Test name
Test status
Simulation time 15270286 ps
CPU time 0.93 seconds
Started Aug 01 07:01:44 PM PDT 24
Finished Aug 01 07:01:45 PM PDT 24
Peak memory 206104 kb
Host smart-18c84411-4100-4d3a-9fd1-cf21ccce74d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683029699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.683029699
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.36749615
Short name T338
Test name
Test status
Simulation time 253276571 ps
CPU time 3.83 seconds
Started Aug 01 07:01:44 PM PDT 24
Finished Aug 01 07:01:48 PM PDT 24
Peak memory 215760 kb
Host smart-957ce507-ff15-45f2-8abf-1c5acaf9b1a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=36749615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.36749615
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2457185274
Short name T207
Test name
Test status
Simulation time 1198913203 ps
CPU time 2.61 seconds
Started Aug 01 07:01:48 PM PDT 24
Finished Aug 01 07:01:51 PM PDT 24
Peak memory 214264 kb
Host smart-345b891d-7ce1-4153-b2cc-2717753b7e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457185274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2457185274
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.654952641
Short name T700
Test name
Test status
Simulation time 140741901 ps
CPU time 4.11 seconds
Started Aug 01 07:01:43 PM PDT 24
Finished Aug 01 07:01:48 PM PDT 24
Peak memory 219560 kb
Host smart-eb60147c-d3d6-4105-82fa-ef803aa66968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654952641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.654952641
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2411352334
Short name T86
Test name
Test status
Simulation time 75431012 ps
CPU time 3.67 seconds
Started Aug 01 07:01:40 PM PDT 24
Finished Aug 01 07:01:44 PM PDT 24
Peak memory 208828 kb
Host smart-b679458f-77a7-49c6-8902-c21e4100ee84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411352334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2411352334
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2750167702
Short name T89
Test name
Test status
Simulation time 128610137 ps
CPU time 2.99 seconds
Started Aug 01 07:01:44 PM PDT 24
Finished Aug 01 07:01:47 PM PDT 24
Peak memory 214240 kb
Host smart-52370390-5638-4e83-837a-03427b5d573c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750167702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2750167702
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3350555025
Short name T217
Test name
Test status
Simulation time 216517721 ps
CPU time 4 seconds
Started Aug 01 07:01:36 PM PDT 24
Finished Aug 01 07:01:40 PM PDT 24
Peak memory 209688 kb
Host smart-63219f11-c14d-4e08-bf79-79d8834d1cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350555025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3350555025
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1759949386
Short name T764
Test name
Test status
Simulation time 155844319 ps
CPU time 6.95 seconds
Started Aug 01 07:01:49 PM PDT 24
Finished Aug 01 07:01:56 PM PDT 24
Peak memory 214336 kb
Host smart-7b512a26-2b04-43b4-b08a-11df5f9d2641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759949386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1759949386
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2694513742
Short name T621
Test name
Test status
Simulation time 127151113 ps
CPU time 3.16 seconds
Started Aug 01 07:01:44 PM PDT 24
Finished Aug 01 07:01:48 PM PDT 24
Peak memory 207976 kb
Host smart-4acd41ca-255d-429c-95a6-54df678e2622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694513742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2694513742
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1655994406
Short name T588
Test name
Test status
Simulation time 155988088 ps
CPU time 2.36 seconds
Started Aug 01 07:01:47 PM PDT 24
Finished Aug 01 07:01:49 PM PDT 24
Peak memory 206948 kb
Host smart-3d9030ce-f904-46b8-af4d-b0a61853591a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655994406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1655994406
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.958973389
Short name T694
Test name
Test status
Simulation time 78741221 ps
CPU time 1.81 seconds
Started Aug 01 07:01:37 PM PDT 24
Finished Aug 01 07:01:39 PM PDT 24
Peak memory 207584 kb
Host smart-df917e14-8fec-4b1d-937c-2bce90b34979
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958973389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.958973389
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2374136280
Short name T403
Test name
Test status
Simulation time 24238132 ps
CPU time 1.81 seconds
Started Aug 01 07:01:42 PM PDT 24
Finished Aug 01 07:01:44 PM PDT 24
Peak memory 206948 kb
Host smart-69dc981e-4816-4d1b-8714-9e038e480f28
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374136280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2374136280
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2063889193
Short name T687
Test name
Test status
Simulation time 193609039 ps
CPU time 4.42 seconds
Started Aug 01 07:01:40 PM PDT 24
Finished Aug 01 07:01:44 PM PDT 24
Peak memory 209484 kb
Host smart-112b6b46-ccb2-4195-9dc7-1cbfa5d4aac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063889193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2063889193
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3360077127
Short name T648
Test name
Test status
Simulation time 197131065 ps
CPU time 4.17 seconds
Started Aug 01 07:01:39 PM PDT 24
Finished Aug 01 07:01:43 PM PDT 24
Peak memory 207860 kb
Host smart-f4ce84a0-f0b9-4e6d-af9d-a4049589eb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360077127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3360077127
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.996901192
Short name T190
Test name
Test status
Simulation time 16675647369 ps
CPU time 170.64 seconds
Started Aug 01 07:01:49 PM PDT 24
Finished Aug 01 07:04:39 PM PDT 24
Peak memory 217604 kb
Host smart-010b8f94-c44e-49c4-bbb1-423ddfc643bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996901192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.996901192
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.3830450150
Short name T178
Test name
Test status
Simulation time 2484635229 ps
CPU time 10.04 seconds
Started Aug 01 07:01:38 PM PDT 24
Finished Aug 01 07:01:48 PM PDT 24
Peak memory 222564 kb
Host smart-07d188e1-9e9c-425d-8199-8aca825503a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830450150 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.3830450150
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2518513014
Short name T495
Test name
Test status
Simulation time 3181726347 ps
CPU time 19.59 seconds
Started Aug 01 07:01:36 PM PDT 24
Finished Aug 01 07:01:56 PM PDT 24
Peak memory 214360 kb
Host smart-d1edfe1f-c5b7-48b0-aeee-943bf7a2efb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518513014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2518513014
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2383742629
Short name T874
Test name
Test status
Simulation time 157115587 ps
CPU time 3.16 seconds
Started Aug 01 07:01:41 PM PDT 24
Finished Aug 01 07:01:44 PM PDT 24
Peak memory 210380 kb
Host smart-a135a08c-fb11-49e7-a6d6-55c3e834c918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383742629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2383742629
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.81340923
Short name T91
Test name
Test status
Simulation time 16553361 ps
CPU time 0.84 seconds
Started Aug 01 06:59:24 PM PDT 24
Finished Aug 01 06:59:25 PM PDT 24
Peak memory 205928 kb
Host smart-0da68374-7c6b-4970-8b20-7b4f9cd96786
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81340923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.81340923
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3185178397
Short name T224
Test name
Test status
Simulation time 104924696 ps
CPU time 4.44 seconds
Started Aug 01 06:59:21 PM PDT 24
Finished Aug 01 06:59:26 PM PDT 24
Peak memory 209720 kb
Host smart-e4703855-269a-470a-b94a-9bac467ea579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185178397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3185178397
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1388803284
Short name T284
Test name
Test status
Simulation time 157779651 ps
CPU time 2.24 seconds
Started Aug 01 06:59:18 PM PDT 24
Finished Aug 01 06:59:21 PM PDT 24
Peak memory 214356 kb
Host smart-e5da5620-d3fd-4946-af8b-de00027b0959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388803284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1388803284
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1621667087
Short name T778
Test name
Test status
Simulation time 74696576 ps
CPU time 3.67 seconds
Started Aug 01 06:59:22 PM PDT 24
Finished Aug 01 06:59:26 PM PDT 24
Peak memory 214296 kb
Host smart-1e817c38-a159-49fe-bd76-cfc2fe1dade8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621667087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1621667087
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.622066493
Short name T377
Test name
Test status
Simulation time 33102092 ps
CPU time 2.07 seconds
Started Aug 01 06:59:21 PM PDT 24
Finished Aug 01 06:59:24 PM PDT 24
Peak memory 214236 kb
Host smart-8bed80cf-9b02-42ce-8e98-1611e0feeeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622066493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.622066493
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3464084706
Short name T646
Test name
Test status
Simulation time 104220291 ps
CPU time 2.4 seconds
Started Aug 01 06:59:23 PM PDT 24
Finished Aug 01 06:59:26 PM PDT 24
Peak memory 214320 kb
Host smart-f379c796-9c1c-4777-9b25-1bbc7071177a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464084706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3464084706
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2116547078
Short name T245
Test name
Test status
Simulation time 1014784941 ps
CPU time 34.85 seconds
Started Aug 01 06:59:22 PM PDT 24
Finished Aug 01 06:59:57 PM PDT 24
Peak memory 210216 kb
Host smart-56e57539-bf5c-49d1-a253-7854e4e82f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116547078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2116547078
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2572899656
Short name T602
Test name
Test status
Simulation time 59419377 ps
CPU time 3.07 seconds
Started Aug 01 06:59:20 PM PDT 24
Finished Aug 01 06:59:24 PM PDT 24
Peak memory 208552 kb
Host smart-7f87dd88-36be-425e-bae4-bb52a3123c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572899656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2572899656
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1791133104
Short name T717
Test name
Test status
Simulation time 191019465 ps
CPU time 6.45 seconds
Started Aug 01 06:59:19 PM PDT 24
Finished Aug 01 06:59:25 PM PDT 24
Peak memory 208236 kb
Host smart-edfd9d50-82c4-4999-8576-a4930616be57
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791133104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1791133104
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3338048561
Short name T662
Test name
Test status
Simulation time 81061288 ps
CPU time 2.49 seconds
Started Aug 01 06:59:19 PM PDT 24
Finished Aug 01 06:59:22 PM PDT 24
Peak memory 207760 kb
Host smart-7934e2ac-7c87-4655-aea1-3508173af7d0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338048561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3338048561
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.321463110
Short name T201
Test name
Test status
Simulation time 157704747 ps
CPU time 5.17 seconds
Started Aug 01 06:59:21 PM PDT 24
Finished Aug 01 06:59:27 PM PDT 24
Peak memory 208228 kb
Host smart-6bb9265a-6010-4dd3-9450-a0e9902f0595
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321463110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.321463110
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.402652325
Short name T511
Test name
Test status
Simulation time 2256919943 ps
CPU time 19.28 seconds
Started Aug 01 06:59:24 PM PDT 24
Finished Aug 01 06:59:44 PM PDT 24
Peak memory 214428 kb
Host smart-533ff7ec-cba7-46e8-a7ba-1ab6381bbdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402652325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.402652325
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2564614888
Short name T686
Test name
Test status
Simulation time 687760137 ps
CPU time 7.21 seconds
Started Aug 01 06:59:19 PM PDT 24
Finished Aug 01 06:59:27 PM PDT 24
Peak memory 207156 kb
Host smart-455180e6-dade-4cb5-9e5f-ca850cc56679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564614888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2564614888
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2330070671
Short name T513
Test name
Test status
Simulation time 672028570 ps
CPU time 8.76 seconds
Started Aug 01 06:59:23 PM PDT 24
Finished Aug 01 06:59:32 PM PDT 24
Peak memory 216584 kb
Host smart-a5ad14fa-21a7-4f2e-94fa-fea08aab4039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330070671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2330070671
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.3451747239
Short name T339
Test name
Test status
Simulation time 167850219 ps
CPU time 11.29 seconds
Started Aug 01 06:59:21 PM PDT 24
Finished Aug 01 06:59:33 PM PDT 24
Peak memory 220784 kb
Host smart-124c0bd0-0c29-4b12-90ce-739dcb39690d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451747239 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.3451747239
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.4214944229
Short name T631
Test name
Test status
Simulation time 297601109 ps
CPU time 3.83 seconds
Started Aug 01 06:59:20 PM PDT 24
Finished Aug 01 06:59:24 PM PDT 24
Peak memory 209960 kb
Host smart-c78a365c-e987-4510-a11d-408d0556488c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214944229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.4214944229
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1113852340
Short name T198
Test name
Test status
Simulation time 265607332 ps
CPU time 2.08 seconds
Started Aug 01 06:59:18 PM PDT 24
Finished Aug 01 06:59:20 PM PDT 24
Peak memory 209900 kb
Host smart-14fd740d-cd6a-4b4a-922f-f4f37d5b3519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113852340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1113852340
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2565884251
Short name T466
Test name
Test status
Simulation time 55471409 ps
CPU time 0.93 seconds
Started Aug 01 06:59:19 PM PDT 24
Finished Aug 01 06:59:21 PM PDT 24
Peak memory 206088 kb
Host smart-46c3c12f-fd97-4add-a8c9-eb05ccea00b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565884251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2565884251
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.40788270
Short name T273
Test name
Test status
Simulation time 1381298962 ps
CPU time 71.49 seconds
Started Aug 01 06:59:19 PM PDT 24
Finished Aug 01 07:00:31 PM PDT 24
Peak memory 215776 kb
Host smart-9380da15-ba23-48f3-9c78-f59e4128362a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=40788270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.40788270
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2645560462
Short name T33
Test name
Test status
Simulation time 44108815 ps
CPU time 2.67 seconds
Started Aug 01 06:59:21 PM PDT 24
Finished Aug 01 06:59:24 PM PDT 24
Peak memory 214496 kb
Host smart-fe36a617-0359-49d6-9bdd-58ccfa5912ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645560462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2645560462
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.4206288636
Short name T492
Test name
Test status
Simulation time 112393893 ps
CPU time 1.66 seconds
Started Aug 01 06:59:22 PM PDT 24
Finished Aug 01 06:59:24 PM PDT 24
Peak memory 207776 kb
Host smart-1125b7ec-77d1-4ec1-872d-119fcb9e999d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206288636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.4206288636
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3381985077
Short name T300
Test name
Test status
Simulation time 102149826 ps
CPU time 2.59 seconds
Started Aug 01 06:59:22 PM PDT 24
Finished Aug 01 06:59:25 PM PDT 24
Peak memory 214320 kb
Host smart-66ee81c6-a23c-4691-9395-b392882de842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381985077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3381985077
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1829272575
Short name T56
Test name
Test status
Simulation time 269606469 ps
CPU time 4.52 seconds
Started Aug 01 06:59:20 PM PDT 24
Finished Aug 01 06:59:25 PM PDT 24
Peak memory 222416 kb
Host smart-bf0bec96-daa5-43cc-a53c-824231bc68a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829272575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1829272575
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3174609311
Short name T204
Test name
Test status
Simulation time 391167765 ps
CPU time 6.4 seconds
Started Aug 01 06:59:21 PM PDT 24
Finished Aug 01 06:59:28 PM PDT 24
Peak memory 216956 kb
Host smart-77404a02-c0fe-4582-add5-db6d5d81abb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174609311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3174609311
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3871824469
Short name T348
Test name
Test status
Simulation time 733196516 ps
CPU time 8.09 seconds
Started Aug 01 06:59:21 PM PDT 24
Finished Aug 01 06:59:29 PM PDT 24
Peak memory 208248 kb
Host smart-9d5ed692-c359-4805-8b25-86937ee190fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871824469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3871824469
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1071879749
Short name T788
Test name
Test status
Simulation time 104329521 ps
CPU time 3.66 seconds
Started Aug 01 06:59:20 PM PDT 24
Finished Aug 01 06:59:23 PM PDT 24
Peak memory 208488 kb
Host smart-309d097a-557f-49c6-b462-899051bb4a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071879749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1071879749
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1987785496
Short name T697
Test name
Test status
Simulation time 391581439 ps
CPU time 5.4 seconds
Started Aug 01 06:59:21 PM PDT 24
Finished Aug 01 06:59:27 PM PDT 24
Peak memory 208856 kb
Host smart-48ef8469-f8c7-4be5-8cfc-09b728f874ed
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987785496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1987785496
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2788299417
Short name T35
Test name
Test status
Simulation time 373595521 ps
CPU time 4.27 seconds
Started Aug 01 06:59:21 PM PDT 24
Finished Aug 01 06:59:26 PM PDT 24
Peak memory 207120 kb
Host smart-14f986c7-e697-4ab4-b9b3-b4b0df36a223
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788299417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2788299417
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.753331700
Short name T897
Test name
Test status
Simulation time 288445035 ps
CPU time 2.99 seconds
Started Aug 01 06:59:21 PM PDT 24
Finished Aug 01 06:59:24 PM PDT 24
Peak memory 206944 kb
Host smart-886c09d8-868a-4ab6-8f87-fad2146b015f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753331700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.753331700
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2472629738
Short name T333
Test name
Test status
Simulation time 730883175 ps
CPU time 4.57 seconds
Started Aug 01 06:59:23 PM PDT 24
Finished Aug 01 06:59:28 PM PDT 24
Peak memory 215584 kb
Host smart-1e73295e-4cf0-4650-861b-9aca42d8f1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472629738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2472629738
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1691710444
Short name T816
Test name
Test status
Simulation time 49960786 ps
CPU time 2.38 seconds
Started Aug 01 06:59:20 PM PDT 24
Finished Aug 01 06:59:22 PM PDT 24
Peak memory 208428 kb
Host smart-53fef69a-cd40-4cd7-89e8-3b08a1e387c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691710444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1691710444
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2363426326
Short name T868
Test name
Test status
Simulation time 3897123179 ps
CPU time 37.79 seconds
Started Aug 01 06:59:21 PM PDT 24
Finished Aug 01 06:59:59 PM PDT 24
Peak memory 217680 kb
Host smart-069c4384-a63a-49f7-abfd-a56af1887076
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363426326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2363426326
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.1657151024
Short name T794
Test name
Test status
Simulation time 227223751 ps
CPU time 8.95 seconds
Started Aug 01 06:59:21 PM PDT 24
Finished Aug 01 06:59:30 PM PDT 24
Peak memory 222516 kb
Host smart-25b652a8-c489-4e66-9fb7-30e71c98eac4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657151024 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.1657151024
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.1878716723
Short name T335
Test name
Test status
Simulation time 376133935 ps
CPU time 4.16 seconds
Started Aug 01 06:59:21 PM PDT 24
Finished Aug 01 06:59:25 PM PDT 24
Peak memory 218280 kb
Host smart-9fed5793-98cf-41ab-a88f-db1558c585d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878716723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1878716723
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2539084952
Short name T391
Test name
Test status
Simulation time 83046159 ps
CPU time 2.84 seconds
Started Aug 01 06:59:20 PM PDT 24
Finished Aug 01 06:59:23 PM PDT 24
Peak memory 210556 kb
Host smart-284121c9-9537-441a-a803-cd5096413955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539084952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2539084952
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.767519751
Short name T730
Test name
Test status
Simulation time 15654848 ps
CPU time 0.76 seconds
Started Aug 01 06:59:34 PM PDT 24
Finished Aug 01 06:59:35 PM PDT 24
Peak memory 205932 kb
Host smart-f2d185b4-817e-47c0-bcf2-71db71b16c82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767519751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.767519751
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.208941152
Short name T98
Test name
Test status
Simulation time 38344839 ps
CPU time 2.91 seconds
Started Aug 01 06:59:32 PM PDT 24
Finished Aug 01 06:59:35 PM PDT 24
Peak memory 214304 kb
Host smart-2cc5a812-1da3-4791-95ef-6b8bf696cd06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=208941152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.208941152
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1659109883
Short name T32
Test name
Test status
Simulation time 34850646 ps
CPU time 1.69 seconds
Started Aug 01 06:59:34 PM PDT 24
Finished Aug 01 06:59:36 PM PDT 24
Peak memory 207912 kb
Host smart-0bf4d261-156e-43ca-bbec-5a2ccf7b40e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659109883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1659109883
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1560380177
Short name T571
Test name
Test status
Simulation time 81936342 ps
CPU time 2.31 seconds
Started Aug 01 06:59:32 PM PDT 24
Finished Aug 01 06:59:35 PM PDT 24
Peak memory 214276 kb
Host smart-d22e7cff-cf6b-4c3f-b697-e4a8ffe16993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560380177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1560380177
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2865654401
Short name T719
Test name
Test status
Simulation time 134874618 ps
CPU time 3.63 seconds
Started Aug 01 06:59:33 PM PDT 24
Finished Aug 01 06:59:37 PM PDT 24
Peak memory 214332 kb
Host smart-176783f0-c135-41a4-997d-d70285bb682d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865654401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2865654401
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.4089614240
Short name T180
Test name
Test status
Simulation time 170478123 ps
CPU time 2.17 seconds
Started Aug 01 06:59:32 PM PDT 24
Finished Aug 01 06:59:35 PM PDT 24
Peak memory 214224 kb
Host smart-6bbd08f0-d94e-41e6-b0f9-74aa81f78a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089614240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.4089614240
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.890134036
Short name T658
Test name
Test status
Simulation time 88716995 ps
CPU time 3.97 seconds
Started Aug 01 06:59:35 PM PDT 24
Finished Aug 01 06:59:40 PM PDT 24
Peak memory 214432 kb
Host smart-e864353d-8720-48d5-ba81-fb0caa04b077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890134036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.890134036
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1950279759
Short name T276
Test name
Test status
Simulation time 438183162 ps
CPU time 4.51 seconds
Started Aug 01 06:59:33 PM PDT 24
Finished Aug 01 06:59:38 PM PDT 24
Peak memory 218184 kb
Host smart-b3c5cb73-5086-43b6-b8d0-86e77b8bd0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950279759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1950279759
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.744530723
Short name T527
Test name
Test status
Simulation time 38965578 ps
CPU time 2.43 seconds
Started Aug 01 06:59:21 PM PDT 24
Finished Aug 01 06:59:23 PM PDT 24
Peak memory 206800 kb
Host smart-608e3651-3a8d-4974-9dc1-596b9c753a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744530723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.744530723
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2160463484
Short name T836
Test name
Test status
Simulation time 1534160244 ps
CPU time 33.46 seconds
Started Aug 01 06:59:24 PM PDT 24
Finished Aug 01 06:59:57 PM PDT 24
Peak memory 208340 kb
Host smart-72b32e83-9848-4195-9347-bd7368a5b92d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160463484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2160463484
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.849086755
Short name T293
Test name
Test status
Simulation time 94815748 ps
CPU time 1.79 seconds
Started Aug 01 06:59:21 PM PDT 24
Finished Aug 01 06:59:24 PM PDT 24
Peak memory 207028 kb
Host smart-62427706-ae8e-4d23-89e8-70d548098dda
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849086755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.849086755
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3898343117
Short name T480
Test name
Test status
Simulation time 34642836 ps
CPU time 1.62 seconds
Started Aug 01 06:59:31 PM PDT 24
Finished Aug 01 06:59:32 PM PDT 24
Peak memory 206784 kb
Host smart-9dd162d4-7236-4758-8645-790c7f85fd61
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898343117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3898343117
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.205051582
Short name T10
Test name
Test status
Simulation time 64690728 ps
CPU time 3.28 seconds
Started Aug 01 06:59:39 PM PDT 24
Finished Aug 01 06:59:42 PM PDT 24
Peak memory 209248 kb
Host smart-9cfb45aa-b751-454d-896f-f0c128df8055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205051582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.205051582
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3686610301
Short name T457
Test name
Test status
Simulation time 96303410 ps
CPU time 3.68 seconds
Started Aug 01 06:59:21 PM PDT 24
Finished Aug 01 06:59:25 PM PDT 24
Peak memory 207092 kb
Host smart-27f4d631-464b-4c3c-a576-c126d002e1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686610301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3686610301
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3138400747
Short name T57
Test name
Test status
Simulation time 7218623978 ps
CPU time 21.41 seconds
Started Aug 01 06:59:34 PM PDT 24
Finished Aug 01 06:59:55 PM PDT 24
Peak memory 216940 kb
Host smart-c0db9943-4251-4344-8f08-13813870998e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138400747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3138400747
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1622378495
Short name T630
Test name
Test status
Simulation time 726581591 ps
CPU time 3.58 seconds
Started Aug 01 06:59:41 PM PDT 24
Finished Aug 01 06:59:45 PM PDT 24
Peak memory 208216 kb
Host smart-810f653e-d1e8-419d-813e-ad57c6e10f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622378495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1622378495
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.434073861
Short name T392
Test name
Test status
Simulation time 107060138 ps
CPU time 2.4 seconds
Started Aug 01 06:59:34 PM PDT 24
Finished Aug 01 06:59:36 PM PDT 24
Peak memory 209996 kb
Host smart-66f5475a-121c-4740-9464-170ac82f068e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434073861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.434073861
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2714689635
Short name T835
Test name
Test status
Simulation time 34632445 ps
CPU time 0.74 seconds
Started Aug 01 06:59:34 PM PDT 24
Finished Aug 01 06:59:34 PM PDT 24
Peak memory 205960 kb
Host smart-711f4235-40db-4bd2-a02c-31712ce8d751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714689635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2714689635
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.4111582698
Short name T405
Test name
Test status
Simulation time 55291410 ps
CPU time 2.62 seconds
Started Aug 01 06:59:38 PM PDT 24
Finished Aug 01 06:59:41 PM PDT 24
Peak memory 209880 kb
Host smart-6a227c27-c5d4-4ea0-8455-72a577d221b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111582698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.4111582698
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1663548352
Short name T384
Test name
Test status
Simulation time 5769051885 ps
CPU time 33.24 seconds
Started Aug 01 06:59:31 PM PDT 24
Finished Aug 01 07:00:05 PM PDT 24
Peak memory 214356 kb
Host smart-6bbc8023-3aba-412f-bcfa-c06f99566269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663548352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1663548352
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2763857382
Short name T628
Test name
Test status
Simulation time 320354384 ps
CPU time 2.18 seconds
Started Aug 01 06:59:32 PM PDT 24
Finished Aug 01 06:59:34 PM PDT 24
Peak memory 214268 kb
Host smart-3b3bd626-7ae8-421b-92d4-9897226ae8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763857382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2763857382
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1204566584
Short name T754
Test name
Test status
Simulation time 244613268 ps
CPU time 2.35 seconds
Started Aug 01 06:59:33 PM PDT 24
Finished Aug 01 06:59:35 PM PDT 24
Peak memory 214836 kb
Host smart-2a58c8f3-15c7-47c0-9f70-daf6e52dd612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204566584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1204566584
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.4085652813
Short name T616
Test name
Test status
Simulation time 2972552449 ps
CPU time 51.62 seconds
Started Aug 01 06:59:33 PM PDT 24
Finished Aug 01 07:00:25 PM PDT 24
Peak memory 208544 kb
Host smart-8b4ed4a3-ff1a-451f-be05-3c32e724399b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085652813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.4085652813
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3867280466
Short name T851
Test name
Test status
Simulation time 579007461 ps
CPU time 6.12 seconds
Started Aug 01 06:59:31 PM PDT 24
Finished Aug 01 06:59:37 PM PDT 24
Peak memory 207848 kb
Host smart-b65abe56-30a3-4df2-b8e3-83864af12763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867280466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3867280466
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1137906000
Short name T651
Test name
Test status
Simulation time 82998984 ps
CPU time 1.81 seconds
Started Aug 01 06:59:33 PM PDT 24
Finished Aug 01 06:59:35 PM PDT 24
Peak memory 207624 kb
Host smart-74c18c95-ae83-4c68-8e7d-c7ab638d7f32
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137906000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1137906000
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.772576276
Short name T777
Test name
Test status
Simulation time 412135249 ps
CPU time 10.99 seconds
Started Aug 01 06:59:47 PM PDT 24
Finished Aug 01 06:59:58 PM PDT 24
Peak memory 208204 kb
Host smart-7378faa6-c7af-4c92-8d8f-5686a87e0aa1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772576276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.772576276
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2712231830
Short name T523
Test name
Test status
Simulation time 273919273 ps
CPU time 4.87 seconds
Started Aug 01 06:59:31 PM PDT 24
Finished Aug 01 06:59:35 PM PDT 24
Peak memory 206916 kb
Host smart-1ff632c2-fb62-429b-b568-d804ddee5a4a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712231830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2712231830
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.95879711
Short name T644
Test name
Test status
Simulation time 112435211 ps
CPU time 1.94 seconds
Started Aug 01 06:59:35 PM PDT 24
Finished Aug 01 06:59:37 PM PDT 24
Peak memory 218224 kb
Host smart-cdcbc0bb-95ba-4c65-8add-5539f21cc392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95879711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.95879711
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.2916927048
Short name T594
Test name
Test status
Simulation time 92284585 ps
CPU time 1.88 seconds
Started Aug 01 06:59:35 PM PDT 24
Finished Aug 01 06:59:37 PM PDT 24
Peak memory 208496 kb
Host smart-3dc4532a-aa53-461d-8462-d65a0392ae81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916927048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2916927048
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.262143440
Short name T654
Test name
Test status
Simulation time 191529471 ps
CPU time 6.23 seconds
Started Aug 01 06:59:33 PM PDT 24
Finished Aug 01 06:59:39 PM PDT 24
Peak memory 222548 kb
Host smart-8c2e6128-980c-4090-b161-9dcbac8c0a52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262143440 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.262143440
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2583268050
Short name T331
Test name
Test status
Simulation time 162644049 ps
CPU time 4.27 seconds
Started Aug 01 06:59:32 PM PDT 24
Finished Aug 01 06:59:36 PM PDT 24
Peak memory 218276 kb
Host smart-27224174-c98b-4c12-87f1-2309ae79ae79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583268050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2583268050
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3347309157
Short name T552
Test name
Test status
Simulation time 56006773 ps
CPU time 2.76 seconds
Started Aug 01 06:59:38 PM PDT 24
Finished Aug 01 06:59:41 PM PDT 24
Peak memory 209956 kb
Host smart-e9af10ff-6527-4f3b-849a-72626226564c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347309157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3347309157
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1324609195
Short name T442
Test name
Test status
Simulation time 11025469 ps
CPU time 0.83 seconds
Started Aug 01 06:59:38 PM PDT 24
Finished Aug 01 06:59:39 PM PDT 24
Peak memory 205944 kb
Host smart-5e2a273e-8a27-499a-b0db-703304f0e43b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324609195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1324609195
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.341982861
Short name T38
Test name
Test status
Simulation time 236752016 ps
CPU time 2.12 seconds
Started Aug 01 06:59:38 PM PDT 24
Finished Aug 01 06:59:40 PM PDT 24
Peak memory 208148 kb
Host smart-80fdcb43-96b2-468b-919f-442922949fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341982861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.341982861
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.510298834
Short name T770
Test name
Test status
Simulation time 349909487 ps
CPU time 2.39 seconds
Started Aug 01 06:59:41 PM PDT 24
Finished Aug 01 06:59:44 PM PDT 24
Peak memory 208920 kb
Host smart-a7f4b732-4f11-4ddf-a6bf-8547ad3e2b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510298834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.510298834
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2317786713
Short name T385
Test name
Test status
Simulation time 460014181 ps
CPU time 3.34 seconds
Started Aug 01 06:59:33 PM PDT 24
Finished Aug 01 06:59:36 PM PDT 24
Peak memory 209196 kb
Host smart-128b45f9-0289-413e-81f0-d7fc424866ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317786713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2317786713
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1383910540
Short name T94
Test name
Test status
Simulation time 76042802 ps
CPU time 2.22 seconds
Started Aug 01 06:59:38 PM PDT 24
Finished Aug 01 06:59:41 PM PDT 24
Peak memory 214240 kb
Host smart-0aedd643-893a-4f8a-a646-b026c8d005d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383910540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1383910540
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1134605736
Short name T214
Test name
Test status
Simulation time 45314672 ps
CPU time 2.9 seconds
Started Aug 01 06:59:33 PM PDT 24
Finished Aug 01 06:59:36 PM PDT 24
Peak memory 220116 kb
Host smart-fd3ffa57-0e3f-407c-a7b6-667581e48ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134605736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1134605736
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3849267799
Short name T578
Test name
Test status
Simulation time 129360111 ps
CPU time 2.37 seconds
Started Aug 01 06:59:41 PM PDT 24
Finished Aug 01 06:59:43 PM PDT 24
Peak memory 207432 kb
Host smart-5576f770-49f9-4ebc-bc3c-f814e9ade95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849267799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3849267799
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1798195645
Short name T888
Test name
Test status
Simulation time 72368156 ps
CPU time 2.85 seconds
Started Aug 01 06:59:41 PM PDT 24
Finished Aug 01 06:59:44 PM PDT 24
Peak memory 208512 kb
Host smart-8abf135b-fbd3-4473-84d5-ca10d92f8c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798195645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1798195645
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.479103078
Short name T410
Test name
Test status
Simulation time 610958887 ps
CPU time 3.21 seconds
Started Aug 01 06:59:32 PM PDT 24
Finished Aug 01 06:59:35 PM PDT 24
Peak memory 206956 kb
Host smart-665b50b8-8d5e-408d-86a8-9523d7149705
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479103078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.479103078
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1650537275
Short name T905
Test name
Test status
Simulation time 900866100 ps
CPU time 2.7 seconds
Started Aug 01 06:59:41 PM PDT 24
Finished Aug 01 06:59:44 PM PDT 24
Peak memory 207028 kb
Host smart-0704125d-e610-47ba-a21c-70782b5ab148
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650537275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1650537275
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3497595550
Short name T196
Test name
Test status
Simulation time 106925255 ps
CPU time 2.9 seconds
Started Aug 01 06:59:32 PM PDT 24
Finished Aug 01 06:59:35 PM PDT 24
Peak memory 208756 kb
Host smart-3c02d478-1b78-44af-ae55-e0e08ea1c200
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497595550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3497595550
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2648650535
Short name T568
Test name
Test status
Simulation time 4165078394 ps
CPU time 17.58 seconds
Started Aug 01 06:59:38 PM PDT 24
Finished Aug 01 06:59:56 PM PDT 24
Peak memory 208248 kb
Host smart-0978d2f1-9ed5-4a3c-9f12-7ea80ae92be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648650535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2648650535
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2766721127
Short name T751
Test name
Test status
Simulation time 47231430 ps
CPU time 2.42 seconds
Started Aug 01 06:59:38 PM PDT 24
Finished Aug 01 06:59:40 PM PDT 24
Peak memory 206688 kb
Host smart-5beebbf4-faae-46bf-8d0c-ef60d4b739da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766721127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2766721127
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1988474185
Short name T657
Test name
Test status
Simulation time 1140708628 ps
CPU time 20.83 seconds
Started Aug 01 06:59:38 PM PDT 24
Finished Aug 01 06:59:59 PM PDT 24
Peak memory 221148 kb
Host smart-f535f5e2-773e-40af-8e03-e719da1a8bbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988474185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1988474185
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1742536059
Short name T401
Test name
Test status
Simulation time 960257393 ps
CPU time 27.56 seconds
Started Aug 01 06:59:35 PM PDT 24
Finished Aug 01 07:00:03 PM PDT 24
Peak memory 208772 kb
Host smart-8302fc11-fad3-45ac-bbda-a5075b27ee06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742536059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1742536059
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2991755174
Short name T567
Test name
Test status
Simulation time 196555742 ps
CPU time 3.54 seconds
Started Aug 01 06:59:38 PM PDT 24
Finished Aug 01 06:59:42 PM PDT 24
Peak memory 210380 kb
Host smart-bc2bf9dd-2bc6-412f-b4d5-e2f16f0963bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991755174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2991755174
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%