Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	75	255	77.27

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	56	224	80.00	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4819

1

T1

7

T2

3

T3

5

auto[1]

489

1

T1

3

T3

1

T13

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4819

1

T1

7

T2

3

T3

5

auto[1]

489

1

T1

3

T3

1

T13

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4766

1

T1

10

T2

2

T3

5

auto[1]

542

1

T2

1

T3

1

T13

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4766

1

T1

10

T2

2

T3

5

auto[1]

542

1

T2

1

T3

1

T13

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	425	1			T2	1		T26	1		T5	1
auto[OpGenId]	1170	1			T2	1		T3	3		T4	2
auto[OpGenSwOut]	1108	1			T2	1		T3	2		T4	1
auto[OpGenHwOut]	2523	1			T1	10		T3	1		T13	1
auto[OpDisable]	82	1			T5	1		T66	1		T203	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	425	1			T2	1		T26	1		T5	1
auto[OpGenId]	1170	1			T2	1		T3	3		T4	2
auto[OpGenSwOut]	1108	1			T2	1		T3	2		T4	1
auto[OpGenHwOut]	2523	1			T1	10		T3	1		T13	1
auto[OpDisable]	82	1			T5	1		T66	1		T203	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4722

1

T1

10

T2

3

T3

3

auto[1]

586

1

T3

3

T26

2

T83

5

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4722

1

T1

10

T2

3

T3

3

auto[1]

586

1

T3

3

T26

2

T83

5

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5047

1

T1

10

T2

3

T3

6

auto[1]

261

1

T82

9

T116

2

T129

12

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1827	1			T1	3		T2	1		T3	3
auto[1]	695	1			T1	3		T3	1		T4	2
auto[2]	705	1			T1	1		T2	1		T3	1
auto[3]	672	1			T1	1		T2	1		T3	1
auto[4]	345	1			T17	1		T83	1		T5	4
auto[5]	379	1			T17	1		T5	1		T18	1
auto[6]	345	1			T1	1		T13	1		T14	1
auto[7]	340	1			T1	1		T14	1		T17	2

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1409	1			T1	2		T13	1		T14	2
clear_one[1]	695	1			T1	3		T3	1		T4	2
clear_one[2]	705	1			T1	1		T2	1		T3	1
clear_one[3]	672	1			T1	1		T2	1		T3	1
clear_none	1827	1			T1	3		T2	1		T3	3

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	977	1			T1	2		T3	1		T4	1
auto[StInit]	621	1			T1	1		T3	1		T13	1
auto[StCreatorRootKey]	566	1			T1	1		T3	1		T14	1
auto[StOwnerIntKey]	514	1			T1	1		T2	1		T4	1
auto[StOwnerKey]	471	1			T1	1		T3	1		T4	1
auto[StDisabled]	1843	1			T1	4		T2	2		T3	2
auto[StInvalid]	316	1			T15	2		T34	4		T48	3

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	977	1			T1	2		T3	1		T4	1
auto[StInit]	621	1			T1	1		T3	1		T13	1
auto[StCreatorRootKey]	566	1			T1	1		T3	1		T14	1
auto[StOwnerIntKey]	514	1			T1	1		T2	1		T4	1
auto[StOwnerKey]	471	1			T1	1		T3	1		T4	1
auto[StDisabled]	1843	1			T1	4		T2	2		T3	2
auto[StInvalid]	316	1			T15	2		T34	4		T48	3

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	56	224	80.00	56

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[1] - auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[1] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StCreatorRootKey]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StCreatorRootKey]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	2
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[6]]	[auto[StOwnerIntKey]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	2	1			T234	1		T235	1		-	-
auto[0]	auto[StReset]	auto[OpGenId]	158	1			T4	1		T5	2		T44	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	149	1			T5	1		T82	1		T42	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	272	1			T1	2		T3	1		T17	1
auto[0]	auto[StInit]	auto[OpAdvance]	30	1			T19	1		T200	1		T236	1
auto[0]	auto[StInit]	auto[OpGenId]	92	1			T18	1		T237	1		T44	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	98	1			T3	1		T13	1		T5	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	166	1			T83	1		T5	1		T80	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	21	1			T78	1		T116	1		T238	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	45	1			T14	1		T32	1		T204	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	58	1			T44	2		T130	2		T60	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	87	1			T5	2		T44	1		T189	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	12	1			T71	1		T239	1		T240	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	26	1			T206	1		T188	1		T131	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	30	1			T2	1		T131	1		T241	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	49	1			T1	1		T5	1		T213	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	14	1			T182	1		T236	1		T77	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	26	1			T5	1		T242	1		T131	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T243	1		T244	1		T191	2
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	42	1			T189	1		T210	1		T131	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	20	1			T82	1		T44	1		T236	1
auto[0]	auto[StDisabled]	auto[OpGenId]	60	1			T3	1		T116	1		T245	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	75	1			T82	3		T44	1		T199	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	171	1			T13	1		T83	2		T81	2
auto[0]	auto[StDisabled]	auto[OpDisable]	20	1			T68	1		T71	1		T246	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	18	1			T48	1		T24	1		T247	1
auto[0]	auto[StInvalid]	auto[OpGenId]	27	1			T34	1		T248	1		T249	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	21	1			T15	1		T34	2		T214	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	21	1			T15	1		T249	1		T24	2
auto[1]	auto[StReset]	auto[OpGenId]	23	1			T123	1		T58	1		T127	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	12	1			T199	1		T89	1		T192	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	45	1			T17	1		T5	1		T250	1
auto[1]	auto[StInit]	auto[OpAdvance]	4	1			T251	1		T252	1		T253	1
auto[1]	auto[StInit]	auto[OpGenId]	12	1			T254	1		T123	1		T134	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	12	1			T5	1		T82	1		T67	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	19	1			T1	1		T81	1		T255	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T82	2		T116	1		T256	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T219	1		T257	1		T258	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T82	1		T203	1		T220	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	33	1			T5	1		T82	1		T200	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T116	1		T54	1		T62	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T259	1		T260	1		T218	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	20	1			T4	1		T78	1		T254	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	42	1			T5	1		T82	2		T44	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T131	1		T23	1		T236	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	16	1			T3	1		T4	1		T44	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T261	1		T72	1		T262	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	50	1			T1	1		T78	1		T82	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	27	1			T129	2		T200	1		T25	1
auto[1]	auto[StDisabled]	auto[OpGenId]	56	1			T206	1		T131	2		T23	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	59	1			T237	1		T44	1		T242	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	146	1			T1	1		T83	1		T78	1
auto[1]	auto[StDisabled]	auto[OpDisable]	13	1			T58	1		T61	1		T62	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	8	1			T89	1		T263	1		T264	1
auto[1]	auto[StInvalid]	auto[OpGenId]	7	1			T89	1		T265	1		T266	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T86	1		T267	1		T264	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T86	1		T268	1		T269	1
auto[2]	auto[StReset]	auto[OpGenId]	17	1			T129	1		T245	1		T67	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	20	1			T5	1		T205	1		T60	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	43	1			T17	1		T83	2		T81	2
auto[2]	auto[StInit]	auto[OpAdvance]	5	1			T270	3		T271	1		T272	1
auto[2]	auto[StInit]	auto[OpGenId]	7	1			T97	2		T273	1		T274	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	7	1			T31	1		T61	1		T46	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	19	1			T275	1		T245	1		T100	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T130	2		T7	1		T276	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	17	1			T129	1		T277	1		T278	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T5	1		T18	1		T129	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	47	1			T17	1		T80	1		T211	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T129	2		T88	1		T62	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	17	1			T45	1		T70	1		T61	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T26	1		T129	1		T100	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	41	1			T17	1		T83	1		T81	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T203	1		T279	1		T77	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	14	1			T188	1		T67	1		T280	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T274	1		T281	1		T257	2
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	37	1			T83	1		T282	1		T250	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	33	1			T2	1		T130	1		T203	1
auto[2]	auto[StDisabled]	auto[OpGenId]	60	1			T26	1		T129	2		T130	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	61	1			T3	1		T13	1		T129	3
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	144	1			T1	1		T17	1		T81	1
auto[2]	auto[StDisabled]	auto[OpDisable]	10	1			T203	1		T71	1		T72	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	6	1			T24	1		T283	1		T284	1
auto[2]	auto[StInvalid]	auto[OpGenId]	10	1			T267	1		T268	1		T285	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	15	1			T263	2		T286	1		T287	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T248	1		T87	1		T288	1
auto[3]	auto[StReset]	auto[OpGenId]	24	1			T27	1		T203	1		T88	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	21	1			T199	1		T203	1		T198	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	37	1			T17	1		T81	1		T130	1
auto[3]	auto[StInit]	auto[OpAdvance]	10	1			T123	1		T261	1		T289	1
auto[3]	auto[StInit]	auto[OpGenId]	6	1			T94	1		T290	1		T291	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	11	1			T292	1		T274	1		T85	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	28	1			T293	1		T60	1		T58	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T294	1		T295	1		T61	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T3	1		T66	1		T54	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	19	1			T23	1		T125	1		T274	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	32	1			T250	1		T275	1		T296	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T297	2		T298	1		-	-
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	20	1			T294	1		T299	1		T25	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T67	1		T133	1		T300	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	37	1			T207	1		T301	1		T302	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T297	1		T230	2		T303	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	10	1			T61	1		T304	1		T305	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T191	1		T306	1		T229	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	32	1			T186	1		T207	1		T307	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	24	1			T129	1		T242	1		T54	2
auto[3]	auto[StDisabled]	auto[OpGenId]	66	1			T2	1		T206	1		T188	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	45	1			T54	1		T67	1		T63	3
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	130	1			T1	1		T17	1		T213	1
auto[3]	auto[StDisabled]	auto[OpDisable]	16	1			T70	1		T73	1		T74	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	4	1			T48	1		T308	1		T288	1
auto[3]	auto[StInvalid]	auto[OpGenId]	20	1			T248	1		T89	2		T309	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T263	1		T310	1		T285	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	20	1			T34	1		T248	1		T86	1
auto[4]	auto[StReset]	auto[OpGenId]	7	1			T71	1		T311	1		T65	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	7	1			T5	1		T62	1		T38	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	16	1			T213	1		T134	1		T312	1
auto[4]	auto[StInit]	auto[OpAdvance]	1	1			T313	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenId]	6	1			T261	1		T94	1		T314	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	4	1			T67	1		T94	1		T315	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	10	1			T316	1		T97	1		T317	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T186	1		T218	1		T77	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	2	1			T5	1		T318	1		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	15	1			T319	1		T320	1		T123	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T5	1		T321	1		T226	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T311	1		T74	1		T274	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T203	1		T292	1		T274	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T80	1		T275	1		T322	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T229	1		T298	1		T230	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	12	1			T241	1		T256	1		T323	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T254	1		T324	1		T325	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	24	1			T81	1		T116	1		T209	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	9	1			T199	1		T135	1		T274	2
auto[4]	auto[StDisabled]	auto[OpGenId]	30	1			T100	1		T326	1		T289	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T5	1		T78	1		T70	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	80	1			T17	1		T83	1		T189	2
auto[4]	auto[StDisabled]	auto[OpDisable]	7	1			T67	1		T62	1		T327	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	10	1			T86	1		T249	1		T87	1
auto[4]	auto[StInvalid]	auto[OpGenId]	6	1			T87	1		T328	1		T329	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T84	1		T330	2		T331	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T294	1		T332	1		T333	2
auto[5]	auto[StReset]	auto[OpGenId]	9	1			T100	1		T61	2		T174	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	7	1			T244	1		T77	2		T252	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	16	1			T334	1		T335	2		T38	1
auto[5]	auto[StInit]	auto[OpAdvance]	7	1			T88	1		T336	1		T226	1
auto[5]	auto[StInit]	auto[OpGenId]	5	1			T58	1		T61	2		T337	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	9	1			T238	1		T338	1		T94	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	12	1			T339	1		T297	1		T229	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T340	1		T47	1		T341	2
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T54	1		T342	1		T72	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T242	1		T343	1		T344	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T81	1		T208	1		T345	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T60	1		T342	1		T346	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T18	1		T278	1		T72	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T54	1		T347	1		T348	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	28	1			T211	1		T209	1		T208	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T261	1		T71	1		T257	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	13	1			T58	1		T239	1		T222	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T349	1		T350	1		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T17	1		T275	1		T208	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	11	1			T261	1		T300	1		T274	1
auto[5]	auto[StDisabled]	auto[OpGenId]	32	1			T25	1		T256	1		T244	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	35	1			T200	1		T203	1		T60	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	81	1			T5	1		T116	1		T213	1
auto[5]	auto[StDisabled]	auto[OpDisable]	5	1			T347	1		T127	1		T274	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	5	1			T287	1		T351	1		T352	1
auto[5]	auto[StInvalid]	auto[OpGenId]	6	1			T265	1		T353	1		T354	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T294	1		T309	1		T354	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T249	1		T294	1		T264	1
auto[6]	auto[StReset]	auto[OpGenId]	8	1			T123	1		T355	1		T356	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	12	1			T54	1		T203	1		T198	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	30	1			T83	1		T213	1		T60	1
auto[6]	auto[StInit]	auto[OpAdvance]	5	1			T44	1		T125	1		T304	1
auto[6]	auto[StInit]	auto[OpGenId]	2	1			T175	1		T47	1		-	-
auto[6]	auto[StInit]	auto[OpGenSwOut]	6	1			T54	1		T357	1		T358	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	7	1			T219	1		T290	1		T359	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T77	1		T305	1		T360	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T58	1		T361	1		T362	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	1	1			T363	1		-	-		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T83	1		T293	1		T364	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T276	1		T262	1		T363	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T237	1		T337	1		T262	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T365	1		T255	1		T185	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T365	1		T54	1		T366	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	5	1			T274	1		T85	1		T367	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T274	1		T77	1		T368	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T80	1		T369	1		T319	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	14	1			T26	1		T370	1		T281	2
auto[6]	auto[StDisabled]	auto[OpGenId]	29	1			T371	1		T54	1		T67	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T13	1		T100	1		T63	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	82	1			T1	1		T14	1		T80	1
auto[6]	auto[StDisabled]	auto[OpDisable]	6	1			T66	1		T219	1		T290	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	2	1			T372	1		T373	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	9	1			T308	1		T89	1		T353	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T328	1		T374	1		T375	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T48	1		T268	1		T310	1
auto[7]	auto[StReset]	auto[OpAdvance]	1	1			T376	1		-	-		-	-
auto[7]	auto[StReset]	auto[OpGenId]	9	1			T26	1		T82	1		T61	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	10	1			T67	1		T123	1		T261	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	22	1			T334	2		T317	1		T285	1
auto[7]	auto[StInit]	auto[OpAdvance]	4	1			T129	1		T97	1		T274	1
auto[7]	auto[StInit]	auto[OpGenId]	1	1			T377	1		-	-		-	-
auto[7]	auto[StInit]	auto[OpGenSwOut]	4	1			T67	1		T94	1		T378	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	12	1			T17	1		T213	1		T131	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T237	1		T134	1		T379	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T67	1		T380	1		T298	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T5	1		T60	1		T381	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	25	1			T1	1		T213	1		T210	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T257	1		T382	1		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	17	1			T274	1		T229	1		T383	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T384	1		T358	1		T385	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T320	1		T386	1		T317	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T292	1		T337	1		T387	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	6	1			T125	1		T289	1		T260	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T388	1		T389	1		T390	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T44	1		T203	1		T316	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	10	1			T274	1		T391	1		T290	1
auto[7]	auto[StDisabled]	auto[OpGenId]	33	1			T206	1		T63	1		T277	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	21	1			T203	2		T61	2		T62	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	67	1			T14	1		T17	1		T80	1
auto[7]	auto[StDisabled]	auto[OpDisable]	5	1			T5	1		T63	1		T392	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	3	1			T372	1		T393	1		T352	1
auto[7]	auto[StInvalid]	auto[OpGenId]	6	1			T268	1		T329	1		T394	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T86	1		T287	1		T312	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T352	1		T395	1		T396	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1409

1

T1

2

T13

1

T14

2

clear_one[1]

auto[0]

auto[0]

auto[0]

384

1

T1

3

T4

2

T17

1

clear_one[1]

auto[0]

auto[0]

auto[1]

135

1

T83

1

T5

1

T78

1

clear_one[1]

auto[0]

auto[1]

auto[0]

140

1

T78

1

T80

2

T44

2

clear_one[1]

auto[0]

auto[1]

auto[1]

36

1

T3

1

T82

1

T237

1

clear_one[2]

auto[0]

auto[0]

auto[0]

437

1

T2

1

T13

1

T17

4

clear_one[2]

auto[0]

auto[0]

auto[1]

118

1

T3

1

T26

2

T83

2

clear_one[2]

auto[1]

auto[0]

auto[0]

111

1

T1

1

T189

1

T207

1

clear_one[2]

auto[1]

auto[0]

auto[1]

39

1

T44

1

T130

4

T59

1

clear_one[3]

auto[0]

auto[0]

auto[0]

427

1

T2

1

T3

1

T17

1

clear_one[3]

auto[0]

auto[1]

auto[0]

130

1

T17

1

T186

1

T250

2

clear_one[3]

auto[1]

auto[0]

auto[0]

92

1

T1

1

T213

1

T207

2

clear_one[3]

auto[1]

auto[1]

auto[0]

23

1

T205

1

T292

1

T397

1

clear_none

auto[0]

auto[0]

auto[0]

1293

1

T1

2

T3

2

T4

1

clear_none

auto[0]

auto[0]

auto[1]

153

1

T83

2

T5

1

T81

2

clear_none

auto[0]

auto[1]

auto[0]

114

1

T2

1

T14

1

T116

1

clear_none

auto[0]

auto[1]

auto[1]

43

1

T5

1

T82

4

T237

1

clear_none

auto[1]

auto[0]

auto[0]

129

1

T1

1

T5

1

T213

2

clear_none

auto[1]

auto[0]

auto[1]

39

1

T3

1

T44

1

T398

1

clear_none

auto[1]

auto[1]

auto[0]

33

1

T13

1

T5

1

T186

1

clear_none

auto[1]

auto[1]

auto[1]

23

1

T44

1

T70

1

T191

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1332	1			T1	2		T13	1		T14	2
clear_all	auto[1]	77	1			T131	1		T261	3		T342	1
clear_one[1]	auto[0]	665	1			T1	3		T3	1		T4	2
clear_one[1]	auto[1]	30	1			T82	5		T116	1		T129	2
clear_one[2]	auto[0]	642	1			T1	1		T2	1		T3	1
clear_one[2]	auto[1]	63	1			T129	10		T130	11		T236	3
clear_one[3]	auto[0]	653	1			T1	1		T2	1		T3	1
clear_one[3]	auto[1]	19	1			T261	1		T132	2		T256	1
clear_none	auto[0]	1755	1			T1	3		T2	1		T3	3
clear_none	auto[1]	72	1			T82	4		T116	1		T130	1