Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11085

1

T1

9

T2

18

T3

21

auto[Attestation]

7738

1

T1

5

T2

10

T3

8

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2772	1			T2	5		T3	2		T4	3
auto[Aes]	3309	1			T1	14		T2	1		T3	5
auto[Kmac]	3285	1			T2	10		T3	7		T4	3
auto[Otbn]	3451	1			T2	4		T3	4		T4	5

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7638	1			T1	8		T2	8		T3	8
auto[OpGenId]	6006	1			T2	8		T3	11		T4	8
auto[OpGenSwOut]	5952	1			T2	10		T3	11		T4	5
auto[OpGenHwOut]	6865	1			T1	14		T2	10		T3	7
auto[OpDisable]	150	1			T5	2		T44	3		T45	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10651

1

T1

8

T2

16

T3

16

auto[OpDoneFail]

15960

1

T1

14

T2

20

T3

21

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6487	1			T1	7		T2	1		T3	5
auto[StInit]	3787	1			T1	2		T2	6		T3	2
auto[StCreatorRootKey]	3154	1			T1	2		T2	3		T3	3
auto[StOwnerIntKey]	2734	1			T1	2		T2	6		T3	6
auto[StOwnerKey]	2518	1			T1	2		T2	5		T3	5
auto[StDisabled]	7931	1			T1	7		T2	15		T3	16

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	337	1			T26	3		T5	2		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	110	1			T26	1		T5	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	95	1			T18	1		T44	1		T130	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	71	1			T2	1		T14	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	59	1			T35	1		T197	1		T198	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	228	1			T3	1		T13	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	332	1			T3	1		T16	2		T26	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	103	1			T2	1		T5	2		T79	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	92	1			T16	1		T131	1		T199	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	72	1			T3	1		T4	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	60	1			T14	1		T16	1		T200	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	198	1			T3	1		T5	1		T190	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	323	1			T4	1		T5	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	106	1			T82	1		T44	1		T190	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	65	1			T79	1		T44	2		T131	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	67	1			T26	1		T5	1		T201	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	54	1			T2	1		T5	2		T79	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	196	1			T2	1		T13	1		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	325	1			T5	2		T82	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	99	1			T2	1		T3	1		T32	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	79	1			T3	1		T13	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	84	1			T26	1		T5	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	49	1			T5	1		T202	1		T200	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	232	1			T14	1		T23	1		T200	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	97	1			T54	1		T203	1		T67	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	94	1			T27	1		T5	1		T35	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	87	1			T26	1		T5	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	72	1			T2	1		T13	1		T35	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	75	1			T4	1		T14	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	250	1			T2	1		T13	2		T5	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	76	1			T54	4		T203	4		T60	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	90	1			T33	1		T26	2		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	93	1			T13	1		T26	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	56	1			T5	1		T44	1		T100	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	67	1			T13	2		T14	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	205	1			T13	1		T5	1		T78	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	79	1			T60	1		T123	2		T71	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	110	1			T82	2		T204	1		T205	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	75	1			T5	1		T82	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	74	1			T2	1		T3	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	69	1			T2	1		T3	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	224	1			T3	3		T5	2		T82	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	74	1			T54	1		T203	2		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	100	1			T13	1		T5	1		T78	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	72	1			T5	1		T129	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	77	1			T2	1		T4	1		T78	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	72	1			T5	1		T44	2		T131	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	228	1			T13	1		T14	2		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	266	1			T3	1		T26	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	102	1			T13	1		T5	2		T187	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	66	1			T16	1		T5	1		T206	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	61	1			T4	1		T13	1		T82	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	49	1			T2	1		T78	1		T116	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	177	1			T13	1		T5	4		T82	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	507	1			T1	6		T26	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	99	1			T188	1		T189	1		T207	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	105	1			T1	1		T16	1		T32	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	93	1			T14	1		T44	1		T208	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	81	1			T206	1		T189	1		T207	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	272	1			T1	2		T3	2		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	416	1			T3	1		T17	7		T26	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	112	1			T2	2		T78	2		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	121	1			T14	1		T80	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	92	1			T2	1		T17	1		T82	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	101	1			T13	1		T17	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	262	1			T2	1		T17	3		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	434	1			T4	1		T83	13		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	139	1			T4	1		T83	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	94	1			T204	1		T209	1		T210	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	113	1			T3	1		T83	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	92	1			T78	1		T116	1		T211	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	281	1			T2	1		T3	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	55	1			T54	2		T203	1		T123	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	86	1			T5	3		T35	1		T212	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	63	1			T5	1		T82	1		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	65	1			T5	1		T130	1		T54	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	49	1			T5	1		T44	1		T200	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	158	1			T2	1		T4	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	63	1			T54	2		T203	3		T60	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	118	1			T1	1		T16	1		T32	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	126	1			T32	1		T5	2		T200	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	66	1			T1	1		T213	1		T189	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	82	1			T1	1		T4	1		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	253	1			T1	2		T13	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	55	1			T54	2		T60	2		T123	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	127	1			T17	1		T5	1		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	107	1			T2	1		T17	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	83	1			T3	1		T5	1		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	82	1			T80	1		T186	1		T205	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	285	1			T2	1		T4	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	78	1			T54	3		T203	2		T123	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	123	1			T32	1		T5	1		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	115	1			T83	1		T5	1		T81	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	94	1			T26	1		T5	1		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	102	1			T14	1		T83	1		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	295	1			T2	1		T4	1		T83	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	199	1			T2	1		T14	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	701	1			T3	1		T13	1		T26	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	205	1			T3	1		T4	1		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	652	1			T2	1		T3	2		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	176	1			T2	1		T26	1		T5	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	635	1			T2	1		T4	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	199	1			T3	1		T13	1		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	669	1			T2	1		T3	1		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	222	1			T2	1		T4	1		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	453	1			T2	1		T13	2		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	202	1			T13	3		T14	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	385	1			T13	1		T33	1		T26	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	205	1			T2	2		T3	2		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	426	1			T3	3		T5	2		T82	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	201	1			T2	1		T4	1		T5	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	422	1			T13	2		T14	2		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	163	1			T2	1		T4	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	558	1			T3	1		T13	2		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	259	1			T1	1		T14	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	898	1			T1	8		T3	2		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	298	1			T2	1		T13	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	806	1			T2	3		T3	1		T17	10
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	285	1			T3	1		T83	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	868	1			T2	1		T3	1		T4	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	164	1			T5	3		T82	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	312	1			T2	1		T4	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	263	1			T1	2		T4	1		T32	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	445	1			T1	3		T13	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	262	1			T2	1		T3	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	477	1			T2	1		T4	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	298	1			T14	1		T26	1		T83	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	509	1			T2	1		T4	1		T32	1