Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32734

1

T1

27

T2

42

T3

42

auto[1]

277

1

T82

5

T116

1

T129

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32744	1			T1	27		T2	42		T3	42
auto[134217728:268435455]	5	1			T236	1		T135	1		T384	1
auto[268435456:402653183]	10	1			T82	1		T236	2		T132	1
auto[402653184:536870911]	14	1			T129	1		T261	3		T256	1
auto[536870912:671088639]	8	1			T131	3		T279	1		T270	1
auto[671088640:805306367]	7	1			T234	1		T271	1		T417	1
auto[805306368:939524095]	5	1			T130	1		T132	1		T387	1
auto[939524096:1073741823]	7	1			T129	1		T270	1		T234	1
auto[1073741824:1207959551]	7	1			T82	1		T135	1		T279	1
auto[1207959552:1342177279]	5	1			T261	1		T281	1		T270	1
auto[1342177280:1476395007]	12	1			T129	1		T261	1		T295	1
auto[1476395008:1610612735]	6	1			T129	1		T130	1		T256	1
auto[1610612736:1744830463]	12	1			T129	1		T132	1		T295	1
auto[1744830464:1879048191]	10	1			T130	1		T131	1		T306	1
auto[1879048192:2013265919]	7	1			T418	1		T419	1		T270	1
auto[2013265920:2147483647]	5	1			T130	1		T261	1		T132	1
auto[2147483648:2281701375]	11	1			T82	2		T105	2		T234	2
auto[2281701376:2415919103]	10	1			T261	1		T132	1		T342	1
auto[2415919104:2550136831]	9	1			T130	1		T131	1		T236	1
auto[2550136832:2684354559]	7	1			T270	1		T234	2		T420	1
auto[2684354560:2818572287]	5	1			T279	1		T297	1		T421	1
auto[2818572288:2952790015]	15	1			T132	1		T306	1		T281	1
auto[2952790016:3087007743]	12	1			T131	1		T236	1		T135	1
auto[3087007744:3221225471]	9	1			T129	1		T236	1		T418	1
auto[3221225472:3355443199]	7	1			T130	1		T131	1		T279	1
auto[3355443200:3489660927]	9	1			T116	1		T261	1		T132	1
auto[3489660928:3623878655]	10	1			T131	1		T261	1		T256	1
auto[3623878656:3758096383]	8	1			T129	2		T281	1		T418	2
auto[3758096384:3892314111]	9	1			T236	1		T279	1		T418	1
auto[3892314112:4026531839]	8	1			T82	1		T130	1		T261	1
auto[4026531840:4160749567]	7	1			T131	1		T422	1		T423	1
auto[4160749568:4294967295]	11	1			T130	1		T131	1		T281	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32734	1			T1	27		T2	42		T3	42
auto[0:134217727]	auto[1]	10	1			T130	2		T418	1		T424	1
auto[134217728:268435455]	auto[1]	5	1			T236	1		T135	1		T384	1
auto[268435456:402653183]	auto[1]	10	1			T82	1		T236	2		T132	1
auto[402653184:536870911]	auto[1]	14	1			T129	1		T261	3		T256	1
auto[536870912:671088639]	auto[1]	8	1			T131	3		T279	1		T270	1
auto[671088640:805306367]	auto[1]	7	1			T234	1		T271	1		T417	1
auto[805306368:939524095]	auto[1]	5	1			T130	1		T132	1		T387	1
auto[939524096:1073741823]	auto[1]	7	1			T129	1		T270	1		T234	1
auto[1073741824:1207959551]	auto[1]	7	1			T82	1		T135	1		T279	1
auto[1207959552:1342177279]	auto[1]	5	1			T261	1		T281	1		T270	1
auto[1342177280:1476395007]	auto[1]	12	1			T129	1		T261	1		T295	1
auto[1476395008:1610612735]	auto[1]	6	1			T129	1		T130	1		T256	1
auto[1610612736:1744830463]	auto[1]	12	1			T129	1		T132	1		T295	1
auto[1744830464:1879048191]	auto[1]	10	1			T130	1		T131	1		T306	1
auto[1879048192:2013265919]	auto[1]	7	1			T418	1		T419	1		T270	1
auto[2013265920:2147483647]	auto[1]	5	1			T130	1		T261	1		T132	1
auto[2147483648:2281701375]	auto[1]	11	1			T82	2		T105	2		T234	2
auto[2281701376:2415919103]	auto[1]	10	1			T261	1		T132	1		T342	1
auto[2415919104:2550136831]	auto[1]	9	1			T130	1		T131	1		T236	1
auto[2550136832:2684354559]	auto[1]	7	1			T270	1		T234	2		T420	1
auto[2684354560:2818572287]	auto[1]	5	1			T279	1		T297	1		T421	1
auto[2818572288:2952790015]	auto[1]	15	1			T132	1		T306	1		T281	1
auto[2952790016:3087007743]	auto[1]	12	1			T131	1		T236	1		T135	1
auto[3087007744:3221225471]	auto[1]	9	1			T129	1		T236	1		T418	1
auto[3221225472:3355443199]	auto[1]	7	1			T130	1		T131	1		T279	1
auto[3355443200:3489660927]	auto[1]	9	1			T116	1		T261	1		T132	1
auto[3489660928:3623878655]	auto[1]	10	1			T131	1		T261	1		T256	1
auto[3623878656:3758096383]	auto[1]	8	1			T129	2		T281	1		T418	2
auto[3758096384:3892314111]	auto[1]	9	1			T236	1		T279	1		T418	1
auto[3892314112:4026531839]	auto[1]	8	1			T82	1		T130	1		T261	1
auto[4026531840:4160749567]	auto[1]	7	1			T131	1		T422	1		T423	1
auto[4160749568:4294967295]	auto[1]	11	1			T130	1		T131	1		T281	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1547

1

T2

4

T3

1

T13

3

auto[1]

1816

1

T3

2

T4

5

T13

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	101	1			T3	1		T15	1		T5	1
auto[134217728:268435455]	91	1			T13	1		T34	1		T82	1
auto[268435456:402653183]	95	1			T5	1		T44	1		T187	1
auto[402653184:536870911]	107	1			T2	1		T13	1		T26	1
auto[536870912:671088639]	101	1			T13	1		T26	1		T5	1
auto[671088640:805306367]	109	1			T78	1		T43	1		T242	1
auto[805306368:939524095]	106	1			T129	1		T242	1		T205	1
auto[939524096:1073741823]	119	1			T2	1		T4	1		T26	1
auto[1073741824:1207959551]	103	1			T2	1		T44	2		T20	1
auto[1207959552:1342177279]	106	1			T26	1		T5	1		T237	1
auto[1342177280:1476395007]	127	1			T2	1		T27	1		T5	5
auto[1476395008:1610612735]	92	1			T15	2		T5	1		T49	2
auto[1610612736:1744830463]	89	1			T15	1		T78	1		T51	1
auto[1744830464:1879048191]	107	1			T4	1		T13	1		T14	1
auto[1879048192:2013265919]	99	1			T129	2		T205	1		T198	1
auto[2013265920:2147483647]	98	1			T5	1		T78	1		T44	1
auto[2147483648:2281701375]	112	1			T4	1		T5	1		T82	1
auto[2281701376:2415919103]	117	1			T27	2		T5	1		T18	1
auto[2415919104:2550136831]	131	1			T3	1		T32	1		T26	1
auto[2550136832:2684354559]	118	1			T14	1		T5	2		T49	1
auto[2684354560:2818572287]	98	1			T42	1		T44	1		T187	1
auto[2818572288:2952790015]	91	1			T4	1		T5	1		T20	1
auto[2952790016:3087007743]	110	1			T3	1		T26	1		T5	1
auto[3087007744:3221225471]	88	1			T5	1		T49	1		T42	2
auto[3221225472:3355443199]	96	1			T13	1		T15	1		T237	1
auto[3355443200:3489660927]	112	1			T14	1		T5	2		T49	1
auto[3489660928:3623878655]	100	1			T237	1		T44	1		T242	1
auto[3623878656:3758096383]	86	1			T5	1		T42	1		T100	1
auto[3758096384:3892314111]	121	1			T26	1		T82	1		T42	1
auto[3892314112:4026531839]	116	1			T4	1		T43	2		T51	1
auto[4026531840:4160749567]	105	1			T14	2		T5	1		T78	1
auto[4160749568:4294967295]	112	1			T34	1		T116	1		T20	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	38	1			T86	1		T203	1		T198	1
auto[0:134217727]	auto[1]	63	1			T3	1		T15	1		T5	1
auto[134217728:268435455]	auto[0]	37	1			T13	1		T34	1		T31	1
auto[134217728:268435455]	auto[1]	54	1			T82	1		T43	1		T116	1
auto[268435456:402653183]	auto[0]	47	1			T5	1		T187	1		T100	1
auto[268435456:402653183]	auto[1]	48	1			T44	1		T130	1		T48	1
auto[402653184:536870911]	auto[0]	46	1			T2	1		T42	1		T28	1
auto[402653184:536870911]	auto[1]	61	1			T13	1		T26	1		T5	1
auto[536870912:671088639]	auto[0]	45	1			T26	1		T23	1		T54	1
auto[536870912:671088639]	auto[1]	56	1			T13	1		T5	1		T44	1
auto[671088640:805306367]	auto[0]	48	1			T78	1		T242	1		T294	1
auto[671088640:805306367]	auto[1]	61	1			T43	1		T200	1		T29	1
auto[805306368:939524095]	auto[0]	53	1			T24	1		T54	1		T67	1
auto[805306368:939524095]	auto[1]	53	1			T129	1		T242	1		T205	1
auto[939524096:1073741823]	auto[0]	55	1			T2	1		T44	2		T28	2
auto[939524096:1073741823]	auto[1]	64	1			T4	1		T26	1		T5	1
auto[1073741824:1207959551]	auto[0]	48	1			T2	1		T20	1		T199	1
auto[1073741824:1207959551]	auto[1]	55	1			T44	2		T100	1		T54	1
auto[1207959552:1342177279]	auto[0]	48	1			T26	1		T237	1		T242	1
auto[1207959552:1342177279]	auto[1]	58	1			T5	1		T70	2		T236	1
auto[1342177280:1476395007]	auto[0]	52	1			T2	1		T82	1		T129	1
auto[1342177280:1476395007]	auto[1]	75	1			T27	1		T5	5		T82	1
auto[1476395008:1610612735]	auto[0]	44	1			T15	1		T49	2		T242	1
auto[1476395008:1610612735]	auto[1]	48	1			T15	1		T5	1		T131	1
auto[1610612736:1744830463]	auto[0]	40	1			T15	1		T78	1		T51	1
auto[1610612736:1744830463]	auto[1]	49	1			T130	1		T23	1		T203	1
auto[1744830464:1879048191]	auto[0]	49	1			T13	1		T26	1		T5	1
auto[1744830464:1879048191]	auto[1]	58	1			T4	1		T14	1		T34	1
auto[1879048192:2013265919]	auto[0]	51	1			T198	1		T60	1		T292	1
auto[1879048192:2013265919]	auto[1]	48	1			T129	2		T205	1		T425	1
auto[2013265920:2147483647]	auto[0]	38	1			T199	1		T25	1		T58	1
auto[2013265920:2147483647]	auto[1]	60	1			T5	1		T78	1		T44	1
auto[2147483648:2281701375]	auto[0]	51	1			T44	1		T51	1		T45	1
auto[2147483648:2281701375]	auto[1]	61	1			T4	1		T5	1		T82	1
auto[2281701376:2415919103]	auto[0]	63	1			T27	1		T5	1		T44	1
auto[2281701376:2415919103]	auto[1]	54	1			T27	1		T18	1		T129	1
auto[2415919104:2550136831]	auto[0]	52	1			T3	1		T44	1		T20	1
auto[2415919104:2550136831]	auto[1]	79	1			T32	1		T26	1		T5	3
auto[2550136832:2684354559]	auto[0]	49	1			T5	1		T49	1		T130	1
auto[2550136832:2684354559]	auto[1]	69	1			T14	1		T5	1		T19	1
auto[2684354560:2818572287]	auto[0]	47	1			T42	1		T187	1		T51	1
auto[2684354560:2818572287]	auto[1]	51	1			T44	1		T54	1		T67	2
auto[2818572288:2952790015]	auto[0]	33	1			T20	1		T199	1		T21	1
auto[2818572288:2952790015]	auto[1]	58	1			T4	1		T5	1		T212	1
auto[2952790016:3087007743]	auto[0]	57	1			T44	1		T51	1		T21	1
auto[2952790016:3087007743]	auto[1]	53	1			T3	1		T26	1		T5	1
auto[3087007744:3221225471]	auto[0]	42	1			T5	1		T49	1		T42	1
auto[3087007744:3221225471]	auto[1]	46	1			T42	1		T426	1		T203	1
auto[3221225472:3355443199]	auto[0]	44	1			T13	1		T15	1		T238	1
auto[3221225472:3355443199]	auto[1]	52	1			T237	1		T130	1		T199	1
auto[3355443200:3489660927]	auto[0]	60	1			T5	2		T49	1		T45	1
auto[3355443200:3489660927]	auto[1]	52	1			T14	1		T44	2		T54	1
auto[3489660928:3623878655]	auto[0]	45	1			T199	1		T135	1		T53	1
auto[3489660928:3623878655]	auto[1]	55	1			T237	1		T44	1		T242	1
auto[3623878656:3758096383]	auto[0]	44	1			T5	1		T42	1		T100	1
auto[3623878656:3758096383]	auto[1]	42	1			T63	1		T261	1		T427	1
auto[3758096384:3892314111]	auto[0]	62	1			T26	1		T82	1		T42	1
auto[3758096384:3892314111]	auto[1]	59	1			T66	1		T405	1		T100	1
auto[3892314112:4026531839]	auto[0]	55	1			T43	2		T51	1		T212	1
auto[3892314112:4026531839]	auto[1]	61	1			T4	1		T199	1		T60	2
auto[4026531840:4160749567]	auto[0]	48	1			T44	1		T187	1		T212	1
auto[4026531840:4160749567]	auto[1]	57	1			T14	2		T5	1		T78	1
auto[4160749568:4294967295]	auto[0]	56	1			T34	1		T20	1		T48	2
auto[4160749568:4294967295]	auto[1]	56	1			T116	1		T212	1		T54	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1567

1

T2

3

T3

1

T13

3

auto[1]

1796

1

T2

1

T3

2

T4

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	90	1			T13	1		T34	1		T5	1
auto[134217728:268435455]	99	1			T4	1		T49	1		T51	1
auto[268435456:402653183]	92	1			T26	1		T27	1		T130	1
auto[402653184:536870911]	108	1			T4	1		T13	1		T5	1
auto[536870912:671088639]	96	1			T13	1		T15	1		T26	1
auto[671088640:805306367]	98	1			T5	2		T49	1		T42	1
auto[805306368:939524095]	98	1			T2	1		T13	1		T5	1
auto[939524096:1073741823]	94	1			T26	1		T49	1		T82	1
auto[1073741824:1207959551]	112	1			T2	1		T44	3		T187	1
auto[1207959552:1342177279]	117	1			T3	1		T18	1		T44	1
auto[1342177280:1476395007]	93	1			T26	1		T49	1		T237	2
auto[1476395008:1610612735]	101	1			T15	1		T5	1		T187	1
auto[1610612736:1744830463]	108	1			T13	1		T23	1		T45	1
auto[1744830464:1879048191]	111	1			T4	1		T26	1		T5	1
auto[1879048192:2013265919]	108	1			T27	1		T5	2		T42	1
auto[2013265920:2147483647]	114	1			T5	1		T42	1		T43	1
auto[2147483648:2281701375]	94	1			T15	1		T26	1		T5	3
auto[2281701376:2415919103]	112	1			T2	1		T34	1		T5	1
auto[2415919104:2550136831]	113	1			T3	1		T4	1		T44	1
auto[2550136832:2684354559]	94	1			T34	1		T26	1		T78	1
auto[2684354560:2818572287]	115	1			T14	1		T82	1		T51	1
auto[2818572288:2952790015]	106	1			T4	1		T5	2		T49	1
auto[2952790016:3087007743]	102	1			T5	2		T49	1		T44	1
auto[3087007744:3221225471]	105	1			T3	1		T14	1		T15	1
auto[3221225472:3355443199]	114	1			T32	1		T5	1		T237	1
auto[3355443200:3489660927]	111	1			T26	1		T23	1		T205	1
auto[3489660928:3623878655]	98	1			T15	1		T5	1		T18	1
auto[3623878656:3758096383]	113	1			T42	1		T44	1		T51	1
auto[3758096384:3892314111]	115	1			T14	1		T5	1		T116	1
auto[3892314112:4026531839]	110	1			T2	1		T5	1		T82	1
auto[4026531840:4160749567]	108	1			T27	1		T5	2		T82	1
auto[4160749568:4294967295]	114	1			T14	2		T5	1		T82	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	45	1			T34	1		T5	1		T238	1
auto[0:134217727]	auto[1]	45	1			T13	1		T217	1		T180	1
auto[134217728:268435455]	auto[0]	43	1			T51	1		T248	1		T89	1
auto[134217728:268435455]	auto[1]	56	1			T4	1		T49	1		T203	1
auto[268435456:402653183]	auto[0]	38	1			T26	1		T292	1		T256	1
auto[268435456:402653183]	auto[1]	54	1			T27	1		T130	1		T100	1
auto[402653184:536870911]	auto[0]	48	1			T13	1		T78	1		T48	1
auto[402653184:536870911]	auto[1]	60	1			T4	1		T5	1		T130	1
auto[536870912:671088639]	auto[0]	50	1			T13	1		T15	1		T129	1
auto[536870912:671088639]	auto[1]	46	1			T26	1		T5	1		T212	1
auto[671088640:805306367]	auto[0]	50	1			T5	1		T49	1		T42	1
auto[671088640:805306367]	auto[1]	48	1			T5	1		T54	1		T67	2
auto[805306368:939524095]	auto[0]	43	1			T205	1		T249	1		T87	1
auto[805306368:939524095]	auto[1]	55	1			T2	1		T13	1		T5	1
auto[939524096:1073741823]	auto[0]	48	1			T26	1		T49	1		T82	1
auto[939524096:1073741823]	auto[1]	46	1			T70	2		T397	1		T88	1
auto[1073741824:1207959551]	auto[0]	56	1			T2	1		T187	1		T29	1
auto[1073741824:1207959551]	auto[1]	56	1			T44	3		T205	1		T405	1
auto[1207959552:1342177279]	auto[0]	58	1			T20	1		T51	1		T212	1
auto[1207959552:1342177279]	auto[1]	59	1			T3	1		T18	1		T44	1
auto[1342177280:1476395007]	auto[0]	36	1			T26	1		T49	1		T24	2
auto[1342177280:1476395007]	auto[1]	57	1			T237	2		T23	1		T398	1
auto[1476395008:1610612735]	auto[0]	54	1			T15	1		T5	1		T187	1
auto[1476395008:1610612735]	auto[1]	47	1			T242	1		T59	1		T180	1
auto[1610612736:1744830463]	auto[0]	56	1			T13	1		T23	1		T28	1
auto[1610612736:1744830463]	auto[1]	52	1			T45	1		T365	1		T249	1
auto[1744830464:1879048191]	auto[0]	53	1			T5	1		T78	1		T43	1
auto[1744830464:1879048191]	auto[1]	58	1			T4	1		T26	1		T82	1
auto[1879048192:2013265919]	auto[0]	54	1			T5	1		T42	1		T44	1
auto[1879048192:2013265919]	auto[1]	54	1			T27	1		T5	1		T20	1
auto[2013265920:2147483647]	auto[0]	51	1			T42	1		T43	1		T86	1
auto[2013265920:2147483647]	auto[1]	63	1			T5	1		T100	1		T54	1
auto[2147483648:2281701375]	auto[0]	39	1			T78	1		T42	1		T212	1
auto[2147483648:2281701375]	auto[1]	55	1			T15	1		T26	1		T5	3
auto[2281701376:2415919103]	auto[0]	51	1			T2	1		T5	1		T238	1
auto[2281701376:2415919103]	auto[1]	61	1			T34	1		T23	1		T24	1
auto[2415919104:2550136831]	auto[0]	52	1			T187	1		T28	1		T54	2
auto[2415919104:2550136831]	auto[1]	61	1			T3	1		T4	1		T44	1
auto[2550136832:2684354559]	auto[0]	43	1			T34	1		T26	1		T42	1
auto[2550136832:2684354559]	auto[1]	51	1			T78	1		T116	1		T131	2
auto[2684354560:2818572287]	auto[0]	47	1			T82	1		T51	1		T21	1
auto[2684354560:2818572287]	auto[1]	68	1			T14	1		T242	1		T212	1
auto[2818572288:2952790015]	auto[0]	43	1			T5	1		T49	1		T248	1
auto[2818572288:2952790015]	auto[1]	63	1			T4	1		T5	1		T129	3
auto[2952790016:3087007743]	auto[0]	48	1			T5	1		T49	1		T199	1
auto[2952790016:3087007743]	auto[1]	54	1			T5	1		T44	1		T200	1
auto[3087007744:3221225471]	auto[0]	52	1			T3	1		T15	1		T405	1
auto[3087007744:3221225471]	auto[1]	53	1			T14	1		T5	2		T44	1
auto[3221225472:3355443199]	auto[0]	50	1			T187	1		T45	1		T203	1
auto[3221225472:3355443199]	auto[1]	64	1			T32	1		T5	1		T237	1
auto[3355443200:3489660927]	auto[0]	50	1			T23	1		T100	1		T203	1
auto[3355443200:3489660927]	auto[1]	61	1			T26	1		T205	1		T243	1
auto[3489660928:3623878655]	auto[0]	50	1			T42	1		T44	2		T248	1
auto[3489660928:3623878655]	auto[1]	48	1			T15	1		T5	1		T18	1
auto[3623878656:3758096383]	auto[0]	45	1			T44	1		T31	1		T54	1
auto[3623878656:3758096383]	auto[1]	68	1			T42	1		T51	1		T130	1
auto[3758096384:3892314111]	auto[0]	52	1			T5	1		T21	1		T144	1
auto[3758096384:3892314111]	auto[1]	63	1			T14	1		T116	1		T44	1
auto[3892314112:4026531839]	auto[0]	65	1			T2	1		T242	1		T86	1
auto[3892314112:4026531839]	auto[1]	45	1			T5	1		T82	1		T54	1
auto[4026531840:4160749567]	auto[0]	41	1			T27	1		T5	1		T214	1
auto[4026531840:4160749567]	auto[1]	67	1			T5	1		T82	1		T48	1
auto[4160749568:4294967295]	auto[0]	56	1			T5	1		T82	1		T44	1
auto[4160749568:4294967295]	auto[1]	58	1			T14	2		T242	1		T200	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1553

1

T2

4

T3

1

T4

1

auto[1]

1810

1

T3

2

T4

4

T13

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	97	1			T5	1		T129	1		T212	1
auto[134217728:268435455]	96	1			T5	1		T116	1		T187	1
auto[268435456:402653183]	101	1			T13	1		T5	1		T49	1
auto[402653184:536870911]	92	1			T3	1		T14	1		T5	1
auto[536870912:671088639]	105	1			T14	1		T15	1		T26	1
auto[671088640:805306367]	117	1			T14	1		T5	1		T187	1
auto[805306368:939524095]	118	1			T15	1		T42	1		T237	1
auto[939524096:1073741823]	108	1			T116	1		T44	2		T212	1
auto[1073741824:1207959551]	96	1			T26	1		T78	2		T237	1
auto[1207959552:1342177279]	96	1			T2	1		T4	1		T43	1
auto[1342177280:1476395007]	105	1			T15	1		T42	1		T51	1
auto[1476395008:1610612735]	96	1			T26	1		T5	2		T18	2
auto[1610612736:1744830463]	92	1			T5	1		T42	2		T44	1
auto[1744830464:1879048191]	92	1			T3	1		T26	2		T5	1
auto[1879048192:2013265919]	112	1			T4	1		T34	1		T44	1
auto[2013265920:2147483647]	125	1			T15	2		T5	1		T49	1
auto[2147483648:2281701375]	134	1			T13	1		T14	1		T5	1
auto[2281701376:2415919103]	105	1			T4	1		T5	1		T82	1
auto[2415919104:2550136831]	108	1			T26	1		T187	1		T130	1
auto[2550136832:2684354559]	111	1			T3	1		T14	1		T27	1
auto[2684354560:2818572287]	106	1			T13	2		T5	2		T49	1
auto[2818572288:2952790015]	113	1			T5	2		T42	1		T19	1
auto[2952790016:3087007743]	90	1			T2	1		T82	2		T44	3
auto[3087007744:3221225471]	98	1			T5	2		T129	1		T29	1
auto[3221225472:3355443199]	111	1			T2	1		T4	1		T34	1
auto[3355443200:3489660927]	115	1			T27	1		T49	1		T43	1
auto[3489660928:3623878655]	101	1			T13	1		T26	1		T5	3
auto[3623878656:3758096383]	98	1			T26	1		T5	2		T54	1
auto[3758096384:3892314111]	105	1			T2	1		T5	1		T82	1
auto[3892314112:4026531839]	116	1			T4	1		T32	1		T5	1
auto[4026531840:4160749567]	111	1			T34	1		T27	1		T49	1
auto[4160749568:4294967295]	93	1			T5	1		T237	1		T48	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T5	1		T129	1		T212	1
auto[0:134217727]	auto[1]	50	1			T249	1		T100	1		T22	1
auto[134217728:268435455]	auto[0]	41	1			T28	1		T425	1		T58	1
auto[134217728:268435455]	auto[1]	55	1			T5	1		T116	1		T187	1
auto[268435456:402653183]	auto[0]	43	1			T13	1		T48	1		T199	1
auto[268435456:402653183]	auto[1]	58	1			T5	1		T49	1		T123	1
auto[402653184:536870911]	auto[0]	39	1			T44	1		T20	1		T51	1
auto[402653184:536870911]	auto[1]	53	1			T3	1		T14	1		T5	1
auto[536870912:671088639]	auto[0]	51	1			T44	2		T130	1		T199	1
auto[536870912:671088639]	auto[1]	54	1			T14	1		T15	1		T26	1
auto[671088640:805306367]	auto[0]	67	1			T187	1		T205	1		T28	1
auto[671088640:805306367]	auto[1]	50	1			T14	1		T5	1		T129	1
auto[805306368:939524095]	auto[0]	61	1			T15	1		T42	1		T237	1
auto[805306368:939524095]	auto[1]	57	1			T200	1		T100	1		T426	1
auto[939524096:1073741823]	auto[0]	53	1			T45	1		T238	1		T31	1
auto[939524096:1073741823]	auto[1]	55	1			T116	1		T44	2		T212	1
auto[1073741824:1207959551]	auto[0]	47	1			T26	1		T51	1		T248	1
auto[1073741824:1207959551]	auto[1]	49	1			T78	2		T237	1		T100	1
auto[1207959552:1342177279]	auto[0]	46	1			T2	1		T144	1		T24	1
auto[1207959552:1342177279]	auto[1]	50	1			T4	1		T43	1		T44	1
auto[1342177280:1476395007]	auto[0]	50	1			T15	1		T42	1		T144	1
auto[1342177280:1476395007]	auto[1]	55	1			T51	1		T203	1		T59	1
auto[1476395008:1610612735]	auto[0]	44	1			T26	1		T54	1		T25	1
auto[1476395008:1610612735]	auto[1]	52	1			T5	2		T18	2		T200	1
auto[1610612736:1744830463]	auto[0]	39	1			T42	1		T20	1		T248	1
auto[1610612736:1744830463]	auto[1]	53	1			T5	1		T42	1		T44	1
auto[1744830464:1879048191]	auto[0]	42	1			T26	1		T42	1		T23	1
auto[1744830464:1879048191]	auto[1]	50	1			T3	1		T26	1		T5	1
auto[1879048192:2013265919]	auto[0]	61	1			T34	1		T44	1		T187	1
auto[1879048192:2013265919]	auto[1]	51	1			T4	1		T131	1		T238	1
auto[2013265920:2147483647]	auto[0]	49	1			T15	1		T42	1		T48	1
auto[2013265920:2147483647]	auto[1]	76	1			T15	1		T5	1		T49	1
auto[2147483648:2281701375]	auto[0]	50	1			T49	1		T78	1		T116	1
auto[2147483648:2281701375]	auto[1]	84	1			T13	1		T14	1		T5	1
auto[2281701376:2415919103]	auto[0]	46	1			T44	1		T248	1		T203	1
auto[2281701376:2415919103]	auto[1]	59	1			T4	1		T5	1		T82	1
auto[2415919104:2550136831]	auto[0]	53	1			T26	1		T187	1		T23	1
auto[2415919104:2550136831]	auto[1]	55	1			T130	1		T242	1		T405	1
auto[2550136832:2684354559]	auto[0]	57	1			T3	1		T5	1		T199	1
auto[2550136832:2684354559]	auto[1]	54	1			T14	1		T27	1		T5	1
auto[2684354560:2818572287]	auto[0]	46	1			T13	2		T5	1		T49	1
auto[2684354560:2818572287]	auto[1]	60	1			T5	1		T44	2		T129	1
auto[2818572288:2952790015]	auto[0]	59	1			T5	2		T42	1		T212	1
auto[2818572288:2952790015]	auto[1]	54	1			T19	1		T129	1		T66	1
auto[2952790016:3087007743]	auto[0]	38	1			T2	1		T82	2		T44	1
auto[2952790016:3087007743]	auto[1]	52	1			T44	2		T242	1		T23	1
auto[3087007744:3221225471]	auto[0]	49	1			T5	1		T129	1		T87	1
auto[3087007744:3221225471]	auto[1]	49	1			T5	1		T29	1		T398	1
auto[3221225472:3355443199]	auto[0]	45	1			T2	1		T4	1		T43	2
auto[3221225472:3355443199]	auto[1]	66	1			T34	1		T214	1		T405	1
auto[3355443200:3489660927]	auto[0]	54	1			T27	1		T49	1		T44	1
auto[3355443200:3489660927]	auto[1]	61	1			T43	1		T242	1		T54	1
auto[3489660928:3623878655]	auto[0]	40	1			T13	1		T5	1		T20	1
auto[3489660928:3623878655]	auto[1]	61	1			T26	1		T5	2		T212	1
auto[3623878656:3758096383]	auto[0]	45	1			T5	2		T54	1		T349	1
auto[3623878656:3758096383]	auto[1]	53	1			T26	1		T299	1		T88	1
auto[3758096384:3892314111]	auto[0]	55	1			T2	1		T20	1		T21	1
auto[3758096384:3892314111]	auto[1]	50	1			T5	1		T82	1		T199	1
auto[3892314112:4026531839]	auto[0]	46	1			T5	1		T82	1		T51	1
auto[3892314112:4026531839]	auto[1]	70	1			T4	1		T32	1		T130	1
auto[4026531840:4160749567]	auto[0]	53	1			T34	1		T49	1		T78	1
auto[4026531840:4160749567]	auto[1]	58	1			T27	1		T54	1		T308	1
auto[4160749568:4294967295]	auto[0]	37	1			T200	1		T248	1		T87	1
auto[4160749568:4294967295]	auto[1]	56	1			T5	1		T237	1		T48	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1570

1

T2

4

T3

2

T4

1

auto[1]

1793

1

T3

1

T4

4

T13

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	122	1			T2	1		T14	1		T5	1
auto[134217728:268435455]	110	1			T3	1		T13	1		T26	1
auto[268435456:402653183]	106	1			T44	1		T187	1		T205	1
auto[402653184:536870911]	101	1			T3	1		T26	1		T82	1
auto[536870912:671088639]	115	1			T3	1		T4	1		T5	1
auto[671088640:805306367]	108	1			T26	1		T5	2		T18	1
auto[805306368:939524095]	92	1			T4	1		T5	1		T82	1
auto[939524096:1073741823]	102	1			T13	1		T14	1		T26	1
auto[1073741824:1207959551]	104	1			T5	3		T82	1		T42	1
auto[1207959552:1342177279]	96	1			T15	1		T34	1		T5	2
auto[1342177280:1476395007]	119	1			T4	1		T13	1		T78	1
auto[1476395008:1610612735]	91	1			T4	1		T15	1		T5	2
auto[1610612736:1744830463]	97	1			T26	1		T5	2		T82	1
auto[1744830464:1879048191]	112	1			T2	1		T14	1		T27	1
auto[1879048192:2013265919]	96	1			T26	1		T43	1		T20	1
auto[2013265920:2147483647]	103	1			T13	1		T5	1		T51	1
auto[2147483648:2281701375]	92	1			T5	2		T187	1		T23	1
auto[2281701376:2415919103]	106	1			T78	1		T82	1		T130	1
auto[2415919104:2550136831]	127	1			T4	1		T34	1		T18	1
auto[2550136832:2684354559]	100	1			T15	1		T78	1		T43	1
auto[2684354560:2818572287]	100	1			T14	1		T44	1		T242	1
auto[2818572288:2952790015]	111	1			T49	1		T42	1		T43	1
auto[2952790016:3087007743]	100	1			T238	1		T21	1		T87	1
auto[3087007744:3221225471]	130	1			T14	1		T15	1		T26	1
auto[3221225472:3355443199]	101	1			T2	1		T32	1		T237	1
auto[3355443200:3489660927]	117	1			T49	1		T42	2		T44	1
auto[3489660928:3623878655]	111	1			T34	1		T5	1		T44	1
auto[3623878656:3758096383]	96	1			T5	1		T129	1		T238	1
auto[3758096384:3892314111]	84	1			T2	1		T13	1		T5	1
auto[3892314112:4026531839]	97	1			T15	1		T26	1		T5	2
auto[4026531840:4160749567]	113	1			T5	1		T49	1		T116	1
auto[4160749568:4294967295]	104	1			T5	2		T116	1		T44	2