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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2944 1 T2 4 T3 3 T4 5
auto[1] 241 1 T82 6 T129 6 T130 9


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 107 1 T2 1 T5 3 T82 1
auto[134217728:268435455] 103 1 T82 1 T44 2 T20 1
auto[268435456:402653183] 92 1 T26 1 T5 2 T82 1
auto[402653184:536870911] 110 1 T13 1 T27 1 T5 4
auto[536870912:671088639] 111 1 T5 1 T82 2 T130 2
auto[671088640:805306367] 103 1 T5 1 T20 1 T129 1
auto[805306368:939524095] 92 1 T43 1 T21 1 T31 1
auto[939524096:1073741823] 85 1 T78 1 T237 1 T44 1
auto[1073741824:1207959551] 114 1 T15 1 T5 2 T44 1
auto[1207959552:1342177279] 108 1 T5 3 T43 1 T20 1
auto[1342177280:1476395007] 117 1 T15 1 T26 2 T116 1
auto[1476395008:1610612735] 102 1 T32 1 T5 1 T78 1
auto[1610612736:1744830463] 111 1 T14 2 T15 1 T82 1
auto[1744830464:1879048191] 109 1 T2 1 T4 1 T26 1
auto[1879048192:2013265919] 98 1 T2 1 T27 1 T42 1
auto[2013265920:2147483647] 97 1 T44 1 T129 2 T242 1
auto[2147483648:2281701375] 89 1 T4 1 T242 1 T45 1
auto[2281701376:2415919103] 103 1 T13 1 T5 1 T82 1
auto[2415919104:2550136831] 100 1 T3 1 T13 1 T26 1
auto[2550136832:2684354559] 90 1 T4 1 T34 1 T26 1
auto[2684354560:2818572287] 104 1 T3 1 T4 1 T14 1
auto[2818572288:2952790015] 90 1 T34 1 T44 1 T129 1
auto[2952790016:3087007743] 90 1 T26 1 T44 1 T48 1
auto[3087007744:3221225471] 90 1 T116 1 T129 1 T130 2
auto[3221225472:3355443199] 98 1 T5 1 T237 1 T131 1
auto[3355443200:3489660927] 95 1 T27 1 T5 1 T20 1
auto[3489660928:3623878655] 99 1 T15 1 T82 1 T237 1
auto[3623878656:3758096383] 87 1 T13 1 T82 2 T129 1
auto[3758096384:3892314111] 87 1 T13 1 T44 2 T214 1
auto[3892314112:4026531839] 91 1 T26 1 T18 1 T44 1
auto[4026531840:4160749567] 99 1 T2 1 T3 1 T4 1
auto[4160749568:4294967295] 114 1 T14 2 T15 1 T34 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 98 1 T2 1 T5 3 T82 1
auto[0:134217727] auto[1] 9 1 T132 3 T256 1 T295 1
auto[134217728:268435455] auto[0] 97 1 T82 1 T44 2 T20 1
auto[134217728:268435455] auto[1] 6 1 T102 1 T105 1 T271 1
auto[268435456:402653183] auto[0] 83 1 T26 1 T5 2 T242 1
auto[268435456:402653183] auto[1] 9 1 T82 1 T261 1 T132 1
auto[402653184:536870911] auto[0] 99 1 T13 1 T27 1 T5 4
auto[402653184:536870911] auto[1] 11 1 T130 1 T131 1 T306 1
auto[536870912:671088639] auto[0] 102 1 T5 1 T82 1 T130 2
auto[536870912:671088639] auto[1] 9 1 T82 1 T256 1 T306 1
auto[671088640:805306367] auto[0] 94 1 T5 1 T20 1 T131 1
auto[671088640:805306367] auto[1] 9 1 T129 1 T131 1 T289 1
auto[805306368:939524095] auto[0] 88 1 T43 1 T21 1 T31 1
auto[805306368:939524095] auto[1] 4 1 T433 2 T434 1 T376 1
auto[939524096:1073741823] auto[0] 81 1 T78 1 T237 1 T44 1
auto[939524096:1073741823] auto[1] 4 1 T135 1 T270 1 T417 1
auto[1073741824:1207959551] auto[0] 108 1 T15 1 T5 2 T44 1
auto[1073741824:1207959551] auto[1] 6 1 T281 2 T297 1 T418 1
auto[1207959552:1342177279] auto[0] 101 1 T5 3 T43 1 T20 1
auto[1207959552:1342177279] auto[1] 7 1 T130 2 T131 1 T256 1
auto[1342177280:1476395007] auto[0] 112 1 T15 1 T26 2 T116 1
auto[1342177280:1476395007] auto[1] 5 1 T131 1 T261 1 T423 1
auto[1476395008:1610612735] auto[0] 92 1 T32 1 T5 1 T78 1
auto[1476395008:1610612735] auto[1] 10 1 T130 1 T342 2 T279 1
auto[1610612736:1744830463] auto[0] 102 1 T14 2 T15 1 T82 1
auto[1610612736:1744830463] auto[1] 9 1 T131 1 T236 1 T132 1
auto[1744830464:1879048191] auto[0] 97 1 T2 1 T4 1 T26 1
auto[1744830464:1879048191] auto[1] 12 1 T130 1 T342 1 T289 1
auto[1879048192:2013265919] auto[0] 96 1 T2 1 T27 1 T42 1
auto[1879048192:2013265919] auto[1] 2 1 T387 1 T435 1 - -
auto[2013265920:2147483647] auto[0] 89 1 T44 1 T242 1 T205 1
auto[2013265920:2147483647] auto[1] 8 1 T129 2 T236 1 T297 1
auto[2147483648:2281701375] auto[0] 86 1 T4 1 T242 1 T45 1
auto[2147483648:2281701375] auto[1] 3 1 T236 1 T261 1 T341 1
auto[2281701376:2415919103] auto[0] 93 1 T13 1 T5 1 T44 1
auto[2281701376:2415919103] auto[1] 10 1 T82 1 T236 1 T295 1
auto[2415919104:2550136831] auto[0] 91 1 T3 1 T13 1 T26 1
auto[2415919104:2550136831] auto[1] 9 1 T82 1 T129 1 T135 1
auto[2550136832:2684354559] auto[0] 84 1 T4 1 T34 1 T26 1
auto[2550136832:2684354559] auto[1] 6 1 T129 1 T256 1 T342 1
auto[2684354560:2818572287] auto[0] 98 1 T3 1 T4 1 T14 1
auto[2684354560:2818572287] auto[1] 6 1 T261 1 T270 2 T417 1
auto[2818572288:2952790015] auto[0] 80 1 T34 1 T44 1 T129 1
auto[2818572288:2952790015] auto[1] 10 1 T256 1 T384 1 T424 1
auto[2952790016:3087007743] auto[0] 86 1 T26 1 T44 1 T48 1
auto[2952790016:3087007743] auto[1] 4 1 T236 1 T297 1 T387 1
auto[3087007744:3221225471] auto[0] 81 1 T116 1 T199 1 T31 1
auto[3087007744:3221225471] auto[1] 9 1 T129 1 T130 2 T236 1
auto[3221225472:3355443199] auto[0] 91 1 T5 1 T237 1 T131 1
auto[3221225472:3355443199] auto[1] 7 1 T132 2 T256 1 T270 1
auto[3355443200:3489660927] auto[0] 90 1 T27 1 T5 1 T20 1
auto[3355443200:3489660927] auto[1] 5 1 T130 1 T306 1 T297 1
auto[3489660928:3623878655] auto[0] 95 1 T15 1 T237 1 T44 2
auto[3489660928:3623878655] auto[1] 4 1 T82 1 T306 1 T279 1
auto[3623878656:3758096383] auto[0] 80 1 T13 1 T82 1 T129 1
auto[3623878656:3758096383] auto[1] 7 1 T82 1 T418 1 T271 2
auto[3758096384:3892314111] auto[0] 80 1 T13 1 T44 2 T214 1
auto[3758096384:3892314111] auto[1] 7 1 T132 1 T135 1 T279 1
auto[3892314112:4026531839] auto[0] 78 1 T26 1 T18 1 T44 1
auto[3892314112:4026531839] auto[1] 13 1 T130 1 T131 1 T236 1
auto[4026531840:4160749567] auto[0] 92 1 T2 1 T3 1 T4 1
auto[4026531840:4160749567] auto[1] 7 1 T131 1 T261 1 T132 1
auto[4160749568:4294967295] auto[0] 100 1 T14 2 T15 1 T34 1
auto[4160749568:4294967295] auto[1] 14 1 T131 1 T135 1 T256 1

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