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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1576 1 T2 4 T3 1 T4 1
auto[1] 1787 1 T3 2 T4 4 T13 2


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 97 1 T4 1 T5 2 T18 1
auto[134217728:268435455] 86 1 T5 1 T49 1 T129 1
auto[268435456:402653183] 93 1 T2 1 T4 1 T14 1
auto[402653184:536870911] 107 1 T13 1 T129 1 T199 1
auto[536870912:671088639] 107 1 T27 1 T49 1 T43 1
auto[671088640:805306367] 119 1 T2 1 T26 1 T5 1
auto[805306368:939524095] 93 1 T14 1 T26 1 T237 1
auto[939524096:1073741823] 108 1 T42 1 T187 1 T23 1
auto[1073741824:1207959551] 105 1 T3 1 T5 2 T44 1
auto[1207959552:1342177279] 104 1 T4 1 T14 1 T26 1
auto[1342177280:1476395007] 109 1 T34 1 T5 2 T42 1
auto[1476395008:1610612735] 103 1 T13 1 T5 2 T82 1
auto[1610612736:1744830463] 96 1 T49 1 T82 1 T42 1
auto[1744830464:1879048191] 116 1 T15 1 T44 1 T248 2
auto[1879048192:2013265919] 122 1 T34 1 T32 1 T129 1
auto[2013265920:2147483647] 73 1 T3 1 T13 1 T26 1
auto[2147483648:2281701375] 111 1 T49 1 T42 1 T44 1
auto[2281701376:2415919103] 128 1 T27 1 T5 1 T51 1
auto[2415919104:2550136831] 94 1 T13 1 T51 1 T205 1
auto[2550136832:2684354559] 108 1 T2 1 T27 1 T131 1
auto[2684354560:2818572287] 108 1 T15 1 T5 2 T82 1
auto[2818572288:2952790015] 103 1 T4 1 T14 1 T5 2
auto[2952790016:3087007743] 122 1 T34 1 T26 1 T5 2
auto[3087007744:3221225471] 89 1 T5 3 T78 1 T19 1
auto[3221225472:3355443199] 104 1 T13 1 T26 1 T5 1
auto[3355443200:3489660927] 91 1 T187 1 T130 1 T212 1
auto[3489660928:3623878655] 129 1 T14 1 T5 1 T43 1
auto[3623878656:3758096383] 121 1 T3 1 T26 2 T5 1
auto[3758096384:3892314111] 96 1 T78 1 T44 1 T248 1
auto[3892314112:4026531839] 108 1 T15 2 T5 1 T82 1
auto[4026531840:4160749567] 101 1 T4 1 T15 1 T5 1
auto[4160749568:4294967295] 112 1 T2 1 T5 1 T82 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 36 1 T5 1 T237 1 T187 1
auto[0:134217727] auto[1] 61 1 T4 1 T5 1 T18 1
auto[134217728:268435455] auto[0] 39 1 T49 1 T129 1 T31 1
auto[134217728:268435455] auto[1] 47 1 T5 1 T60 1 T123 2
auto[268435456:402653183] auto[0] 50 1 T2 1 T44 1 T48 1
auto[268435456:402653183] auto[1] 43 1 T4 1 T14 1 T242 1
auto[402653184:536870911] auto[0] 57 1 T13 1 T248 1 T87 1
auto[402653184:536870911] auto[1] 50 1 T129 1 T199 1 T203 2
auto[536870912:671088639] auto[0] 43 1 T49 1 T187 1 T212 1
auto[536870912:671088639] auto[1] 64 1 T27 1 T43 1 T237 1
auto[671088640:805306367] auto[0] 50 1 T2 1 T49 1 T42 1
auto[671088640:805306367] auto[1] 69 1 T26 1 T5 1 T44 1
auto[805306368:939524095] auto[0] 38 1 T26 1 T237 1 T199 1
auto[805306368:939524095] auto[1] 55 1 T14 1 T44 1 T130 1
auto[939524096:1073741823] auto[0] 56 1 T42 1 T187 1 T21 2
auto[939524096:1073741823] auto[1] 52 1 T23 1 T214 1 T70 1
auto[1073741824:1207959551] auto[0] 53 1 T44 1 T308 1 T254 1
auto[1073741824:1207959551] auto[1] 52 1 T3 1 T5 2 T20 1
auto[1207959552:1342177279] auto[0] 52 1 T26 1 T5 1 T43 1
auto[1207959552:1342177279] auto[1] 52 1 T4 1 T14 1 T49 1
auto[1342177280:1476395007] auto[0] 61 1 T34 1 T5 1 T42 1
auto[1342177280:1476395007] auto[1] 48 1 T5 1 T43 1 T44 2
auto[1476395008:1610612735] auto[0] 57 1 T13 1 T42 1 T243 1
auto[1476395008:1610612735] auto[1] 46 1 T5 2 T82 1 T31 1
auto[1610612736:1744830463] auto[0] 49 1 T82 1 T21 1 T86 1
auto[1610612736:1744830463] auto[1] 47 1 T49 1 T42 1 T44 1
auto[1744830464:1879048191] auto[0] 55 1 T15 1 T248 2 T60 1
auto[1744830464:1879048191] auto[1] 61 1 T44 1 T86 1 T100 1
auto[1879048192:2013265919] auto[0] 61 1 T34 1 T129 1 T200 1
auto[1879048192:2013265919] auto[1] 61 1 T32 1 T214 1 T123 1
auto[2013265920:2147483647] auto[0] 28 1 T3 1 T13 1 T26 1
auto[2013265920:2147483647] auto[1] 45 1 T5 1 T78 1 T44 2
auto[2147483648:2281701375] auto[0] 54 1 T49 1 T42 1 T238 1
auto[2147483648:2281701375] auto[1] 57 1 T44 1 T130 1 T243 1
auto[2281701376:2415919103] auto[0] 61 1 T27 1 T51 1 T29 1
auto[2281701376:2415919103] auto[1] 67 1 T5 1 T212 1 T199 1
auto[2415919104:2550136831] auto[0] 39 1 T28 1 T198 1 T60 1
auto[2415919104:2550136831] auto[1] 55 1 T13 1 T51 1 T205 1
auto[2550136832:2684354559] auto[0] 53 1 T2 1 T249 1 T288 1
auto[2550136832:2684354559] auto[1] 55 1 T27 1 T131 1 T238 1
auto[2684354560:2818572287] auto[0] 49 1 T15 1 T5 1 T129 1
auto[2684354560:2818572287] auto[1] 59 1 T5 1 T82 1 T130 1
auto[2818572288:2952790015] auto[0] 49 1 T4 1 T5 1 T116 1
auto[2818572288:2952790015] auto[1] 54 1 T14 1 T5 1 T45 1
auto[2952790016:3087007743] auto[0] 54 1 T26 1 T78 1 T31 1
auto[2952790016:3087007743] auto[1] 68 1 T34 1 T5 2 T18 1
auto[3087007744:3221225471] auto[0] 37 1 T5 1 T20 1 T29 1
auto[3087007744:3221225471] auto[1] 52 1 T5 2 T78 1 T19 1
auto[3221225472:3355443199] auto[0] 45 1 T214 1 T31 1 T144 1
auto[3221225472:3355443199] auto[1] 59 1 T13 1 T26 1 T5 1
auto[3355443200:3489660927] auto[0] 39 1 T212 1 T144 1 T28 1
auto[3355443200:3489660927] auto[1] 52 1 T187 1 T130 1 T132 1
auto[3489660928:3623878655] auto[0] 59 1 T5 1 T43 1 T44 2
auto[3489660928:3623878655] auto[1] 70 1 T14 1 T44 1 T51 1
auto[3623878656:3758096383] auto[0] 56 1 T5 1 T20 1 T48 1
auto[3623878656:3758096383] auto[1] 65 1 T3 1 T26 2 T42 1
auto[3758096384:3892314111] auto[0] 42 1 T78 1 T248 1 T198 1
auto[3758096384:3892314111] auto[1] 54 1 T44 1 T203 1 T69 1
auto[3892314112:4026531839] auto[0] 52 1 T15 1 T5 1 T82 1
auto[3892314112:4026531839] auto[1] 56 1 T15 1 T116 1 T44 1
auto[4026531840:4160749567] auto[0] 50 1 T5 1 T44 1 T203 1
auto[4026531840:4160749567] auto[1] 51 1 T4 1 T15 1 T242 1
auto[4160749568:4294967295] auto[0] 52 1 T2 1 T5 1 T51 1
auto[4160749568:4294967295] auto[1] 60 1 T82 1 T116 1 T398 2

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