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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.04 98.11 98.42 100.00 99.02 98.41 91.14


Total test records in report: 1078
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T119 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3326062827 Aug 02 05:56:25 PM PDT 24 Aug 02 05:56:33 PM PDT 24 514741475 ps
T1008 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1180264861 Aug 02 05:56:23 PM PDT 24 Aug 02 05:56:39 PM PDT 24 2341994536 ps
T1009 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3113696698 Aug 02 05:56:27 PM PDT 24 Aug 02 05:56:29 PM PDT 24 53530023 ps
T1010 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.378647112 Aug 02 05:56:46 PM PDT 24 Aug 02 05:56:48 PM PDT 24 61597163 ps
T1011 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.481512165 Aug 02 05:56:50 PM PDT 24 Aug 02 05:56:52 PM PDT 24 47722987 ps
T1012 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.269812149 Aug 02 05:56:24 PM PDT 24 Aug 02 05:56:24 PM PDT 24 12391950 ps
T1013 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2722434613 Aug 02 05:56:55 PM PDT 24 Aug 02 05:56:55 PM PDT 24 30800382 ps
T1014 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3570566569 Aug 02 05:56:16 PM PDT 24 Aug 02 05:56:22 PM PDT 24 277669822 ps
T1015 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.487841822 Aug 02 05:56:56 PM PDT 24 Aug 02 05:56:57 PM PDT 24 18027077 ps
T1016 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1078785850 Aug 02 05:56:52 PM PDT 24 Aug 02 05:56:54 PM PDT 24 34077655 ps
T1017 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2048779319 Aug 02 05:56:50 PM PDT 24 Aug 02 05:56:55 PM PDT 24 2339747368 ps
T1018 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.290054197 Aug 02 05:56:54 PM PDT 24 Aug 02 05:56:55 PM PDT 24 10022605 ps
T1019 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1683867300 Aug 02 05:56:47 PM PDT 24 Aug 02 05:56:50 PM PDT 24 40860278 ps
T1020 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2140704506 Aug 02 05:56:47 PM PDT 24 Aug 02 05:56:49 PM PDT 24 97797939 ps
T1021 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.4042772107 Aug 02 05:56:23 PM PDT 24 Aug 02 05:56:25 PM PDT 24 378335070 ps
T1022 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3982107167 Aug 02 05:56:24 PM PDT 24 Aug 02 05:56:25 PM PDT 24 21249412 ps
T1023 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.915898820 Aug 02 05:56:30 PM PDT 24 Aug 02 05:56:37 PM PDT 24 493681854 ps
T1024 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3715779836 Aug 02 05:56:25 PM PDT 24 Aug 02 05:56:27 PM PDT 24 98077275 ps
T1025 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1513102222 Aug 02 05:56:27 PM PDT 24 Aug 02 05:56:28 PM PDT 24 116895433 ps
T1026 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2682220248 Aug 02 05:56:43 PM PDT 24 Aug 02 05:56:44 PM PDT 24 8996591 ps
T1027 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.251243069 Aug 02 05:56:53 PM PDT 24 Aug 02 05:56:54 PM PDT 24 10853014 ps
T161 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.592937060 Aug 02 05:56:19 PM PDT 24 Aug 02 05:56:24 PM PDT 24 199674159 ps
T1028 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1374045975 Aug 02 05:56:48 PM PDT 24 Aug 02 05:56:53 PM PDT 24 168131234 ps
T1029 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1729332642 Aug 02 05:56:54 PM PDT 24 Aug 02 05:56:55 PM PDT 24 9353950 ps
T1030 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3965027105 Aug 02 05:56:49 PM PDT 24 Aug 02 05:57:03 PM PDT 24 400888130 ps
T1031 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1450034864 Aug 02 05:56:34 PM PDT 24 Aug 02 05:56:38 PM PDT 24 504591779 ps
T1032 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3159420917 Aug 02 05:56:30 PM PDT 24 Aug 02 05:56:32 PM PDT 24 44822281 ps
T1033 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1727035061 Aug 02 05:56:16 PM PDT 24 Aug 02 05:56:17 PM PDT 24 33348804 ps
T1034 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.493632159 Aug 02 05:56:19 PM PDT 24 Aug 02 05:56:20 PM PDT 24 18278283 ps
T1035 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3106924713 Aug 02 05:56:50 PM PDT 24 Aug 02 05:56:51 PM PDT 24 42042422 ps
T1036 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.999219632 Aug 02 05:56:48 PM PDT 24 Aug 02 05:56:50 PM PDT 24 639330941 ps
T1037 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.4292333901 Aug 02 05:56:48 PM PDT 24 Aug 02 05:56:52 PM PDT 24 289210043 ps
T1038 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.294860579 Aug 02 05:56:17 PM PDT 24 Aug 02 05:56:19 PM PDT 24 46180017 ps
T1039 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.428883385 Aug 02 05:56:22 PM PDT 24 Aug 02 05:56:24 PM PDT 24 427139811 ps
T1040 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1158292238 Aug 02 05:56:50 PM PDT 24 Aug 02 05:56:51 PM PDT 24 17357496 ps
T1041 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.117020010 Aug 02 05:56:57 PM PDT 24 Aug 02 05:56:58 PM PDT 24 10566760 ps
T1042 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1311948046 Aug 02 05:56:32 PM PDT 24 Aug 02 05:56:34 PM PDT 24 46152549 ps
T1043 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.4058071502 Aug 02 05:56:58 PM PDT 24 Aug 02 05:56:58 PM PDT 24 27432031 ps
T1044 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3758363317 Aug 02 05:56:42 PM PDT 24 Aug 02 05:56:43 PM PDT 24 21791511 ps
T1045 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1408975511 Aug 02 05:56:46 PM PDT 24 Aug 02 05:56:47 PM PDT 24 15199287 ps
T1046 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.858668703 Aug 02 05:56:30 PM PDT 24 Aug 02 05:56:32 PM PDT 24 34305902 ps
T1047 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1512526741 Aug 02 05:57:05 PM PDT 24 Aug 02 05:57:06 PM PDT 24 17529363 ps
T162 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2088023159 Aug 02 05:56:30 PM PDT 24 Aug 02 05:56:36 PM PDT 24 1508644624 ps
T1048 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.881036164 Aug 02 05:56:30 PM PDT 24 Aug 02 05:56:31 PM PDT 24 13985323 ps
T1049 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2871343894 Aug 02 05:56:54 PM PDT 24 Aug 02 05:56:55 PM PDT 24 20949665 ps
T1050 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3558793040 Aug 02 05:56:18 PM PDT 24 Aug 02 05:56:24 PM PDT 24 252975936 ps
T157 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.632290849 Aug 02 05:56:27 PM PDT 24 Aug 02 05:56:32 PM PDT 24 340746552 ps
T1051 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3414055246 Aug 02 05:56:20 PM PDT 24 Aug 02 05:56:21 PM PDT 24 15870898 ps
T1052 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.759793024 Aug 02 05:56:19 PM PDT 24 Aug 02 05:56:21 PM PDT 24 52134178 ps
T1053 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.515117691 Aug 02 05:56:18 PM PDT 24 Aug 02 05:56:21 PM PDT 24 118424445 ps
T1054 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2799018232 Aug 02 05:56:56 PM PDT 24 Aug 02 05:56:57 PM PDT 24 20298541 ps
T169 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1040913243 Aug 02 05:56:25 PM PDT 24 Aug 02 05:56:29 PM PDT 24 177200784 ps
T1055 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.312140527 Aug 02 05:56:45 PM PDT 24 Aug 02 05:56:46 PM PDT 24 24116166 ps
T1056 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2047899193 Aug 02 05:56:55 PM PDT 24 Aug 02 05:56:56 PM PDT 24 18570279 ps
T1057 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2760245147 Aug 02 05:56:18 PM PDT 24 Aug 02 05:56:22 PM PDT 24 450617563 ps
T171 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2748107686 Aug 02 05:56:40 PM PDT 24 Aug 02 05:56:44 PM PDT 24 157704857 ps
T1058 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.4169156054 Aug 02 05:56:50 PM PDT 24 Aug 02 05:56:52 PM PDT 24 147632212 ps
T1059 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1832655593 Aug 02 05:56:42 PM PDT 24 Aug 02 05:56:44 PM PDT 24 69223115 ps
T1060 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3110898579 Aug 02 05:56:42 PM PDT 24 Aug 02 05:56:43 PM PDT 24 73157172 ps
T1061 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.918066952 Aug 02 05:56:17 PM PDT 24 Aug 02 05:56:24 PM PDT 24 540673412 ps
T1062 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3460455221 Aug 02 05:56:31 PM PDT 24 Aug 02 05:56:40 PM PDT 24 195192559 ps
T154 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3970515335 Aug 02 05:56:52 PM PDT 24 Aug 02 05:56:59 PM PDT 24 300383294 ps
T1063 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1120060861 Aug 02 05:56:52 PM PDT 24 Aug 02 05:56:53 PM PDT 24 11772099 ps
T1064 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3938220917 Aug 02 05:56:35 PM PDT 24 Aug 02 05:56:36 PM PDT 24 9793752 ps
T1065 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1699027025 Aug 02 05:56:30 PM PDT 24 Aug 02 05:56:39 PM PDT 24 4317740522 ps
T1066 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1630849196 Aug 02 05:56:33 PM PDT 24 Aug 02 05:56:35 PM PDT 24 67846316 ps
T1067 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1947287490 Aug 02 05:56:59 PM PDT 24 Aug 02 05:57:00 PM PDT 24 53346073 ps
T1068 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.37215451 Aug 02 05:56:53 PM PDT 24 Aug 02 05:56:55 PM PDT 24 56804918 ps
T1069 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2448243109 Aug 02 05:56:49 PM PDT 24 Aug 02 05:56:52 PM PDT 24 68938166 ps
T1070 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.925030499 Aug 02 05:56:24 PM PDT 24 Aug 02 05:56:25 PM PDT 24 14677503 ps
T1071 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.472518697 Aug 02 05:56:55 PM PDT 24 Aug 02 05:56:56 PM PDT 24 13025266 ps
T1072 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2854545430 Aug 02 05:56:24 PM PDT 24 Aug 02 05:56:26 PM PDT 24 117412514 ps
T1073 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3918724323 Aug 02 05:56:42 PM PDT 24 Aug 02 05:56:52 PM PDT 24 492458748 ps
T1074 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3581561590 Aug 02 05:56:20 PM PDT 24 Aug 02 05:56:21 PM PDT 24 114137344 ps
T1075 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.59749301 Aug 02 05:56:37 PM PDT 24 Aug 02 05:56:46 PM PDT 24 462800106 ps
T1076 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.881557712 Aug 02 05:56:48 PM PDT 24 Aug 02 05:56:51 PM PDT 24 147457708 ps
T1077 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2705781853 Aug 02 05:56:48 PM PDT 24 Aug 02 05:56:49 PM PDT 24 129793893 ps
T1078 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3298793827 Aug 02 05:56:22 PM PDT 24 Aug 02 05:56:30 PM PDT 24 194607548 ps

Test location /workspace/coverage/default/6.keymgr_random.1661243563
Short name T14
Test name
Test status
Simulation time 113088191 ps
CPU time 5.41 seconds
Started Aug 02 05:12:13 PM PDT 24
Finished Aug 02 05:12:19 PM PDT 24
Peak memory 208292 kb
Host smart-7ac0f6a9-2888-4e56-b585-6c365334e0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661243563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1661243563
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.3764630037
Short name T5
Test name
Test status
Simulation time 2926779676 ps
CPU time 25.82 seconds
Started Aug 02 05:13:08 PM PDT 24
Finished Aug 02 05:13:34 PM PDT 24
Peak memory 222712 kb
Host smart-8c7b197c-6d7f-4d8e-b251-28bb390392b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764630037 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.3764630037
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3738633505
Short name T44
Test name
Test status
Simulation time 1268293520 ps
CPU time 13.16 seconds
Started Aug 02 05:12:15 PM PDT 24
Finished Aug 02 05:12:29 PM PDT 24
Peak memory 221268 kb
Host smart-fe030104-bdb7-4132-86a8-e5fa199b3270
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738633505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3738633505
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2388606005
Short name T41
Test name
Test status
Simulation time 347873286 ps
CPU time 10.62 seconds
Started Aug 02 05:11:47 PM PDT 24
Finished Aug 02 05:11:58 PM PDT 24
Peak memory 231320 kb
Host smart-7aae1b28-04ab-420a-b851-4bbecb04b2d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388606005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2388606005
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.1114335732
Short name T70
Test name
Test status
Simulation time 1981741564 ps
CPU time 18.82 seconds
Started Aug 02 05:12:32 PM PDT 24
Finished Aug 02 05:12:51 PM PDT 24
Peak memory 222672 kb
Host smart-2ef20a1e-4eef-4ecf-b819-248e278555ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114335732 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.1114335732
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2884351152
Short name T54
Test name
Test status
Simulation time 2879981893 ps
CPU time 22.49 seconds
Started Aug 02 05:12:38 PM PDT 24
Finished Aug 02 05:13:00 PM PDT 24
Peak memory 222540 kb
Host smart-bb035e6b-677b-4d78-81ac-b3e06b740f12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884351152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2884351152
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.129503743
Short name T61
Test name
Test status
Simulation time 2223886067 ps
CPU time 56.79 seconds
Started Aug 02 05:12:57 PM PDT 24
Finished Aug 02 05:13:53 PM PDT 24
Peak memory 215468 kb
Host smart-13c9783f-9d93-47d5-9fb6-776d2908c382
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129503743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.129503743
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3946721706
Short name T129
Test name
Test status
Simulation time 1405611496 ps
CPU time 7.79 seconds
Started Aug 02 05:13:07 PM PDT 24
Finished Aug 02 05:13:15 PM PDT 24
Peak memory 215836 kb
Host smart-7c98fe1c-abf0-4a9a-87bd-7822f908bdba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3946721706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3946721706
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.687081785
Short name T15
Test name
Test status
Simulation time 114677350 ps
CPU time 3.13 seconds
Started Aug 02 05:12:56 PM PDT 24
Finished Aug 02 05:12:59 PM PDT 24
Peak memory 214236 kb
Host smart-37f62045-cc33-40db-9b26-506d333ac8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687081785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.687081785
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2269860260
Short name T110
Test name
Test status
Simulation time 738007958 ps
CPU time 12.6 seconds
Started Aug 02 05:56:22 PM PDT 24
Finished Aug 02 05:56:34 PM PDT 24
Peak memory 214608 kb
Host smart-5e8d1b3c-0c20-4f52-8f51-ec6a3cd55017
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269860260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2269860260
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2404513039
Short name T130
Test name
Test status
Simulation time 230595834 ps
CPU time 11.19 seconds
Started Aug 02 05:13:10 PM PDT 24
Finished Aug 02 05:13:22 PM PDT 24
Peak memory 215648 kb
Host smart-60afbb47-dd9f-432a-b526-4a1f48b13df2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2404513039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2404513039
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1316997899
Short name T8
Test name
Test status
Simulation time 735971231 ps
CPU time 4.6 seconds
Started Aug 02 05:13:14 PM PDT 24
Finished Aug 02 05:13:19 PM PDT 24
Peak memory 209596 kb
Host smart-3eb2e5ea-7643-46df-8d45-c4698515c91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316997899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1316997899
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.811821111
Short name T21
Test name
Test status
Simulation time 166971050 ps
CPU time 5.81 seconds
Started Aug 02 05:12:20 PM PDT 24
Finished Aug 02 05:12:26 PM PDT 24
Peak memory 210452 kb
Host smart-fee9652e-853d-4393-88c4-67838c28849f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811821111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.811821111
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1442003092
Short name T261
Test name
Test status
Simulation time 226857093 ps
CPU time 6.67 seconds
Started Aug 02 05:13:02 PM PDT 24
Finished Aug 02 05:13:09 PM PDT 24
Peak memory 215556 kb
Host smart-bab6a385-8fe7-4fd9-90f4-661c6de5c9cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1442003092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1442003092
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.1345923393
Short name T16
Test name
Test status
Simulation time 126512819 ps
CPU time 4.24 seconds
Started Aug 02 05:12:28 PM PDT 24
Finished Aug 02 05:12:37 PM PDT 24
Peak memory 210144 kb
Host smart-d86c0ed9-adc7-4d7d-9d22-f85469af2558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345923393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1345923393
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.791612167
Short name T58
Test name
Test status
Simulation time 781968097 ps
CPU time 21.07 seconds
Started Aug 02 05:12:58 PM PDT 24
Finished Aug 02 05:13:19 PM PDT 24
Peak memory 222532 kb
Host smart-3270e2d1-95a5-4bf6-873f-bbfa49087da4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791612167 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.791612167
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1725047666
Short name T23
Test name
Test status
Simulation time 289222217 ps
CPU time 3.47 seconds
Started Aug 02 05:12:38 PM PDT 24
Finished Aug 02 05:12:42 PM PDT 24
Peak memory 222484 kb
Host smart-1e90190c-054e-4e59-a2e8-377718591b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725047666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1725047666
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.544156793
Short name T112
Test name
Test status
Simulation time 298187766 ps
CPU time 3.29 seconds
Started Aug 02 05:56:16 PM PDT 24
Finished Aug 02 05:56:20 PM PDT 24
Peak memory 214704 kb
Host smart-d8e399db-6214-4bf2-98b3-a17de88f9691
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544156793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.544156793
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.246384543
Short name T433
Test name
Test status
Simulation time 725495317 ps
CPU time 10.62 seconds
Started Aug 02 05:13:14 PM PDT 24
Finished Aug 02 05:13:25 PM PDT 24
Peak memory 215688 kb
Host smart-e56018c4-ffad-4965-aca1-8326d45fc4ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=246384543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.246384543
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1829332999
Short name T92
Test name
Test status
Simulation time 81980926 ps
CPU time 3.56 seconds
Started Aug 02 05:13:46 PM PDT 24
Finished Aug 02 05:13:50 PM PDT 24
Peak memory 209508 kb
Host smart-3a757f6c-4714-40ed-b707-4ae3499c15c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829332999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1829332999
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3775586319
Short name T60
Test name
Test status
Simulation time 661277127 ps
CPU time 7.98 seconds
Started Aug 02 05:14:04 PM PDT 24
Finished Aug 02 05:14:12 PM PDT 24
Peak memory 215268 kb
Host smart-e3ba98b5-a322-4ef5-b11d-06d448b3d045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775586319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3775586319
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3901309021
Short name T82
Test name
Test status
Simulation time 163464239 ps
CPU time 6.18 seconds
Started Aug 02 05:12:22 PM PDT 24
Finished Aug 02 05:12:28 PM PDT 24
Peak memory 215748 kb
Host smart-cc99f086-caea-4c19-ae14-159aa2b478e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3901309021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3901309021
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.735532714
Short name T203
Test name
Test status
Simulation time 2047378038 ps
CPU time 13.02 seconds
Started Aug 02 05:14:03 PM PDT 24
Finished Aug 02 05:14:16 PM PDT 24
Peak memory 222516 kb
Host smart-af64e5ae-a1f4-48ea-b8a9-7d0fb27d8771
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735532714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.735532714
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.563714119
Short name T281
Test name
Test status
Simulation time 252103677 ps
CPU time 7.51 seconds
Started Aug 02 05:13:54 PM PDT 24
Finished Aug 02 05:14:02 PM PDT 24
Peak memory 215536 kb
Host smart-e9f1bfcd-4567-4f8e-8727-3b1f5de8f68f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=563714119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.563714119
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2192739303
Short name T236
Test name
Test status
Simulation time 818788116 ps
CPU time 7.68 seconds
Started Aug 02 05:12:28 PM PDT 24
Finished Aug 02 05:12:36 PM PDT 24
Peak memory 214212 kb
Host smart-4cd20dde-7ee0-4572-b13f-7c53a89f56f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2192739303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2192739303
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.948049914
Short name T146
Test name
Test status
Simulation time 575961026 ps
CPU time 5.16 seconds
Started Aug 02 05:13:22 PM PDT 24
Finished Aug 02 05:13:27 PM PDT 24
Peak memory 218208 kb
Host smart-1fb8286a-7d17-457a-a8b5-7df03faa7acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948049914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.948049914
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3052409046
Short name T274
Test name
Test status
Simulation time 1482353530 ps
CPU time 40.6 seconds
Started Aug 02 05:12:36 PM PDT 24
Finished Aug 02 05:13:17 PM PDT 24
Peak memory 222436 kb
Host smart-d98c29ae-6bb6-4825-8217-095a6e1235cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052409046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3052409046
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3312327069
Short name T36
Test name
Test status
Simulation time 100687725 ps
CPU time 3.59 seconds
Started Aug 02 05:14:07 PM PDT 24
Finished Aug 02 05:14:11 PM PDT 24
Peak memory 218152 kb
Host smart-fbcf604f-d1c5-4930-8d64-ac1a44e8c90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312327069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3312327069
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3914328615
Short name T46
Test name
Test status
Simulation time 6960376585 ps
CPU time 49.58 seconds
Started Aug 02 05:12:16 PM PDT 24
Finished Aug 02 05:13:06 PM PDT 24
Peak memory 222540 kb
Host smart-8c0618ab-4210-4463-afa0-d25621e62d6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914328615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3914328615
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.176548057
Short name T29
Test name
Test status
Simulation time 71251261 ps
CPU time 3.39 seconds
Started Aug 02 05:12:56 PM PDT 24
Finished Aug 02 05:13:00 PM PDT 24
Peak memory 222520 kb
Host smart-862d5347-4d54-4b86-802d-6834c595aef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176548057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.176548057
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.3328843272
Short name T67
Test name
Test status
Simulation time 5017955774 ps
CPU time 17.83 seconds
Started Aug 02 05:12:10 PM PDT 24
Finished Aug 02 05:12:28 PM PDT 24
Peak memory 221976 kb
Host smart-1ff67676-9bd6-4386-b56b-6af6bd8bfc71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328843272 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.3328843272
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1108413255
Short name T420
Test name
Test status
Simulation time 3597552613 ps
CPU time 19.66 seconds
Started Aug 02 05:13:23 PM PDT 24
Finished Aug 02 05:13:43 PM PDT 24
Peak memory 215928 kb
Host smart-20ff769b-d547-4906-ace8-12c3b8149d44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1108413255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1108413255
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2410316338
Short name T20
Test name
Test status
Simulation time 116052961 ps
CPU time 4.27 seconds
Started Aug 02 05:13:20 PM PDT 24
Finished Aug 02 05:13:24 PM PDT 24
Peak memory 210600 kb
Host smart-e5e4a7e8-f247-45ec-9655-34fad0966e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410316338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2410316338
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.4278812107
Short name T160
Test name
Test status
Simulation time 531498194 ps
CPU time 7.21 seconds
Started Aug 02 05:56:11 PM PDT 24
Finished Aug 02 05:56:18 PM PDT 24
Peak memory 206264 kb
Host smart-013a0102-bb23-45d0-ad5e-64b8936460bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278812107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.4278812107
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3217707624
Short name T279
Test name
Test status
Simulation time 117826890 ps
CPU time 6.48 seconds
Started Aug 02 05:13:30 PM PDT 24
Finished Aug 02 05:13:37 PM PDT 24
Peak memory 214416 kb
Host smart-2b00b7bc-a82a-403e-bc96-a52c1fb8bf95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3217707624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3217707624
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1909243940
Short name T89
Test name
Test status
Simulation time 34942991 ps
CPU time 2.2 seconds
Started Aug 02 05:13:05 PM PDT 24
Finished Aug 02 05:13:07 PM PDT 24
Peak memory 222568 kb
Host smart-b45a387e-025d-448d-a3bb-ff7857a46a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909243940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1909243940
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3232143006
Short name T219
Test name
Test status
Simulation time 927374109 ps
CPU time 24.84 seconds
Started Aug 02 05:13:38 PM PDT 24
Finished Aug 02 05:14:03 PM PDT 24
Peak memory 220888 kb
Host smart-3fc5fd75-f25f-4619-b778-6baf2ede4da3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232143006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3232143006
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2684843245
Short name T153
Test name
Test status
Simulation time 821991292 ps
CPU time 5.97 seconds
Started Aug 02 05:56:22 PM PDT 24
Finished Aug 02 05:56:29 PM PDT 24
Peak memory 206124 kb
Host smart-7ab45c60-2830-4a92-bd08-5b2c819b0075
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684843245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.2684843245
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1708948538
Short name T441
Test name
Test status
Simulation time 25670523 ps
CPU time 0.83 seconds
Started Aug 02 05:12:08 PM PDT 24
Finished Aug 02 05:12:09 PM PDT 24
Peak memory 205956 kb
Host smart-a645184b-7a1b-40d6-90b4-f1f5d5971d65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708948538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1708948538
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.683643078
Short name T17
Test name
Test status
Simulation time 546903285 ps
CPU time 18.67 seconds
Started Aug 02 05:14:10 PM PDT 24
Finished Aug 02 05:14:29 PM PDT 24
Peak memory 208992 kb
Host smart-b900cb65-d260-4e3c-b511-1788141fa849
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683643078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.683643078
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3128416238
Short name T191
Test name
Test status
Simulation time 571288653 ps
CPU time 20.33 seconds
Started Aug 02 05:12:15 PM PDT 24
Finished Aug 02 05:12:35 PM PDT 24
Peak memory 221380 kb
Host smart-f28fd669-823a-4e4b-8e81-4d9477af6ceb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128416238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3128416238
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.584460099
Short name T328
Test name
Test status
Simulation time 100817048 ps
CPU time 2.84 seconds
Started Aug 02 05:12:16 PM PDT 24
Finished Aug 02 05:12:19 PM PDT 24
Peak memory 214392 kb
Host smart-6b123961-17df-4539-93c8-5166d278208f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584460099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.584460099
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1879592323
Short name T270
Test name
Test status
Simulation time 419667946 ps
CPU time 23.34 seconds
Started Aug 02 05:13:07 PM PDT 24
Finished Aug 02 05:13:30 PM PDT 24
Peak memory 215176 kb
Host smart-73505d8d-b9e8-4046-8e85-fac8941dc7a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1879592323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1879592323
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.707868155
Short name T285
Test name
Test status
Simulation time 410181174 ps
CPU time 3.73 seconds
Started Aug 02 05:12:10 PM PDT 24
Finished Aug 02 05:12:14 PM PDT 24
Peak memory 214284 kb
Host smart-3b72f600-0301-405b-947d-4c1b5adc020e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707868155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.707868155
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2796996345
Short name T56
Test name
Test status
Simulation time 66231319 ps
CPU time 2.77 seconds
Started Aug 02 05:13:50 PM PDT 24
Finished Aug 02 05:13:53 PM PDT 24
Peak memory 210200 kb
Host smart-cb3ba654-55be-4bcc-b84f-54c48b3b2c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796996345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2796996345
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1077544264
Short name T384
Test name
Test status
Simulation time 2058151249 ps
CPU time 11.31 seconds
Started Aug 02 05:13:16 PM PDT 24
Finished Aug 02 05:13:28 PM PDT 24
Peak memory 222444 kb
Host smart-57b92d2e-6a8e-4b08-b163-5f8596cc469a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1077544264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1077544264
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1689173242
Short name T47
Test name
Test status
Simulation time 2366142155 ps
CPU time 40.56 seconds
Started Aug 02 05:13:57 PM PDT 24
Finished Aug 02 05:14:38 PM PDT 24
Peak memory 216528 kb
Host smart-7d32d5e8-d837-4558-8cae-ef451c64be51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689173242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1689173242
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1455650883
Short name T156
Test name
Test status
Simulation time 817449217 ps
CPU time 7.9 seconds
Started Aug 02 05:56:33 PM PDT 24
Finished Aug 02 05:56:41 PM PDT 24
Peak memory 214388 kb
Host smart-187beb74-afbf-4314-aba6-52e0946a4f07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455650883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1455650883
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1841852976
Short name T87
Test name
Test status
Simulation time 118605821 ps
CPU time 3.22 seconds
Started Aug 02 05:12:37 PM PDT 24
Finished Aug 02 05:12:41 PM PDT 24
Peak memory 214328 kb
Host smart-3f1a23d1-3a0c-4651-a482-c33517b88bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841852976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1841852976
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.115359251
Short name T150
Test name
Test status
Simulation time 88412293 ps
CPU time 3.68 seconds
Started Aug 02 05:13:12 PM PDT 24
Finished Aug 02 05:13:16 PM PDT 24
Peak memory 222644 kb
Host smart-b15ed676-9577-4e7e-a9ee-9da5c67c5c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115359251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.115359251
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1144263076
Short name T147
Test name
Test status
Simulation time 144504060 ps
CPU time 4.65 seconds
Started Aug 02 05:13:46 PM PDT 24
Finished Aug 02 05:13:51 PM PDT 24
Peak memory 222460 kb
Host smart-9d8d0f0b-4061-4735-a843-14acda8d8407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144263076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1144263076
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2052194800
Short name T145
Test name
Test status
Simulation time 76789853 ps
CPU time 3.08 seconds
Started Aug 02 05:13:48 PM PDT 24
Finished Aug 02 05:13:51 PM PDT 24
Peak memory 217104 kb
Host smart-865cc056-2bcb-4198-b5fa-bac932afcdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052194800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2052194800
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1702312563
Short name T209
Test name
Test status
Simulation time 577530745 ps
CPU time 2.75 seconds
Started Aug 02 05:12:24 PM PDT 24
Finished Aug 02 05:12:26 PM PDT 24
Peak memory 206752 kb
Host smart-60cecece-c7a2-4031-97b7-06ad2484decc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702312563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1702312563
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.173770454
Short name T297
Test name
Test status
Simulation time 112869311 ps
CPU time 3.87 seconds
Started Aug 02 05:12:42 PM PDT 24
Finished Aug 02 05:12:46 PM PDT 24
Peak memory 215616 kb
Host smart-477e773f-b387-4f55-ae3d-47d96d769f21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=173770454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.173770454
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.4049998452
Short name T352
Test name
Test status
Simulation time 95105906 ps
CPU time 3.34 seconds
Started Aug 02 05:12:44 PM PDT 24
Finished Aug 02 05:12:48 PM PDT 24
Peak memory 222216 kb
Host smart-523dd593-9232-422e-afb0-c83a8246d982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049998452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.4049998452
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1232659421
Short name T732
Test name
Test status
Simulation time 493454921 ps
CPU time 26.3 seconds
Started Aug 02 05:12:03 PM PDT 24
Finished Aug 02 05:12:30 PM PDT 24
Peak memory 216812 kb
Host smart-039e0524-d665-44ca-8e50-144e5709941d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232659421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1232659421
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.889183511
Short name T404
Test name
Test status
Simulation time 64180926 ps
CPU time 2.46 seconds
Started Aug 02 05:13:06 PM PDT 24
Finished Aug 02 05:13:08 PM PDT 24
Peak memory 214332 kb
Host smart-6596db1e-0b5b-48e8-a529-f13a5834f006
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=889183511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.889183511
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1870647221
Short name T305
Test name
Test status
Simulation time 1939641451 ps
CPU time 61.56 seconds
Started Aug 02 05:14:00 PM PDT 24
Finished Aug 02 05:15:01 PM PDT 24
Peak memory 216228 kb
Host smart-4cd514a1-2aa7-47fc-8ccb-db50c660dd24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870647221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1870647221
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3570566569
Short name T1014
Test name
Test status
Simulation time 277669822 ps
CPU time 5.35 seconds
Started Aug 02 05:56:16 PM PDT 24
Finished Aug 02 05:56:22 PM PDT 24
Peak memory 214580 kb
Host smart-8c692353-ac49-4d12-870b-afb64c23e624
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570566569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3570566569
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3116436931
Short name T268
Test name
Test status
Simulation time 35468671 ps
CPU time 2.64 seconds
Started Aug 02 05:12:39 PM PDT 24
Finished Aug 02 05:12:42 PM PDT 24
Peak memory 214476 kb
Host smart-b365bf68-d3db-4808-af2a-3584cfcebd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116436931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3116436931
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.126460108
Short name T387
Test name
Test status
Simulation time 82785628 ps
CPU time 4.43 seconds
Started Aug 02 05:12:56 PM PDT 24
Finished Aug 02 05:13:00 PM PDT 24
Peak memory 215484 kb
Host smart-7c62a2ad-5597-42d7-bdc9-31085bc3ae04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=126460108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.126460108
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3301319763
Short name T24
Test name
Test status
Simulation time 102768007 ps
CPU time 3.6 seconds
Started Aug 02 05:13:08 PM PDT 24
Finished Aug 02 05:13:11 PM PDT 24
Peak memory 214280 kb
Host smart-fa2d7e63-072a-4041-a650-f63779392dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301319763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3301319763
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2473070483
Short name T230
Test name
Test status
Simulation time 4216569543 ps
CPU time 47.2 seconds
Started Aug 02 05:13:24 PM PDT 24
Finished Aug 02 05:14:12 PM PDT 24
Peak memory 215704 kb
Host smart-8bd8fec7-a7c9-4386-8ec3-fa21a79fefb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473070483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2473070483
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.3494616268
Short name T291
Test name
Test status
Simulation time 850928028 ps
CPU time 30.16 seconds
Started Aug 02 05:12:06 PM PDT 24
Finished Aug 02 05:12:36 PM PDT 24
Peak memory 222472 kb
Host smart-e411729d-5366-4d97-9275-aa3ab402f014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494616268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3494616268
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.727382072
Short name T312
Test name
Test status
Simulation time 143274198 ps
CPU time 2.4 seconds
Started Aug 02 05:13:35 PM PDT 24
Finished Aug 02 05:13:37 PM PDT 24
Peak memory 215416 kb
Host smart-5c0de9c6-a0c5-4660-9d5f-d7f4693e012b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727382072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.727382072
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3487846834
Short name T123
Test name
Test status
Simulation time 652573922 ps
CPU time 14.52 seconds
Started Aug 02 05:13:52 PM PDT 24
Finished Aug 02 05:14:06 PM PDT 24
Peak memory 222588 kb
Host smart-5a355711-e0c6-44b4-aecb-35723eb6c1c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487846834 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3487846834
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.91687086
Short name T97
Test name
Test status
Simulation time 63925226 ps
CPU time 3.43 seconds
Started Aug 02 05:14:02 PM PDT 24
Finished Aug 02 05:14:06 PM PDT 24
Peak memory 214340 kb
Host smart-a44e28b9-b023-4d55-8dd2-ee0230a37f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91687086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.91687086
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2239016558
Short name T151
Test name
Test status
Simulation time 496934442 ps
CPU time 5.55 seconds
Started Aug 02 05:56:49 PM PDT 24
Finished Aug 02 05:56:54 PM PDT 24
Peak memory 214344 kb
Host smart-144dcd5d-8247-4aaf-b599-8ab211ab73ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239016558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2239016558
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.119820772
Short name T96
Test name
Test status
Simulation time 611312882 ps
CPU time 5.66 seconds
Started Aug 02 05:12:34 PM PDT 24
Finished Aug 02 05:12:40 PM PDT 24
Peak memory 209532 kb
Host smart-bc03ef83-272a-4a07-855e-b2afdb395d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119820772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.119820772
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.860693755
Short name T88
Test name
Test status
Simulation time 185356687 ps
CPU time 4.56 seconds
Started Aug 02 05:13:05 PM PDT 24
Finished Aug 02 05:13:09 PM PDT 24
Peak memory 214260 kb
Host smart-6bd6b6e4-7770-4dce-85c4-dee43229f98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860693755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.860693755
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2270909990
Short name T152
Test name
Test status
Simulation time 823328567 ps
CPU time 23.73 seconds
Started Aug 02 05:12:57 PM PDT 24
Finished Aug 02 05:13:21 PM PDT 24
Peak memory 210372 kb
Host smart-b68884a9-bdfb-4093-80d4-cb87f8539754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270909990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2270909990
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.1570670147
Short name T149
Test name
Test status
Simulation time 120315581 ps
CPU time 2.96 seconds
Started Aug 02 05:13:58 PM PDT 24
Finished Aug 02 05:14:01 PM PDT 24
Peak memory 222652 kb
Host smart-bdc89901-ffd8-451a-9f3f-dc35603a033c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570670147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1570670147
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1172271895
Short name T301
Test name
Test status
Simulation time 144563009 ps
CPU time 4.42 seconds
Started Aug 02 05:11:56 PM PDT 24
Finished Aug 02 05:12:01 PM PDT 24
Peak memory 207856 kb
Host smart-e4bdf9e6-a9e3-42d6-8e5d-767bc0d9cb0d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172271895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1172271895
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2453840436
Short name T377
Test name
Test status
Simulation time 3008833600 ps
CPU time 31.02 seconds
Started Aug 02 05:12:05 PM PDT 24
Finished Aug 02 05:12:37 PM PDT 24
Peak memory 222580 kb
Host smart-7884f0bd-da63-40f8-840a-c1da868e16d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453840436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2453840436
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2272538994
Short name T421
Test name
Test status
Simulation time 3212575300 ps
CPU time 46.39 seconds
Started Aug 02 05:12:10 PM PDT 24
Finished Aug 02 05:12:57 PM PDT 24
Peak memory 214984 kb
Host smart-abd053e8-9ff3-40fb-a9c6-80f49618f42f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2272538994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2272538994
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3287810396
Short name T234
Test name
Test status
Simulation time 52429354 ps
CPU time 3.69 seconds
Started Aug 02 05:13:07 PM PDT 24
Finished Aug 02 05:13:11 PM PDT 24
Peak memory 214356 kb
Host smart-3f7a71e5-7e10-458a-86c1-8d2277f1f508
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3287810396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3287810396
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2720480618
Short name T376
Test name
Test status
Simulation time 436875488 ps
CPU time 5.18 seconds
Started Aug 02 05:13:16 PM PDT 24
Finished Aug 02 05:13:21 PM PDT 24
Peak memory 215224 kb
Host smart-8f2eff3f-51c5-49f6-80ee-9ac2d5e4c2c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2720480618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2720480618
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3943894291
Short name T373
Test name
Test status
Simulation time 215161488 ps
CPU time 4.34 seconds
Started Aug 02 05:13:13 PM PDT 24
Finished Aug 02 05:13:17 PM PDT 24
Peak memory 219472 kb
Host smart-e1143131-9c5a-4558-a3c2-e2f800d88cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943894291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3943894291
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.799955379
Short name T313
Test name
Test status
Simulation time 3504206338 ps
CPU time 7.27 seconds
Started Aug 02 05:13:19 PM PDT 24
Finished Aug 02 05:13:27 PM PDT 24
Peak memory 214380 kb
Host smart-60c223ab-a95e-42e4-9dbc-b5b18f1d668c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799955379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.799955379
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1221707857
Short name T294
Test name
Test status
Simulation time 614483363 ps
CPU time 4.39 seconds
Started Aug 02 05:13:36 PM PDT 24
Finished Aug 02 05:13:40 PM PDT 24
Peak memory 220680 kb
Host smart-dfaa7347-ca18-43fa-986e-261a75635960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221707857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1221707857
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.4148877223
Short name T545
Test name
Test status
Simulation time 93989750 ps
CPU time 3.92 seconds
Started Aug 02 05:14:07 PM PDT 24
Finished Aug 02 05:14:11 PM PDT 24
Peak memory 207416 kb
Host smart-f71b3c22-56fe-4a02-a180-fe89113111ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148877223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.4148877223
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2748107686
Short name T171
Test name
Test status
Simulation time 157704857 ps
CPU time 3.98 seconds
Started Aug 02 05:56:40 PM PDT 24
Finished Aug 02 05:56:44 PM PDT 24
Peak memory 214324 kb
Host smart-a7811e15-4eff-4ef1-8052-1ac4f403bd02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748107686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2748107686
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3970515335
Short name T154
Test name
Test status
Simulation time 300383294 ps
CPU time 7.22 seconds
Started Aug 02 05:56:52 PM PDT 24
Finished Aug 02 05:56:59 PM PDT 24
Peak memory 214400 kb
Host smart-5d4e8faf-b654-453d-bb4b-f4cad23a36c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970515335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3970515335
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3305262432
Short name T22
Test name
Test status
Simulation time 483914353 ps
CPU time 4.6 seconds
Started Aug 02 05:12:06 PM PDT 24
Finished Aug 02 05:12:11 PM PDT 24
Peak memory 217000 kb
Host smart-9df6d245-13ba-489b-8fb7-e9fd3edf8313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305262432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3305262432
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.518896690
Short name T11
Test name
Test status
Simulation time 2794163317 ps
CPU time 16.34 seconds
Started Aug 02 05:12:10 PM PDT 24
Finished Aug 02 05:12:26 PM PDT 24
Peak memory 232452 kb
Host smart-e0330ef2-45f2-4df7-aea8-3fc3be19140b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518896690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.518896690
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.498611231
Short name T165
Test name
Test status
Simulation time 220574783 ps
CPU time 1.59 seconds
Started Aug 02 05:13:52 PM PDT 24
Finished Aug 02 05:13:54 PM PDT 24
Peak memory 209664 kb
Host smart-87a1e0e1-87c6-4c48-a543-bf2ca2681aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498611231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.498611231
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2366764058
Short name T148
Test name
Test status
Simulation time 241165420 ps
CPU time 2.94 seconds
Started Aug 02 05:12:27 PM PDT 24
Finished Aug 02 05:12:30 PM PDT 24
Peak memory 217688 kb
Host smart-eec73cc2-8e89-41ca-9e0d-94c96469c385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366764058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2366764058
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1688394857
Short name T692
Test name
Test status
Simulation time 58245309 ps
CPU time 2.06 seconds
Started Aug 02 05:11:48 PM PDT 24
Finished Aug 02 05:11:50 PM PDT 24
Peak memory 214256 kb
Host smart-c057c44c-570b-4ddb-9d7c-28604d73185a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688394857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1688394857
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1284620734
Short name T260
Test name
Test status
Simulation time 80911041 ps
CPU time 1.79 seconds
Started Aug 02 05:11:45 PM PDT 24
Finished Aug 02 05:11:47 PM PDT 24
Peak memory 206844 kb
Host smart-2269800c-d26e-4db6-8f57-75252d90d70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284620734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1284620734
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1263953340
Short name T52
Test name
Test status
Simulation time 58626841 ps
CPU time 1.84 seconds
Started Aug 02 05:12:24 PM PDT 24
Finished Aug 02 05:12:26 PM PDT 24
Peak memory 209980 kb
Host smart-1e2c9f05-b933-4ca0-af38-5fe9e42b4838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263953340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1263953340
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.287127911
Short name T31
Test name
Test status
Simulation time 533951765 ps
CPU time 16.07 seconds
Started Aug 02 05:12:23 PM PDT 24
Finished Aug 02 05:12:39 PM PDT 24
Peak memory 214608 kb
Host smart-a97f7477-4d88-4d62-9596-4bd861b1daca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287127911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.287127911
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2160450052
Short name T257
Test name
Test status
Simulation time 26007692758 ps
CPU time 111.16 seconds
Started Aug 02 05:12:30 PM PDT 24
Finished Aug 02 05:14:21 PM PDT 24
Peak memory 222648 kb
Host smart-97e529ff-959a-473f-8148-f1ad5995f0ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160450052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2160450052
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2552411362
Short name T611
Test name
Test status
Simulation time 177891990 ps
CPU time 7.69 seconds
Started Aug 02 05:12:31 PM PDT 24
Finished Aug 02 05:12:39 PM PDT 24
Peak memory 208292 kb
Host smart-70c37e43-66cb-4867-b5e2-d66e231a6917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552411362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2552411362
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1296593017
Short name T1
Test name
Test status
Simulation time 3948765056 ps
CPU time 51.82 seconds
Started Aug 02 05:12:02 PM PDT 24
Finished Aug 02 05:12:54 PM PDT 24
Peak memory 209100 kb
Host smart-26394231-f05c-478b-b44b-a9ef79f8e001
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296593017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1296593017
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.4066153738
Short name T7
Test name
Test status
Simulation time 358345457 ps
CPU time 3.22 seconds
Started Aug 02 05:12:38 PM PDT 24
Finished Aug 02 05:12:41 PM PDT 24
Peak memory 208860 kb
Host smart-39aa1d2b-c0ce-4f51-9174-bd7b10475342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066153738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.4066153738
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1372370023
Short name T350
Test name
Test status
Simulation time 290817349 ps
CPU time 3.73 seconds
Started Aug 02 05:13:14 PM PDT 24
Finished Aug 02 05:13:18 PM PDT 24
Peak memory 207492 kb
Host smart-2d4cf7ba-8276-4da6-877d-c2e88c2a4943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372370023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1372370023
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.868270447
Short name T388
Test name
Test status
Simulation time 80921393 ps
CPU time 3 seconds
Started Aug 02 05:13:38 PM PDT 24
Finished Aug 02 05:13:41 PM PDT 24
Peak memory 206792 kb
Host smart-92598436-6008-4188-a9c7-c6ddfc66e919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868270447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.868270447
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2603740245
Short name T228
Test name
Test status
Simulation time 1605468411 ps
CPU time 6.32 seconds
Started Aug 02 05:13:37 PM PDT 24
Finished Aug 02 05:13:44 PM PDT 24
Peak memory 214260 kb
Host smart-8f892815-1126-4c58-a9c5-83e98ab2981b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603740245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2603740245
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.810635588
Short name T331
Test name
Test status
Simulation time 38376997 ps
CPU time 2.2 seconds
Started Aug 02 05:13:37 PM PDT 24
Finished Aug 02 05:13:40 PM PDT 24
Peak memory 214328 kb
Host smart-f15a068f-eba8-4d1c-b3ec-e13b50da9f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810635588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.810635588
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_random.1547674930
Short name T363
Test name
Test status
Simulation time 59674542 ps
CPU time 3.79 seconds
Started Aug 02 05:14:07 PM PDT 24
Finished Aug 02 05:14:11 PM PDT 24
Peak memory 208112 kb
Host smart-e9578e0d-3221-43e7-ad65-e501af836231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547674930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1547674930
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2094440663
Short name T216
Test name
Test status
Simulation time 351374280 ps
CPU time 4.77 seconds
Started Aug 02 05:12:31 PM PDT 24
Finished Aug 02 05:12:36 PM PDT 24
Peak memory 214344 kb
Host smart-df3f7c01-b55b-492f-894a-87a944900dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094440663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2094440663
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.489724783
Short name T9
Test name
Test status
Simulation time 578039570 ps
CPU time 6.75 seconds
Started Aug 02 05:12:15 PM PDT 24
Finished Aug 02 05:12:22 PM PDT 24
Peak memory 237180 kb
Host smart-ced1283d-167d-4381-871d-eced06cdd51a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489724783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.489724783
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.166225779
Short name T136
Test name
Test status
Simulation time 238376934 ps
CPU time 4.06 seconds
Started Aug 02 05:56:22 PM PDT 24
Finished Aug 02 05:56:27 PM PDT 24
Peak memory 206252 kb
Host smart-a99754b7-9434-45ec-adff-27db06e7668e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166225779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.166225779
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3961123555
Short name T968
Test name
Test status
Simulation time 432049906 ps
CPU time 12.28 seconds
Started Aug 02 05:56:20 PM PDT 24
Finished Aug 02 05:56:32 PM PDT 24
Peak memory 206148 kb
Host smart-d35c5a43-0cf2-4036-bfc0-ff663149d548
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961123555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
961123555
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3148946659
Short name T923
Test name
Test status
Simulation time 215746394 ps
CPU time 1.41 seconds
Started Aug 02 05:56:13 PM PDT 24
Finished Aug 02 05:56:15 PM PDT 24
Peak memory 206172 kb
Host smart-9d826410-ebd6-42ed-ab74-a3a698cbf97b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148946659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
148946659
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3581561590
Short name T1074
Test name
Test status
Simulation time 114137344 ps
CPU time 1.13 seconds
Started Aug 02 05:56:20 PM PDT 24
Finished Aug 02 05:56:21 PM PDT 24
Peak memory 206084 kb
Host smart-c8162d3d-17ab-4b91-8dd8-1b2de4dc0fb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581561590 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3581561590
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3414055246
Short name T1051
Test name
Test status
Simulation time 15870898 ps
CPU time 1.14 seconds
Started Aug 02 05:56:20 PM PDT 24
Finished Aug 02 05:56:21 PM PDT 24
Peak memory 205968 kb
Host smart-406c09e3-f2d4-42cb-9353-9cd8f47cde86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414055246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3414055246
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3747839499
Short name T936
Test name
Test status
Simulation time 10890079 ps
CPU time 0.85 seconds
Started Aug 02 05:56:11 PM PDT 24
Finished Aug 02 05:56:12 PM PDT 24
Peak memory 205872 kb
Host smart-cb103ec4-fa6b-4183-a20e-ed33354bcb9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747839499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3747839499
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.849520256
Short name T939
Test name
Test status
Simulation time 136777926 ps
CPU time 2.36 seconds
Started Aug 02 05:56:18 PM PDT 24
Finished Aug 02 05:56:21 PM PDT 24
Peak memory 206192 kb
Host smart-93a6156c-3286-4268-b923-443addb79ed1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849520256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.849520256
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3940738228
Short name T1000
Test name
Test status
Simulation time 305917515 ps
CPU time 4.14 seconds
Started Aug 02 05:56:13 PM PDT 24
Finished Aug 02 05:56:17 PM PDT 24
Peak memory 214668 kb
Host smart-3e679447-7797-454e-ba8f-b58a39293951
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940738228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3940738228
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1527421365
Short name T987
Test name
Test status
Simulation time 53429920 ps
CPU time 1.76 seconds
Started Aug 02 05:56:09 PM PDT 24
Finished Aug 02 05:56:11 PM PDT 24
Peak memory 206204 kb
Host smart-72448527-0ef4-430b-90b5-116787c8d623
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527421365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1527421365
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3558793040
Short name T1050
Test name
Test status
Simulation time 252975936 ps
CPU time 6.19 seconds
Started Aug 02 05:56:18 PM PDT 24
Finished Aug 02 05:56:24 PM PDT 24
Peak memory 206236 kb
Host smart-f3a1f118-1ec5-458d-9e01-592b2f81dea4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558793040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
558793040
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.249271970
Short name T921
Test name
Test status
Simulation time 2142418426 ps
CPU time 9.47 seconds
Started Aug 02 05:56:16 PM PDT 24
Finished Aug 02 05:56:26 PM PDT 24
Peak memory 206204 kb
Host smart-bcb4cd39-ba99-49d0-8ba0-43f7e3919e4a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249271970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.249271970
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3507492798
Short name T967
Test name
Test status
Simulation time 127584336 ps
CPU time 1.12 seconds
Started Aug 02 05:56:25 PM PDT 24
Finished Aug 02 05:56:26 PM PDT 24
Peak memory 206180 kb
Host smart-21abef79-39ac-489b-a82b-d85a78797c8c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507492798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
507492798
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3610798093
Short name T986
Test name
Test status
Simulation time 127290190 ps
CPU time 2.58 seconds
Started Aug 02 05:56:17 PM PDT 24
Finished Aug 02 05:56:19 PM PDT 24
Peak memory 214540 kb
Host smart-f1898cc0-4b57-4ad9-a6fa-b9d8def6e215
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610798093 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3610798093
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.417417615
Short name T940
Test name
Test status
Simulation time 18272329 ps
CPU time 1.01 seconds
Started Aug 02 05:56:22 PM PDT 24
Finished Aug 02 05:56:24 PM PDT 24
Peak memory 206156 kb
Host smart-80ceaad5-858d-464c-be15-6be3c98d8ceb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417417615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.417417615
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1727035061
Short name T1033
Test name
Test status
Simulation time 33348804 ps
CPU time 0.73 seconds
Started Aug 02 05:56:16 PM PDT 24
Finished Aug 02 05:56:17 PM PDT 24
Peak memory 205988 kb
Host smart-7378853c-77f1-4822-8abe-26d6dfc50c8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727035061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1727035061
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1998895986
Short name T961
Test name
Test status
Simulation time 436615881 ps
CPU time 2.75 seconds
Started Aug 02 05:56:18 PM PDT 24
Finished Aug 02 05:56:21 PM PDT 24
Peak memory 206228 kb
Host smart-dfde35dd-18fd-4e61-9ab7-901140eb96bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998895986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1998895986
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2760245147
Short name T1057
Test name
Test status
Simulation time 450617563 ps
CPU time 4.4 seconds
Started Aug 02 05:56:18 PM PDT 24
Finished Aug 02 05:56:22 PM PDT 24
Peak memory 214604 kb
Host smart-9ddca0f7-7802-4940-87cd-ae77de1ce681
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760245147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2760245147
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3692335838
Short name T976
Test name
Test status
Simulation time 1470133256 ps
CPU time 15.13 seconds
Started Aug 02 05:56:19 PM PDT 24
Finished Aug 02 05:56:34 PM PDT 24
Peak memory 214688 kb
Host smart-3bffd467-16c4-4aec-b52a-e01d8812d175
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692335838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3692335838
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.428883385
Short name T1039
Test name
Test status
Simulation time 427139811 ps
CPU time 2.19 seconds
Started Aug 02 05:56:22 PM PDT 24
Finished Aug 02 05:56:24 PM PDT 24
Peak memory 214536 kb
Host smart-fcae8110-9c9a-4ca9-94a6-2291f4cb8e5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428883385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.428883385
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.481512165
Short name T1011
Test name
Test status
Simulation time 47722987 ps
CPU time 1.61 seconds
Started Aug 02 05:56:50 PM PDT 24
Finished Aug 02 05:56:52 PM PDT 24
Peak memory 214468 kb
Host smart-4b927185-09b0-40a2-be47-07f1a07a55d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481512165 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.481512165
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.881036164
Short name T1048
Test name
Test status
Simulation time 13985323 ps
CPU time 0.85 seconds
Started Aug 02 05:56:30 PM PDT 24
Finished Aug 02 05:56:31 PM PDT 24
Peak memory 205980 kb
Host smart-b0385f78-e3c9-4eb4-bb84-da8bbff66255
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881036164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.881036164
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2165025494
Short name T930
Test name
Test status
Simulation time 17275354 ps
CPU time 0.84 seconds
Started Aug 02 05:56:31 PM PDT 24
Finished Aug 02 05:56:32 PM PDT 24
Peak memory 205980 kb
Host smart-280cd914-f602-4e48-84d5-145fd702b0e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165025494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2165025494
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3106924713
Short name T1035
Test name
Test status
Simulation time 42042422 ps
CPU time 1.41 seconds
Started Aug 02 05:56:50 PM PDT 24
Finished Aug 02 05:56:51 PM PDT 24
Peak memory 206196 kb
Host smart-89371fa0-d9d5-4d9d-9959-e0e8ab36a008
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106924713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3106924713
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2130151920
Short name T114
Test name
Test status
Simulation time 492644866 ps
CPU time 2.47 seconds
Started Aug 02 05:56:32 PM PDT 24
Finished Aug 02 05:56:34 PM PDT 24
Peak memory 214680 kb
Host smart-7771af64-1fef-484f-8644-af2eb89229a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130151920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2130151920
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3460455221
Short name T1062
Test name
Test status
Simulation time 195192559 ps
CPU time 8.4 seconds
Started Aug 02 05:56:31 PM PDT 24
Finished Aug 02 05:56:40 PM PDT 24
Peak memory 220748 kb
Host smart-3735ca17-3850-42d1-a1ab-fcba86140091
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460455221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3460455221
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1450034864
Short name T1031
Test name
Test status
Simulation time 504591779 ps
CPU time 3.81 seconds
Started Aug 02 05:56:34 PM PDT 24
Finished Aug 02 05:56:38 PM PDT 24
Peak memory 214452 kb
Host smart-92a3b89b-87b8-4bc2-b39a-d05d1c51ed18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450034864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1450034864
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.591844126
Short name T173
Test name
Test status
Simulation time 353478440 ps
CPU time 4.95 seconds
Started Aug 02 05:56:31 PM PDT 24
Finished Aug 02 05:56:36 PM PDT 24
Peak memory 215776 kb
Host smart-82cb73e4-2949-4128-94c3-8b0febd36530
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591844126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.591844126
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1311948046
Short name T1042
Test name
Test status
Simulation time 46152549 ps
CPU time 2.13 seconds
Started Aug 02 05:56:32 PM PDT 24
Finished Aug 02 05:56:34 PM PDT 24
Peak memory 214500 kb
Host smart-5c5e0c43-d3f0-4686-9577-3aecdbacebc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311948046 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1311948046
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3362394993
Short name T143
Test name
Test status
Simulation time 47048718 ps
CPU time 1.1 seconds
Started Aug 02 05:56:32 PM PDT 24
Finished Aug 02 05:56:34 PM PDT 24
Peak memory 206244 kb
Host smart-99d2f63c-343c-462a-bfef-42f32311340c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362394993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3362394993
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1490347930
Short name T913
Test name
Test status
Simulation time 212420467 ps
CPU time 0.88 seconds
Started Aug 02 05:56:50 PM PDT 24
Finished Aug 02 05:56:51 PM PDT 24
Peak memory 205972 kb
Host smart-0cfb73be-a353-4d4f-b751-75b7880b8875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490347930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1490347930
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1630849196
Short name T1066
Test name
Test status
Simulation time 67846316 ps
CPU time 1.48 seconds
Started Aug 02 05:56:33 PM PDT 24
Finished Aug 02 05:56:35 PM PDT 24
Peak memory 206172 kb
Host smart-07f55b25-7a66-47b8-8f03-1b99b111b907
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630849196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1630849196
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2858817747
Short name T965
Test name
Test status
Simulation time 149883822 ps
CPU time 2.27 seconds
Started Aug 02 05:56:31 PM PDT 24
Finished Aug 02 05:56:34 PM PDT 24
Peak memory 219092 kb
Host smart-59faf7ef-0904-425f-81c2-e13944e3b36d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858817747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2858817747
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.272431996
Short name T1005
Test name
Test status
Simulation time 151691371 ps
CPU time 4.04 seconds
Started Aug 02 05:56:35 PM PDT 24
Finished Aug 02 05:56:39 PM PDT 24
Peak memory 214684 kb
Host smart-815f0bde-65ef-4a23-b68c-9ab39a12645f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272431996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_shadow_reg_errors_with_csr_rw.272431996
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.948464957
Short name T947
Test name
Test status
Simulation time 62792083 ps
CPU time 2.53 seconds
Started Aug 02 05:56:32 PM PDT 24
Finished Aug 02 05:56:34 PM PDT 24
Peak memory 222568 kb
Host smart-b05efd05-6d92-4aae-ad51-c6e200331d97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948464957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.948464957
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2647153030
Short name T926
Test name
Test status
Simulation time 155515725 ps
CPU time 1.74 seconds
Started Aug 02 05:56:42 PM PDT 24
Finished Aug 02 05:56:43 PM PDT 24
Peak memory 219704 kb
Host smart-8c5ce7a6-5b3a-41cb-a7ac-2d7c875961a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647153030 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2647153030
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3099568819
Short name T964
Test name
Test status
Simulation time 56549875 ps
CPU time 1.22 seconds
Started Aug 02 05:56:40 PM PDT 24
Finished Aug 02 05:56:41 PM PDT 24
Peak memory 206240 kb
Host smart-1d223204-1784-4be3-8103-b8a52d815730
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099568819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3099568819
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3913606359
Short name T980
Test name
Test status
Simulation time 38744265 ps
CPU time 0.71 seconds
Started Aug 02 05:56:40 PM PDT 24
Finished Aug 02 05:56:41 PM PDT 24
Peak memory 206016 kb
Host smart-58c69f0b-f42c-4ec8-8b73-2f149ee0f0b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913606359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3913606359
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3949569904
Short name T960
Test name
Test status
Simulation time 39157917 ps
CPU time 2.21 seconds
Started Aug 02 05:56:43 PM PDT 24
Finished Aug 02 05:56:46 PM PDT 24
Peak memory 206116 kb
Host smart-f799e06f-aaa9-4c3f-b8dd-d6e70bb12b72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949569904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3949569904
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.334243817
Short name T115
Test name
Test status
Simulation time 458086272 ps
CPU time 2.94 seconds
Started Aug 02 05:56:50 PM PDT 24
Finished Aug 02 05:56:53 PM PDT 24
Peak memory 214412 kb
Host smart-3f41066e-7064-45a5-b63a-ab94ca51d537
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334243817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.334243817
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2048779319
Short name T1017
Test name
Test status
Simulation time 2339747368 ps
CPU time 4.66 seconds
Started Aug 02 05:56:50 PM PDT 24
Finished Aug 02 05:56:55 PM PDT 24
Peak memory 220328 kb
Host smart-b6dd0153-40f1-468c-803c-41ebb47850f8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048779319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2048779319
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.537505605
Short name T915
Test name
Test status
Simulation time 154421667 ps
CPU time 3.13 seconds
Started Aug 02 05:56:43 PM PDT 24
Finished Aug 02 05:56:47 PM PDT 24
Peak memory 214372 kb
Host smart-92be2533-229f-4c6f-beca-4e01003ed0fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537505605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.537505605
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3110898579
Short name T1060
Test name
Test status
Simulation time 73157172 ps
CPU time 1.09 seconds
Started Aug 02 05:56:42 PM PDT 24
Finished Aug 02 05:56:43 PM PDT 24
Peak memory 206320 kb
Host smart-c35cfb1e-e204-453a-b2d1-505b1f4c5dfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110898579 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3110898579
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.239046973
Short name T953
Test name
Test status
Simulation time 11259011 ps
CPU time 1.03 seconds
Started Aug 02 05:56:40 PM PDT 24
Finished Aug 02 05:56:41 PM PDT 24
Peak memory 206212 kb
Host smart-43a2e0e0-13f4-4ee8-8208-4b961f868941
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239046973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.239046973
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3758363317
Short name T1044
Test name
Test status
Simulation time 21791511 ps
CPU time 0.81 seconds
Started Aug 02 05:56:42 PM PDT 24
Finished Aug 02 05:56:43 PM PDT 24
Peak memory 205932 kb
Host smart-119d758d-29be-4175-a61e-aabba4e97215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758363317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3758363317
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1832655593
Short name T1059
Test name
Test status
Simulation time 69223115 ps
CPU time 2.5 seconds
Started Aug 02 05:56:42 PM PDT 24
Finished Aug 02 05:56:44 PM PDT 24
Peak memory 206228 kb
Host smart-452d86d7-f7ed-4a95-b04b-14a166755914
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832655593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1832655593
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2146224084
Short name T122
Test name
Test status
Simulation time 141827646 ps
CPU time 4.47 seconds
Started Aug 02 05:56:39 PM PDT 24
Finished Aug 02 05:56:43 PM PDT 24
Peak memory 214604 kb
Host smart-4148d390-8813-4773-946f-576da8d29547
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146224084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2146224084
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3918724323
Short name T1073
Test name
Test status
Simulation time 492458748 ps
CPU time 10.25 seconds
Started Aug 02 05:56:42 PM PDT 24
Finished Aug 02 05:56:52 PM PDT 24
Peak memory 214756 kb
Host smart-45a583d5-484a-471f-b11a-03015f0a0b79
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918724323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3918724323
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.4068758696
Short name T927
Test name
Test status
Simulation time 477533231 ps
CPU time 3.19 seconds
Started Aug 02 05:56:40 PM PDT 24
Finished Aug 02 05:56:44 PM PDT 24
Peak memory 214432 kb
Host smart-9e0666b1-ebf1-49b9-baf0-6a758da1ebc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068758696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.4068758696
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.928572927
Short name T172
Test name
Test status
Simulation time 206359409 ps
CPU time 7.03 seconds
Started Aug 02 05:56:42 PM PDT 24
Finished Aug 02 05:56:49 PM PDT 24
Peak memory 215664 kb
Host smart-81d7a3b1-bf35-4cab-86ae-b7abffdb77d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928572927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.928572927
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.320071838
Short name T914
Test name
Test status
Simulation time 78182860 ps
CPU time 1.36 seconds
Started Aug 02 05:56:40 PM PDT 24
Finished Aug 02 05:56:41 PM PDT 24
Peak memory 206284 kb
Host smart-844cb10e-e554-4c72-9c9c-eaf10b79cc1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320071838 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.320071838
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2530962070
Short name T979
Test name
Test status
Simulation time 198729684 ps
CPU time 1.53 seconds
Started Aug 02 05:56:42 PM PDT 24
Finished Aug 02 05:56:44 PM PDT 24
Peak memory 206108 kb
Host smart-30e8eae3-04ad-4f09-a0af-6c293cf9a54a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530962070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2530962070
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2682220248
Short name T1026
Test name
Test status
Simulation time 8996591 ps
CPU time 0.82 seconds
Started Aug 02 05:56:43 PM PDT 24
Finished Aug 02 05:56:44 PM PDT 24
Peak memory 205888 kb
Host smart-26807be7-9471-41b9-827e-78dc4ecc9206
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682220248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2682220248
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1411678616
Short name T1002
Test name
Test status
Simulation time 22748258 ps
CPU time 1.59 seconds
Started Aug 02 05:56:40 PM PDT 24
Finished Aug 02 05:56:42 PM PDT 24
Peak memory 206192 kb
Host smart-03384595-675f-4bce-953f-3475a99917c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411678616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1411678616
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2617820651
Short name T969
Test name
Test status
Simulation time 518630146 ps
CPU time 2.02 seconds
Started Aug 02 05:56:42 PM PDT 24
Finished Aug 02 05:56:44 PM PDT 24
Peak memory 214620 kb
Host smart-f9bca606-e7e6-439f-98a8-5cbb8276a845
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617820651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2617820651
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1869262017
Short name T1007
Test name
Test status
Simulation time 654928936 ps
CPU time 4.67 seconds
Started Aug 02 05:56:40 PM PDT 24
Finished Aug 02 05:56:45 PM PDT 24
Peak memory 220692 kb
Host smart-07895cdd-0619-4fd9-afe7-2d7acf1852dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869262017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1869262017
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.4186113696
Short name T981
Test name
Test status
Simulation time 182827704 ps
CPU time 3.56 seconds
Started Aug 02 05:56:41 PM PDT 24
Finished Aug 02 05:56:44 PM PDT 24
Peak memory 214444 kb
Host smart-85e66faf-dc6e-46e0-85cc-e065ecd56783
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186113696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.4186113696
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.249641486
Short name T401
Test name
Test status
Simulation time 259675081 ps
CPU time 8.61 seconds
Started Aug 02 05:56:40 PM PDT 24
Finished Aug 02 05:56:48 PM PDT 24
Peak memory 214408 kb
Host smart-c6014fa6-b417-4bc7-aa43-436945899389
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249641486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err
.249641486
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2140704506
Short name T1020
Test name
Test status
Simulation time 97797939 ps
CPU time 1.31 seconds
Started Aug 02 05:56:47 PM PDT 24
Finished Aug 02 05:56:49 PM PDT 24
Peak memory 206296 kb
Host smart-210b276d-6968-4a69-b2bb-11652511fa74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140704506 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2140704506
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1158292238
Short name T1040
Test name
Test status
Simulation time 17357496 ps
CPU time 0.97 seconds
Started Aug 02 05:56:50 PM PDT 24
Finished Aug 02 05:56:51 PM PDT 24
Peak memory 206028 kb
Host smart-7e25bf2f-9aba-4bca-b50d-ab92370953be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158292238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1158292238
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2940634116
Short name T999
Test name
Test status
Simulation time 29684608 ps
CPU time 0.71 seconds
Started Aug 02 05:56:40 PM PDT 24
Finished Aug 02 05:56:41 PM PDT 24
Peak memory 205964 kb
Host smart-1405a468-c242-48cb-8790-529c93c9a566
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940634116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2940634116
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.881557712
Short name T1076
Test name
Test status
Simulation time 147457708 ps
CPU time 2.23 seconds
Started Aug 02 05:56:48 PM PDT 24
Finished Aug 02 05:56:51 PM PDT 24
Peak memory 206056 kb
Host smart-6805a4a3-0112-4e74-8d7d-c557a13e6928
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881557712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.881557712
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.305130385
Short name T113
Test name
Test status
Simulation time 290562824 ps
CPU time 1.61 seconds
Started Aug 02 05:56:40 PM PDT 24
Finished Aug 02 05:56:42 PM PDT 24
Peak memory 214688 kb
Host smart-47f81988-8322-4b1d-aaaf-8658ce08b4a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305130385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.305130385
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2309355278
Short name T117
Test name
Test status
Simulation time 432629136 ps
CPU time 8.01 seconds
Started Aug 02 05:56:38 PM PDT 24
Finished Aug 02 05:56:46 PM PDT 24
Peak memory 220888 kb
Host smart-771d11f1-e04b-4970-835d-62503cc3e480
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309355278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2309355278
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.812813021
Short name T920
Test name
Test status
Simulation time 41558295 ps
CPU time 1.59 seconds
Started Aug 02 05:56:40 PM PDT 24
Finished Aug 02 05:56:42 PM PDT 24
Peak memory 214408 kb
Host smart-ff2afa4e-b5ed-4f08-928f-0082ef9460cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812813021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.812813021
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.160548999
Short name T168
Test name
Test status
Simulation time 266453623 ps
CPU time 5.27 seconds
Started Aug 02 05:56:38 PM PDT 24
Finished Aug 02 05:56:43 PM PDT 24
Peak memory 214436 kb
Host smart-fcf983a2-b8ab-4d2d-92ad-0233fafca1b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160548999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.160548999
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2245345572
Short name T957
Test name
Test status
Simulation time 94792628 ps
CPU time 1.48 seconds
Started Aug 02 05:56:47 PM PDT 24
Finished Aug 02 05:56:48 PM PDT 24
Peak memory 214484 kb
Host smart-b451d4c4-bd9d-4a3d-a34a-c098e68d87af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245345572 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2245345572
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3079910743
Short name T137
Test name
Test status
Simulation time 99653471 ps
CPU time 1.29 seconds
Started Aug 02 05:56:52 PM PDT 24
Finished Aug 02 05:56:53 PM PDT 24
Peak memory 206220 kb
Host smart-8d57c1ee-a492-4e63-8c04-bc76ea22d494
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079910743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3079910743
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.4060663691
Short name T943
Test name
Test status
Simulation time 10698896 ps
CPU time 0.72 seconds
Started Aug 02 05:56:47 PM PDT 24
Finished Aug 02 05:56:48 PM PDT 24
Peak memory 205916 kb
Host smart-51082174-7c83-40f1-8433-ac7d84e13628
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060663691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.4060663691
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1078785850
Short name T1016
Test name
Test status
Simulation time 34077655 ps
CPU time 1.98 seconds
Started Aug 02 05:56:52 PM PDT 24
Finished Aug 02 05:56:54 PM PDT 24
Peak memory 206248 kb
Host smart-9da9ed98-1bc0-4f6c-8eeb-80e110c98e0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078785850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1078785850
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1374045975
Short name T1028
Test name
Test status
Simulation time 168131234 ps
CPU time 4.72 seconds
Started Aug 02 05:56:48 PM PDT 24
Finished Aug 02 05:56:53 PM PDT 24
Peak memory 214660 kb
Host smart-ad082dc6-4a24-4fe2-bd58-bd31a67eebbf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374045975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1374045975
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3582168794
Short name T118
Test name
Test status
Simulation time 474350166 ps
CPU time 10.12 seconds
Started Aug 02 05:56:49 PM PDT 24
Finished Aug 02 05:56:59 PM PDT 24
Peak memory 214684 kb
Host smart-e626a051-e474-4b09-a84a-7eb17a4ebf36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582168794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3582168794
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.307184422
Short name T985
Test name
Test status
Simulation time 77092708 ps
CPU time 1.97 seconds
Started Aug 02 05:56:49 PM PDT 24
Finished Aug 02 05:56:51 PM PDT 24
Peak memory 222500 kb
Host smart-6b9eea8c-c4dc-4624-ac95-38cfb29ccefe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307184422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.307184422
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1623640735
Short name T932
Test name
Test status
Simulation time 195594414 ps
CPU time 2.07 seconds
Started Aug 02 05:56:47 PM PDT 24
Finished Aug 02 05:56:49 PM PDT 24
Peak memory 214472 kb
Host smart-cf28aefd-6b82-4e20-bff0-1e991cc9b481
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623640735 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1623640735
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.378647112
Short name T1010
Test name
Test status
Simulation time 61597163 ps
CPU time 1.16 seconds
Started Aug 02 05:56:46 PM PDT 24
Finished Aug 02 05:56:48 PM PDT 24
Peak memory 206160 kb
Host smart-880300f8-b941-4ca6-ba82-18c42e845f42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378647112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.378647112
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1120060861
Short name T1063
Test name
Test status
Simulation time 11772099 ps
CPU time 0.86 seconds
Started Aug 02 05:56:52 PM PDT 24
Finished Aug 02 05:56:53 PM PDT 24
Peak memory 205984 kb
Host smart-7bbb564c-bef2-4acd-932e-6caf0432e35f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120060861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1120060861
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1366965979
Short name T984
Test name
Test status
Simulation time 62340826 ps
CPU time 2.66 seconds
Started Aug 02 05:56:49 PM PDT 24
Finished Aug 02 05:56:51 PM PDT 24
Peak memory 206152 kb
Host smart-ef099dc5-2367-4484-8d3d-a191a8ff5f59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366965979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1366965979
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.4169156054
Short name T1058
Test name
Test status
Simulation time 147632212 ps
CPU time 2.04 seconds
Started Aug 02 05:56:50 PM PDT 24
Finished Aug 02 05:56:52 PM PDT 24
Peak memory 214776 kb
Host smart-2d69b353-82d5-485c-9ac3-d24e498047b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169156054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.4169156054
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.4292333901
Short name T1037
Test name
Test status
Simulation time 289210043 ps
CPU time 3.79 seconds
Started Aug 02 05:56:48 PM PDT 24
Finished Aug 02 05:56:52 PM PDT 24
Peak memory 214676 kb
Host smart-129faf9e-ba40-49e0-a7ed-43805de0d539
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292333901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.4292333901
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1683867300
Short name T1019
Test name
Test status
Simulation time 40860278 ps
CPU time 2.4 seconds
Started Aug 02 05:56:47 PM PDT 24
Finished Aug 02 05:56:50 PM PDT 24
Peak memory 214408 kb
Host smart-99622f7d-427b-4a80-abe7-8dfb73920e9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683867300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1683867300
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2705781853
Short name T1077
Test name
Test status
Simulation time 129793893 ps
CPU time 1.22 seconds
Started Aug 02 05:56:48 PM PDT 24
Finished Aug 02 05:56:49 PM PDT 24
Peak memory 214480 kb
Host smart-f91d7d7c-b516-45b1-b5c1-000279b35fd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705781853 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2705781853
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.312140527
Short name T1055
Test name
Test status
Simulation time 24116166 ps
CPU time 0.97 seconds
Started Aug 02 05:56:45 PM PDT 24
Finished Aug 02 05:56:46 PM PDT 24
Peak memory 206032 kb
Host smart-b74bdb4f-ccff-4eff-ad62-d08339868c40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312140527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.312140527
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1408975511
Short name T1045
Test name
Test status
Simulation time 15199287 ps
CPU time 0.74 seconds
Started Aug 02 05:56:46 PM PDT 24
Finished Aug 02 05:56:47 PM PDT 24
Peak memory 205896 kb
Host smart-82e41b78-44a2-46e2-b6fd-e54245ad1b76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408975511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1408975511
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2195252411
Short name T988
Test name
Test status
Simulation time 114697312 ps
CPU time 2.16 seconds
Started Aug 02 05:56:52 PM PDT 24
Finished Aug 02 05:56:54 PM PDT 24
Peak memory 206232 kb
Host smart-22f2b004-c1a2-4a76-bf6f-5f748e6ffbd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195252411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2195252411
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1466081037
Short name T1004
Test name
Test status
Simulation time 533371049 ps
CPU time 2 seconds
Started Aug 02 05:56:52 PM PDT 24
Finished Aug 02 05:56:54 PM PDT 24
Peak memory 214760 kb
Host smart-81e18ade-e2da-4eb7-9270-5381b2799c57
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466081037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1466081037
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3965027105
Short name T1030
Test name
Test status
Simulation time 400888130 ps
CPU time 13.43 seconds
Started Aug 02 05:56:49 PM PDT 24
Finished Aug 02 05:57:03 PM PDT 24
Peak memory 214720 kb
Host smart-ef36e1c2-6ffb-407b-bcb7-68c650eb25ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965027105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3965027105
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2448243109
Short name T1069
Test name
Test status
Simulation time 68938166 ps
CPU time 3.23 seconds
Started Aug 02 05:56:49 PM PDT 24
Finished Aug 02 05:56:52 PM PDT 24
Peak memory 214364 kb
Host smart-2343292c-3036-4c31-b4ea-1f4e74bf789a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448243109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2448243109
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.188429620
Short name T164
Test name
Test status
Simulation time 108373372 ps
CPU time 3.7 seconds
Started Aug 02 05:56:48 PM PDT 24
Finished Aug 02 05:56:52 PM PDT 24
Peak memory 214248 kb
Host smart-752e2543-efe6-41fd-a085-b6eb13297b11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188429620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.188429620
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3854063535
Short name T966
Test name
Test status
Simulation time 70650161 ps
CPU time 2.14 seconds
Started Aug 02 05:56:54 PM PDT 24
Finished Aug 02 05:56:56 PM PDT 24
Peak memory 214528 kb
Host smart-a975caba-6de7-4360-ba24-695a2a5a229a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854063535 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3854063535
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2090687704
Short name T989
Test name
Test status
Simulation time 38547860 ps
CPU time 1.23 seconds
Started Aug 02 05:56:53 PM PDT 24
Finished Aug 02 05:56:54 PM PDT 24
Peak memory 206144 kb
Host smart-ba7087d1-f095-4683-9214-a4b23355a336
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090687704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2090687704
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1558833749
Short name T974
Test name
Test status
Simulation time 38292512 ps
CPU time 0.89 seconds
Started Aug 02 05:56:56 PM PDT 24
Finished Aug 02 05:56:58 PM PDT 24
Peak memory 205972 kb
Host smart-d14e58a6-b2e1-4ef6-9117-2d9694a45360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558833749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1558833749
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2466975758
Short name T141
Test name
Test status
Simulation time 260237231 ps
CPU time 2.6 seconds
Started Aug 02 05:56:56 PM PDT 24
Finished Aug 02 05:56:59 PM PDT 24
Peak memory 206172 kb
Host smart-3415ead1-fc66-4148-8761-7b585d8caaaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466975758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2466975758
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.999219632
Short name T1036
Test name
Test status
Simulation time 639330941 ps
CPU time 1.82 seconds
Started Aug 02 05:56:48 PM PDT 24
Finished Aug 02 05:56:50 PM PDT 24
Peak memory 214760 kb
Host smart-80d1468a-385a-41dd-9df3-e00ad4bbd268
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999219632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.999219632
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3870794183
Short name T121
Test name
Test status
Simulation time 783108329 ps
CPU time 15.22 seconds
Started Aug 02 05:56:47 PM PDT 24
Finished Aug 02 05:57:02 PM PDT 24
Peak memory 214796 kb
Host smart-c9d1e55b-4b43-4edc-b3f7-96e032eedd03
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870794183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3870794183
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2116722876
Short name T998
Test name
Test status
Simulation time 36567916 ps
CPU time 3.08 seconds
Started Aug 02 05:56:51 PM PDT 24
Finished Aug 02 05:56:54 PM PDT 24
Peak memory 214488 kb
Host smart-b7b87a65-e152-408b-a756-489d59c4d9b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116722876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2116722876
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.207093830
Short name T954
Test name
Test status
Simulation time 482920441 ps
CPU time 9.7 seconds
Started Aug 02 05:56:46 PM PDT 24
Finished Aug 02 05:56:56 PM PDT 24
Peak memory 214360 kb
Host smart-2b302e41-b589-476a-8867-c0724e1a43b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207093830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err
.207093830
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3298793827
Short name T1078
Test name
Test status
Simulation time 194607548 ps
CPU time 7.34 seconds
Started Aug 02 05:56:22 PM PDT 24
Finished Aug 02 05:56:30 PM PDT 24
Peak memory 206196 kb
Host smart-a36b262c-cf42-4f68-8bcc-51d8020197e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298793827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
298793827
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3914682144
Short name T993
Test name
Test status
Simulation time 545041891 ps
CPU time 6.3 seconds
Started Aug 02 05:56:18 PM PDT 24
Finished Aug 02 05:56:25 PM PDT 24
Peak memory 206152 kb
Host smart-b22def26-b283-4162-b78c-1f2719cfafab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914682144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
914682144
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3814976005
Short name T949
Test name
Test status
Simulation time 40871250 ps
CPU time 0.92 seconds
Started Aug 02 05:56:20 PM PDT 24
Finished Aug 02 05:56:21 PM PDT 24
Peak memory 205832 kb
Host smart-859bbec6-e19f-4a41-92e6-9c291b63f610
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814976005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
814976005
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3525139098
Short name T924
Test name
Test status
Simulation time 215433731 ps
CPU time 2.2 seconds
Started Aug 02 05:56:20 PM PDT 24
Finished Aug 02 05:56:22 PM PDT 24
Peak memory 214296 kb
Host smart-4b3bb194-6cbf-49ca-b8d8-380e45926dbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525139098 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3525139098
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.352793123
Short name T138
Test name
Test status
Simulation time 36740990 ps
CPU time 1.58 seconds
Started Aug 02 05:56:23 PM PDT 24
Finished Aug 02 05:56:24 PM PDT 24
Peak memory 206292 kb
Host smart-fea24d26-73dc-4b6d-a4f9-ea134d2cacd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352793123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.352793123
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3982107167
Short name T1022
Test name
Test status
Simulation time 21249412 ps
CPU time 0.72 seconds
Started Aug 02 05:56:24 PM PDT 24
Finished Aug 02 05:56:25 PM PDT 24
Peak memory 205968 kb
Host smart-940e375b-d2e7-4eff-ad23-feff96ce1a6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982107167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3982107167
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.605620076
Short name T971
Test name
Test status
Simulation time 220443911 ps
CPU time 3.56 seconds
Started Aug 02 05:56:19 PM PDT 24
Finished Aug 02 05:56:23 PM PDT 24
Peak memory 206184 kb
Host smart-e6554914-a369-4b1b-803d-8e268f891861
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605620076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.605620076
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1921139783
Short name T959
Test name
Test status
Simulation time 255321846 ps
CPU time 1.63 seconds
Started Aug 02 05:56:25 PM PDT 24
Finished Aug 02 05:56:26 PM PDT 24
Peak memory 214544 kb
Host smart-5ac9fc79-40c4-43e8-b28c-3bd8e4f57c17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921139783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1921139783
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.759793024
Short name T1052
Test name
Test status
Simulation time 52134178 ps
CPU time 2.62 seconds
Started Aug 02 05:56:19 PM PDT 24
Finished Aug 02 05:56:21 PM PDT 24
Peak memory 214300 kb
Host smart-7b2bdc4e-98e3-4ca1-ad9c-69211cbea38c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759793024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.
759793024
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1729332642
Short name T1029
Test name
Test status
Simulation time 9353950 ps
CPU time 0.72 seconds
Started Aug 02 05:56:54 PM PDT 24
Finished Aug 02 05:56:55 PM PDT 24
Peak memory 205932 kb
Host smart-07e31e50-6cc2-4042-8c01-b35532df69f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729332642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1729332642
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2799018232
Short name T1054
Test name
Test status
Simulation time 20298541 ps
CPU time 0.73 seconds
Started Aug 02 05:56:56 PM PDT 24
Finished Aug 02 05:56:57 PM PDT 24
Peak memory 205972 kb
Host smart-a4d37022-3057-499a-822d-1fbdfa7f7f3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799018232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2799018232
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.290054197
Short name T1018
Test name
Test status
Simulation time 10022605 ps
CPU time 0.8 seconds
Started Aug 02 05:56:54 PM PDT 24
Finished Aug 02 05:56:55 PM PDT 24
Peak memory 205988 kb
Host smart-b37bc058-ce4a-411a-94e2-8895247261b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290054197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.290054197
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.420877644
Short name T972
Test name
Test status
Simulation time 13583583 ps
CPU time 0.73 seconds
Started Aug 02 05:56:53 PM PDT 24
Finished Aug 02 05:56:53 PM PDT 24
Peak memory 206000 kb
Host smart-b3086202-23df-4396-b204-e0d9f30766cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420877644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.420877644
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2722434613
Short name T1013
Test name
Test status
Simulation time 30800382 ps
CPU time 0.69 seconds
Started Aug 02 05:56:55 PM PDT 24
Finished Aug 02 05:56:55 PM PDT 24
Peak memory 205976 kb
Host smart-1b40acb2-f65b-4cb9-83cd-ed93e1a95185
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722434613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2722434613
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1512526741
Short name T1047
Test name
Test status
Simulation time 17529363 ps
CPU time 0.72 seconds
Started Aug 02 05:57:05 PM PDT 24
Finished Aug 02 05:57:06 PM PDT 24
Peak memory 205904 kb
Host smart-7f5cf703-08ef-45c4-a1cf-a300759fbd08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512526741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1512526741
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2871343894
Short name T1049
Test name
Test status
Simulation time 20949665 ps
CPU time 0.86 seconds
Started Aug 02 05:56:54 PM PDT 24
Finished Aug 02 05:56:55 PM PDT 24
Peak memory 205932 kb
Host smart-8ef10716-c654-4014-9e3e-88f13ca6576b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871343894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2871343894
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.487841822
Short name T1015
Test name
Test status
Simulation time 18027077 ps
CPU time 0.87 seconds
Started Aug 02 05:56:56 PM PDT 24
Finished Aug 02 05:56:57 PM PDT 24
Peak memory 205992 kb
Host smart-42372726-7e6a-4529-b651-29aad1d11610
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487841822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.487841822
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.4264953438
Short name T929
Test name
Test status
Simulation time 13709921 ps
CPU time 0.74 seconds
Started Aug 02 05:56:54 PM PDT 24
Finished Aug 02 05:56:55 PM PDT 24
Peak memory 206000 kb
Host smart-c675cb3e-381d-48e7-ab21-87f5e34eace4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264953438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.4264953438
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2568695030
Short name T996
Test name
Test status
Simulation time 44604860 ps
CPU time 0.87 seconds
Started Aug 02 05:56:58 PM PDT 24
Finished Aug 02 05:56:59 PM PDT 24
Peak memory 205964 kb
Host smart-c31951ce-2d40-405f-bbb8-5483581c0eab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568695030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2568695030
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1129027784
Short name T944
Test name
Test status
Simulation time 68043222 ps
CPU time 3.79 seconds
Started Aug 02 05:56:19 PM PDT 24
Finished Aug 02 05:56:22 PM PDT 24
Peak memory 206140 kb
Host smart-8c892930-cc54-4c59-b9f8-9257cf7637f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129027784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
129027784
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.918066952
Short name T1061
Test name
Test status
Simulation time 540673412 ps
CPU time 6.28 seconds
Started Aug 02 05:56:17 PM PDT 24
Finished Aug 02 05:56:24 PM PDT 24
Peak memory 206252 kb
Host smart-7de19c02-3562-4351-a7dc-eaa356ec2685
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918066952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.918066952
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.493632159
Short name T1034
Test name
Test status
Simulation time 18278283 ps
CPU time 0.88 seconds
Started Aug 02 05:56:19 PM PDT 24
Finished Aug 02 05:56:20 PM PDT 24
Peak memory 205988 kb
Host smart-b2de7009-c2b1-4ad2-8627-db33ca823bb4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493632159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.493632159
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2723279965
Short name T952
Test name
Test status
Simulation time 53141585 ps
CPU time 1.27 seconds
Started Aug 02 05:56:23 PM PDT 24
Finished Aug 02 05:56:25 PM PDT 24
Peak memory 206288 kb
Host smart-7c678b1f-8b5f-49f7-98ad-1d0329cdf57d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723279965 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2723279965
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3719882633
Short name T925
Test name
Test status
Simulation time 48965743 ps
CPU time 1.25 seconds
Started Aug 02 05:56:19 PM PDT 24
Finished Aug 02 05:56:20 PM PDT 24
Peak memory 206100 kb
Host smart-f8df89c9-bbcb-4851-90b6-0bde80f08420
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719882633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3719882633
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.750867107
Short name T992
Test name
Test status
Simulation time 13830401 ps
CPU time 0.75 seconds
Started Aug 02 05:56:19 PM PDT 24
Finished Aug 02 05:56:20 PM PDT 24
Peak memory 205924 kb
Host smart-5bd105a4-ea3b-4c71-8d67-e18d25ac908b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750867107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.750867107
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.294860579
Short name T1038
Test name
Test status
Simulation time 46180017 ps
CPU time 1.68 seconds
Started Aug 02 05:56:17 PM PDT 24
Finished Aug 02 05:56:19 PM PDT 24
Peak memory 206156 kb
Host smart-be82ee43-37b2-4a68-b766-8af0972ae72f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294860579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.294860579
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2204176316
Short name T956
Test name
Test status
Simulation time 640841102 ps
CPU time 2.44 seconds
Started Aug 02 05:56:17 PM PDT 24
Finished Aug 02 05:56:19 PM PDT 24
Peak memory 214788 kb
Host smart-a3fa8d19-bc9b-4a0e-8b73-7da521a21f5e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204176316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2204176316
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.485356215
Short name T120
Test name
Test status
Simulation time 1284306794 ps
CPU time 12.41 seconds
Started Aug 02 05:56:25 PM PDT 24
Finished Aug 02 05:56:37 PM PDT 24
Peak memory 214696 kb
Host smart-8d7454fb-038f-4070-919b-1a1a5e1e39d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485356215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_shadow_reg_errors_with_csr_rw.485356215
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.515117691
Short name T1053
Test name
Test status
Simulation time 118424445 ps
CPU time 3.29 seconds
Started Aug 02 05:56:18 PM PDT 24
Finished Aug 02 05:56:21 PM PDT 24
Peak memory 222672 kb
Host smart-2475e69f-81b9-48e2-96aa-f2f3231d9567
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515117691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.515117691
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.592937060
Short name T161
Test name
Test status
Simulation time 199674159 ps
CPU time 5.27 seconds
Started Aug 02 05:56:19 PM PDT 24
Finished Aug 02 05:56:24 PM PDT 24
Peak memory 214364 kb
Host smart-fd34835c-acb6-418d-a8d0-2dd9726493a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592937060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
592937060
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.294539917
Short name T912
Test name
Test status
Simulation time 15121200 ps
CPU time 0.72 seconds
Started Aug 02 05:56:55 PM PDT 24
Finished Aug 02 05:56:56 PM PDT 24
Peak memory 205996 kb
Host smart-7ebb1ecb-2d8e-4ddb-a1fe-09c4904f893f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294539917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.294539917
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.639308277
Short name T935
Test name
Test status
Simulation time 14108628 ps
CPU time 0.74 seconds
Started Aug 02 05:56:56 PM PDT 24
Finished Aug 02 05:56:57 PM PDT 24
Peak memory 205888 kb
Host smart-a8fe751f-921a-4ba0-b754-85fa58ea0eb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639308277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.639308277
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.472518697
Short name T1071
Test name
Test status
Simulation time 13025266 ps
CPU time 0.72 seconds
Started Aug 02 05:56:55 PM PDT 24
Finished Aug 02 05:56:56 PM PDT 24
Peak memory 205912 kb
Host smart-443f5ad9-fe7c-4f63-9123-325146dd1327
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472518697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.472518697
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3553463544
Short name T950
Test name
Test status
Simulation time 27282010 ps
CPU time 0.95 seconds
Started Aug 02 05:56:56 PM PDT 24
Finished Aug 02 05:56:57 PM PDT 24
Peak memory 206168 kb
Host smart-ee36e73c-1e67-40e8-8927-40a08037bc40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553463544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3553463544
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.583696854
Short name T970
Test name
Test status
Simulation time 32733554 ps
CPU time 0.82 seconds
Started Aug 02 05:56:59 PM PDT 24
Finished Aug 02 05:57:00 PM PDT 24
Peak memory 205948 kb
Host smart-eba89eca-78fd-4baa-9ee7-600c023873e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583696854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.583696854
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2864029265
Short name T918
Test name
Test status
Simulation time 12512234 ps
CPU time 0.77 seconds
Started Aug 02 05:56:59 PM PDT 24
Finished Aug 02 05:57:00 PM PDT 24
Peak memory 205948 kb
Host smart-c282a5e1-44c7-4309-a9bf-6f1c4777333a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864029265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2864029265
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1923283682
Short name T975
Test name
Test status
Simulation time 10345052 ps
CPU time 0.71 seconds
Started Aug 02 05:56:56 PM PDT 24
Finished Aug 02 05:56:57 PM PDT 24
Peak memory 205928 kb
Host smart-e557055f-9cda-4a74-a9ba-2e67e9c1ac71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923283682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1923283682
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.4058071502
Short name T1043
Test name
Test status
Simulation time 27432031 ps
CPU time 0.7 seconds
Started Aug 02 05:56:58 PM PDT 24
Finished Aug 02 05:56:58 PM PDT 24
Peak memory 206016 kb
Host smart-23b36f05-9245-4888-bfc8-9a932004537a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058071502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.4058071502
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3414063458
Short name T942
Test name
Test status
Simulation time 18692365 ps
CPU time 0.8 seconds
Started Aug 02 05:56:55 PM PDT 24
Finished Aug 02 05:56:56 PM PDT 24
Peak memory 205908 kb
Host smart-d50e42a2-54f4-40bb-943c-414cdf639754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414063458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3414063458
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1310439032
Short name T917
Test name
Test status
Simulation time 19513304 ps
CPU time 0.74 seconds
Started Aug 02 05:57:00 PM PDT 24
Finished Aug 02 05:57:01 PM PDT 24
Peak memory 205968 kb
Host smart-37a4b76e-12ed-4d17-a72b-32c1522450af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310439032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1310439032
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1325892054
Short name T142
Test name
Test status
Simulation time 2564877288 ps
CPU time 10.24 seconds
Started Aug 02 05:56:26 PM PDT 24
Finished Aug 02 05:56:36 PM PDT 24
Peak memory 206268 kb
Host smart-c3b63ce5-70c4-426c-9acc-3d3f8ec83e56
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325892054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
325892054
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1180264861
Short name T1008
Test name
Test status
Simulation time 2341994536 ps
CPU time 15.77 seconds
Started Aug 02 05:56:23 PM PDT 24
Finished Aug 02 05:56:39 PM PDT 24
Peak memory 206280 kb
Host smart-da419f6b-612c-4f53-be6f-f550dd4062c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180264861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
180264861
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3622882819
Short name T983
Test name
Test status
Simulation time 56427092 ps
CPU time 1.29 seconds
Started Aug 02 05:56:30 PM PDT 24
Finished Aug 02 05:56:31 PM PDT 24
Peak memory 206120 kb
Host smart-6ae35a9c-f359-405d-8439-338b5ad1322a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622882819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
622882819
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2727819339
Short name T991
Test name
Test status
Simulation time 76370197 ps
CPU time 1.51 seconds
Started Aug 02 05:56:26 PM PDT 24
Finished Aug 02 05:56:28 PM PDT 24
Peak memory 206288 kb
Host smart-c53c6f38-80de-41b9-bbe0-6aa381417a22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727819339 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2727819339
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.873795641
Short name T140
Test name
Test status
Simulation time 49638917 ps
CPU time 1.28 seconds
Started Aug 02 05:56:25 PM PDT 24
Finished Aug 02 05:56:26 PM PDT 24
Peak memory 206204 kb
Host smart-39cc633c-a25e-4271-ba8f-b67d259ddc67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873795641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.873795641
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.925030499
Short name T1070
Test name
Test status
Simulation time 14677503 ps
CPU time 0.73 seconds
Started Aug 02 05:56:24 PM PDT 24
Finished Aug 02 05:56:25 PM PDT 24
Peak memory 205968 kb
Host smart-50618736-46c4-466f-9482-4ade7713d50b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925030499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.925030499
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1092853330
Short name T977
Test name
Test status
Simulation time 52655358 ps
CPU time 1.68 seconds
Started Aug 02 05:56:25 PM PDT 24
Finished Aug 02 05:56:27 PM PDT 24
Peak memory 206176 kb
Host smart-065f4309-46b8-4abe-9463-a5da7f9c6e34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092853330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1092853330
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2854545430
Short name T1072
Test name
Test status
Simulation time 117412514 ps
CPU time 1.99 seconds
Started Aug 02 05:56:24 PM PDT 24
Finished Aug 02 05:56:26 PM PDT 24
Peak memory 214704 kb
Host smart-79250833-59a5-4e2d-8aa7-7d7ca08f9397
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854545430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2854545430
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1699027025
Short name T1065
Test name
Test status
Simulation time 4317740522 ps
CPU time 8.67 seconds
Started Aug 02 05:56:30 PM PDT 24
Finished Aug 02 05:56:39 PM PDT 24
Peak memory 214712 kb
Host smart-df535f8b-60a0-4cfc-b144-7667a98a6fbc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699027025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1699027025
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3715779836
Short name T1024
Test name
Test status
Simulation time 98077275 ps
CPU time 2.19 seconds
Started Aug 02 05:56:25 PM PDT 24
Finished Aug 02 05:56:27 PM PDT 24
Peak memory 214448 kb
Host smart-80c9ecd7-4d0c-45d6-b236-e2730e2b8581
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715779836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3715779836
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1829228803
Short name T163
Test name
Test status
Simulation time 92328794 ps
CPU time 3.2 seconds
Started Aug 02 05:56:26 PM PDT 24
Finished Aug 02 05:56:30 PM PDT 24
Peak memory 206188 kb
Host smart-cb09393b-f3af-4879-9324-6444aafcdc3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829228803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1829228803
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.251243069
Short name T1027
Test name
Test status
Simulation time 10853014 ps
CPU time 0.71 seconds
Started Aug 02 05:56:53 PM PDT 24
Finished Aug 02 05:56:54 PM PDT 24
Peak memory 205976 kb
Host smart-bc7791d5-f12b-4912-8016-28c162f1061b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251243069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.251243069
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1947287490
Short name T1067
Test name
Test status
Simulation time 53346073 ps
CPU time 0.85 seconds
Started Aug 02 05:56:59 PM PDT 24
Finished Aug 02 05:57:00 PM PDT 24
Peak memory 205948 kb
Host smart-95186fae-64c1-4b6d-b1c2-4e2259661eb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947287490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1947287490
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.90828155
Short name T931
Test name
Test status
Simulation time 27900370 ps
CPU time 0.77 seconds
Started Aug 02 05:56:55 PM PDT 24
Finished Aug 02 05:56:56 PM PDT 24
Peak memory 205944 kb
Host smart-d295c397-49b1-452b-80d2-7c12cea17c70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90828155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.90828155
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3438710322
Short name T1001
Test name
Test status
Simulation time 7320595 ps
CPU time 0.8 seconds
Started Aug 02 05:56:56 PM PDT 24
Finished Aug 02 05:56:57 PM PDT 24
Peak memory 206008 kb
Host smart-3de404fd-97a7-498d-b3d8-49c811f92f0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438710322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3438710322
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1096176203
Short name T958
Test name
Test status
Simulation time 9701136 ps
CPU time 0.77 seconds
Started Aug 02 05:57:04 PM PDT 24
Finished Aug 02 05:57:05 PM PDT 24
Peak memory 205980 kb
Host smart-596d1157-c435-49c0-9de8-7309835c53f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096176203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1096176203
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3128594618
Short name T922
Test name
Test status
Simulation time 12534161 ps
CPU time 0.86 seconds
Started Aug 02 05:56:53 PM PDT 24
Finished Aug 02 05:56:54 PM PDT 24
Peak memory 205940 kb
Host smart-c83d4450-8c4d-47d0-b8c5-6b146ea70390
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128594618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3128594618
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2047899193
Short name T1056
Test name
Test status
Simulation time 18570279 ps
CPU time 0.81 seconds
Started Aug 02 05:56:55 PM PDT 24
Finished Aug 02 05:56:56 PM PDT 24
Peak memory 205924 kb
Host smart-9288ab75-ea8b-4fd5-ae4e-905ae214042f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047899193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2047899193
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.117020010
Short name T1041
Test name
Test status
Simulation time 10566760 ps
CPU time 0.78 seconds
Started Aug 02 05:56:57 PM PDT 24
Finished Aug 02 05:56:58 PM PDT 24
Peak memory 206016 kb
Host smart-53de0972-a5c5-481b-bade-836a18e4537e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117020010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.117020010
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.817657227
Short name T945
Test name
Test status
Simulation time 30667480 ps
CPU time 0.77 seconds
Started Aug 02 05:56:53 PM PDT 24
Finished Aug 02 05:56:54 PM PDT 24
Peak memory 205976 kb
Host smart-2bfd7cd6-ad11-4657-a4bb-f1e797a80ab6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817657227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.817657227
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1685260436
Short name T928
Test name
Test status
Simulation time 29096161 ps
CPU time 0.74 seconds
Started Aug 02 05:56:58 PM PDT 24
Finished Aug 02 05:56:59 PM PDT 24
Peak memory 205852 kb
Host smart-550aaa8b-d2b2-4cfb-b0d4-1938a94740f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685260436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1685260436
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.37215451
Short name T1068
Test name
Test status
Simulation time 56804918 ps
CPU time 1.89 seconds
Started Aug 02 05:56:53 PM PDT 24
Finished Aug 02 05:56:55 PM PDT 24
Peak memory 214556 kb
Host smart-cadc2028-72f6-4097-b7c7-79a21e273880
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37215451 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.37215451
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.4259414475
Short name T963
Test name
Test status
Simulation time 29333229 ps
CPU time 1.03 seconds
Started Aug 02 05:56:26 PM PDT 24
Finished Aug 02 05:56:27 PM PDT 24
Peak memory 206028 kb
Host smart-f45fd6c7-2d43-40f8-8bdc-53fe507b7b38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259414475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.4259414475
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.852197719
Short name T933
Test name
Test status
Simulation time 7439877 ps
CPU time 0.77 seconds
Started Aug 02 05:56:25 PM PDT 24
Finished Aug 02 05:56:26 PM PDT 24
Peak memory 205996 kb
Host smart-d47fdcee-2831-418c-9dc6-de4bd1b4a188
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852197719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.852197719
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.858668703
Short name T1046
Test name
Test status
Simulation time 34305902 ps
CPU time 2.04 seconds
Started Aug 02 05:56:30 PM PDT 24
Finished Aug 02 05:56:32 PM PDT 24
Peak memory 206216 kb
Host smart-dbcebc4b-abcd-48d8-a694-b5c884f92aba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858668703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.858668703
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.4042772107
Short name T1021
Test name
Test status
Simulation time 378335070 ps
CPU time 2.02 seconds
Started Aug 02 05:56:23 PM PDT 24
Finished Aug 02 05:56:25 PM PDT 24
Peak memory 214624 kb
Host smart-d6e1ca1e-8985-4f56-91d9-2ab621a43c8e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042772107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.4042772107
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3326062827
Short name T119
Test name
Test status
Simulation time 514741475 ps
CPU time 8.01 seconds
Started Aug 02 05:56:25 PM PDT 24
Finished Aug 02 05:56:33 PM PDT 24
Peak memory 214636 kb
Host smart-4e0edecc-8aad-4f56-96fd-5564dc189796
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326062827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.3326062827
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3159420917
Short name T1032
Test name
Test status
Simulation time 44822281 ps
CPU time 1.83 seconds
Started Aug 02 05:56:30 PM PDT 24
Finished Aug 02 05:56:32 PM PDT 24
Peak memory 214432 kb
Host smart-c5167c72-4b13-4b31-9845-e2077792947e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159420917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3159420917
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.632290849
Short name T157
Test name
Test status
Simulation time 340746552 ps
CPU time 5.38 seconds
Started Aug 02 05:56:27 PM PDT 24
Finished Aug 02 05:56:32 PM PDT 24
Peak memory 214392 kb
Host smart-5bb03b3d-21f5-4bb4-bee1-3befd73e5bc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632290849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
632290849
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.860056296
Short name T941
Test name
Test status
Simulation time 62916979 ps
CPU time 2.64 seconds
Started Aug 02 05:56:24 PM PDT 24
Finished Aug 02 05:56:26 PM PDT 24
Peak memory 214356 kb
Host smart-0f92a6cd-f6b4-40c8-9246-8c63db38e65b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860056296 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.860056296
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1513102222
Short name T1025
Test name
Test status
Simulation time 116895433 ps
CPU time 1.34 seconds
Started Aug 02 05:56:27 PM PDT 24
Finished Aug 02 05:56:28 PM PDT 24
Peak memory 206168 kb
Host smart-a6c8bfee-c68b-4543-98cf-7cc8c32ccc1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513102222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1513102222
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.269812149
Short name T1012
Test name
Test status
Simulation time 12391950 ps
CPU time 0.72 seconds
Started Aug 02 05:56:24 PM PDT 24
Finished Aug 02 05:56:24 PM PDT 24
Peak memory 206012 kb
Host smart-044594a9-2d3a-4a4b-a1ac-4d1b70f5f49c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269812149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.269812149
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3500962009
Short name T962
Test name
Test status
Simulation time 25581993 ps
CPU time 1.41 seconds
Started Aug 02 05:56:24 PM PDT 24
Finished Aug 02 05:56:26 PM PDT 24
Peak memory 206220 kb
Host smart-d5f609c5-010e-43cb-803d-d87ecc571012
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500962009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3500962009
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1425059287
Short name T111
Test name
Test status
Simulation time 86535701 ps
CPU time 1.75 seconds
Started Aug 02 05:56:27 PM PDT 24
Finished Aug 02 05:56:29 PM PDT 24
Peak memory 214688 kb
Host smart-cf597ffd-41a3-4342-a600-c0b9473af9ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425059287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1425059287
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.915898820
Short name T1023
Test name
Test status
Simulation time 493681854 ps
CPU time 7.23 seconds
Started Aug 02 05:56:30 PM PDT 24
Finished Aug 02 05:56:37 PM PDT 24
Peak memory 220728 kb
Host smart-76204bb5-2610-4a3a-8f29-0e2d3d9fa2c4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915898820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.915898820
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2602766601
Short name T997
Test name
Test status
Simulation time 130608535 ps
CPU time 2.09 seconds
Started Aug 02 05:56:26 PM PDT 24
Finished Aug 02 05:56:28 PM PDT 24
Peak memory 214528 kb
Host smart-a7814976-286f-4aea-8d44-251521cd5554
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602766601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2602766601
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2088023159
Short name T162
Test name
Test status
Simulation time 1508644624 ps
CPU time 5.85 seconds
Started Aug 02 05:56:30 PM PDT 24
Finished Aug 02 05:56:36 PM PDT 24
Peak memory 215340 kb
Host smart-d0229399-6d2b-4c84-a81d-3cc41d4c08bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088023159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2088023159
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1543504164
Short name T1003
Test name
Test status
Simulation time 160722323 ps
CPU time 2.04 seconds
Started Aug 02 05:56:31 PM PDT 24
Finished Aug 02 05:56:34 PM PDT 24
Peak memory 214456 kb
Host smart-2040919e-d305-4254-8f3c-4dfb3af1797a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543504164 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.1543504164
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3113696698
Short name T1009
Test name
Test status
Simulation time 53530023 ps
CPU time 1.01 seconds
Started Aug 02 05:56:27 PM PDT 24
Finished Aug 02 05:56:29 PM PDT 24
Peak memory 206188 kb
Host smart-d202000a-472d-4a73-b5f4-83816c632fba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113696698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3113696698
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2558013801
Short name T919
Test name
Test status
Simulation time 51539563 ps
CPU time 0.78 seconds
Started Aug 02 05:56:27 PM PDT 24
Finished Aug 02 05:56:27 PM PDT 24
Peak memory 205944 kb
Host smart-4b8dc7c7-9e87-433b-b199-3de002d1302d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558013801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2558013801
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.4155362238
Short name T139
Test name
Test status
Simulation time 67588322 ps
CPU time 1.67 seconds
Started Aug 02 05:56:31 PM PDT 24
Finished Aug 02 05:56:33 PM PDT 24
Peak memory 206120 kb
Host smart-9520e864-3a25-4103-be8f-82bc04449722
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155362238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.4155362238
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3140737909
Short name T978
Test name
Test status
Simulation time 80236536 ps
CPU time 2.58 seconds
Started Aug 02 05:56:30 PM PDT 24
Finished Aug 02 05:56:33 PM PDT 24
Peak memory 214676 kb
Host smart-82b3deff-611a-4a97-b93b-f03565f7aada
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140737909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3140737909
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1634635167
Short name T937
Test name
Test status
Simulation time 69053340 ps
CPU time 3.3 seconds
Started Aug 02 05:56:27 PM PDT 24
Finished Aug 02 05:56:30 PM PDT 24
Peak memory 214744 kb
Host smart-9fdc8a9b-d8bd-48a0-98e4-281b242a53b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634635167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.1634635167
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2112366409
Short name T990
Test name
Test status
Simulation time 470820492 ps
CPU time 2.84 seconds
Started Aug 02 05:56:24 PM PDT 24
Finished Aug 02 05:56:27 PM PDT 24
Peak memory 214532 kb
Host smart-ae97336f-e456-4a7c-b2b0-b7f387dfe16c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112366409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2112366409
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1040913243
Short name T169
Test name
Test status
Simulation time 177200784 ps
CPU time 3.23 seconds
Started Aug 02 05:56:25 PM PDT 24
Finished Aug 02 05:56:29 PM PDT 24
Peak memory 214408 kb
Host smart-00e4f7c4-cdd6-4faa-be53-df5f5e24e3b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040913243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1040913243
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3677421055
Short name T916
Test name
Test status
Simulation time 196191387 ps
CPU time 1.41 seconds
Started Aug 02 05:56:32 PM PDT 24
Finished Aug 02 05:56:34 PM PDT 24
Peak memory 214424 kb
Host smart-e9e8f64f-12ae-4336-9322-19d46a33b5f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677421055 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3677421055
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2221984584
Short name T948
Test name
Test status
Simulation time 53106399 ps
CPU time 1.24 seconds
Started Aug 02 05:56:33 PM PDT 24
Finished Aug 02 05:56:35 PM PDT 24
Peak memory 206280 kb
Host smart-54efa580-b7de-4386-b999-3e77aa1da7c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221984584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2221984584
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3938220917
Short name T1064
Test name
Test status
Simulation time 9793752 ps
CPU time 0.89 seconds
Started Aug 02 05:56:35 PM PDT 24
Finished Aug 02 05:56:36 PM PDT 24
Peak memory 205956 kb
Host smart-93a6293e-c2c4-4771-ae91-b8a4f52c3ec9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938220917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3938220917
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3930819375
Short name T973
Test name
Test status
Simulation time 382230295 ps
CPU time 1.55 seconds
Started Aug 02 05:56:34 PM PDT 24
Finished Aug 02 05:56:36 PM PDT 24
Peak memory 206172 kb
Host smart-cb907bb9-2d2e-458b-9388-fc1b8b99fac0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930819375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3930819375
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.317767256
Short name T951
Test name
Test status
Simulation time 309911506 ps
CPU time 2.54 seconds
Started Aug 02 05:56:34 PM PDT 24
Finished Aug 02 05:56:37 PM PDT 24
Peak memory 214664 kb
Host smart-a6a5a3c2-fbf7-4add-8288-bf1041e3dadd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317767256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow
_reg_errors.317767256
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.59749301
Short name T1075
Test name
Test status
Simulation time 462800106 ps
CPU time 9.28 seconds
Started Aug 02 05:56:37 PM PDT 24
Finished Aug 02 05:56:46 PM PDT 24
Peak memory 220820 kb
Host smart-e00550f8-f8e0-4a73-8d32-8400c9b97056
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59749301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.ke
ymgr_shadow_reg_errors_with_csr_rw.59749301
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3761182141
Short name T994
Test name
Test status
Simulation time 54751196 ps
CPU time 2.41 seconds
Started Aug 02 05:56:32 PM PDT 24
Finished Aug 02 05:56:35 PM PDT 24
Peak memory 206216 kb
Host smart-b8e3a871-28f0-49e1-91f7-8916a0a9687f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761182141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3761182141
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.222118410
Short name T170
Test name
Test status
Simulation time 708268691 ps
CPU time 4.31 seconds
Started Aug 02 05:56:50 PM PDT 24
Finished Aug 02 05:56:54 PM PDT 24
Peak memory 215340 kb
Host smart-0d3ba174-1784-4f8f-b650-5b5a98dc3dfb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222118410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
222118410
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.4189475012
Short name T946
Test name
Test status
Simulation time 21304485 ps
CPU time 1.6 seconds
Started Aug 02 05:56:50 PM PDT 24
Finished Aug 02 05:56:52 PM PDT 24
Peak memory 214092 kb
Host smart-72fae371-f237-4441-ba10-2444aa1303c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189475012 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.4189475012
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1181176742
Short name T938
Test name
Test status
Simulation time 17643029 ps
CPU time 0.99 seconds
Started Aug 02 05:56:32 PM PDT 24
Finished Aug 02 05:56:33 PM PDT 24
Peak memory 205976 kb
Host smart-29de47d6-1969-4954-bc04-62cdcb48a85d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181176742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1181176742
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3921794337
Short name T934
Test name
Test status
Simulation time 18921036 ps
CPU time 0.69 seconds
Started Aug 02 05:56:32 PM PDT 24
Finished Aug 02 05:56:33 PM PDT 24
Peak memory 205988 kb
Host smart-55aabd4f-d076-4782-ab69-f5f3abd1c0bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921794337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3921794337
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1861788220
Short name T1006
Test name
Test status
Simulation time 140463320 ps
CPU time 2.32 seconds
Started Aug 02 05:56:31 PM PDT 24
Finished Aug 02 05:56:33 PM PDT 24
Peak memory 206240 kb
Host smart-fe70399e-3f8d-40ef-aa39-5b0b4fe47749
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861788220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1861788220
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.722455232
Short name T982
Test name
Test status
Simulation time 77340414 ps
CPU time 2.5 seconds
Started Aug 02 05:56:33 PM PDT 24
Finished Aug 02 05:56:36 PM PDT 24
Peak memory 214656 kb
Host smart-eb40e84c-44b4-4271-a40b-830a79b36575
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722455232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.722455232
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1659839148
Short name T955
Test name
Test status
Simulation time 757564133 ps
CPU time 4.91 seconds
Started Aug 02 05:56:30 PM PDT 24
Finished Aug 02 05:56:35 PM PDT 24
Peak memory 214704 kb
Host smart-deb2a27f-1a58-4c75-b79f-c442655c8198
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659839148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1659839148
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3766509021
Short name T995
Test name
Test status
Simulation time 436513476 ps
CPU time 2.92 seconds
Started Aug 02 05:56:33 PM PDT 24
Finished Aug 02 05:56:36 PM PDT 24
Peak memory 214364 kb
Host smart-6fa4abd1-b21f-4d7d-bde7-000a8e0b1608
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766509021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3766509021
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1681855054
Short name T166
Test name
Test status
Simulation time 237989928 ps
CPU time 9.19 seconds
Started Aug 02 05:56:50 PM PDT 24
Finished Aug 02 05:56:59 PM PDT 24
Peak memory 214368 kb
Host smart-1c4272b7-eaf7-486f-9d5a-beead45b3db6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681855054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1681855054
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3873651406
Short name T709
Test name
Test status
Simulation time 17043659 ps
CPU time 0.91 seconds
Started Aug 02 05:11:56 PM PDT 24
Finished Aug 02 05:11:57 PM PDT 24
Peak memory 206052 kb
Host smart-19167248-3bd3-473c-8a75-b65e160ce512
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873651406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3873651406
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2680086824
Short name T422
Test name
Test status
Simulation time 271414483 ps
CPU time 13.92 seconds
Started Aug 02 05:11:56 PM PDT 24
Finished Aug 02 05:12:10 PM PDT 24
Peak memory 214708 kb
Host smart-2bfb4c30-d62b-474d-9705-5f956555a038
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2680086824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2680086824
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.4048371289
Short name T592
Test name
Test status
Simulation time 239814940 ps
CPU time 6.18 seconds
Started Aug 02 05:12:09 PM PDT 24
Finished Aug 02 05:12:15 PM PDT 24
Peak memory 222524 kb
Host smart-81d82f09-793b-422d-8cb5-7c2cd9873ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048371289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.4048371289
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2444408538
Short name T75
Test name
Test status
Simulation time 30163025 ps
CPU time 1.85 seconds
Started Aug 02 05:12:02 PM PDT 24
Finished Aug 02 05:12:04 PM PDT 24
Peak memory 207220 kb
Host smart-145d4b95-b109-4422-ba68-972e46e99227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444408538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2444408538
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2181168528
Short name T394
Test name
Test status
Simulation time 156775568 ps
CPU time 3.8 seconds
Started Aug 02 05:12:00 PM PDT 24
Finished Aug 02 05:12:04 PM PDT 24
Peak memory 214416 kb
Host smart-7d44b9b8-238d-412e-9def-c82c186eb129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181168528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2181168528
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_random.4097712812
Short name T657
Test name
Test status
Simulation time 102302166 ps
CPU time 4.71 seconds
Started Aug 02 05:12:04 PM PDT 24
Finished Aug 02 05:12:09 PM PDT 24
Peak memory 214360 kb
Host smart-065644a6-315d-4896-bc2f-cd12848d83bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097712812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.4097712812
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2329355881
Short name T843
Test name
Test status
Simulation time 167202078 ps
CPU time 3.82 seconds
Started Aug 02 05:11:58 PM PDT 24
Finished Aug 02 05:12:01 PM PDT 24
Peak memory 206696 kb
Host smart-1adcb367-1517-4e74-aad7-c218548b9836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329355881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2329355881
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.468485258
Short name T613
Test name
Test status
Simulation time 59300959 ps
CPU time 3.13 seconds
Started Aug 02 05:12:06 PM PDT 24
Finished Aug 02 05:12:09 PM PDT 24
Peak memory 208652 kb
Host smart-4b76f399-8c6d-4a10-a56c-8ab7a8206fb2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468485258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.468485258
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.653553234
Short name T322
Test name
Test status
Simulation time 516044525 ps
CPU time 3.47 seconds
Started Aug 02 05:11:45 PM PDT 24
Finished Aug 02 05:11:48 PM PDT 24
Peak memory 207072 kb
Host smart-ddec2166-8986-48c6-9186-1247ac79c232
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653553234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.653553234
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2437966257
Short name T355
Test name
Test status
Simulation time 434097070 ps
CPU time 4.94 seconds
Started Aug 02 05:12:07 PM PDT 24
Finished Aug 02 05:12:12 PM PDT 24
Peak memory 210088 kb
Host smart-4b8dd0ca-bbf7-4ce3-81e2-24e42da88ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437966257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2437966257
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1636348100
Short name T460
Test name
Test status
Simulation time 88780554 ps
CPU time 2.24 seconds
Started Aug 02 05:12:05 PM PDT 24
Finished Aug 02 05:12:08 PM PDT 24
Peak memory 208448 kb
Host smart-e84ccad7-fdcf-4e00-a91f-7d71d2ad008e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636348100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1636348100
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.3719314835
Short name T646
Test name
Test status
Simulation time 443419118 ps
CPU time 8.07 seconds
Started Aug 02 05:12:18 PM PDT 24
Finished Aug 02 05:12:26 PM PDT 24
Peak memory 220224 kb
Host smart-2f26f7c6-349a-47c1-a4f7-5f6af66d587a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719314835 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.3719314835
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1000677898
Short name T700
Test name
Test status
Simulation time 178649522 ps
CPU time 5.64 seconds
Started Aug 02 05:12:09 PM PDT 24
Finished Aug 02 05:12:15 PM PDT 24
Peak memory 208204 kb
Host smart-6eea5a6d-320b-4821-af93-4e37fdd6f3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000677898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1000677898
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.2728883345
Short name T760
Test name
Test status
Simulation time 67333804 ps
CPU time 2.78 seconds
Started Aug 02 05:12:00 PM PDT 24
Finished Aug 02 05:12:02 PM PDT 24
Peak memory 210220 kb
Host smart-749a80c8-1690-498d-9844-808573c04016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728883345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2728883345
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3538932593
Short name T295
Test name
Test status
Simulation time 208366601 ps
CPU time 6.36 seconds
Started Aug 02 05:12:08 PM PDT 24
Finished Aug 02 05:12:14 PM PDT 24
Peak memory 214808 kb
Host smart-34363842-b5dd-4dc2-b9ae-545ae769f1e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3538932593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3538932593
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2228758379
Short name T65
Test name
Test status
Simulation time 247668980 ps
CPU time 3.95 seconds
Started Aug 02 05:12:14 PM PDT 24
Finished Aug 02 05:12:19 PM PDT 24
Peak memory 221448 kb
Host smart-d3167b8b-8d28-45fc-a925-541d56295caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228758379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2228758379
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1382807162
Short name T66
Test name
Test status
Simulation time 275679831 ps
CPU time 2.64 seconds
Started Aug 02 05:11:57 PM PDT 24
Finished Aug 02 05:11:59 PM PDT 24
Peak memory 208088 kb
Host smart-e73d36b6-d241-4e57-a109-39749fd600f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382807162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1382807162
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3199873545
Short name T95
Test name
Test status
Simulation time 78702503 ps
CPU time 4 seconds
Started Aug 02 05:12:07 PM PDT 24
Finished Aug 02 05:12:11 PM PDT 24
Peak memory 209660 kb
Host smart-f50bef3e-3afc-47ba-adfd-2ab5b835e5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199873545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3199873545
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3439642954
Short name T308
Test name
Test status
Simulation time 51692162 ps
CPU time 2.01 seconds
Started Aug 02 05:12:20 PM PDT 24
Finished Aug 02 05:12:22 PM PDT 24
Peak memory 214332 kb
Host smart-cca09998-9d2e-4081-9691-3c9fb4f59ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439642954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3439642954
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2273884174
Short name T232
Test name
Test status
Simulation time 222741282 ps
CPU time 2.86 seconds
Started Aug 02 05:11:56 PM PDT 24
Finished Aug 02 05:11:59 PM PDT 24
Peak memory 207768 kb
Host smart-27ed380e-8754-4c0f-8b3e-f98e0d1f2367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273884174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2273884174
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1789023934
Short name T616
Test name
Test status
Simulation time 144977468 ps
CPU time 3.88 seconds
Started Aug 02 05:11:58 PM PDT 24
Finished Aug 02 05:12:02 PM PDT 24
Peak memory 208292 kb
Host smart-3de73c91-c7aa-43be-a39f-68353fcd4492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789023934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1789023934
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.776451721
Short name T633
Test name
Test status
Simulation time 628509453 ps
CPU time 7.16 seconds
Started Aug 02 05:12:04 PM PDT 24
Finished Aug 02 05:12:11 PM PDT 24
Peak memory 208688 kb
Host smart-679beaef-0724-459f-8212-46bdda34c732
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776451721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.776451721
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.620186530
Short name T728
Test name
Test status
Simulation time 48885100 ps
CPU time 2.78 seconds
Started Aug 02 05:11:58 PM PDT 24
Finished Aug 02 05:12:01 PM PDT 24
Peak memory 206892 kb
Host smart-50c4bf65-828f-4007-878a-e036fc6b97d9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620186530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.620186530
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2955103677
Short name T855
Test name
Test status
Simulation time 192236734 ps
CPU time 3.86 seconds
Started Aug 02 05:12:10 PM PDT 24
Finished Aug 02 05:12:14 PM PDT 24
Peak memory 208756 kb
Host smart-8f9f3758-c97e-4efc-be48-cfe2dbe8ad5c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955103677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2955103677
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1147062692
Short name T752
Test name
Test status
Simulation time 162293230 ps
CPU time 2.55 seconds
Started Aug 02 05:12:08 PM PDT 24
Finished Aug 02 05:12:10 PM PDT 24
Peak memory 209192 kb
Host smart-bae94e93-b0d4-464b-966a-b567e4b8c18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147062692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1147062692
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1558450474
Short name T816
Test name
Test status
Simulation time 119252957 ps
CPU time 2.98 seconds
Started Aug 02 05:12:02 PM PDT 24
Finished Aug 02 05:12:05 PM PDT 24
Peak memory 208336 kb
Host smart-3653d223-8507-4d20-ab62-04f7bf535e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558450474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1558450474
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3032803346
Short name T476
Test name
Test status
Simulation time 1238538116 ps
CPU time 9.35 seconds
Started Aug 02 05:11:44 PM PDT 24
Finished Aug 02 05:11:54 PM PDT 24
Peak memory 214348 kb
Host smart-43512dec-854c-4e39-92e6-b6c1b1b3cbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032803346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3032803346
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2560677869
Short name T742
Test name
Test status
Simulation time 28986122 ps
CPU time 0.8 seconds
Started Aug 02 05:12:24 PM PDT 24
Finished Aug 02 05:12:24 PM PDT 24
Peak memory 205948 kb
Host smart-606ef704-6cb3-4092-9fc9-789986501771
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560677869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2560677869
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1826835917
Short name T431
Test name
Test status
Simulation time 101032778 ps
CPU time 4.11 seconds
Started Aug 02 05:12:22 PM PDT 24
Finished Aug 02 05:12:26 PM PDT 24
Peak memory 215108 kb
Host smart-523f8a53-988e-4172-ac18-9cf745f4ff6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1826835917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1826835917
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2338284622
Short name T540
Test name
Test status
Simulation time 118535299 ps
CPU time 4.36 seconds
Started Aug 02 05:12:25 PM PDT 24
Finished Aug 02 05:12:34 PM PDT 24
Peak memory 210096 kb
Host smart-1a740882-3989-496a-8924-3b6e72b52884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338284622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2338284622
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3394020298
Short name T568
Test name
Test status
Simulation time 84239494 ps
CPU time 3.86 seconds
Started Aug 02 05:12:23 PM PDT 24
Finished Aug 02 05:12:27 PM PDT 24
Peak memory 209916 kb
Host smart-19eacd99-bdb5-4269-ac4d-9086c4b00008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394020298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3394020298
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.796222636
Short name T283
Test name
Test status
Simulation time 84931247 ps
CPU time 1.89 seconds
Started Aug 02 05:12:23 PM PDT 24
Finished Aug 02 05:12:25 PM PDT 24
Peak memory 214304 kb
Host smart-eb34be64-526d-42d8-afc0-7e8cab4a9ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796222636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.796222636
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3269600207
Short name T674
Test name
Test status
Simulation time 135117136 ps
CPU time 2.07 seconds
Started Aug 02 05:12:27 PM PDT 24
Finished Aug 02 05:12:29 PM PDT 24
Peak memory 222384 kb
Host smart-7f083632-1a84-4a1a-bcc4-b22266603055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269600207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3269600207
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2331343211
Short name T42
Test name
Test status
Simulation time 278415875 ps
CPU time 4.34 seconds
Started Aug 02 05:12:19 PM PDT 24
Finished Aug 02 05:12:23 PM PDT 24
Peak memory 219952 kb
Host smart-71849414-cd31-43e9-af7c-725c41c5586a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331343211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2331343211
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3745270266
Short name T107
Test name
Test status
Simulation time 554815714 ps
CPU time 6.2 seconds
Started Aug 02 05:12:19 PM PDT 24
Finished Aug 02 05:12:25 PM PDT 24
Peak memory 209848 kb
Host smart-1c21a69b-f3e7-4c8e-889e-7780b0f67e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745270266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3745270266
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1802248678
Short name T188
Test name
Test status
Simulation time 31174927 ps
CPU time 1.9 seconds
Started Aug 02 05:12:24 PM PDT 24
Finished Aug 02 05:12:26 PM PDT 24
Peak memory 208212 kb
Host smart-0d5b2ea7-c1bb-478c-b3f0-00083b2d8a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802248678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1802248678
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2495935124
Short name T637
Test name
Test status
Simulation time 91792808 ps
CPU time 3.13 seconds
Started Aug 02 05:12:31 PM PDT 24
Finished Aug 02 05:12:34 PM PDT 24
Peak memory 206824 kb
Host smart-2adf8bd0-eb61-4d1c-8bbe-9a9033abe3e2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495935124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2495935124
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.4098205822
Short name T683
Test name
Test status
Simulation time 84751723 ps
CPU time 2.32 seconds
Started Aug 02 05:12:25 PM PDT 24
Finished Aug 02 05:12:27 PM PDT 24
Peak memory 207028 kb
Host smart-44f37b68-0778-4012-9a1b-d45263dae5dd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098205822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.4098205822
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2077342322
Short name T535
Test name
Test status
Simulation time 635161296 ps
CPU time 2.85 seconds
Started Aug 02 05:12:26 PM PDT 24
Finished Aug 02 05:12:29 PM PDT 24
Peak memory 207140 kb
Host smart-e3419afe-a119-4408-8b76-a90e622b8568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077342322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2077342322
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2398695698
Short name T903
Test name
Test status
Simulation time 528954372 ps
CPU time 2.74 seconds
Started Aug 02 05:12:27 PM PDT 24
Finished Aug 02 05:12:30 PM PDT 24
Peak memory 208396 kb
Host smart-8bb0d5c8-72d0-4fcb-9c36-c224a0ceecc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398695698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2398695698
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.4168478239
Short name T617
Test name
Test status
Simulation time 136563300 ps
CPU time 8.5 seconds
Started Aug 02 05:12:26 PM PDT 24
Finished Aug 02 05:12:35 PM PDT 24
Peak memory 221940 kb
Host smart-d8556cb5-fa81-470d-8c75-8c66e9a79fb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168478239 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.4168478239
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1741107138
Short name T587
Test name
Test status
Simulation time 43992538 ps
CPU time 2.98 seconds
Started Aug 02 05:12:24 PM PDT 24
Finished Aug 02 05:12:27 PM PDT 24
Peak memory 207508 kb
Host smart-2fcc6431-9727-4580-afba-a57141bcbc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741107138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1741107138
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2173669358
Short name T531
Test name
Test status
Simulation time 24607711 ps
CPU time 0.78 seconds
Started Aug 02 05:12:37 PM PDT 24
Finished Aug 02 05:12:38 PM PDT 24
Peak memory 205820 kb
Host smart-efa5780c-83b7-46af-9a56-bd4c92668d86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173669358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2173669358
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3213557185
Short name T380
Test name
Test status
Simulation time 310867132 ps
CPU time 3.06 seconds
Started Aug 02 05:12:24 PM PDT 24
Finished Aug 02 05:12:33 PM PDT 24
Peak memory 214276 kb
Host smart-a8d0da0c-1c79-4435-9bed-0e29a9560003
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3213557185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3213557185
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3614716003
Short name T622
Test name
Test status
Simulation time 1784901297 ps
CPU time 20.75 seconds
Started Aug 02 05:12:21 PM PDT 24
Finished Aug 02 05:12:42 PM PDT 24
Peak memory 220396 kb
Host smart-f695693c-dbb5-41ce-8f49-6fda103d494c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614716003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3614716003
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.4133302552
Short name T392
Test name
Test status
Simulation time 54912282 ps
CPU time 2.91 seconds
Started Aug 02 05:12:11 PM PDT 24
Finished Aug 02 05:12:15 PM PDT 24
Peak memory 209212 kb
Host smart-b93ad5d3-6e7e-48d0-8c9c-87ff53a6a10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133302552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.4133302552
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1443905546
Short name T34
Test name
Test status
Simulation time 69914913 ps
CPU time 2.61 seconds
Started Aug 02 05:12:34 PM PDT 24
Finished Aug 02 05:12:37 PM PDT 24
Peak memory 214384 kb
Host smart-0a2498bd-48c6-427d-836c-efae0d854c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443905546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1443905546
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3564841189
Short name T284
Test name
Test status
Simulation time 98924603 ps
CPU time 4.21 seconds
Started Aug 02 05:12:34 PM PDT 24
Finished Aug 02 05:12:39 PM PDT 24
Peak memory 214284 kb
Host smart-b098f7b6-30c0-48c4-b421-4e81c246fd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564841189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3564841189
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2847244334
Short name T868
Test name
Test status
Simulation time 317861137 ps
CPU time 3.67 seconds
Started Aug 02 05:12:21 PM PDT 24
Finished Aug 02 05:12:25 PM PDT 24
Peak memory 208008 kb
Host smart-c968ca92-0d88-4c6b-a958-1f9270322011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847244334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2847244334
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.563971767
Short name T643
Test name
Test status
Simulation time 480668619 ps
CPU time 4.39 seconds
Started Aug 02 05:12:25 PM PDT 24
Finished Aug 02 05:12:29 PM PDT 24
Peak memory 208728 kb
Host smart-b2e2e68b-5579-4503-bb91-fd928672c02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563971767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.563971767
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.788882699
Short name T371
Test name
Test status
Simulation time 814596411 ps
CPU time 22.05 seconds
Started Aug 02 05:12:30 PM PDT 24
Finished Aug 02 05:12:53 PM PDT 24
Peak memory 208136 kb
Host smart-94b19fea-35a0-49d7-973d-e0aa70ab6012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788882699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.788882699
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2300058962
Short name T706
Test name
Test status
Simulation time 101404648 ps
CPU time 2.54 seconds
Started Aug 02 05:12:24 PM PDT 24
Finished Aug 02 05:12:27 PM PDT 24
Peak memory 207020 kb
Host smart-1d36b776-fecd-4e74-afd6-a9ad307fff16
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300058962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2300058962
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3471194640
Short name T900
Test name
Test status
Simulation time 42611120 ps
CPU time 1.75 seconds
Started Aug 02 05:12:23 PM PDT 24
Finished Aug 02 05:12:25 PM PDT 24
Peak memory 206924 kb
Host smart-4828999f-a163-48e4-bead-1f741a29201b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471194640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3471194640
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3367391062
Short name T628
Test name
Test status
Simulation time 251733316 ps
CPU time 2.96 seconds
Started Aug 02 05:12:28 PM PDT 24
Finished Aug 02 05:12:31 PM PDT 24
Peak memory 208596 kb
Host smart-832ee3b9-bab9-44f7-92dd-06dc0f49148c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367391062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3367391062
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3454156242
Short name T362
Test name
Test status
Simulation time 37069490 ps
CPU time 2.35 seconds
Started Aug 02 05:12:36 PM PDT 24
Finished Aug 02 05:12:39 PM PDT 24
Peak memory 214432 kb
Host smart-1a758876-a354-4a64-a004-0c3bdd448e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454156242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3454156242
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.2842297953
Short name T526
Test name
Test status
Simulation time 133087686 ps
CPU time 2.49 seconds
Started Aug 02 05:12:21 PM PDT 24
Finished Aug 02 05:12:24 PM PDT 24
Peak memory 206924 kb
Host smart-9fb0904b-1dee-4624-98c4-5b24e1ea2c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842297953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2842297953
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1495435181
Short name T621
Test name
Test status
Simulation time 403984730 ps
CPU time 3.56 seconds
Started Aug 02 05:12:25 PM PDT 24
Finished Aug 02 05:12:29 PM PDT 24
Peak memory 207648 kb
Host smart-83a56fdd-19c7-44e7-b4a4-83882c8dd06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495435181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1495435181
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3035720211
Short name T457
Test name
Test status
Simulation time 251080965 ps
CPU time 2.34 seconds
Started Aug 02 05:12:38 PM PDT 24
Finished Aug 02 05:12:41 PM PDT 24
Peak memory 209768 kb
Host smart-c001498e-0d8b-4c82-a79c-a66350b969d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035720211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3035720211
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.687709501
Short name T451
Test name
Test status
Simulation time 13272122 ps
CPU time 0.79 seconds
Started Aug 02 05:12:32 PM PDT 24
Finished Aug 02 05:12:33 PM PDT 24
Peak memory 205884 kb
Host smart-acf438ab-5a83-4a60-b9b8-728fc4e30012
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687709501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.687709501
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1236155055
Short name T430
Test name
Test status
Simulation time 810491675 ps
CPU time 12.36 seconds
Started Aug 02 05:12:55 PM PDT 24
Finished Aug 02 05:13:07 PM PDT 24
Peak memory 214352 kb
Host smart-45dbd264-36ba-4daf-83b9-7b263233704c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1236155055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1236155055
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2977615533
Short name T498
Test name
Test status
Simulation time 35062766 ps
CPU time 2.13 seconds
Started Aug 02 05:12:46 PM PDT 24
Finished Aug 02 05:12:48 PM PDT 24
Peak memory 214312 kb
Host smart-ab12b96e-c1ef-4c3a-8a7a-b340a36310df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977615533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2977615533
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1071062354
Short name T327
Test name
Test status
Simulation time 78811108 ps
CPU time 2.19 seconds
Started Aug 02 05:12:33 PM PDT 24
Finished Aug 02 05:12:35 PM PDT 24
Peak memory 218176 kb
Host smart-96a58e9e-b296-4998-9f1a-753fc8aabb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071062354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1071062354
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2127643488
Short name T348
Test name
Test status
Simulation time 4612277664 ps
CPU time 74.6 seconds
Started Aug 02 05:12:35 PM PDT 24
Finished Aug 02 05:13:50 PM PDT 24
Peak memory 221784 kb
Host smart-0e6e8027-9320-4411-900c-93b46438feef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127643488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2127643488
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3431913073
Short name T839
Test name
Test status
Simulation time 40317921 ps
CPU time 2.26 seconds
Started Aug 02 05:12:41 PM PDT 24
Finished Aug 02 05:12:43 PM PDT 24
Peak memory 214196 kb
Host smart-f80bd3f0-662a-424c-841e-a8549aed5164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431913073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3431913073
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.542673457
Short name T549
Test name
Test status
Simulation time 530227319 ps
CPU time 3.85 seconds
Started Aug 02 05:12:32 PM PDT 24
Finished Aug 02 05:12:36 PM PDT 24
Peak memory 222568 kb
Host smart-170052ad-4bc5-40d5-8825-85ea9c72c60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542673457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.542673457
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.2886474212
Short name T647
Test name
Test status
Simulation time 233000985 ps
CPU time 6.64 seconds
Started Aug 02 05:12:31 PM PDT 24
Finished Aug 02 05:12:38 PM PDT 24
Peak memory 209076 kb
Host smart-7132f173-7b5d-41a9-a5ac-f370dfcd10b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886474212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2886474212
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3142686923
Short name T667
Test name
Test status
Simulation time 234733733 ps
CPU time 2.91 seconds
Started Aug 02 05:12:53 PM PDT 24
Finished Aug 02 05:12:56 PM PDT 24
Peak memory 206756 kb
Host smart-3b236eea-292c-40b4-a858-e360935ad351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142686923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3142686923
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3903106651
Short name T710
Test name
Test status
Simulation time 239431215 ps
CPU time 5.96 seconds
Started Aug 02 05:12:28 PM PDT 24
Finished Aug 02 05:12:34 PM PDT 24
Peak memory 208340 kb
Host smart-6fe6813c-e9c4-466c-b87b-7627fe619241
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903106651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3903106651
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3584603516
Short name T849
Test name
Test status
Simulation time 4041103916 ps
CPU time 24.97 seconds
Started Aug 02 05:12:42 PM PDT 24
Finished Aug 02 05:13:07 PM PDT 24
Peak memory 208548 kb
Host smart-c0a0358c-6c8a-4bb8-81dd-ac861e2373dd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584603516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3584603516
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3355913394
Short name T573
Test name
Test status
Simulation time 34872701 ps
CPU time 2.56 seconds
Started Aug 02 05:12:46 PM PDT 24
Finished Aug 02 05:12:48 PM PDT 24
Peak memory 208968 kb
Host smart-a9aea102-0624-46c9-9130-63bef250e34f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355913394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3355913394
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.305660186
Short name T736
Test name
Test status
Simulation time 73790701 ps
CPU time 1.65 seconds
Started Aug 02 05:12:37 PM PDT 24
Finished Aug 02 05:12:39 PM PDT 24
Peak memory 207848 kb
Host smart-afc1d92a-a650-4bf4-8206-2ddc4ab83a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305660186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.305660186
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1670619779
Short name T588
Test name
Test status
Simulation time 65948044 ps
CPU time 2.72 seconds
Started Aug 02 05:12:33 PM PDT 24
Finished Aug 02 05:12:35 PM PDT 24
Peak memory 206896 kb
Host smart-c37218d4-ce86-4791-83c6-3889de556df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670619779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1670619779
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.4120153056
Short name T192
Test name
Test status
Simulation time 5463513786 ps
CPU time 32.89 seconds
Started Aug 02 05:12:41 PM PDT 24
Finished Aug 02 05:13:14 PM PDT 24
Peak memory 222508 kb
Host smart-2a543029-2e5e-462a-9c62-ecee4d1bed6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120153056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.4120153056
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.2632000664
Short name T200
Test name
Test status
Simulation time 8325124343 ps
CPU time 88.79 seconds
Started Aug 02 05:12:32 PM PDT 24
Finished Aug 02 05:14:01 PM PDT 24
Peak memory 209140 kb
Host smart-c9f78ca7-c063-4801-a532-02859523b454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632000664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2632000664
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1052486569
Short name T729
Test name
Test status
Simulation time 57536585 ps
CPU time 2.49 seconds
Started Aug 02 05:12:29 PM PDT 24
Finished Aug 02 05:12:32 PM PDT 24
Peak memory 210116 kb
Host smart-7bdef558-8fe4-4499-a8c7-9fe7106f7671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052486569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1052486569
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1397505805
Short name T812
Test name
Test status
Simulation time 42273300 ps
CPU time 0.82 seconds
Started Aug 02 05:12:48 PM PDT 24
Finished Aug 02 05:12:49 PM PDT 24
Peak memory 206020 kb
Host smart-8ca7101e-260b-48e5-a7e9-ab266c52dfc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397505805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1397505805
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3697107620
Short name T132
Test name
Test status
Simulation time 1429825886 ps
CPU time 5.68 seconds
Started Aug 02 05:12:37 PM PDT 24
Finished Aug 02 05:12:43 PM PDT 24
Peak memory 222532 kb
Host smart-7ad3a149-4714-4014-89fa-364eae5ae14b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3697107620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3697107620
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1945312778
Short name T439
Test name
Test status
Simulation time 425338796 ps
CPU time 3.62 seconds
Started Aug 02 05:12:49 PM PDT 24
Finished Aug 02 05:12:53 PM PDT 24
Peak memory 209264 kb
Host smart-97d052f3-397b-46df-828e-3aaefea811b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945312778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1945312778
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.4264062750
Short name T396
Test name
Test status
Simulation time 39208132 ps
CPU time 2.04 seconds
Started Aug 02 05:12:31 PM PDT 24
Finished Aug 02 05:12:34 PM PDT 24
Peak memory 214336 kb
Host smart-efb70124-bb18-43f2-8624-e6ef90b64887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264062750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.4264062750
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.3951968465
Short name T610
Test name
Test status
Simulation time 419639658 ps
CPU time 4.18 seconds
Started Aug 02 05:12:44 PM PDT 24
Finished Aug 02 05:12:48 PM PDT 24
Peak memory 220096 kb
Host smart-cc0f4dae-dca0-445a-aab6-04b16e39315b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951968465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3951968465
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3331628726
Short name T425
Test name
Test status
Simulation time 179932868 ps
CPU time 7.18 seconds
Started Aug 02 05:12:54 PM PDT 24
Finished Aug 02 05:13:01 PM PDT 24
Peak memory 222428 kb
Host smart-97388f7f-2e9b-4eca-91fa-1ec9f1f0c726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331628726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3331628726
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.772747160
Short name T807
Test name
Test status
Simulation time 101867589 ps
CPU time 4.11 seconds
Started Aug 02 05:12:48 PM PDT 24
Finished Aug 02 05:12:52 PM PDT 24
Peak memory 208540 kb
Host smart-b043292d-6571-4e5e-bff9-6aadc0f7c517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772747160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.772747160
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2535103094
Short name T108
Test name
Test status
Simulation time 103851577 ps
CPU time 3.48 seconds
Started Aug 02 05:12:36 PM PDT 24
Finished Aug 02 05:12:39 PM PDT 24
Peak memory 208696 kb
Host smart-65b9a478-ad7d-451b-8de9-b0f9306065e2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535103094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2535103094
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2002643859
Short name T841
Test name
Test status
Simulation time 390520903 ps
CPU time 2.82 seconds
Started Aug 02 05:12:30 PM PDT 24
Finished Aug 02 05:12:33 PM PDT 24
Peak memory 206840 kb
Host smart-da1caee6-1427-4417-930d-53eb7659e069
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002643859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2002643859
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1425120548
Short name T335
Test name
Test status
Simulation time 124642957 ps
CPU time 3.09 seconds
Started Aug 02 05:12:29 PM PDT 24
Finished Aug 02 05:12:33 PM PDT 24
Peak memory 208572 kb
Host smart-c612b5b6-9433-4b76-833f-871a314c2724
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425120548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1425120548
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.914516184
Short name T204
Test name
Test status
Simulation time 59780369 ps
CPU time 2.43 seconds
Started Aug 02 05:12:32 PM PDT 24
Finished Aug 02 05:12:34 PM PDT 24
Peak memory 207120 kb
Host smart-9cf9bbcb-cbb8-4104-948b-42cd463a8dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914516184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.914516184
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2745685396
Short name T482
Test name
Test status
Simulation time 574809246 ps
CPU time 3.54 seconds
Started Aug 02 05:12:44 PM PDT 24
Finished Aug 02 05:12:48 PM PDT 24
Peak memory 208560 kb
Host smart-83863fa1-2b8e-4bff-9bec-36bebdfddec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745685396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2745685396
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2531069181
Short name T104
Test name
Test status
Simulation time 184972531 ps
CPU time 1.78 seconds
Started Aug 02 05:12:30 PM PDT 24
Finished Aug 02 05:12:32 PM PDT 24
Peak memory 209808 kb
Host smart-ad783b70-088d-48c5-9896-242a451630f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531069181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2531069181
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.4166236320
Short name T771
Test name
Test status
Simulation time 69442266 ps
CPU time 0.83 seconds
Started Aug 02 05:12:28 PM PDT 24
Finished Aug 02 05:12:29 PM PDT 24
Peak memory 205916 kb
Host smart-86d5c3c7-c225-4ecc-bc7c-37a76837deee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166236320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.4166236320
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3011481183
Short name T766
Test name
Test status
Simulation time 57328010 ps
CPU time 2.48 seconds
Started Aug 02 05:12:29 PM PDT 24
Finished Aug 02 05:12:32 PM PDT 24
Peak memory 216984 kb
Host smart-7ee209c2-c187-478d-bb55-492eadab274a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011481183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3011481183
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1068541765
Short name T538
Test name
Test status
Simulation time 74078017 ps
CPU time 2.03 seconds
Started Aug 02 05:12:30 PM PDT 24
Finished Aug 02 05:12:42 PM PDT 24
Peak memory 214432 kb
Host smart-eb3c7866-3c67-4e22-9406-33c31d8095b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068541765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1068541765
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.4060279734
Short name T630
Test name
Test status
Simulation time 194041768 ps
CPU time 2.07 seconds
Started Aug 02 05:12:27 PM PDT 24
Finished Aug 02 05:12:29 PM PDT 24
Peak memory 214316 kb
Host smart-649bee87-9efa-401f-a9e2-e3bdd7209d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060279734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.4060279734
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2278840674
Short name T269
Test name
Test status
Simulation time 59508656 ps
CPU time 2.26 seconds
Started Aug 02 05:12:46 PM PDT 24
Finished Aug 02 05:12:49 PM PDT 24
Peak memory 214376 kb
Host smart-754f99e1-701e-45d3-9f38-beb1543ff662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278840674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2278840674
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2957389921
Short name T507
Test name
Test status
Simulation time 382546712 ps
CPU time 2.35 seconds
Started Aug 02 05:12:36 PM PDT 24
Finished Aug 02 05:12:38 PM PDT 24
Peak memory 220340 kb
Host smart-a71ae3eb-d6ab-4641-9268-edbd1a48daf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957389921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2957389921
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.4225608998
Short name T4
Test name
Test status
Simulation time 2715104541 ps
CPU time 6.2 seconds
Started Aug 02 05:12:33 PM PDT 24
Finished Aug 02 05:12:40 PM PDT 24
Peak memory 214404 kb
Host smart-e33732c0-4b23-46b9-8bc2-06f08b0888da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225608998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.4225608998
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.195341470
Short name T278
Test name
Test status
Simulation time 139391300 ps
CPU time 2.28 seconds
Started Aug 02 05:12:41 PM PDT 24
Finished Aug 02 05:12:43 PM PDT 24
Peak memory 207036 kb
Host smart-84d37304-12fa-4377-a1f3-8ddfa5c47b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195341470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.195341470
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3395495198
Short name T690
Test name
Test status
Simulation time 676894630 ps
CPU time 5.96 seconds
Started Aug 02 05:12:30 PM PDT 24
Finished Aug 02 05:12:36 PM PDT 24
Peak memory 208824 kb
Host smart-3fc161a9-2c33-45fe-8e02-aa66e263cfc6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395495198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3395495198
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2680708844
Short name T80
Test name
Test status
Simulation time 918082803 ps
CPU time 24.74 seconds
Started Aug 02 05:12:24 PM PDT 24
Finished Aug 02 05:12:49 PM PDT 24
Peak memory 208116 kb
Host smart-0217b184-45da-4b68-89f9-df3905248e96
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680708844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2680708844
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.291531045
Short name T778
Test name
Test status
Simulation time 69684335 ps
CPU time 2.06 seconds
Started Aug 02 05:12:32 PM PDT 24
Finished Aug 02 05:12:34 PM PDT 24
Peak memory 207040 kb
Host smart-d0960377-4fd8-4600-a3b1-f229c10c961d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291531045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.291531045
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.634261653
Short name T379
Test name
Test status
Simulation time 231023912 ps
CPU time 3.73 seconds
Started Aug 02 05:12:24 PM PDT 24
Finished Aug 02 05:12:28 PM PDT 24
Peak memory 214364 kb
Host smart-cf4e9b1b-7db3-4b29-886c-57c9ea19e305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634261653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.634261653
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2472481339
Short name T447
Test name
Test status
Simulation time 6543027507 ps
CPU time 25.1 seconds
Started Aug 02 05:12:53 PM PDT 24
Finished Aug 02 05:13:19 PM PDT 24
Peak memory 208568 kb
Host smart-57c26780-25fe-44f3-86fe-4cb9c63ac8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472481339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2472481339
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.4177849557
Short name T703
Test name
Test status
Simulation time 5446240430 ps
CPU time 128.86 seconds
Started Aug 02 05:12:35 PM PDT 24
Finished Aug 02 05:14:44 PM PDT 24
Peak memory 222412 kb
Host smart-6a3fa790-8e3a-415b-8c9a-0bfe11a0b200
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177849557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.4177849557
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.2454670189
Short name T158
Test name
Test status
Simulation time 529545599 ps
CPU time 18.75 seconds
Started Aug 02 05:12:28 PM PDT 24
Finished Aug 02 05:12:47 PM PDT 24
Peak memory 222696 kb
Host smart-52a49909-3187-4859-9644-90031b78a9fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454670189 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.2454670189
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.669938014
Short name T679
Test name
Test status
Simulation time 2293148563 ps
CPU time 7.91 seconds
Started Aug 02 05:12:32 PM PDT 24
Finished Aug 02 05:12:45 PM PDT 24
Peak memory 207704 kb
Host smart-2f728f13-e689-4067-bb11-23843e9388e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669938014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.669938014
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.2568111265
Short name T39
Test name
Test status
Simulation time 195879836 ps
CPU time 2.49 seconds
Started Aug 02 05:12:25 PM PDT 24
Finished Aug 02 05:12:28 PM PDT 24
Peak memory 210668 kb
Host smart-99a9aeee-baed-4c37-b12d-72533e6994d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568111265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.2568111265
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.483099118
Short name T828
Test name
Test status
Simulation time 18617592 ps
CPU time 0.78 seconds
Started Aug 02 05:12:54 PM PDT 24
Finished Aug 02 05:12:55 PM PDT 24
Peak memory 205972 kb
Host smart-02c05b41-90c9-4bd2-a4c7-03c53fd0ac12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483099118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.483099118
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3172561761
Short name T419
Test name
Test status
Simulation time 424816121 ps
CPU time 2.79 seconds
Started Aug 02 05:12:34 PM PDT 24
Finished Aug 02 05:12:37 PM PDT 24
Peak memory 214364 kb
Host smart-6d0cce94-6a59-460b-b271-1e3da5fe5de4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3172561761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3172561761
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3240154882
Short name T559
Test name
Test status
Simulation time 220569864 ps
CPU time 7.09 seconds
Started Aug 02 05:12:37 PM PDT 24
Finished Aug 02 05:12:45 PM PDT 24
Peak memory 209688 kb
Host smart-e7a4043d-8ee3-4f22-8b00-a50d0cdbb33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240154882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3240154882
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3055666853
Short name T661
Test name
Test status
Simulation time 125068455 ps
CPU time 2.16 seconds
Started Aug 02 05:12:27 PM PDT 24
Finished Aug 02 05:12:29 PM PDT 24
Peak memory 207072 kb
Host smart-1d590443-a385-4443-96db-7918f29e5a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055666853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3055666853
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2256426673
Short name T761
Test name
Test status
Simulation time 107782932 ps
CPU time 2.02 seconds
Started Aug 02 05:12:54 PM PDT 24
Finished Aug 02 05:12:56 PM PDT 24
Peak memory 222428 kb
Host smart-3e799b54-a4fe-4a2e-907d-459ff182d1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256426673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2256426673
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1550345138
Short name T837
Test name
Test status
Simulation time 331340505 ps
CPU time 4.73 seconds
Started Aug 02 05:12:50 PM PDT 24
Finished Aug 02 05:12:56 PM PDT 24
Peak memory 214236 kb
Host smart-0a6692d2-09b2-4c16-9d87-77b61efc9f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550345138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1550345138
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.268847648
Short name T756
Test name
Test status
Simulation time 451573878 ps
CPU time 10.63 seconds
Started Aug 02 05:12:35 PM PDT 24
Finished Aug 02 05:12:46 PM PDT 24
Peak memory 214444 kb
Host smart-1a2c7a29-8140-4e39-b70a-cf395939c766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268847648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.268847648
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3351092968
Short name T326
Test name
Test status
Simulation time 180048558 ps
CPU time 2.55 seconds
Started Aug 02 05:12:32 PM PDT 24
Finished Aug 02 05:12:34 PM PDT 24
Peak memory 206812 kb
Host smart-b754f1e2-9130-4f19-b040-0166e264b5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351092968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3351092968
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3614347999
Short name T845
Test name
Test status
Simulation time 69333968 ps
CPU time 3.35 seconds
Started Aug 02 05:12:38 PM PDT 24
Finished Aug 02 05:12:47 PM PDT 24
Peak memory 209152 kb
Host smart-e43ae0b9-4159-4c5f-9866-5d1abc951351
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614347999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3614347999
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3634574784
Short name T466
Test name
Test status
Simulation time 267033189 ps
CPU time 8.66 seconds
Started Aug 02 05:12:27 PM PDT 24
Finished Aug 02 05:12:35 PM PDT 24
Peak memory 207984 kb
Host smart-5569a208-62d0-4cd5-a0cf-7bd3e1c2fa6a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634574784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3634574784
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2510224410
Short name T851
Test name
Test status
Simulation time 721739209 ps
CPU time 3.08 seconds
Started Aug 02 05:12:46 PM PDT 24
Finished Aug 02 05:12:49 PM PDT 24
Peak memory 206848 kb
Host smart-004f1032-c34b-498b-bbe1-47258bb46f5b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510224410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2510224410
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3663909010
Short name T251
Test name
Test status
Simulation time 29852737 ps
CPU time 2.13 seconds
Started Aug 02 05:12:38 PM PDT 24
Finished Aug 02 05:12:41 PM PDT 24
Peak memory 220648 kb
Host smart-10dfba3a-626d-42f1-b1eb-b89e50a1e83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663909010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3663909010
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2471377025
Short name T656
Test name
Test status
Simulation time 126659800 ps
CPU time 3.18 seconds
Started Aug 02 05:12:29 PM PDT 24
Finished Aug 02 05:12:32 PM PDT 24
Peak memory 206916 kb
Host smart-97cf0dce-e9d7-4a2f-b221-329bb99bf98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471377025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2471377025
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3071645906
Short name T391
Test name
Test status
Simulation time 39514837 ps
CPU time 2.55 seconds
Started Aug 02 05:12:52 PM PDT 24
Finished Aug 02 05:12:55 PM PDT 24
Peak memory 207356 kb
Host smart-e46a88d3-668d-4fb5-a4cf-8891375ba9cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071645906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3071645906
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.2668728441
Short name T298
Test name
Test status
Simulation time 1914639121 ps
CPU time 18.72 seconds
Started Aug 02 05:12:43 PM PDT 24
Finished Aug 02 05:13:02 PM PDT 24
Peak memory 222468 kb
Host smart-bdd369b5-681a-4233-a5a7-71ad5074707d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668728441 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.2668728441
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2668805809
Short name T910
Test name
Test status
Simulation time 648808550 ps
CPU time 13.88 seconds
Started Aug 02 05:12:47 PM PDT 24
Finished Aug 02 05:13:01 PM PDT 24
Peak memory 214368 kb
Host smart-b168c948-8390-4cd5-bf12-7132dcd793d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668805809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2668805809
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3128396495
Short name T128
Test name
Test status
Simulation time 141850811 ps
CPU time 1.92 seconds
Started Aug 02 05:12:36 PM PDT 24
Finished Aug 02 05:12:38 PM PDT 24
Peak memory 210164 kb
Host smart-9cea3d40-f017-4d3f-812d-eb9991d498ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128396495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3128396495
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1824572591
Short name T794
Test name
Test status
Simulation time 10154304 ps
CPU time 0.77 seconds
Started Aug 02 05:13:02 PM PDT 24
Finished Aug 02 05:13:03 PM PDT 24
Peak memory 205920 kb
Host smart-2fd7b6b1-10c7-4d57-930d-d5cf62fcac7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824572591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1824572591
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.746567384
Short name T306
Test name
Test status
Simulation time 3266143845 ps
CPU time 33.83 seconds
Started Aug 02 05:12:37 PM PDT 24
Finished Aug 02 05:13:11 PM PDT 24
Peak memory 215756 kb
Host smart-fa49bb65-ddc6-46fa-9300-e5c28d983777
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=746567384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.746567384
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1878374791
Short name T180
Test name
Test status
Simulation time 400380497 ps
CPU time 3.53 seconds
Started Aug 02 05:12:57 PM PDT 24
Finished Aug 02 05:13:01 PM PDT 24
Peak memory 219000 kb
Host smart-e94eead7-3ceb-4bc5-adb9-40bf5c00686a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878374791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1878374791
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3567178452
Short name T847
Test name
Test status
Simulation time 95152918 ps
CPU time 4.07 seconds
Started Aug 02 05:12:40 PM PDT 24
Finished Aug 02 05:12:44 PM PDT 24
Peak memory 209772 kb
Host smart-d25a2056-43a8-4674-b1bb-d03a3b0d5b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567178452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3567178452
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1855506581
Short name T826
Test name
Test status
Simulation time 189882585 ps
CPU time 3.58 seconds
Started Aug 02 05:12:32 PM PDT 24
Finished Aug 02 05:12:35 PM PDT 24
Peak memory 214232 kb
Host smart-f9dafca5-d1fe-4d9c-9785-03486bea29ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855506581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1855506581
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2047998338
Short name T288
Test name
Test status
Simulation time 1053778389 ps
CPU time 5.05 seconds
Started Aug 02 05:12:46 PM PDT 24
Finished Aug 02 05:12:51 PM PDT 24
Peak memory 214292 kb
Host smart-1314e716-f2ab-4348-bbea-79789934f7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047998338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2047998338
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.986294564
Short name T6
Test name
Test status
Simulation time 172867524 ps
CPU time 3.67 seconds
Started Aug 02 05:12:41 PM PDT 24
Finished Aug 02 05:12:44 PM PDT 24
Peak memory 209856 kb
Host smart-c6fa7f30-b921-4ad0-981e-590785f174d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986294564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.986294564
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3099989130
Short name T240
Test name
Test status
Simulation time 27946167 ps
CPU time 2.19 seconds
Started Aug 02 05:12:58 PM PDT 24
Finished Aug 02 05:13:00 PM PDT 24
Peak memory 207636 kb
Host smart-d283151b-a9a0-4a30-a408-0ed89ecadc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099989130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3099989130
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2099727206
Short name T614
Test name
Test status
Simulation time 3364500045 ps
CPU time 36.8 seconds
Started Aug 02 05:12:52 PM PDT 24
Finished Aug 02 05:13:29 PM PDT 24
Peak memory 208584 kb
Host smart-0618b90f-3bc8-47bd-83fe-94d8d353a28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099727206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2099727206
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3177762986
Short name T345
Test name
Test status
Simulation time 31140242 ps
CPU time 2.33 seconds
Started Aug 02 05:12:41 PM PDT 24
Finished Aug 02 05:12:44 PM PDT 24
Peak memory 206952 kb
Host smart-fc357a56-485c-431d-a6d4-627affc864d1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177762986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3177762986
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.235197189
Short name T461
Test name
Test status
Simulation time 127547143 ps
CPU time 3.33 seconds
Started Aug 02 05:12:32 PM PDT 24
Finished Aug 02 05:12:36 PM PDT 24
Peak memory 208824 kb
Host smart-e0df0a8a-66e9-4780-acb2-f7bceec5c367
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235197189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.235197189
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.4055677240
Short name T369
Test name
Test status
Simulation time 42460338 ps
CPU time 2.43 seconds
Started Aug 02 05:12:49 PM PDT 24
Finished Aug 02 05:12:52 PM PDT 24
Peak memory 207020 kb
Host smart-9433bbb3-451c-4652-9f73-8ae886f77ab2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055677240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.4055677240
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3798938185
Short name T409
Test name
Test status
Simulation time 343223171 ps
CPU time 2.74 seconds
Started Aug 02 05:12:48 PM PDT 24
Finished Aug 02 05:12:51 PM PDT 24
Peak memory 209196 kb
Host smart-aa3d90d3-6d9a-4564-9c51-12922b4a2e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798938185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3798938185
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3300175704
Short name T522
Test name
Test status
Simulation time 545682362 ps
CPU time 12.97 seconds
Started Aug 02 05:12:36 PM PDT 24
Finished Aug 02 05:12:50 PM PDT 24
Peak memory 208304 kb
Host smart-335c2d1a-672a-4bd9-b3f1-4f1c305c98a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300175704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3300175704
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.1820666403
Short name T100
Test name
Test status
Simulation time 145413167 ps
CPU time 5.14 seconds
Started Aug 02 05:12:59 PM PDT 24
Finished Aug 02 05:13:04 PM PDT 24
Peak memory 215252 kb
Host smart-abd49d39-d5b1-474c-8f1c-3d8d0fd29d4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820666403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.1820666403
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1392495839
Short name T651
Test name
Test status
Simulation time 200188221 ps
CPU time 5.4 seconds
Started Aug 02 05:13:08 PM PDT 24
Finished Aug 02 05:13:14 PM PDT 24
Peak memory 208312 kb
Host smart-2059b13e-7a0a-4879-8249-9829e9cc5dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392495839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1392495839
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.271946006
Short name T493
Test name
Test status
Simulation time 67513356 ps
CPU time 2.63 seconds
Started Aug 02 05:12:52 PM PDT 24
Finished Aug 02 05:12:54 PM PDT 24
Peak memory 209932 kb
Host smart-b63c11bb-fe90-4b9d-b26e-84dcf48c0d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271946006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.271946006
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1616559715
Short name T98
Test name
Test status
Simulation time 53374173 ps
CPU time 0.78 seconds
Started Aug 02 05:12:38 PM PDT 24
Finished Aug 02 05:12:39 PM PDT 24
Peak memory 205968 kb
Host smart-fbe1d745-7a4c-4c0c-8c1e-45d8d0d1c9d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616559715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1616559715
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1781847270
Short name T583
Test name
Test status
Simulation time 41325255 ps
CPU time 1.97 seconds
Started Aug 02 05:12:34 PM PDT 24
Finished Aug 02 05:12:36 PM PDT 24
Peak memory 209200 kb
Host smart-6f2b52a5-c7a7-47dc-973e-827624b27713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781847270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1781847270
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1976088376
Short name T59
Test name
Test status
Simulation time 298388258 ps
CPU time 4.01 seconds
Started Aug 02 05:12:39 PM PDT 24
Finished Aug 02 05:12:44 PM PDT 24
Peak memory 214256 kb
Host smart-d8e83155-2f3d-4ae0-aee9-9d937e9d3844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976088376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1976088376
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3071697901
Short name T25
Test name
Test status
Simulation time 255118753 ps
CPU time 4.32 seconds
Started Aug 02 05:12:56 PM PDT 24
Finished Aug 02 05:13:01 PM PDT 24
Peak memory 208644 kb
Host smart-4bb5270f-72db-4a59-9e63-2d26b404840f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071697901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3071697901
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1842957149
Short name T804
Test name
Test status
Simulation time 89615423 ps
CPU time 3.21 seconds
Started Aug 02 05:12:59 PM PDT 24
Finished Aug 02 05:13:02 PM PDT 24
Peak memory 221388 kb
Host smart-10d10feb-632e-4ec4-ab72-991bc9a14a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842957149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1842957149
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1216421427
Short name T212
Test name
Test status
Simulation time 168035208 ps
CPU time 2.8 seconds
Started Aug 02 05:12:56 PM PDT 24
Finished Aug 02 05:12:59 PM PDT 24
Peak memory 209544 kb
Host smart-f97e674e-484a-4aa9-9dd0-28e913a6cf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216421427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1216421427
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.1859977106
Short name T550
Test name
Test status
Simulation time 101030790 ps
CPU time 5.05 seconds
Started Aug 02 05:12:53 PM PDT 24
Finished Aug 02 05:12:58 PM PDT 24
Peak memory 209040 kb
Host smart-94ec0ada-c32e-4428-931b-ff8d621666f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859977106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1859977106
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1500507331
Short name T846
Test name
Test status
Simulation time 130736285 ps
CPU time 4.01 seconds
Started Aug 02 05:12:42 PM PDT 24
Finished Aug 02 05:12:46 PM PDT 24
Peak memory 208700 kb
Host smart-733fc8d2-1945-4a72-a258-c92c2d608746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500507331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1500507331
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.2756693517
Short name T865
Test name
Test status
Simulation time 88908618 ps
CPU time 3.69 seconds
Started Aug 02 05:12:45 PM PDT 24
Finished Aug 02 05:12:49 PM PDT 24
Peak memory 208728 kb
Host smart-526b0da8-2b96-4f46-8714-5129849e745f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756693517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2756693517
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.3256231051
Short name T472
Test name
Test status
Simulation time 192705879 ps
CPU time 2.82 seconds
Started Aug 02 05:12:45 PM PDT 24
Finished Aug 02 05:12:48 PM PDT 24
Peak memory 206848 kb
Host smart-70ff84c0-a138-46be-96d6-d7d65eb13221
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256231051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3256231051
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3634657311
Short name T745
Test name
Test status
Simulation time 38995780 ps
CPU time 2.63 seconds
Started Aug 02 05:12:58 PM PDT 24
Finished Aug 02 05:13:00 PM PDT 24
Peak memory 208408 kb
Host smart-f3c8f6d7-4f5e-43b4-ab70-ddbd292072b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634657311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3634657311
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2511177393
Short name T197
Test name
Test status
Simulation time 220158958 ps
CPU time 4.37 seconds
Started Aug 02 05:12:54 PM PDT 24
Finished Aug 02 05:12:59 PM PDT 24
Peak memory 208348 kb
Host smart-0a0f6ef8-5116-451b-a6ab-1f8977f130db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511177393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2511177393
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.2310738702
Short name T127
Test name
Test status
Simulation time 5518977636 ps
CPU time 22.48 seconds
Started Aug 02 05:12:47 PM PDT 24
Finished Aug 02 05:13:10 PM PDT 24
Peak memory 222564 kb
Host smart-c3a448a9-d10a-4cef-9e7c-6c765e6374eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310738702 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.2310738702
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1913306240
Short name T529
Test name
Test status
Simulation time 273995853 ps
CPU time 4.52 seconds
Started Aug 02 05:12:38 PM PDT 24
Finished Aug 02 05:12:47 PM PDT 24
Peak memory 209420 kb
Host smart-aa9a857e-5ce2-40c5-80a9-97c81ccbb0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913306240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1913306240
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3942411311
Short name T759
Test name
Test status
Simulation time 55155872 ps
CPU time 1.83 seconds
Started Aug 02 05:12:46 PM PDT 24
Finished Aug 02 05:12:48 PM PDT 24
Peak memory 209904 kb
Host smart-250a6ad2-bfca-459e-b979-dbea513a481a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942411311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3942411311
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2162975679
Short name T440
Test name
Test status
Simulation time 14399025 ps
CPU time 0.94 seconds
Started Aug 02 05:12:54 PM PDT 24
Finished Aug 02 05:12:55 PM PDT 24
Peak memory 206168 kb
Host smart-9a713392-ca72-4257-b2e8-3f798b6e1f4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162975679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2162975679
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2724575016
Short name T818
Test name
Test status
Simulation time 35172067 ps
CPU time 1.51 seconds
Started Aug 02 05:12:52 PM PDT 24
Finished Aug 02 05:12:54 PM PDT 24
Peak memory 207524 kb
Host smart-c13879eb-4c5a-4269-a25d-2134cf60aea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724575016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2724575016
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2878881104
Short name T353
Test name
Test status
Simulation time 104025706 ps
CPU time 2.72 seconds
Started Aug 02 05:12:51 PM PDT 24
Finished Aug 02 05:12:54 PM PDT 24
Peak memory 222328 kb
Host smart-ff95a5b0-7ab9-484a-8777-bfc8d375098c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878881104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2878881104
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2651898345
Short name T310
Test name
Test status
Simulation time 215671481 ps
CPU time 3.01 seconds
Started Aug 02 05:12:48 PM PDT 24
Finished Aug 02 05:12:51 PM PDT 24
Peak memory 214892 kb
Host smart-38f43491-4c76-4f53-998b-6abbbde1c247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651898345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2651898345
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2467523604
Short name T323
Test name
Test status
Simulation time 392984871 ps
CPU time 3.7 seconds
Started Aug 02 05:12:59 PM PDT 24
Finished Aug 02 05:13:03 PM PDT 24
Peak memory 209624 kb
Host smart-5f89295e-6821-47a8-b62e-853d7961dbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467523604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2467523604
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.4146168950
Short name T905
Test name
Test status
Simulation time 136253406 ps
CPU time 2.84 seconds
Started Aug 02 05:12:52 PM PDT 24
Finished Aug 02 05:12:55 PM PDT 24
Peak memory 207004 kb
Host smart-fc9df241-6a59-403e-96af-a140e8c991d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146168950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.4146168950
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1961658469
Short name T245
Test name
Test status
Simulation time 58700330 ps
CPU time 2.93 seconds
Started Aug 02 05:12:53 PM PDT 24
Finished Aug 02 05:12:57 PM PDT 24
Peak memory 208552 kb
Host smart-9a87ca7a-70ac-4a02-9c68-9c3d17d46dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961658469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1961658469
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3948903137
Short name T739
Test name
Test status
Simulation time 568507789 ps
CPU time 18.87 seconds
Started Aug 02 05:13:01 PM PDT 24
Finished Aug 02 05:13:20 PM PDT 24
Peak memory 208836 kb
Host smart-8cfd49d2-e790-40d4-b4db-82b147825947
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948903137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3948903137
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1390390706
Short name T275
Test name
Test status
Simulation time 68443383 ps
CPU time 1.87 seconds
Started Aug 02 05:12:45 PM PDT 24
Finished Aug 02 05:12:47 PM PDT 24
Peak memory 208964 kb
Host smart-17c58014-3353-404d-834e-ea1d8fadb8ca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390390706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1390390706
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3159581149
Short name T875
Test name
Test status
Simulation time 29915012 ps
CPU time 2.25 seconds
Started Aug 02 05:12:54 PM PDT 24
Finished Aug 02 05:12:56 PM PDT 24
Peak memory 207024 kb
Host smart-ac7b898d-3d12-455e-b312-0fb35b46d48c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159581149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3159581149
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2519808142
Short name T381
Test name
Test status
Simulation time 105745184 ps
CPU time 1.98 seconds
Started Aug 02 05:12:48 PM PDT 24
Finished Aug 02 05:12:50 PM PDT 24
Peak memory 214304 kb
Host smart-34b91e74-3da4-4149-b3f3-cb78a7626920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519808142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2519808142
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.4045948583
Short name T603
Test name
Test status
Simulation time 505650345 ps
CPU time 3.16 seconds
Started Aug 02 05:12:37 PM PDT 24
Finished Aug 02 05:12:40 PM PDT 24
Peak memory 208532 kb
Host smart-ccd46aaa-174e-40e7-9007-4f2a17339555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045948583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.4045948583
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2468229562
Short name T272
Test name
Test status
Simulation time 1210989166 ps
CPU time 31.49 seconds
Started Aug 02 05:12:47 PM PDT 24
Finished Aug 02 05:13:19 PM PDT 24
Peak memory 216456 kb
Host smart-3856fd1e-bb14-46e9-9dcf-e3deff7cedf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468229562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2468229562
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.862973349
Short name T516
Test name
Test status
Simulation time 1061354559 ps
CPU time 3.61 seconds
Started Aug 02 05:12:35 PM PDT 24
Finished Aug 02 05:12:39 PM PDT 24
Peak memory 214348 kb
Host smart-99ca2bf0-be63-4394-9960-c8a82de72714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862973349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.862973349
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2056204469
Short name T842
Test name
Test status
Simulation time 256243902 ps
CPU time 6.19 seconds
Started Aug 02 05:12:59 PM PDT 24
Finished Aug 02 05:13:05 PM PDT 24
Peak memory 210880 kb
Host smart-c690d591-c730-409d-a169-8b6598849c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056204469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2056204469
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.4282690004
Short name T12
Test name
Test status
Simulation time 13772187 ps
CPU time 0.9 seconds
Started Aug 02 05:12:47 PM PDT 24
Finished Aug 02 05:12:48 PM PDT 24
Peak memory 205960 kb
Host smart-ae6b2199-4da9-4f22-b392-3b363ba148c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282690004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.4282690004
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1982342198
Short name T429
Test name
Test status
Simulation time 65703001 ps
CPU time 4.45 seconds
Started Aug 02 05:12:52 PM PDT 24
Finished Aug 02 05:12:57 PM PDT 24
Peak memory 215248 kb
Host smart-7e7143f4-5ad7-43f5-acc3-4bacb684b586
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1982342198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1982342198
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.447035407
Short name T551
Test name
Test status
Simulation time 715986120 ps
CPU time 4.85 seconds
Started Aug 02 05:12:45 PM PDT 24
Finished Aug 02 05:12:50 PM PDT 24
Peak memory 221528 kb
Host smart-1f3d0768-95f5-423e-9f3e-deffc6201900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447035407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.447035407
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.3653901958
Short name T561
Test name
Test status
Simulation time 158226813 ps
CPU time 4.02 seconds
Started Aug 02 05:12:48 PM PDT 24
Finished Aug 02 05:12:52 PM PDT 24
Peak memory 209656 kb
Host smart-e6465f82-dcdc-4719-a4a5-dcca01057587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653901958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3653901958
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1670310920
Short name T631
Test name
Test status
Simulation time 69314153 ps
CPU time 2.02 seconds
Started Aug 02 05:12:52 PM PDT 24
Finished Aug 02 05:12:55 PM PDT 24
Peak memory 214360 kb
Host smart-6671c202-6504-4c14-a4b4-5ec859ea7133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670310920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1670310920
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2728702790
Short name T368
Test name
Test status
Simulation time 135885917 ps
CPU time 2.88 seconds
Started Aug 02 05:12:42 PM PDT 24
Finished Aug 02 05:12:45 PM PDT 24
Peak memory 218260 kb
Host smart-17b721bd-bb9a-4972-8186-c6cb9d5668bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728702790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2728702790
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2011765061
Short name T513
Test name
Test status
Simulation time 311496010 ps
CPU time 3.41 seconds
Started Aug 02 05:12:56 PM PDT 24
Finished Aug 02 05:12:59 PM PDT 24
Peak memory 208616 kb
Host smart-375214e6-19f9-4a4f-aae8-886115db2e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011765061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2011765061
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1801683262
Short name T320
Test name
Test status
Simulation time 319603082 ps
CPU time 6.78 seconds
Started Aug 02 05:12:51 PM PDT 24
Finished Aug 02 05:12:58 PM PDT 24
Peak memory 208576 kb
Host smart-7245872e-e4a4-4813-99ea-540f131f2883
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801683262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1801683262
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.476811752
Short name T632
Test name
Test status
Simulation time 76776210 ps
CPU time 2.96 seconds
Started Aug 02 05:12:47 PM PDT 24
Finished Aug 02 05:12:50 PM PDT 24
Peak memory 206976 kb
Host smart-846e2fd4-c3b2-4ff7-9ed2-fa473529079b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476811752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.476811752
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3578221756
Short name T883
Test name
Test status
Simulation time 291020364 ps
CPU time 2.69 seconds
Started Aug 02 05:12:45 PM PDT 24
Finished Aug 02 05:12:48 PM PDT 24
Peak memory 207040 kb
Host smart-c580cc28-fc24-4a4b-adb8-59672c94645d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578221756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3578221756
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.560746838
Short name T681
Test name
Test status
Simulation time 871492539 ps
CPU time 18.87 seconds
Started Aug 02 05:12:50 PM PDT 24
Finished Aug 02 05:13:08 PM PDT 24
Peak memory 209508 kb
Host smart-a9f1e56b-77e7-4500-85f4-491c5ac09b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560746838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.560746838
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2636941166
Short name T665
Test name
Test status
Simulation time 374775854 ps
CPU time 2.43 seconds
Started Aug 02 05:12:51 PM PDT 24
Finished Aug 02 05:12:54 PM PDT 24
Peak memory 208724 kb
Host smart-853154fa-d734-4c1a-8d3d-f085d02d4d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636941166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2636941166
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3002730499
Short name T822
Test name
Test status
Simulation time 294762205 ps
CPU time 11.77 seconds
Started Aug 02 05:12:56 PM PDT 24
Finished Aug 02 05:13:08 PM PDT 24
Peak memory 215124 kb
Host smart-67a6d3bc-6cc6-4492-b56b-b91b1ff9a8c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002730499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3002730499
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.3992018199
Short name T178
Test name
Test status
Simulation time 1174437594 ps
CPU time 7.92 seconds
Started Aug 02 05:12:40 PM PDT 24
Finished Aug 02 05:12:48 PM PDT 24
Peak memory 222652 kb
Host smart-12c7b7c5-22f7-474a-a57d-4a0ba8216318
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992018199 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.3992018199
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2323114261
Short name T856
Test name
Test status
Simulation time 900096647 ps
CPU time 6.54 seconds
Started Aug 02 05:12:40 PM PDT 24
Finished Aug 02 05:12:47 PM PDT 24
Peak memory 210040 kb
Host smart-e04d676f-a88b-40b2-b960-90ba28eefc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323114261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2323114261
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3645967931
Short name T536
Test name
Test status
Simulation time 782717706 ps
CPU time 4.76 seconds
Started Aug 02 05:12:43 PM PDT 24
Finished Aug 02 05:12:48 PM PDT 24
Peak memory 210436 kb
Host smart-8a1af7ad-c3e3-4173-91de-8d8c318d6572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645967931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3645967931
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3422722488
Short name T670
Test name
Test status
Simulation time 33524383 ps
CPU time 0.73 seconds
Started Aug 02 05:12:21 PM PDT 24
Finished Aug 02 05:12:21 PM PDT 24
Peak memory 205920 kb
Host smart-791fad38-3e18-4a24-a1b5-f5becde6eb2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422722488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3422722488
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.302684897
Short name T356
Test name
Test status
Simulation time 531101234 ps
CPU time 6.19 seconds
Started Aug 02 05:12:06 PM PDT 24
Finished Aug 02 05:12:12 PM PDT 24
Peak memory 218236 kb
Host smart-ec52f792-68c1-468f-ab18-8f640dd4dd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302684897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.302684897
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1167718619
Short name T372
Test name
Test status
Simulation time 87341783 ps
CPU time 3.91 seconds
Started Aug 02 05:12:02 PM PDT 24
Finished Aug 02 05:12:06 PM PDT 24
Peak memory 214312 kb
Host smart-bf1a655d-e845-42fe-8fdc-63a18ad240f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167718619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1167718619
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2146966990
Short name T782
Test name
Test status
Simulation time 212962578 ps
CPU time 2.5 seconds
Started Aug 02 05:12:21 PM PDT 24
Finished Aug 02 05:12:23 PM PDT 24
Peak memory 214328 kb
Host smart-f5bcfce4-1038-409f-9ba7-fd6f849c00b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146966990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2146966990
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3520414615
Short name T677
Test name
Test status
Simulation time 40102284 ps
CPU time 2.21 seconds
Started Aug 02 05:12:08 PM PDT 24
Finished Aug 02 05:12:10 PM PDT 24
Peak memory 214392 kb
Host smart-95551869-3814-4224-bd71-1b0b07c97b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520414615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3520414615
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1492975185
Short name T864
Test name
Test status
Simulation time 353103412 ps
CPU time 4.17 seconds
Started Aug 02 05:12:02 PM PDT 24
Finished Aug 02 05:12:06 PM PDT 24
Peak memory 218196 kb
Host smart-aeaefe99-0ece-4d43-935a-ca8c2825229b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492975185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1492975185
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3199089732
Short name T678
Test name
Test status
Simulation time 434094588 ps
CPU time 5.71 seconds
Started Aug 02 05:12:14 PM PDT 24
Finished Aug 02 05:12:20 PM PDT 24
Peak memory 208428 kb
Host smart-e3bc191e-a0f8-46e0-896c-57c3e52d8464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199089732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3199089732
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1656019575
Short name T302
Test name
Test status
Simulation time 158779133 ps
CPU time 2.35 seconds
Started Aug 02 05:12:15 PM PDT 24
Finished Aug 02 05:12:17 PM PDT 24
Peak memory 206924 kb
Host smart-82fcadc6-ac2d-4b1b-8077-38fcf7ab08cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656019575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1656019575
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1105902711
Short name T293
Test name
Test status
Simulation time 67374405 ps
CPU time 3.36 seconds
Started Aug 02 05:12:05 PM PDT 24
Finished Aug 02 05:12:09 PM PDT 24
Peak memory 208576 kb
Host smart-2708baaa-128e-4148-b45d-ce71d5652462
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105902711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1105902711
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1515752168
Short name T474
Test name
Test status
Simulation time 33083837 ps
CPU time 2.44 seconds
Started Aug 02 05:12:03 PM PDT 24
Finished Aug 02 05:12:05 PM PDT 24
Peak memory 215656 kb
Host smart-55e29802-2950-4a03-b99f-a81f840da2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515752168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1515752168
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.663845701
Short name T741
Test name
Test status
Simulation time 1475259596 ps
CPU time 24.43 seconds
Started Aug 02 05:12:17 PM PDT 24
Finished Aug 02 05:12:41 PM PDT 24
Peak memory 208248 kb
Host smart-a3b95bac-c37b-49e3-83a3-bd03df14660b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663845701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.663845701
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2231113251
Short name T793
Test name
Test status
Simulation time 772998429 ps
CPU time 8.75 seconds
Started Aug 02 05:12:05 PM PDT 24
Finished Aug 02 05:12:14 PM PDT 24
Peak memory 209832 kb
Host smart-b5abea7c-3bd4-4880-acab-e636ffbcbc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231113251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2231113251
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1207626439
Short name T800
Test name
Test status
Simulation time 323438260 ps
CPU time 6.58 seconds
Started Aug 02 05:11:58 PM PDT 24
Finished Aug 02 05:12:05 PM PDT 24
Peak memory 211048 kb
Host smart-d5600e5e-c190-475a-95f8-085570469269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207626439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1207626439
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1526368170
Short name T757
Test name
Test status
Simulation time 35687811 ps
CPU time 0.74 seconds
Started Aug 02 05:13:01 PM PDT 24
Finished Aug 02 05:13:02 PM PDT 24
Peak memory 206000 kb
Host smart-fab90615-cf2d-4657-a4d9-61f6feaec387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526368170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1526368170
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1067142075
Short name T131
Test name
Test status
Simulation time 239918769 ps
CPU time 4.58 seconds
Started Aug 02 05:12:43 PM PDT 24
Finished Aug 02 05:12:48 PM PDT 24
Peak memory 214360 kb
Host smart-9be7f416-0f63-4463-b5fa-72da638ae6c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1067142075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1067142075
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.580159802
Short name T30
Test name
Test status
Simulation time 111655190 ps
CPU time 2.65 seconds
Started Aug 02 05:12:38 PM PDT 24
Finished Aug 02 05:12:41 PM PDT 24
Peak memory 207864 kb
Host smart-59d526ce-b5fe-462b-baad-b1c199a08b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580159802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.580159802
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3575132792
Short name T713
Test name
Test status
Simulation time 79742894 ps
CPU time 1.41 seconds
Started Aug 02 05:12:54 PM PDT 24
Finished Aug 02 05:12:56 PM PDT 24
Peak memory 207784 kb
Host smart-5a9d0104-40e2-4d1e-ab75-0b0416876758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575132792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3575132792
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.4130158432
Short name T585
Test name
Test status
Simulation time 307250152 ps
CPU time 1.75 seconds
Started Aug 02 05:12:56 PM PDT 24
Finished Aug 02 05:12:57 PM PDT 24
Peak memory 214968 kb
Host smart-08d16534-d716-41fe-8830-467ab1e60973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130158432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.4130158432
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2638489290
Short name T887
Test name
Test status
Simulation time 429929398 ps
CPU time 6.05 seconds
Started Aug 02 05:12:45 PM PDT 24
Finished Aug 02 05:12:51 PM PDT 24
Peak memory 214352 kb
Host smart-bbc80c24-fba6-4457-8d7b-02ba4c4c98f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638489290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2638489290
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_random.2793800184
Short name T820
Test name
Test status
Simulation time 287983723 ps
CPU time 6.32 seconds
Started Aug 02 05:13:00 PM PDT 24
Finished Aug 02 05:13:07 PM PDT 24
Peak memory 207952 kb
Host smart-4b4797be-6bb0-4e6a-8b20-ec760fc880bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793800184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2793800184
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2669459960
Short name T687
Test name
Test status
Simulation time 82724607 ps
CPU time 2.82 seconds
Started Aug 02 05:12:53 PM PDT 24
Finished Aug 02 05:12:55 PM PDT 24
Peak memory 206740 kb
Host smart-92fb2328-1069-419c-a45a-923d0e9d5be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669459960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2669459960
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3720078509
Short name T208
Test name
Test status
Simulation time 65649755 ps
CPU time 3.17 seconds
Started Aug 02 05:12:45 PM PDT 24
Finished Aug 02 05:12:48 PM PDT 24
Peak memory 206932 kb
Host smart-b49ad593-ad3d-4c67-8e57-df6ae2658b1a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720078509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3720078509
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3483163520
Short name T747
Test name
Test status
Simulation time 144881743 ps
CPU time 4.3 seconds
Started Aug 02 05:12:47 PM PDT 24
Finished Aug 02 05:12:51 PM PDT 24
Peak memory 208092 kb
Host smart-89a4c573-9ccc-42d4-989e-09edf95cb7c1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483163520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3483163520
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2479206967
Short name T898
Test name
Test status
Simulation time 64484471 ps
CPU time 3.19 seconds
Started Aug 02 05:12:55 PM PDT 24
Finished Aug 02 05:12:58 PM PDT 24
Peak memory 208636 kb
Host smart-e207464b-c180-4ea9-bb3e-fd15df6b12d8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479206967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2479206967
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.4257455159
Short name T852
Test name
Test status
Simulation time 230262275 ps
CPU time 3.4 seconds
Started Aug 02 05:13:00 PM PDT 24
Finished Aug 02 05:13:04 PM PDT 24
Peak memory 209448 kb
Host smart-960f73da-1550-4616-8040-b7c61d86a0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257455159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.4257455159
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2100713251
Short name T582
Test name
Test status
Simulation time 33346938 ps
CPU time 2.31 seconds
Started Aug 02 05:12:54 PM PDT 24
Finished Aug 02 05:12:56 PM PDT 24
Peak memory 207168 kb
Host smart-ea9c81e5-628c-4127-8dd3-20ff9721bf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100713251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2100713251
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1325667285
Short name T791
Test name
Test status
Simulation time 191703744 ps
CPU time 5.65 seconds
Started Aug 02 05:12:51 PM PDT 24
Finished Aug 02 05:12:57 PM PDT 24
Peak memory 215016 kb
Host smart-94475be6-1c44-4985-8397-ba66c4b739f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325667285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1325667285
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.719621812
Short name T176
Test name
Test status
Simulation time 589736793 ps
CPU time 22.46 seconds
Started Aug 02 05:12:52 PM PDT 24
Finished Aug 02 05:13:14 PM PDT 24
Peak memory 222576 kb
Host smart-f2788f94-5cc0-4b83-af34-8bc79d6f10ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719621812 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.719621812
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.756566419
Short name T697
Test name
Test status
Simulation time 3694591259 ps
CPU time 59.37 seconds
Started Aug 02 05:12:44 PM PDT 24
Finished Aug 02 05:13:44 PM PDT 24
Peak memory 209880 kb
Host smart-4f26d7b9-b4b7-4864-a6e3-003d9391ed9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756566419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.756566419
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.4254579930
Short name T699
Test name
Test status
Simulation time 450064204 ps
CPU time 5.05 seconds
Started Aug 02 05:12:52 PM PDT 24
Finished Aug 02 05:12:58 PM PDT 24
Peak memory 210616 kb
Host smart-096d8b6e-1c86-4953-9679-a1fb75de4cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254579930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.4254579930
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.756945423
Short name T650
Test name
Test status
Simulation time 31779694 ps
CPU time 0.78 seconds
Started Aug 02 05:12:55 PM PDT 24
Finished Aug 02 05:12:56 PM PDT 24
Peak memory 205932 kb
Host smart-2952264b-9ded-4439-9d72-0037a3b11567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756945423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.756945423
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3546679131
Short name T271
Test name
Test status
Simulation time 68048498 ps
CPU time 2.59 seconds
Started Aug 02 05:13:01 PM PDT 24
Finished Aug 02 05:13:04 PM PDT 24
Peak memory 214436 kb
Host smart-bcd4e5e0-8a9b-49b2-b8a3-5605b89d4fc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3546679131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3546679131
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.925208381
Short name T19
Test name
Test status
Simulation time 60698447 ps
CPU time 1.53 seconds
Started Aug 02 05:13:09 PM PDT 24
Finished Aug 02 05:13:10 PM PDT 24
Peak memory 215072 kb
Host smart-b686cd9d-3422-4544-9115-fd26cb4f1352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925208381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.925208381
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1556033590
Short name T702
Test name
Test status
Simulation time 56257413 ps
CPU time 2.02 seconds
Started Aug 02 05:12:49 PM PDT 24
Finished Aug 02 05:12:51 PM PDT 24
Peak memory 208196 kb
Host smart-6ee01298-cda0-4078-8590-6e13b9a33504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556033590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1556033590
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2069526456
Short name T277
Test name
Test status
Simulation time 104010245 ps
CPU time 4.68 seconds
Started Aug 02 05:13:02 PM PDT 24
Finished Aug 02 05:13:06 PM PDT 24
Peak memory 214512 kb
Host smart-ba6fda78-336d-41fd-b884-b3e98eff5ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069526456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2069526456
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.4102464004
Short name T267
Test name
Test status
Simulation time 72211344 ps
CPU time 2.47 seconds
Started Aug 02 05:12:56 PM PDT 24
Finished Aug 02 05:12:59 PM PDT 24
Peak memory 214156 kb
Host smart-84961911-9bb4-4c42-96b3-b01c5fa9a967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102464004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.4102464004
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1911997873
Short name T217
Test name
Test status
Simulation time 60362124 ps
CPU time 2.93 seconds
Started Aug 02 05:12:55 PM PDT 24
Finished Aug 02 05:12:58 PM PDT 24
Peak memory 214368 kb
Host smart-ab164e9f-0340-466f-b6c5-9bd6eea9e2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911997873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1911997873
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.835056060
Short name T370
Test name
Test status
Simulation time 108777384 ps
CPU time 2.28 seconds
Started Aug 02 05:12:42 PM PDT 24
Finished Aug 02 05:12:45 PM PDT 24
Peak memory 214328 kb
Host smart-0f1efebd-3af4-439f-b7b2-ccfa4cdec6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835056060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.835056060
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1920039146
Short name T316
Test name
Test status
Simulation time 3898854014 ps
CPU time 24.26 seconds
Started Aug 02 05:12:59 PM PDT 24
Finished Aug 02 05:13:23 PM PDT 24
Peak memory 208640 kb
Host smart-a56f0c51-aa8d-4355-adee-f5b7e3d4d726
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920039146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1920039146
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1048239119
Short name T533
Test name
Test status
Simulation time 288885169 ps
CPU time 3.91 seconds
Started Aug 02 05:12:50 PM PDT 24
Finished Aug 02 05:12:55 PM PDT 24
Peak memory 208928 kb
Host smart-30f9be13-41d5-40e8-bcf2-65973dc89104
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048239119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1048239119
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2125520513
Short name T184
Test name
Test status
Simulation time 55704791 ps
CPU time 2.47 seconds
Started Aug 02 05:13:00 PM PDT 24
Finished Aug 02 05:13:03 PM PDT 24
Peak memory 208660 kb
Host smart-bf8f4346-f057-4a4c-8071-6afb975fc5d8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125520513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2125520513
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2870171138
Short name T543
Test name
Test status
Simulation time 1129766634 ps
CPU time 4.87 seconds
Started Aug 02 05:12:51 PM PDT 24
Finished Aug 02 05:12:56 PM PDT 24
Peak memory 209792 kb
Host smart-1b279148-fee8-4d04-87df-fa450e4f373e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870171138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2870171138
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1305746229
Short name T464
Test name
Test status
Simulation time 30288796 ps
CPU time 2.19 seconds
Started Aug 02 05:13:07 PM PDT 24
Finished Aug 02 05:13:09 PM PDT 24
Peak memory 207016 kb
Host smart-a22904d4-9836-4195-82cd-611470e9964c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305746229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1305746229
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2951045802
Short name T218
Test name
Test status
Simulation time 2426457195 ps
CPU time 67.48 seconds
Started Aug 02 05:13:10 PM PDT 24
Finished Aug 02 05:14:17 PM PDT 24
Peak memory 216852 kb
Host smart-c7659502-b07f-460e-a94c-5d7a590d9496
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951045802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2951045802
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.739173130
Short name T840
Test name
Test status
Simulation time 1162132435 ps
CPU time 10.34 seconds
Started Aug 02 05:13:03 PM PDT 24
Finished Aug 02 05:13:14 PM PDT 24
Peak memory 221948 kb
Host smart-254dd76c-c360-4d09-ade4-308b86488089
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739173130 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.739173130
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.495050972
Short name T508
Test name
Test status
Simulation time 185476221 ps
CPU time 3.82 seconds
Started Aug 02 05:13:06 PM PDT 24
Finished Aug 02 05:13:10 PM PDT 24
Peak memory 209080 kb
Host smart-48ff9aa2-03e7-4ecf-994a-c42f13bb9465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495050972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.495050972
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.726082554
Short name T400
Test name
Test status
Simulation time 160880052 ps
CPU time 1.99 seconds
Started Aug 02 05:13:02 PM PDT 24
Finished Aug 02 05:13:04 PM PDT 24
Peak memory 209848 kb
Host smart-c03322d0-4fc3-4f39-8d56-3d2f157afb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726082554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.726082554
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3444580519
Short name T562
Test name
Test status
Simulation time 53048575 ps
CPU time 0.85 seconds
Started Aug 02 05:12:49 PM PDT 24
Finished Aug 02 05:12:50 PM PDT 24
Peak memory 206012 kb
Host smart-280c55e3-8ea5-4f66-a080-bc5be8842e70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444580519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3444580519
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2508053969
Short name T488
Test name
Test status
Simulation time 80956584 ps
CPU time 3.76 seconds
Started Aug 02 05:13:02 PM PDT 24
Finished Aug 02 05:13:06 PM PDT 24
Peak memory 222684 kb
Host smart-112767c4-7ddc-4fba-aa58-c8e8a13a0739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508053969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2508053969
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3586105045
Short name T69
Test name
Test status
Simulation time 1157450049 ps
CPU time 9.03 seconds
Started Aug 02 05:12:55 PM PDT 24
Finished Aug 02 05:13:04 PM PDT 24
Peak memory 209592 kb
Host smart-5433d74b-c699-4242-9439-a25960f74e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586105045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3586105045
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1381182544
Short name T375
Test name
Test status
Simulation time 159264080 ps
CPU time 2.73 seconds
Started Aug 02 05:12:42 PM PDT 24
Finished Aug 02 05:12:45 PM PDT 24
Peak memory 214292 kb
Host smart-3225a662-98da-4b14-973e-dfef840d476f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381182544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1381182544
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3511121211
Short name T133
Test name
Test status
Simulation time 82927544 ps
CPU time 3.95 seconds
Started Aug 02 05:13:06 PM PDT 24
Finished Aug 02 05:13:10 PM PDT 24
Peak memory 209880 kb
Host smart-6e906f6b-581a-4c9f-bdec-52f978bf899c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511121211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3511121211
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.1860082590
Short name T477
Test name
Test status
Simulation time 148456902 ps
CPU time 4.71 seconds
Started Aug 02 05:13:02 PM PDT 24
Finished Aug 02 05:13:07 PM PDT 24
Peak memory 207904 kb
Host smart-f16f7d01-ff9f-4ce2-85ca-2429b4437682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860082590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1860082590
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3497813032
Short name T682
Test name
Test status
Simulation time 141008485 ps
CPU time 3.73 seconds
Started Aug 02 05:13:01 PM PDT 24
Finished Aug 02 05:13:04 PM PDT 24
Peak memory 208508 kb
Host smart-6233fd66-5cd0-4a13-afba-6d7fabb36fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497813032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3497813032
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2691590900
Short name T809
Test name
Test status
Simulation time 181848833 ps
CPU time 5.2 seconds
Started Aug 02 05:12:59 PM PDT 24
Finished Aug 02 05:13:04 PM PDT 24
Peak memory 207812 kb
Host smart-e8f57e96-87af-4353-a555-d13c3d6e1c2c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691590900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2691590900
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3162937620
Short name T542
Test name
Test status
Simulation time 126871116 ps
CPU time 4.38 seconds
Started Aug 02 05:12:49 PM PDT 24
Finished Aug 02 05:12:54 PM PDT 24
Peak memory 208392 kb
Host smart-b5ffa4a1-6a98-495f-80e1-1e19fd1c6dbc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162937620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3162937620
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2816689207
Short name T567
Test name
Test status
Simulation time 211353363 ps
CPU time 2.68 seconds
Started Aug 02 05:13:06 PM PDT 24
Finished Aug 02 05:13:09 PM PDT 24
Peak memory 206968 kb
Host smart-7d4df16c-3da3-4aac-acaa-7b3b39530a12
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816689207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2816689207
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3040828736
Short name T758
Test name
Test status
Simulation time 444257082 ps
CPU time 4.88 seconds
Started Aug 02 05:13:08 PM PDT 24
Finished Aug 02 05:13:13 PM PDT 24
Peak memory 208104 kb
Host smart-53bf494a-5fc0-495d-96e5-e75c9349d0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040828736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3040828736
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.951763229
Short name T863
Test name
Test status
Simulation time 156106754 ps
CPU time 3.5 seconds
Started Aug 02 05:12:56 PM PDT 24
Finished Aug 02 05:13:00 PM PDT 24
Peak memory 206684 kb
Host smart-d810392f-9c01-47fa-b26c-027cb460191f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951763229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.951763229
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3924710303
Short name T77
Test name
Test status
Simulation time 2692565585 ps
CPU time 60.4 seconds
Started Aug 02 05:13:02 PM PDT 24
Finished Aug 02 05:14:02 PM PDT 24
Peak memory 221856 kb
Host smart-c6fd7010-1afd-4cdc-95fb-de2ea93b04e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924710303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3924710303
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.733031992
Short name T51
Test name
Test status
Simulation time 462698743 ps
CPU time 8.77 seconds
Started Aug 02 05:12:57 PM PDT 24
Finished Aug 02 05:13:06 PM PDT 24
Peak memory 220516 kb
Host smart-128f90cc-bf73-4398-89ef-bfa7c5f08dfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733031992 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.733031992
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.431235378
Short name T494
Test name
Test status
Simulation time 44783234 ps
CPU time 2.85 seconds
Started Aug 02 05:13:06 PM PDT 24
Finished Aug 02 05:13:09 PM PDT 24
Peak memory 207948 kb
Host smart-156b1a1f-d72a-43d1-8d13-c18e1d12c2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431235378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.431235378
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.2866003997
Short name T584
Test name
Test status
Simulation time 893359331 ps
CPU time 4.07 seconds
Started Aug 02 05:12:49 PM PDT 24
Finished Aug 02 05:12:53 PM PDT 24
Peak memory 210204 kb
Host smart-2e4a4385-9d79-4932-891c-772194ae00b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866003997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2866003997
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2239113374
Short name T506
Test name
Test status
Simulation time 7742224 ps
CPU time 0.71 seconds
Started Aug 02 05:12:59 PM PDT 24
Finished Aug 02 05:12:59 PM PDT 24
Peak memory 205968 kb
Host smart-35e5dc72-b39b-4b78-998c-5c1a084c6990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239113374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2239113374
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.603639073
Short name T28
Test name
Test status
Simulation time 73887233 ps
CPU time 3.34 seconds
Started Aug 02 05:13:05 PM PDT 24
Finished Aug 02 05:13:08 PM PDT 24
Peak memory 214212 kb
Host smart-c700441b-3f64-4f38-a784-65acd3ece7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603639073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.603639073
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1204562840
Short name T737
Test name
Test status
Simulation time 1233365711 ps
CPU time 3.98 seconds
Started Aug 02 05:13:05 PM PDT 24
Finished Aug 02 05:13:14 PM PDT 24
Peak memory 218264 kb
Host smart-4114c179-35e0-48a3-923c-413dcddd9af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204562840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1204562840
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3435909941
Short name T220
Test name
Test status
Simulation time 154808351 ps
CPU time 3.28 seconds
Started Aug 02 05:12:59 PM PDT 24
Finished Aug 02 05:13:03 PM PDT 24
Peak memory 214340 kb
Host smart-e27cf0b1-1a10-4bbb-a22c-abff5ecdf8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435909941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3435909941
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.126705284
Short name T755
Test name
Test status
Simulation time 1069029295 ps
CPU time 8.36 seconds
Started Aug 02 05:13:00 PM PDT 24
Finished Aug 02 05:13:08 PM PDT 24
Peak memory 214348 kb
Host smart-e5dc80eb-f475-4c23-8c41-567db9ca8f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126705284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.126705284
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1317447193
Short name T241
Test name
Test status
Simulation time 1649206488 ps
CPU time 21.28 seconds
Started Aug 02 05:12:54 PM PDT 24
Finished Aug 02 05:13:16 PM PDT 24
Peak memory 208004 kb
Host smart-c3eac601-8885-4c74-b88a-344f9e71817e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317447193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1317447193
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3822789360
Short name T319
Test name
Test status
Simulation time 63394603 ps
CPU time 3.17 seconds
Started Aug 02 05:12:47 PM PDT 24
Finished Aug 02 05:12:51 PM PDT 24
Peak memory 206972 kb
Host smart-81ce5d63-9c53-445d-a6a0-a19d17914f74
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822789360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3822789360
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3266137390
Short name T605
Test name
Test status
Simulation time 62533064 ps
CPU time 2.93 seconds
Started Aug 02 05:12:58 PM PDT 24
Finished Aug 02 05:13:01 PM PDT 24
Peak memory 208332 kb
Host smart-1f59ab96-94be-4374-b617-8a1233cb0709
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266137390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3266137390
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.2560005913
Short name T517
Test name
Test status
Simulation time 53075685 ps
CPU time 2.75 seconds
Started Aug 02 05:13:11 PM PDT 24
Finished Aug 02 05:13:14 PM PDT 24
Peak memory 208276 kb
Host smart-05dc3e9a-103a-47ac-96f0-d9fefc58ee63
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560005913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2560005913
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.626254044
Short name T825
Test name
Test status
Simulation time 390217375 ps
CPU time 3.13 seconds
Started Aug 02 05:13:00 PM PDT 24
Finished Aug 02 05:13:03 PM PDT 24
Peak memory 216032 kb
Host smart-55a87c98-31a9-46cf-9726-f0580f79f6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626254044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.626254044
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1439092922
Short name T627
Test name
Test status
Simulation time 70686132 ps
CPU time 3.06 seconds
Started Aug 02 05:12:57 PM PDT 24
Finished Aug 02 05:13:00 PM PDT 24
Peak memory 208692 kb
Host smart-88a85060-9ef2-44e4-99b2-a87003e27430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439092922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1439092922
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.3410862066
Short name T325
Test name
Test status
Simulation time 3519106864 ps
CPU time 24.71 seconds
Started Aug 02 05:13:11 PM PDT 24
Finished Aug 02 05:13:36 PM PDT 24
Peak memory 215072 kb
Host smart-27992378-77c6-49f6-824c-eb07c9a3d25a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410862066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3410862066
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.93162177
Short name T691
Test name
Test status
Simulation time 176925030 ps
CPU time 5 seconds
Started Aug 02 05:13:09 PM PDT 24
Finished Aug 02 05:13:14 PM PDT 24
Peak memory 209884 kb
Host smart-4202db1e-b362-4a4b-a85e-83e8a03add14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93162177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.93162177
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2605250194
Short name T478
Test name
Test status
Simulation time 21497512 ps
CPU time 0.75 seconds
Started Aug 02 05:13:19 PM PDT 24
Finished Aug 02 05:13:20 PM PDT 24
Peak memory 205996 kb
Host smart-a3f3294c-e2b4-4375-bad0-0cd05667fda6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605250194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2605250194
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.508907306
Short name T620
Test name
Test status
Simulation time 4966364271 ps
CPU time 56.53 seconds
Started Aug 02 05:13:02 PM PDT 24
Finished Aug 02 05:13:59 PM PDT 24
Peak memory 217464 kb
Host smart-697d51dd-57dc-4ffe-9ee0-687b7bec4b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508907306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.508907306
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.1685401661
Short name T427
Test name
Test status
Simulation time 1277310254 ps
CPU time 10.86 seconds
Started Aug 02 05:13:04 PM PDT 24
Finished Aug 02 05:13:15 PM PDT 24
Peak memory 214456 kb
Host smart-034be1c8-a53b-4b7c-9c35-a37d47726809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685401661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1685401661
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.602819379
Short name T263
Test name
Test status
Simulation time 55839511 ps
CPU time 2.37 seconds
Started Aug 02 05:13:07 PM PDT 24
Finished Aug 02 05:13:10 PM PDT 24
Peak memory 222408 kb
Host smart-d21e7921-e685-496f-9647-31141bf3fa33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602819379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.602819379
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1980300492
Short name T224
Test name
Test status
Simulation time 234927967 ps
CPU time 3.1 seconds
Started Aug 02 05:13:00 PM PDT 24
Finished Aug 02 05:13:03 PM PDT 24
Peak memory 219640 kb
Host smart-a324d365-b4ca-474e-a453-93bb4e664e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980300492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1980300492
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3404308362
Short name T867
Test name
Test status
Simulation time 119061598 ps
CPU time 2.64 seconds
Started Aug 02 05:12:57 PM PDT 24
Finished Aug 02 05:13:00 PM PDT 24
Peak memory 208724 kb
Host smart-5b6d2cfc-ae7f-4d05-9ec5-ebd9d0f2b5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404308362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3404308362
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.580786034
Short name T672
Test name
Test status
Simulation time 3182149289 ps
CPU time 22.63 seconds
Started Aug 02 05:12:52 PM PDT 24
Finished Aug 02 05:13:15 PM PDT 24
Peak memory 208512 kb
Host smart-a23615a9-27e2-4446-b808-71d24568fda0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580786034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.580786034
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.11312685
Short name T806
Test name
Test status
Simulation time 120634235 ps
CPU time 3.2 seconds
Started Aug 02 05:13:05 PM PDT 24
Finished Aug 02 05:13:08 PM PDT 24
Peak memory 208700 kb
Host smart-f2f77cfd-c1e7-41f2-8390-01a87f423ef7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11312685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.11312685
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1196553270
Short name T574
Test name
Test status
Simulation time 472880055 ps
CPU time 3.49 seconds
Started Aug 02 05:12:58 PM PDT 24
Finished Aug 02 05:13:02 PM PDT 24
Peak memory 206988 kb
Host smart-9460cbd0-74a2-4f13-8fdb-c40b5d08f4ec
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196553270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1196553270
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.730405036
Short name T570
Test name
Test status
Simulation time 105712407 ps
CPU time 2.99 seconds
Started Aug 02 05:13:02 PM PDT 24
Finished Aug 02 05:13:05 PM PDT 24
Peak memory 218044 kb
Host smart-fb67a419-9763-41ba-87de-bd8e44410680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730405036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.730405036
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.417543948
Short name T416
Test name
Test status
Simulation time 119738843 ps
CPU time 4.08 seconds
Started Aug 02 05:13:01 PM PDT 24
Finished Aug 02 05:13:05 PM PDT 24
Peak memory 208860 kb
Host smart-9499c449-a1a6-4c12-ac11-2cc07ffee561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417543948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.417543948
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1955433462
Short name T63
Test name
Test status
Simulation time 489566517 ps
CPU time 13.57 seconds
Started Aug 02 05:13:17 PM PDT 24
Finished Aug 02 05:13:30 PM PDT 24
Peak memory 220464 kb
Host smart-5ae41d5b-e9e8-499e-9fb3-35cb64529d3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955433462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1955433462
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1511872030
Short name T300
Test name
Test status
Simulation time 1048286362 ps
CPU time 3.93 seconds
Started Aug 02 05:13:02 PM PDT 24
Finished Aug 02 05:13:06 PM PDT 24
Peak memory 207312 kb
Host smart-0242ce0b-1f78-4615-a0e0-9219e207f2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511872030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1511872030
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1428473718
Short name T509
Test name
Test status
Simulation time 187293152 ps
CPU time 2.16 seconds
Started Aug 02 05:13:05 PM PDT 24
Finished Aug 02 05:13:07 PM PDT 24
Peak memory 210240 kb
Host smart-1ebbd6c1-0801-4d40-a088-80a5d36901ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428473718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1428473718
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2617721661
Short name T497
Test name
Test status
Simulation time 9405769 ps
CPU time 0.81 seconds
Started Aug 02 05:13:12 PM PDT 24
Finished Aug 02 05:13:13 PM PDT 24
Peak memory 206048 kb
Host smart-cee88016-5947-4631-87e8-a116ec7b8c66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617721661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2617721661
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.717116475
Short name T519
Test name
Test status
Simulation time 141450049 ps
CPU time 5.29 seconds
Started Aug 02 05:13:05 PM PDT 24
Finished Aug 02 05:13:11 PM PDT 24
Peak memory 219880 kb
Host smart-263b67b7-b48e-4384-b67e-f9a9a25be19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717116475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.717116475
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.109990825
Short name T719
Test name
Test status
Simulation time 86974651 ps
CPU time 3.5 seconds
Started Aug 02 05:13:02 PM PDT 24
Finished Aug 02 05:13:06 PM PDT 24
Peak memory 209352 kb
Host smart-6b3e49b8-a51a-4b74-a815-7fc20134688f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109990825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.109990825
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.432487788
Short name T93
Test name
Test status
Simulation time 167618026 ps
CPU time 4.13 seconds
Started Aug 02 05:13:06 PM PDT 24
Finished Aug 02 05:13:10 PM PDT 24
Peak memory 209360 kb
Host smart-8d1c01c6-1ece-4c1a-bd05-58fddc6a7dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432487788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.432487788
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2001660078
Short name T615
Test name
Test status
Simulation time 787270204 ps
CPU time 4.04 seconds
Started Aug 02 05:13:17 PM PDT 24
Finished Aug 02 05:13:22 PM PDT 24
Peak memory 220628 kb
Host smart-4f1b3f3a-0865-433b-9365-987749c8abdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001660078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2001660078
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2003868168
Short name T731
Test name
Test status
Simulation time 1054402019 ps
CPU time 4.56 seconds
Started Aug 02 05:13:06 PM PDT 24
Finished Aug 02 05:13:11 PM PDT 24
Peak memory 214444 kb
Host smart-00d609a1-4bbe-4595-bd34-78f952315488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003868168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2003868168
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2756902776
Short name T186
Test name
Test status
Simulation time 393466355 ps
CPU time 9.5 seconds
Started Aug 02 05:13:02 PM PDT 24
Finished Aug 02 05:13:12 PM PDT 24
Peak memory 208052 kb
Host smart-a0635dbe-c2b7-4915-b601-c454410da873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756902776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2756902776
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3977650595
Short name T787
Test name
Test status
Simulation time 858009929 ps
CPU time 4.05 seconds
Started Aug 02 05:13:08 PM PDT 24
Finished Aug 02 05:13:12 PM PDT 24
Peak memory 207072 kb
Host smart-cfa3f41b-076a-47dc-ad76-27fd5829eefc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977650595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3977650595
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2966017716
Short name T880
Test name
Test status
Simulation time 154685896 ps
CPU time 3.55 seconds
Started Aug 02 05:13:16 PM PDT 24
Finished Aug 02 05:13:19 PM PDT 24
Peak memory 207052 kb
Host smart-f68970b3-64c0-4fb0-83e4-2dd28a7b61f5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966017716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2966017716
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1036654104
Short name T210
Test name
Test status
Simulation time 103620044 ps
CPU time 3.6 seconds
Started Aug 02 05:13:04 PM PDT 24
Finished Aug 02 05:13:08 PM PDT 24
Peak memory 207012 kb
Host smart-2a3778d6-f2ce-44d3-9c93-73305a1ac9b7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036654104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1036654104
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3155229161
Short name T276
Test name
Test status
Simulation time 73275110 ps
CPU time 2.53 seconds
Started Aug 02 05:13:09 PM PDT 24
Finished Aug 02 05:13:12 PM PDT 24
Peak memory 209848 kb
Host smart-d562720d-92c9-4523-b075-f959ff714f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155229161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3155229161
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.450053851
Short name T410
Test name
Test status
Simulation time 56803981 ps
CPU time 2.75 seconds
Started Aug 02 05:13:07 PM PDT 24
Finished Aug 02 05:13:10 PM PDT 24
Peak memory 208796 kb
Host smart-f2f50649-cc5f-4933-a517-5d76231c6313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450053851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.450053851
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3923993528
Short name T606
Test name
Test status
Simulation time 9011044688 ps
CPU time 37.84 seconds
Started Aug 02 05:13:09 PM PDT 24
Finished Aug 02 05:13:47 PM PDT 24
Peak memory 222472 kb
Host smart-478ee565-f375-455c-85ee-2223e31a6b50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923993528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3923993528
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1952382024
Short name T618
Test name
Test status
Simulation time 46050991 ps
CPU time 3.02 seconds
Started Aug 02 05:13:15 PM PDT 24
Finished Aug 02 05:13:18 PM PDT 24
Peak memory 207692 kb
Host smart-e46b57ba-cc61-4a2c-8531-530245e4cd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952382024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1952382024
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.4288297768
Short name T866
Test name
Test status
Simulation time 45716763 ps
CPU time 1.98 seconds
Started Aug 02 05:13:09 PM PDT 24
Finished Aug 02 05:13:11 PM PDT 24
Peak memory 210056 kb
Host smart-95e39f55-6aba-4a91-ad60-c2583343b54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288297768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.4288297768
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1184474432
Short name T468
Test name
Test status
Simulation time 19046671 ps
CPU time 0.69 seconds
Started Aug 02 05:13:18 PM PDT 24
Finished Aug 02 05:13:18 PM PDT 24
Peak memory 206000 kb
Host smart-7b3a773a-e9e3-4dbc-a994-f99f0eee56d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184474432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1184474432
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.193374932
Short name T38
Test name
Test status
Simulation time 490407067 ps
CPU time 5.22 seconds
Started Aug 02 05:13:12 PM PDT 24
Finished Aug 02 05:13:17 PM PDT 24
Peak memory 214316 kb
Host smart-c941c0c6-ab5a-40f1-83c3-68cc7de9af15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193374932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.193374932
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3421619334
Short name T546
Test name
Test status
Simulation time 78132933 ps
CPU time 3.46 seconds
Started Aug 02 05:13:04 PM PDT 24
Finished Aug 02 05:13:08 PM PDT 24
Peak memory 214320 kb
Host smart-f94f02f5-249d-4192-9c2f-6e1c54a1b2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421619334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3421619334
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3986532381
Short name T722
Test name
Test status
Simulation time 57592602 ps
CPU time 2.4 seconds
Started Aug 02 05:13:06 PM PDT 24
Finished Aug 02 05:13:09 PM PDT 24
Peak memory 214212 kb
Host smart-0ef77d5e-6a9e-48f8-8a1f-7b7c07ad0720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986532381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3986532381
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.980945770
Short name T640
Test name
Test status
Simulation time 171250297 ps
CPU time 2.92 seconds
Started Aug 02 05:13:09 PM PDT 24
Finished Aug 02 05:13:12 PM PDT 24
Peak memory 214984 kb
Host smart-4ad4c4ab-89d8-407f-b8c3-ee0161e136ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980945770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.980945770
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.196068059
Short name T187
Test name
Test status
Simulation time 86210821 ps
CPU time 3.23 seconds
Started Aug 02 05:13:03 PM PDT 24
Finished Aug 02 05:13:07 PM PDT 24
Peak memory 220020 kb
Host smart-da6bdc6b-2e8f-48f5-9b51-5cba4d1b8374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196068059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.196068059
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3006990101
Short name T259
Test name
Test status
Simulation time 113769937 ps
CPU time 5.24 seconds
Started Aug 02 05:13:11 PM PDT 24
Finished Aug 02 05:13:17 PM PDT 24
Peak memory 222356 kb
Host smart-4de3e945-5af3-4aed-a68b-65619e5ca77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006990101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3006990101
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2483188925
Short name T361
Test name
Test status
Simulation time 169722243 ps
CPU time 7.1 seconds
Started Aug 02 05:13:23 PM PDT 24
Finished Aug 02 05:13:30 PM PDT 24
Peak memory 207584 kb
Host smart-e95f2412-d828-4b75-aa49-6e508a51e637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483188925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2483188925
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1057411568
Short name T189
Test name
Test status
Simulation time 154264386 ps
CPU time 4.3 seconds
Started Aug 02 05:13:05 PM PDT 24
Finished Aug 02 05:13:10 PM PDT 24
Peak memory 207160 kb
Host smart-fb128789-c8cf-4708-b1b0-56c7074f9480
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057411568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1057411568
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.173240944
Short name T317
Test name
Test status
Simulation time 38090148 ps
CPU time 2.56 seconds
Started Aug 02 05:13:18 PM PDT 24
Finished Aug 02 05:13:20 PM PDT 24
Peak memory 208668 kb
Host smart-dfe09912-333d-4928-b85f-488723a981b3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173240944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.173240944
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.613799550
Short name T626
Test name
Test status
Simulation time 68316082 ps
CPU time 1.8 seconds
Started Aug 02 05:13:03 PM PDT 24
Finished Aug 02 05:13:04 PM PDT 24
Peak memory 207028 kb
Host smart-c986dd04-1b43-4dde-b7e6-7bdff76c043c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613799550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.613799550
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1871293399
Short name T385
Test name
Test status
Simulation time 205460528 ps
CPU time 5.9 seconds
Started Aug 02 05:13:10 PM PDT 24
Finished Aug 02 05:13:16 PM PDT 24
Peak memory 214300 kb
Host smart-1d01ee1a-c9ae-441f-aea9-cc28a251b363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871293399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1871293399
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1051018429
Short name T907
Test name
Test status
Simulation time 77575634 ps
CPU time 1.75 seconds
Started Aug 02 05:13:07 PM PDT 24
Finished Aug 02 05:13:08 PM PDT 24
Peak memory 206976 kb
Host smart-64662c5f-ff0e-4d39-b197-9b519748431e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051018429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1051018429
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.591632833
Short name T193
Test name
Test status
Simulation time 8686077684 ps
CPU time 25.56 seconds
Started Aug 02 05:13:05 PM PDT 24
Finished Aug 02 05:13:31 PM PDT 24
Peak memory 221248 kb
Host smart-0bc0de83-6d31-4afb-ac54-185663a23db4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591632833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.591632833
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.315296361
Short name T770
Test name
Test status
Simulation time 1688328895 ps
CPU time 7.83 seconds
Started Aug 02 05:12:59 PM PDT 24
Finished Aug 02 05:13:07 PM PDT 24
Peak memory 208536 kb
Host smart-a9171bc5-2cb6-4dca-8f46-7276108540ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315296361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.315296361
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2011365934
Short name T57
Test name
Test status
Simulation time 97152011 ps
CPU time 2.5 seconds
Started Aug 02 05:13:20 PM PDT 24
Finished Aug 02 05:13:23 PM PDT 24
Peak memory 210292 kb
Host smart-e2e9f245-bdb8-4e7e-82aa-fb51c9d50cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011365934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2011365934
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.471746537
Short name T442
Test name
Test status
Simulation time 25929708 ps
CPU time 0.76 seconds
Started Aug 02 05:13:10 PM PDT 24
Finished Aug 02 05:13:11 PM PDT 24
Peak memory 205980 kb
Host smart-4cbb0579-5950-4303-a225-da7de876f2d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471746537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.471746537
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2734657682
Short name T780
Test name
Test status
Simulation time 118398320 ps
CPU time 2.3 seconds
Started Aug 02 05:13:12 PM PDT 24
Finished Aug 02 05:13:15 PM PDT 24
Peak memory 220100 kb
Host smart-96d47109-3bed-427e-bd2b-7ac85731e5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734657682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2734657682
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.477203017
Short name T634
Test name
Test status
Simulation time 471867476 ps
CPU time 2.51 seconds
Started Aug 02 05:13:16 PM PDT 24
Finished Aug 02 05:13:19 PM PDT 24
Peak memory 208452 kb
Host smart-64868b78-1d7e-4794-92dc-ed46f074f759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477203017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.477203017
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1941325454
Short name T90
Test name
Test status
Simulation time 86423233 ps
CPU time 3.85 seconds
Started Aug 02 05:13:17 PM PDT 24
Finished Aug 02 05:13:21 PM PDT 24
Peak memory 208656 kb
Host smart-02f59207-a2b4-4f6a-9652-262c05618706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941325454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1941325454
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.494457517
Short name T808
Test name
Test status
Simulation time 160280760 ps
CPU time 3.43 seconds
Started Aug 02 05:13:11 PM PDT 24
Finished Aug 02 05:13:15 PM PDT 24
Peak memory 214204 kb
Host smart-694d164d-9a4d-454f-ae97-3d2cb7d4817f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494457517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.494457517
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2720261142
Short name T49
Test name
Test status
Simulation time 440747797 ps
CPU time 3.42 seconds
Started Aug 02 05:13:05 PM PDT 24
Finished Aug 02 05:13:09 PM PDT 24
Peak memory 214560 kb
Host smart-87155d13-947b-4164-ba21-3724f354fad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720261142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2720261142
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.200847026
Short name T748
Test name
Test status
Simulation time 169234699 ps
CPU time 4.22 seconds
Started Aug 02 05:13:23 PM PDT 24
Finished Aug 02 05:13:33 PM PDT 24
Peak memory 207252 kb
Host smart-0d2db351-ebd2-49f2-a1d0-f00a40d16456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200847026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.200847026
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.763691956
Short name T581
Test name
Test status
Simulation time 254780291 ps
CPU time 2.81 seconds
Started Aug 02 05:13:14 PM PDT 24
Finished Aug 02 05:13:17 PM PDT 24
Peak memory 206940 kb
Host smart-69c37518-9b4e-4355-8bcc-1ccf961a6533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763691956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.763691956
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.100847939
Short name T455
Test name
Test status
Simulation time 117984344 ps
CPU time 3.97 seconds
Started Aug 02 05:13:10 PM PDT 24
Finished Aug 02 05:13:14 PM PDT 24
Peak memory 206940 kb
Host smart-dcc14dba-e2aa-43bf-ac1a-69cdbf39092e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100847939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.100847939
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2404524552
Short name T503
Test name
Test status
Simulation time 525919239 ps
CPU time 3.05 seconds
Started Aug 02 05:13:06 PM PDT 24
Finished Aug 02 05:13:09 PM PDT 24
Peak memory 208672 kb
Host smart-0906c17f-246b-4f42-98db-ad6cb4b01c0e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404524552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2404524552
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.4025924008
Short name T798
Test name
Test status
Simulation time 568187880 ps
CPU time 4.24 seconds
Started Aug 02 05:13:04 PM PDT 24
Finished Aug 02 05:13:08 PM PDT 24
Peak memory 208156 kb
Host smart-2d2f6b9e-8c2e-4682-a487-98dab068f68b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025924008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.4025924008
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3121610141
Short name T724
Test name
Test status
Simulation time 1292333564 ps
CPU time 3.93 seconds
Started Aug 02 05:13:17 PM PDT 24
Finished Aug 02 05:13:21 PM PDT 24
Peak memory 216024 kb
Host smart-e88e64dc-8927-4016-8be0-ef299335c528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121610141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3121610141
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.559507689
Short name T79
Test name
Test status
Simulation time 372988496 ps
CPU time 4.6 seconds
Started Aug 02 05:13:18 PM PDT 24
Finished Aug 02 05:13:22 PM PDT 24
Peak memory 208044 kb
Host smart-d35f160d-9ddf-435d-984f-1ae042158c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559507689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.559507689
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3963793702
Short name T244
Test name
Test status
Simulation time 168367065448 ps
CPU time 308.2 seconds
Started Aug 02 05:13:07 PM PDT 24
Finished Aug 02 05:18:16 PM PDT 24
Peak memory 222568 kb
Host smart-a60086f3-b248-402c-bbb3-849ea8da9380
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963793702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3963793702
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.641716566
Short name T159
Test name
Test status
Simulation time 713542850 ps
CPU time 9.84 seconds
Started Aug 02 05:13:10 PM PDT 24
Finished Aug 02 05:13:19 PM PDT 24
Peak memory 222564 kb
Host smart-15631210-4134-4412-ad78-cb1b27ceebf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641716566 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.641716566
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.4214013065
Short name T871
Test name
Test status
Simulation time 125744015 ps
CPU time 5.73 seconds
Started Aug 02 05:13:12 PM PDT 24
Finished Aug 02 05:13:18 PM PDT 24
Peak memory 210232 kb
Host smart-3d45639d-0647-4708-853a-db67a9ec38ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214013065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.4214013065
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.46897920
Short name T788
Test name
Test status
Simulation time 97878123 ps
CPU time 2.83 seconds
Started Aug 02 05:13:38 PM PDT 24
Finished Aug 02 05:13:41 PM PDT 24
Peak memory 210432 kb
Host smart-2fc764bf-79d4-436b-a103-d9f3b30081cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46897920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.46897920
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.108738398
Short name T712
Test name
Test status
Simulation time 10508934 ps
CPU time 0.89 seconds
Started Aug 02 05:13:10 PM PDT 24
Finished Aug 02 05:13:11 PM PDT 24
Peak memory 205968 kb
Host smart-c4ee091c-f6b6-411e-bff2-69bdb7af2297
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108738398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.108738398
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.507028048
Short name T734
Test name
Test status
Simulation time 320404707 ps
CPU time 6.22 seconds
Started Aug 02 05:13:18 PM PDT 24
Finished Aug 02 05:13:25 PM PDT 24
Peak memory 214300 kb
Host smart-cd23141a-4bf6-4d8b-9dd5-8bd8183badf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507028048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.507028048
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2375415550
Short name T378
Test name
Test status
Simulation time 386044007 ps
CPU time 4.46 seconds
Started Aug 02 05:13:09 PM PDT 24
Finished Aug 02 05:13:14 PM PDT 24
Peak memory 209280 kb
Host smart-e2fad64e-8282-4140-81cb-d027fbb5ee51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375415550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2375415550
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1661574340
Short name T669
Test name
Test status
Simulation time 480105904 ps
CPU time 3.85 seconds
Started Aug 02 05:13:12 PM PDT 24
Finished Aug 02 05:13:17 PM PDT 24
Peak memory 218660 kb
Host smart-f60b6459-7487-486d-bb67-1fe4897eed7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661574340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1661574340
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.834760657
Short name T904
Test name
Test status
Simulation time 1355548875 ps
CPU time 31.74 seconds
Started Aug 02 05:13:17 PM PDT 24
Finished Aug 02 05:13:49 PM PDT 24
Peak memory 209716 kb
Host smart-495d7ed0-ebdd-40de-81f9-3f3085d1ec81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834760657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.834760657
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.248629010
Short name T727
Test name
Test status
Simulation time 423605451 ps
CPU time 10.75 seconds
Started Aug 02 05:13:13 PM PDT 24
Finished Aug 02 05:13:24 PM PDT 24
Peak memory 207964 kb
Host smart-92e1d97e-31c3-44d5-986d-c3e1c54aa6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248629010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.248629010
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.596253368
Short name T511
Test name
Test status
Simulation time 54055906 ps
CPU time 2.31 seconds
Started Aug 02 05:13:17 PM PDT 24
Finished Aug 02 05:13:20 PM PDT 24
Peak memory 207404 kb
Host smart-58b719f2-e217-42ad-a66e-b83d7adc1e38
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596253368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.596253368
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1056444138
Short name T523
Test name
Test status
Simulation time 160113339 ps
CPU time 5.28 seconds
Started Aug 02 05:13:22 PM PDT 24
Finished Aug 02 05:13:28 PM PDT 24
Peak memory 207996 kb
Host smart-de680a77-c126-4fd3-b8bf-8c05ce5f1be0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056444138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1056444138
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.141054917
Short name T575
Test name
Test status
Simulation time 174902256 ps
CPU time 7.3 seconds
Started Aug 02 05:13:08 PM PDT 24
Finished Aug 02 05:13:15 PM PDT 24
Peak memory 208848 kb
Host smart-26c9d697-395d-413b-8247-7cacc5bbbb76
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141054917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.141054917
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3693568869
Short name T750
Test name
Test status
Simulation time 51961949 ps
CPU time 2.12 seconds
Started Aug 02 05:13:07 PM PDT 24
Finished Aug 02 05:13:10 PM PDT 24
Peak memory 214340 kb
Host smart-d6575a55-e468-46ef-b83b-6ad73a6397ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693568869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3693568869
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3190677239
Short name T495
Test name
Test status
Simulation time 284301154 ps
CPU time 3.04 seconds
Started Aug 02 05:13:16 PM PDT 24
Finished Aug 02 05:13:20 PM PDT 24
Peak memory 208460 kb
Host smart-1e66e65d-1193-47da-8cba-8bef25e71991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190677239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3190677239
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1740938822
Short name T783
Test name
Test status
Simulation time 2071387115 ps
CPU time 39.67 seconds
Started Aug 02 05:13:12 PM PDT 24
Finished Aug 02 05:13:52 PM PDT 24
Peak memory 222456 kb
Host smart-38814844-93f4-42c3-86c2-faa329fbc3b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740938822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1740938822
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.1121639225
Short name T179
Test name
Test status
Simulation time 3785507345 ps
CPU time 27.54 seconds
Started Aug 02 05:13:13 PM PDT 24
Finished Aug 02 05:13:41 PM PDT 24
Peak memory 222492 kb
Host smart-294d36e7-5468-4aa6-ad7c-a408aba1f33c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121639225 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.1121639225
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.493654313
Short name T688
Test name
Test status
Simulation time 249405209 ps
CPU time 5.9 seconds
Started Aug 02 05:13:12 PM PDT 24
Finished Aug 02 05:13:18 PM PDT 24
Peak memory 214244 kb
Host smart-a1b133ee-cc69-4ae7-a4e9-e10ac745aa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493654313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.493654313
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1002002930
Short name T694
Test name
Test status
Simulation time 130580318 ps
CPU time 2.03 seconds
Started Aug 02 05:13:10 PM PDT 24
Finished Aug 02 05:13:12 PM PDT 24
Peak memory 209636 kb
Host smart-58c0531e-8944-4652-9726-eaf8df889401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002002930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1002002930
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1906427310
Short name T642
Test name
Test status
Simulation time 29599165 ps
CPU time 0.82 seconds
Started Aug 02 05:13:19 PM PDT 24
Finished Aug 02 05:13:20 PM PDT 24
Peak memory 206024 kb
Host smart-87b82d18-66b1-4104-96ac-dce7de6babb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906427310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1906427310
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1954706740
Short name T895
Test name
Test status
Simulation time 1649718558 ps
CPU time 13.76 seconds
Started Aug 02 05:13:13 PM PDT 24
Finished Aug 02 05:13:27 PM PDT 24
Peak memory 208916 kb
Host smart-d7709834-c086-41fd-a355-7ba9f002246a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954706740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1954706740
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3075797075
Short name T698
Test name
Test status
Simulation time 477146224 ps
CPU time 5.43 seconds
Started Aug 02 05:13:05 PM PDT 24
Finished Aug 02 05:13:11 PM PDT 24
Peak memory 214548 kb
Host smart-f7eddf55-5488-49a4-b068-da0d7f6b2a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075797075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3075797075
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3386744343
Short name T265
Test name
Test status
Simulation time 44064078 ps
CPU time 2.42 seconds
Started Aug 02 05:13:10 PM PDT 24
Finished Aug 02 05:13:13 PM PDT 24
Peak memory 214476 kb
Host smart-8e41642c-342c-4abe-8252-37e8e45765bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386744343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3386744343
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3803363138
Short name T483
Test name
Test status
Simulation time 155157726 ps
CPU time 3.27 seconds
Started Aug 02 05:13:16 PM PDT 24
Finished Aug 02 05:13:20 PM PDT 24
Peak memory 208748 kb
Host smart-4f4a5179-cd8e-4c1a-9da4-9095c0417776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803363138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3803363138
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.768560267
Short name T596
Test name
Test status
Simulation time 88494154 ps
CPU time 3.75 seconds
Started Aug 02 05:13:24 PM PDT 24
Finished Aug 02 05:13:28 PM PDT 24
Peak memory 207952 kb
Host smart-fa9f003e-3072-4e2d-a56a-216a32547ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768560267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.768560267
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.851445106
Short name T833
Test name
Test status
Simulation time 111824111 ps
CPU time 3.01 seconds
Started Aug 02 05:13:11 PM PDT 24
Finished Aug 02 05:13:15 PM PDT 24
Peak memory 208772 kb
Host smart-d4d35f4c-8f88-4e43-b332-f1374b900142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851445106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.851445106
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1017353188
Short name T744
Test name
Test status
Simulation time 132568301 ps
CPU time 4.42 seconds
Started Aug 02 05:13:08 PM PDT 24
Finished Aug 02 05:13:13 PM PDT 24
Peak memory 208028 kb
Host smart-e4214552-abc0-41b5-be29-d57ea3157ff9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017353188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1017353188
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.411060986
Short name T714
Test name
Test status
Simulation time 641867702 ps
CPU time 6.9 seconds
Started Aug 02 05:13:08 PM PDT 24
Finished Aug 02 05:13:15 PM PDT 24
Peak memory 208060 kb
Host smart-71996711-01d5-4262-ac0c-ece9076e9785
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411060986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.411060986
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3891009184
Short name T777
Test name
Test status
Simulation time 1197603204 ps
CPU time 14.64 seconds
Started Aug 02 05:13:18 PM PDT 24
Finished Aug 02 05:13:33 PM PDT 24
Peak memory 208064 kb
Host smart-ce364f38-f50e-455a-8010-43d27c5d53b0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891009184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3891009184
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3322070202
Short name T426
Test name
Test status
Simulation time 216687037 ps
CPU time 6.86 seconds
Started Aug 02 05:13:17 PM PDT 24
Finished Aug 02 05:13:24 PM PDT 24
Peak memory 208908 kb
Host smart-51b9ae9d-2f65-4e7d-974a-c29da169d18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322070202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3322070202
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.374625203
Short name T501
Test name
Test status
Simulation time 717436447 ps
CPU time 18.36 seconds
Started Aug 02 05:13:38 PM PDT 24
Finished Aug 02 05:13:56 PM PDT 24
Peak memory 207864 kb
Host smart-1a883af5-148e-427a-b387-6f6533b67f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374625203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.374625203
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.587720856
Short name T26
Test name
Test status
Simulation time 234483684 ps
CPU time 5.16 seconds
Started Aug 02 05:13:19 PM PDT 24
Finished Aug 02 05:13:25 PM PDT 24
Peak memory 219664 kb
Host smart-bd96911b-d784-4c35-8ea3-48cf25fd5ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587720856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.587720856
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1065503268
Short name T50
Test name
Test status
Simulation time 158306261 ps
CPU time 1.68 seconds
Started Aug 02 05:13:10 PM PDT 24
Finished Aug 02 05:13:12 PM PDT 24
Peak memory 210140 kb
Host smart-f394cdaa-8e68-430b-80f2-91147ac43b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065503268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1065503268
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.3398729710
Short name T873
Test name
Test status
Simulation time 12353207 ps
CPU time 0.91 seconds
Started Aug 02 05:12:13 PM PDT 24
Finished Aug 02 05:12:14 PM PDT 24
Peak memory 205980 kb
Host smart-13e78b59-8470-4daf-9b84-8785a98099ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398729710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3398729710
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.62708513
Short name T116
Test name
Test status
Simulation time 56670054 ps
CPU time 3.44 seconds
Started Aug 02 05:12:14 PM PDT 24
Finished Aug 02 05:12:18 PM PDT 24
Peak memory 214224 kb
Host smart-666dc85a-c055-4b30-9b04-b15256b1c4da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=62708513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.62708513
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2143903688
Short name T671
Test name
Test status
Simulation time 169002652 ps
CPU time 3.17 seconds
Started Aug 02 05:11:59 PM PDT 24
Finished Aug 02 05:12:03 PM PDT 24
Peak memory 222608 kb
Host smart-d76d89c6-af14-4109-a83b-9198ab229fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143903688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2143903688
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2449881775
Short name T784
Test name
Test status
Simulation time 162384412 ps
CPU time 1.65 seconds
Started Aug 02 05:12:09 PM PDT 24
Finished Aug 02 05:12:11 PM PDT 24
Peak memory 207572 kb
Host smart-b07bb50f-35f7-49c8-965b-543608324d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449881775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2449881775
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2200271130
Short name T264
Test name
Test status
Simulation time 34386939 ps
CPU time 2.48 seconds
Started Aug 02 05:12:10 PM PDT 24
Finished Aug 02 05:12:13 PM PDT 24
Peak memory 214424 kb
Host smart-56b35b51-59ac-4ca7-9c12-c00351247a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200271130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2200271130
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2315290226
Short name T815
Test name
Test status
Simulation time 904880314 ps
CPU time 2.25 seconds
Started Aug 02 05:12:14 PM PDT 24
Finished Aug 02 05:12:16 PM PDT 24
Peak memory 216508 kb
Host smart-9d05f814-b500-4c52-aeca-50481286901d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315290226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2315290226
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2084852994
Short name T850
Test name
Test status
Simulation time 4726857931 ps
CPU time 43.72 seconds
Started Aug 02 05:11:53 PM PDT 24
Finished Aug 02 05:12:37 PM PDT 24
Peak memory 208724 kb
Host smart-c0ec0186-4439-424a-8cec-97c0eb76ab33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084852994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2084852994
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1504041256
Short name T40
Test name
Test status
Simulation time 2380251298 ps
CPU time 14.79 seconds
Started Aug 02 05:12:18 PM PDT 24
Finished Aug 02 05:12:33 PM PDT 24
Peak memory 235604 kb
Host smart-7527be16-6fc9-40de-8f25-d0fcc9984b60
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504041256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1504041256
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.441940270
Short name T505
Test name
Test status
Simulation time 51416035 ps
CPU time 2.83 seconds
Started Aug 02 05:12:07 PM PDT 24
Finished Aug 02 05:12:10 PM PDT 24
Peak memory 207064 kb
Host smart-99602dcd-2429-4403-bbeb-6852b8491389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441940270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.441940270
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.249099268
Short name T408
Test name
Test status
Simulation time 2598923809 ps
CPU time 22.17 seconds
Started Aug 02 05:12:04 PM PDT 24
Finished Aug 02 05:12:27 PM PDT 24
Peak memory 207904 kb
Host smart-97478be0-6884-45aa-ae29-2a034a3daeae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249099268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.249099268
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2464945146
Short name T835
Test name
Test status
Simulation time 90734649 ps
CPU time 2.69 seconds
Started Aug 02 05:12:09 PM PDT 24
Finished Aug 02 05:12:12 PM PDT 24
Peak memory 206936 kb
Host smart-f3254eb2-c54d-49a6-a23d-42738184ef41
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464945146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2464945146
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1468472840
Short name T83
Test name
Test status
Simulation time 163853257 ps
CPU time 3.96 seconds
Started Aug 02 05:12:10 PM PDT 24
Finished Aug 02 05:12:14 PM PDT 24
Peak memory 208688 kb
Host smart-7ef5bcb7-9482-4ec7-95e3-13e7496afdc7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468472840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1468472840
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1149157746
Short name T238
Test name
Test status
Simulation time 2538882088 ps
CPU time 23.79 seconds
Started Aug 02 05:12:12 PM PDT 24
Finished Aug 02 05:12:36 PM PDT 24
Peak memory 209708 kb
Host smart-a96d2f13-74fe-43e4-8ba1-91c3c6b28d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149157746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1149157746
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3251618534
Short name T446
Test name
Test status
Simulation time 234448868 ps
CPU time 2.92 seconds
Started Aug 02 05:12:09 PM PDT 24
Finished Aug 02 05:12:12 PM PDT 24
Peak memory 208592 kb
Host smart-172f31f6-e94e-4e0a-9e39-7e2dc0260405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251618534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3251618534
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.457262473
Short name T237
Test name
Test status
Simulation time 350847231 ps
CPU time 4.69 seconds
Started Aug 02 05:12:14 PM PDT 24
Finished Aug 02 05:12:18 PM PDT 24
Peak memory 207600 kb
Host smart-b1f8a192-d6a5-42f8-91ac-91e8984236d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457262473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.457262473
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2629348682
Short name T902
Test name
Test status
Simulation time 41515411 ps
CPU time 1.51 seconds
Started Aug 02 05:12:02 PM PDT 24
Finished Aug 02 05:12:04 PM PDT 24
Peak memory 210272 kb
Host smart-3c4040a7-2f00-47f9-b786-dae250a09f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629348682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2629348682
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3490380055
Short name T454
Test name
Test status
Simulation time 34424302 ps
CPU time 0.69 seconds
Started Aug 02 05:13:20 PM PDT 24
Finished Aug 02 05:13:20 PM PDT 24
Peak memory 205808 kb
Host smart-a0015b6e-1feb-4018-95a0-c6782cf79662
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490380055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3490380055
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.144355645
Short name T225
Test name
Test status
Simulation time 291787254 ps
CPU time 2.79 seconds
Started Aug 02 05:13:16 PM PDT 24
Finished Aug 02 05:13:19 PM PDT 24
Peak memory 209808 kb
Host smart-56a3a7dc-c1f3-4fc3-994e-98bc0e9179e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144355645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.144355645
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3619557934
Short name T735
Test name
Test status
Simulation time 712540509 ps
CPU time 2.24 seconds
Started Aug 02 05:13:08 PM PDT 24
Finished Aug 02 05:13:10 PM PDT 24
Peak memory 208676 kb
Host smart-51f95a56-9ee6-494b-9ccc-3379860e05ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619557934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3619557934
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3546921675
Short name T676
Test name
Test status
Simulation time 101403852 ps
CPU time 1.68 seconds
Started Aug 02 05:13:24 PM PDT 24
Finished Aug 02 05:13:26 PM PDT 24
Peak memory 214360 kb
Host smart-2960bdaa-5095-4e80-9d5c-4edb9adef5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546921675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3546921675
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.891963263
Short name T393
Test name
Test status
Simulation time 46870483 ps
CPU time 1.8 seconds
Started Aug 02 05:13:21 PM PDT 24
Finished Aug 02 05:13:22 PM PDT 24
Peak memory 214268 kb
Host smart-887f5868-1a02-4ed1-ba4f-f722e2f0a526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891963263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.891963263
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.1167823617
Short name T484
Test name
Test status
Simulation time 416124029 ps
CPU time 5.04 seconds
Started Aug 02 05:13:12 PM PDT 24
Finished Aug 02 05:13:18 PM PDT 24
Peak memory 215220 kb
Host smart-aa3b2e41-6c70-49f3-a4f5-9ce0e52aad0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167823617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1167823617
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.495672309
Short name T521
Test name
Test status
Simulation time 1065290633 ps
CPU time 25.73 seconds
Started Aug 02 05:13:07 PM PDT 24
Finished Aug 02 05:13:33 PM PDT 24
Peak memory 208812 kb
Host smart-5656edc0-f01e-429f-ad19-93c387d029d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495672309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.495672309
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3515184903
Short name T775
Test name
Test status
Simulation time 62992191 ps
CPU time 2.9 seconds
Started Aug 02 05:13:27 PM PDT 24
Finished Aug 02 05:13:30 PM PDT 24
Peak memory 208012 kb
Host smart-dccd0b62-0727-40a1-bde3-901c7d3bd90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515184903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3515184903
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2274627524
Short name T539
Test name
Test status
Simulation time 348258888 ps
CPU time 3.05 seconds
Started Aug 02 05:13:19 PM PDT 24
Finished Aug 02 05:13:22 PM PDT 24
Peak memory 208804 kb
Host smart-7c4cfd2c-ac06-4f03-948b-b74ae21155ba
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274627524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2274627524
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3107533317
Short name T803
Test name
Test status
Simulation time 394848416 ps
CPU time 8.28 seconds
Started Aug 02 05:13:34 PM PDT 24
Finished Aug 02 05:13:42 PM PDT 24
Peak memory 208996 kb
Host smart-f436c982-5e96-4329-a5ea-8e614630e110
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107533317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3107533317
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.303907682
Short name T307
Test name
Test status
Simulation time 82951001 ps
CPU time 3.09 seconds
Started Aug 02 05:13:17 PM PDT 24
Finished Aug 02 05:13:20 PM PDT 24
Peak memory 206992 kb
Host smart-08bbef38-bd66-4149-bcfb-404ca3ab66ee
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303907682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.303907682
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.1113931196
Short name T680
Test name
Test status
Simulation time 51111532 ps
CPU time 3.06 seconds
Started Aug 02 05:13:35 PM PDT 24
Finished Aug 02 05:13:38 PM PDT 24
Peak memory 220524 kb
Host smart-dea1da76-d7e5-4400-b837-a2b2634cd4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113931196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1113931196
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.4259926176
Short name T202
Test name
Test status
Simulation time 274329072 ps
CPU time 2.78 seconds
Started Aug 02 05:13:14 PM PDT 24
Finished Aug 02 05:13:16 PM PDT 24
Peak memory 206524 kb
Host smart-1a87ba84-d46b-46ae-beed-9cfbb615f100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259926176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.4259926176
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2162635318
Short name T126
Test name
Test status
Simulation time 255101595 ps
CPU time 10.65 seconds
Started Aug 02 05:13:19 PM PDT 24
Finished Aug 02 05:13:30 PM PDT 24
Peak memory 219700 kb
Host smart-d59cedad-9159-4b07-882e-6d7cd3bf689b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162635318 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2162635318
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3114159785
Short name T198
Test name
Test status
Simulation time 123750784 ps
CPU time 6.36 seconds
Started Aug 02 05:13:19 PM PDT 24
Finished Aug 02 05:13:25 PM PDT 24
Peak memory 209972 kb
Host smart-88878f95-fc3d-4afc-bbcc-03fb1702ee48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114159785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3114159785
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.330351154
Short name T740
Test name
Test status
Simulation time 209999368 ps
CPU time 5.58 seconds
Started Aug 02 05:13:22 PM PDT 24
Finished Aug 02 05:13:28 PM PDT 24
Peak memory 210176 kb
Host smart-a4ecbf1f-270d-49fc-8e4d-acb1a7c257e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330351154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.330351154
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2797666342
Short name T897
Test name
Test status
Simulation time 12591959 ps
CPU time 0.86 seconds
Started Aug 02 05:13:29 PM PDT 24
Finished Aug 02 05:13:30 PM PDT 24
Peak memory 206024 kb
Host smart-13487566-bce7-4658-b1c0-cc6d275d9cfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797666342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2797666342
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.4186764437
Short name T342
Test name
Test status
Simulation time 182788636 ps
CPU time 5.55 seconds
Started Aug 02 05:13:26 PM PDT 24
Finished Aug 02 05:13:31 PM PDT 24
Peak memory 214908 kb
Host smart-cfcc090d-5d03-43c3-8e7d-f1e55f05bd30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4186764437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.4186764437
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.959161315
Short name T593
Test name
Test status
Simulation time 267783265 ps
CPU time 3.06 seconds
Started Aug 02 05:13:16 PM PDT 24
Finished Aug 02 05:13:19 PM PDT 24
Peak memory 218396 kb
Host smart-6fa9501e-6072-429c-af22-21f10188028c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959161315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.959161315
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1315275894
Short name T91
Test name
Test status
Simulation time 6988216132 ps
CPU time 38.48 seconds
Started Aug 02 05:13:27 PM PDT 24
Finished Aug 02 05:14:08 PM PDT 24
Peak memory 214372 kb
Host smart-a36a7f33-297d-4563-a939-afc277a302a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315275894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1315275894
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3166086690
Short name T248
Test name
Test status
Simulation time 141600878 ps
CPU time 2.61 seconds
Started Aug 02 05:13:32 PM PDT 24
Finished Aug 02 05:13:35 PM PDT 24
Peak memory 214144 kb
Host smart-ede2c429-bb38-4da8-80cf-5c9293efc4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166086690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3166086690
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.4264148204
Short name T144
Test name
Test status
Simulation time 25323832 ps
CPU time 1.86 seconds
Started Aug 02 05:13:13 PM PDT 24
Finished Aug 02 05:13:15 PM PDT 24
Peak memory 208052 kb
Host smart-9f72fc30-8f72-49c6-9e5e-d9909c91b95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264148204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.4264148204
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.94885460
Short name T473
Test name
Test status
Simulation time 599393093 ps
CPU time 15.08 seconds
Started Aug 02 05:13:22 PM PDT 24
Finished Aug 02 05:13:37 PM PDT 24
Peak memory 214376 kb
Host smart-6306a2ee-984d-4199-875a-80c01d902d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94885460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.94885460
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3056323514
Short name T797
Test name
Test status
Simulation time 62681314 ps
CPU time 2.76 seconds
Started Aug 02 05:13:10 PM PDT 24
Finished Aug 02 05:13:13 PM PDT 24
Peak memory 207004 kb
Host smart-85770d0d-d832-4b9d-b9ea-efb4e65f7e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056323514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3056323514
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.617291827
Short name T207
Test name
Test status
Simulation time 833329962 ps
CPU time 19.19 seconds
Started Aug 02 05:13:33 PM PDT 24
Finished Aug 02 05:13:52 PM PDT 24
Peak memory 208156 kb
Host smart-ebcbc7b7-9f00-4600-a0e6-b82969878a97
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617291827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.617291827
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1130620699
Short name T654
Test name
Test status
Simulation time 157613455 ps
CPU time 4.83 seconds
Started Aug 02 05:13:21 PM PDT 24
Finished Aug 02 05:13:26 PM PDT 24
Peak memory 208660 kb
Host smart-96ceb68a-1986-4415-886c-79ea490f5e51
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130620699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1130620699
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1613426873
Short name T599
Test name
Test status
Simulation time 307366954 ps
CPU time 3.03 seconds
Started Aug 02 05:13:12 PM PDT 24
Finished Aug 02 05:13:16 PM PDT 24
Peak memory 208728 kb
Host smart-ddc4526c-40aa-42cd-9d35-84d8a69aee72
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613426873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1613426873
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.390896958
Short name T811
Test name
Test status
Simulation time 87730481 ps
CPU time 3.32 seconds
Started Aug 02 05:13:20 PM PDT 24
Finished Aug 02 05:13:23 PM PDT 24
Peak memory 208776 kb
Host smart-ddd52e7e-d61e-4dc7-b689-f60374d05ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390896958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.390896958
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3333945538
Short name T565
Test name
Test status
Simulation time 119331174 ps
CPU time 2.72 seconds
Started Aug 02 05:13:31 PM PDT 24
Finished Aug 02 05:13:34 PM PDT 24
Peak memory 208612 kb
Host smart-79883912-910d-4119-916c-444c876717f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333945538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3333945538
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.486881945
Short name T229
Test name
Test status
Simulation time 1875654506 ps
CPU time 30.2 seconds
Started Aug 02 05:13:28 PM PDT 24
Finished Aug 02 05:14:00 PM PDT 24
Peak memory 222632 kb
Host smart-d20e27fe-f244-455d-9ecc-aed1279e23c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486881945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.486881945
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1352584520
Short name T823
Test name
Test status
Simulation time 54070253 ps
CPU time 2.51 seconds
Started Aug 02 05:13:30 PM PDT 24
Finished Aug 02 05:13:37 PM PDT 24
Peak memory 207796 kb
Host smart-def60333-4b4a-4b11-8194-b348797726e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352584520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1352584520
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2748805736
Short name T805
Test name
Test status
Simulation time 149413676 ps
CPU time 1.9 seconds
Started Aug 02 05:13:17 PM PDT 24
Finished Aug 02 05:13:19 PM PDT 24
Peak memory 209692 kb
Host smart-dc3fb8b2-f9b4-4756-9317-2441ad1a6952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748805736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2748805736
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.4060225082
Short name T830
Test name
Test status
Simulation time 12704320 ps
CPU time 0.92 seconds
Started Aug 02 05:13:28 PM PDT 24
Finished Aug 02 05:13:29 PM PDT 24
Peak memory 206144 kb
Host smart-642d4d62-cad6-4903-a981-5b74f1cf0749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060225082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.4060225082
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.735032506
Short name T341
Test name
Test status
Simulation time 129225407 ps
CPU time 6.27 seconds
Started Aug 02 05:13:46 PM PDT 24
Finished Aug 02 05:13:52 PM PDT 24
Peak memory 214360 kb
Host smart-bac6061e-5007-4662-a00e-4982894ed843
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=735032506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.735032506
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.654641713
Short name T908
Test name
Test status
Simulation time 142354793 ps
CPU time 2.22 seconds
Started Aug 02 05:13:45 PM PDT 24
Finished Aug 02 05:13:48 PM PDT 24
Peak memory 214296 kb
Host smart-87e99a13-3ace-47ce-9b6c-f301960eefec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654641713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.654641713
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.166272668
Short name T85
Test name
Test status
Simulation time 114762701 ps
CPU time 5.09 seconds
Started Aug 02 05:13:17 PM PDT 24
Finished Aug 02 05:13:22 PM PDT 24
Peak memory 222336 kb
Host smart-ab8b7b7b-dd28-4dd9-8604-30aea8216ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166272668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.166272668
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3140176270
Short name T351
Test name
Test status
Simulation time 59170527 ps
CPU time 2.52 seconds
Started Aug 02 05:13:17 PM PDT 24
Finished Aug 02 05:13:20 PM PDT 24
Peak memory 205940 kb
Host smart-0076a692-4cea-4d4b-88ba-228a171cef39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140176270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3140176270
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3290819416
Short name T733
Test name
Test status
Simulation time 49666338 ps
CPU time 3.43 seconds
Started Aug 02 05:13:33 PM PDT 24
Finished Aug 02 05:13:37 PM PDT 24
Peak memory 214220 kb
Host smart-b6713124-0fe3-4144-ab5e-9900662cadf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290819416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3290819416
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.665518727
Short name T366
Test name
Test status
Simulation time 67261017 ps
CPU time 4.1 seconds
Started Aug 02 05:13:20 PM PDT 24
Finished Aug 02 05:13:24 PM PDT 24
Peak memory 214432 kb
Host smart-ce272812-88a2-4418-b90a-91a84bf5a28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665518727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.665518727
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3274452832
Short name T666
Test name
Test status
Simulation time 153436172 ps
CPU time 3.17 seconds
Started Aug 02 05:13:21 PM PDT 24
Finished Aug 02 05:13:25 PM PDT 24
Peak memory 208392 kb
Host smart-37bcb9c0-c4e0-4091-b532-38c04bc32501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274452832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3274452832
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1947197887
Short name T479
Test name
Test status
Simulation time 290615861 ps
CPU time 3.23 seconds
Started Aug 02 05:13:18 PM PDT 24
Finished Aug 02 05:13:22 PM PDT 24
Peak memory 208620 kb
Host smart-4c631e8b-bdc3-41a9-b2d4-148a8f4f73e1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947197887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1947197887
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.340936773
Short name T893
Test name
Test status
Simulation time 243847339 ps
CPU time 3.36 seconds
Started Aug 02 05:13:31 PM PDT 24
Finished Aug 02 05:13:35 PM PDT 24
Peak memory 208976 kb
Host smart-9b1d7f2d-a18d-4235-8418-9fe5f4ff429d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340936773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.340936773
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2668110314
Short name T786
Test name
Test status
Simulation time 239547071 ps
CPU time 6.15 seconds
Started Aug 02 05:13:23 PM PDT 24
Finished Aug 02 05:13:29 PM PDT 24
Peak memory 208328 kb
Host smart-9df01cc3-bdd9-4833-86a5-4351c988cb32
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668110314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2668110314
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2827474668
Short name T321
Test name
Test status
Simulation time 64966292 ps
CPU time 2.31 seconds
Started Aug 02 05:13:17 PM PDT 24
Finished Aug 02 05:13:20 PM PDT 24
Peak memory 209396 kb
Host smart-0468904c-a712-43f1-9f4b-ea29517bf5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827474668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2827474668
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.4036496879
Short name T874
Test name
Test status
Simulation time 10061161598 ps
CPU time 27.37 seconds
Started Aug 02 05:13:19 PM PDT 24
Finished Aug 02 05:13:46 PM PDT 24
Peak memory 209120 kb
Host smart-f509f495-4bd9-446a-bdcc-7eab697e08df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036496879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.4036496879
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.383199877
Short name T304
Test name
Test status
Simulation time 16733671066 ps
CPU time 185.73 seconds
Started Aug 02 05:13:38 PM PDT 24
Finished Aug 02 05:16:44 PM PDT 24
Peak memory 222600 kb
Host smart-6efe9d39-6f42-484f-931b-3e489b8d1e2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383199877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.383199877
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.968128196
Short name T72
Test name
Test status
Simulation time 533328047 ps
CPU time 14.33 seconds
Started Aug 02 05:13:21 PM PDT 24
Finished Aug 02 05:13:35 PM PDT 24
Peak memory 222620 kb
Host smart-99b8d9a3-f75b-4429-a8dc-5aae6107c4bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968128196 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.968128196
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2243548956
Short name T623
Test name
Test status
Simulation time 262480614 ps
CPU time 5.74 seconds
Started Aug 02 05:13:19 PM PDT 24
Finished Aug 02 05:13:25 PM PDT 24
Peak memory 208792 kb
Host smart-f4077a87-2aa2-49e7-952c-f1ade6b22df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243548956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2243548956
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1623800015
Short name T876
Test name
Test status
Simulation time 50829811 ps
CPU time 1.19 seconds
Started Aug 02 05:13:18 PM PDT 24
Finished Aug 02 05:13:24 PM PDT 24
Peak memory 208424 kb
Host smart-b1cbda25-9435-43a2-85b2-eeaaac3dba9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623800015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1623800015
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3442523495
Short name T527
Test name
Test status
Simulation time 42275774 ps
CPU time 0.78 seconds
Started Aug 02 05:13:20 PM PDT 24
Finished Aug 02 05:13:21 PM PDT 24
Peak memory 205920 kb
Host smart-e3c6fa59-23e6-42f3-8298-ad4e535e1563
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442523495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3442523495
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2676521947
Short name T801
Test name
Test status
Simulation time 38063459 ps
CPU time 2.4 seconds
Started Aug 02 05:13:31 PM PDT 24
Finished Aug 02 05:13:34 PM PDT 24
Peak memory 219524 kb
Host smart-78ab756a-bccf-4436-bdd6-5484902ddc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676521947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2676521947
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2872670126
Short name T395
Test name
Test status
Simulation time 151969003 ps
CPU time 3.46 seconds
Started Aug 02 05:13:21 PM PDT 24
Finished Aug 02 05:13:25 PM PDT 24
Peak memory 214324 kb
Host smart-e5fa74f9-3e0f-4583-a768-04302c79ebd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872670126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2872670126
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2409619304
Short name T504
Test name
Test status
Simulation time 137122234 ps
CPU time 2.78 seconds
Started Aug 02 05:13:19 PM PDT 24
Finished Aug 02 05:13:22 PM PDT 24
Peak memory 214212 kb
Host smart-aa6f4878-a2d3-4ed8-b0c7-5f83a7a874a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409619304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2409619304
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.4239558337
Short name T524
Test name
Test status
Simulation time 210477554 ps
CPU time 3.83 seconds
Started Aug 02 05:13:20 PM PDT 24
Finished Aug 02 05:13:24 PM PDT 24
Peak memory 207968 kb
Host smart-c3f61e42-1f0e-40aa-bf0f-30e5223fc3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239558337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.4239558337
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.103121814
Short name T489
Test name
Test status
Simulation time 91731093 ps
CPU time 2.25 seconds
Started Aug 02 05:13:18 PM PDT 24
Finished Aug 02 05:13:21 PM PDT 24
Peak memory 208756 kb
Host smart-cc4e050f-bc03-469c-a73e-b551377b6e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103121814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.103121814
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.4036722490
Short name T625
Test name
Test status
Simulation time 441742030 ps
CPU time 3.77 seconds
Started Aug 02 05:13:23 PM PDT 24
Finished Aug 02 05:13:27 PM PDT 24
Peak memory 206808 kb
Host smart-9f9bedc0-3346-4c08-98c1-66d70531419f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036722490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.4036722490
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3516502915
Short name T860
Test name
Test status
Simulation time 1408588789 ps
CPU time 5.75 seconds
Started Aug 02 05:13:20 PM PDT 24
Finished Aug 02 05:13:26 PM PDT 24
Peak memory 208156 kb
Host smart-a26a7a72-e441-4624-bf95-c3a6e280a867
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516502915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3516502915
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2950867636
Short name T552
Test name
Test status
Simulation time 67775470 ps
CPU time 3.03 seconds
Started Aug 02 05:13:19 PM PDT 24
Finished Aug 02 05:13:22 PM PDT 24
Peak memory 207220 kb
Host smart-bf846a72-1966-4a47-a27a-62a3cf91a242
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950867636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2950867636
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1028002622
Short name T299
Test name
Test status
Simulation time 138882367 ps
CPU time 2.93 seconds
Started Aug 02 05:13:20 PM PDT 24
Finished Aug 02 05:13:23 PM PDT 24
Peak memory 209684 kb
Host smart-e2e0520b-a248-4942-aea7-98bec6182c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028002622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1028002622
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2625148229
Short name T753
Test name
Test status
Simulation time 947934369 ps
CPU time 3.02 seconds
Started Aug 02 05:13:17 PM PDT 24
Finished Aug 02 05:13:20 PM PDT 24
Peak memory 208304 kb
Host smart-4800115c-a955-4753-9be3-ab720590fbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625148229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2625148229
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1755925417
Short name T896
Test name
Test status
Simulation time 2942634988 ps
CPU time 70.52 seconds
Started Aug 02 05:13:24 PM PDT 24
Finished Aug 02 05:14:35 PM PDT 24
Peak memory 216376 kb
Host smart-6fca424b-5413-44a9-b5a7-793150688684
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755925417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1755925417
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1405891171
Short name T383
Test name
Test status
Simulation time 157660095 ps
CPU time 6.14 seconds
Started Aug 02 05:13:19 PM PDT 24
Finished Aug 02 05:13:25 PM PDT 24
Peak memory 207672 kb
Host smart-c31e4915-1514-4440-b123-0d276248a66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405891171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1405891171
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1394896719
Short name T196
Test name
Test status
Simulation time 189425648 ps
CPU time 2.37 seconds
Started Aug 02 05:13:16 PM PDT 24
Finished Aug 02 05:13:19 PM PDT 24
Peak memory 210136 kb
Host smart-a4dead99-d891-4ced-b83b-52437134d5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394896719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1394896719
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2631764030
Short name T572
Test name
Test status
Simulation time 15122275 ps
CPU time 0.77 seconds
Started Aug 02 05:13:27 PM PDT 24
Finished Aug 02 05:13:27 PM PDT 24
Peak memory 205896 kb
Host smart-0a0f31d9-e938-4341-9de9-0f249fb55ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631764030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2631764030
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1893791369
Short name T435
Test name
Test status
Simulation time 212025152 ps
CPU time 11.79 seconds
Started Aug 02 05:13:46 PM PDT 24
Finished Aug 02 05:13:58 PM PDT 24
Peak memory 215472 kb
Host smart-cfefb686-0aa1-4953-9d4e-5ad6ded66cf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1893791369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1893791369
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1836179676
Short name T233
Test name
Test status
Simulation time 553259317 ps
CPU time 3.8 seconds
Started Aug 02 05:13:32 PM PDT 24
Finished Aug 02 05:13:36 PM PDT 24
Peak memory 217052 kb
Host smart-d23dc221-832e-4872-b7ca-402ae0dcce8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836179676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1836179676
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2324766597
Short name T347
Test name
Test status
Simulation time 59060128 ps
CPU time 3.18 seconds
Started Aug 02 05:13:22 PM PDT 24
Finished Aug 02 05:13:25 PM PDT 24
Peak memory 209568 kb
Host smart-d7c5331c-7f78-4abf-9a65-700c2880b26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324766597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2324766597
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1028868962
Short name T834
Test name
Test status
Simulation time 626216204 ps
CPU time 5.14 seconds
Started Aug 02 05:13:41 PM PDT 24
Finished Aug 02 05:13:46 PM PDT 24
Peak memory 222308 kb
Host smart-a644eefd-b675-412b-bd78-0975eb1bcb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028868962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1028868962
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3778658277
Short name T134
Test name
Test status
Simulation time 138456853 ps
CPU time 3.48 seconds
Started Aug 02 05:13:20 PM PDT 24
Finished Aug 02 05:13:23 PM PDT 24
Peak memory 219948 kb
Host smart-342b1c1e-939b-4b91-8770-33c727831b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778658277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3778658277
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.3339285734
Short name T415
Test name
Test status
Simulation time 982716677 ps
CPU time 24.48 seconds
Started Aug 02 05:13:46 PM PDT 24
Finished Aug 02 05:14:10 PM PDT 24
Peak memory 214208 kb
Host smart-ea246707-aacc-4fa4-8b8a-ee1db8ce6418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339285734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3339285734
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.692332253
Short name T832
Test name
Test status
Simulation time 2901759824 ps
CPU time 27.45 seconds
Started Aug 02 05:13:15 PM PDT 24
Finished Aug 02 05:13:43 PM PDT 24
Peak memory 208936 kb
Host smart-4311c1c2-bf31-4d98-a64d-fcee6bf1e2ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692332253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.692332253
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1115350403
Short name T781
Test name
Test status
Simulation time 2082146541 ps
CPU time 14.91 seconds
Started Aug 02 05:13:36 PM PDT 24
Finished Aug 02 05:13:51 PM PDT 24
Peak memory 208780 kb
Host smart-cd164572-3c17-43b9-b78c-e5f3adaaf6d8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115350403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1115350403
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1627243513
Short name T528
Test name
Test status
Simulation time 1327156461 ps
CPU time 6.34 seconds
Started Aug 02 05:13:24 PM PDT 24
Finished Aug 02 05:13:30 PM PDT 24
Peak memory 207880 kb
Host smart-009d25f6-6ae8-40b2-bcc7-d2f605b37055
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627243513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1627243513
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3601543538
Short name T518
Test name
Test status
Simulation time 302300869 ps
CPU time 3.61 seconds
Started Aug 02 05:13:26 PM PDT 24
Finished Aug 02 05:13:30 PM PDT 24
Peak memory 218500 kb
Host smart-b8479259-103c-4b2a-8134-c7713dfb8e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601543538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3601543538
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1277747668
Short name T872
Test name
Test status
Simulation time 125382016 ps
CPU time 3.05 seconds
Started Aug 02 05:13:38 PM PDT 24
Finished Aug 02 05:13:41 PM PDT 24
Peak memory 206684 kb
Host smart-15d5d2b7-d9dc-40e9-a773-dab741b6b035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277747668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1277747668
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.690611089
Short name T367
Test name
Test status
Simulation time 270168355 ps
CPU time 11.56 seconds
Started Aug 02 05:13:18 PM PDT 24
Finished Aug 02 05:13:30 PM PDT 24
Peak memory 216608 kb
Host smart-93b97676-393b-4b4b-b082-7acd09741bc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690611089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.690611089
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.4167654463
Short name T813
Test name
Test status
Simulation time 684644363 ps
CPU time 23.93 seconds
Started Aug 02 05:13:28 PM PDT 24
Finished Aug 02 05:13:52 PM PDT 24
Peak memory 222792 kb
Host smart-1687ef3d-11a5-4682-aa7f-7afd87c322fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167654463 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.4167654463
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.458597380
Short name T239
Test name
Test status
Simulation time 372101028 ps
CPU time 4.49 seconds
Started Aug 02 05:13:24 PM PDT 24
Finished Aug 02 05:13:29 PM PDT 24
Peak memory 222448 kb
Host smart-e5e7736c-74fe-49fa-bc2f-1064af4185f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458597380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.458597380
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1583535729
Short name T35
Test name
Test status
Simulation time 68406379 ps
CPU time 2.49 seconds
Started Aug 02 05:13:45 PM PDT 24
Finished Aug 02 05:13:48 PM PDT 24
Peak memory 209812 kb
Host smart-0d22ebf0-54cf-4978-8506-04f3370c883e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583535729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1583535729
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2086552472
Short name T720
Test name
Test status
Simulation time 13389407 ps
CPU time 0.97 seconds
Started Aug 02 05:13:22 PM PDT 24
Finished Aug 02 05:13:23 PM PDT 24
Peak memory 206156 kb
Host smart-86fcdc2a-6a26-4215-81d4-a2bd9bfb5d16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086552472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2086552472
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3321741528
Short name T609
Test name
Test status
Simulation time 81960797 ps
CPU time 3.42 seconds
Started Aug 02 05:13:37 PM PDT 24
Finished Aug 02 05:13:41 PM PDT 24
Peak memory 210000 kb
Host smart-f3fe2ba4-b87c-44d0-b6fd-1aa12a3579a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321741528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3321741528
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1002459220
Short name T718
Test name
Test status
Simulation time 185069602 ps
CPU time 1.89 seconds
Started Aug 02 05:13:25 PM PDT 24
Finished Aug 02 05:13:27 PM PDT 24
Peak memory 207660 kb
Host smart-0c24c6e9-ca43-47e9-93fe-1b28041ce545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002459220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1002459220
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2465050473
Short name T214
Test name
Test status
Simulation time 666014693 ps
CPU time 3.22 seconds
Started Aug 02 05:13:28 PM PDT 24
Finished Aug 02 05:13:33 PM PDT 24
Peak memory 220616 kb
Host smart-3b7b7a42-8cc2-4edb-bca5-588148446b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465050473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2465050473
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1330245797
Short name T223
Test name
Test status
Simulation time 58474510 ps
CPU time 2.8 seconds
Started Aug 02 05:13:34 PM PDT 24
Finished Aug 02 05:13:37 PM PDT 24
Peak memory 220016 kb
Host smart-38b41726-0d3c-4485-a692-39ac10a4c810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330245797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1330245797
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1103173068
Short name T707
Test name
Test status
Simulation time 4039521781 ps
CPU time 26.96 seconds
Started Aug 02 05:13:30 PM PDT 24
Finished Aug 02 05:13:57 PM PDT 24
Peak memory 209304 kb
Host smart-73cc7385-a375-4bbc-bf69-9f3dea746beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103173068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1103173068
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3953243678
Short name T183
Test name
Test status
Simulation time 286836852 ps
CPU time 5.64 seconds
Started Aug 02 05:13:28 PM PDT 24
Finished Aug 02 05:13:35 PM PDT 24
Peak memory 208676 kb
Host smart-7c7245e2-2bc8-4c0f-afe8-b0ba6b232cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953243678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3953243678
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3276291996
Short name T685
Test name
Test status
Simulation time 584729211 ps
CPU time 3.86 seconds
Started Aug 02 05:13:56 PM PDT 24
Finished Aug 02 05:14:00 PM PDT 24
Peak memory 208768 kb
Host smart-d36702a9-acaf-4a50-966d-4008397b114e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276291996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3276291996
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.389871010
Short name T891
Test name
Test status
Simulation time 206940867 ps
CPU time 2.89 seconds
Started Aug 02 05:13:30 PM PDT 24
Finished Aug 02 05:13:33 PM PDT 24
Peak memory 207040 kb
Host smart-3f4a06d7-41ec-4358-98bb-e9690388d816
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389871010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.389871010
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1583918464
Short name T660
Test name
Test status
Simulation time 1617653697 ps
CPU time 51.48 seconds
Started Aug 02 05:13:49 PM PDT 24
Finished Aug 02 05:14:41 PM PDT 24
Peak memory 208552 kb
Host smart-f4042dfd-adb8-4120-a0c6-5f939b1278cd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583918464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1583918464
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1649276977
Short name T349
Test name
Test status
Simulation time 1066421329 ps
CPU time 25.52 seconds
Started Aug 02 05:13:19 PM PDT 24
Finished Aug 02 05:13:45 PM PDT 24
Peak memory 214308 kb
Host smart-e96fa34d-7246-4314-838f-5c3f48eb2122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649276977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1649276977
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1346101881
Short name T530
Test name
Test status
Simulation time 407212775 ps
CPU time 2.82 seconds
Started Aug 02 05:13:24 PM PDT 24
Finished Aug 02 05:13:27 PM PDT 24
Peak memory 208728 kb
Host smart-337865d5-9fd2-49fe-b3d1-be0bcdc37ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346101881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1346101881
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2256422727
Short name T177
Test name
Test status
Simulation time 340080409 ps
CPU time 12.43 seconds
Started Aug 02 05:13:31 PM PDT 24
Finished Aug 02 05:13:43 PM PDT 24
Peak memory 220352 kb
Host smart-3e7dc101-11df-43be-ae0d-e78a60c67a28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256422727 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2256422727
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3289767879
Short name T738
Test name
Test status
Simulation time 130089146 ps
CPU time 2.67 seconds
Started Aug 02 05:13:33 PM PDT 24
Finished Aug 02 05:13:36 PM PDT 24
Peak memory 210208 kb
Host smart-d595a730-0ac2-4d18-9129-9f4bd8e598d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289767879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3289767879
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.914610037
Short name T167
Test name
Test status
Simulation time 31798408 ps
CPU time 2 seconds
Started Aug 02 05:13:29 PM PDT 24
Finished Aug 02 05:13:31 PM PDT 24
Peak memory 209720 kb
Host smart-33f010f5-5831-46b4-beb3-61800b11e8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914610037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.914610037
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3128074816
Short name T901
Test name
Test status
Simulation time 17249174 ps
CPU time 0.77 seconds
Started Aug 02 05:13:45 PM PDT 24
Finished Aug 02 05:13:46 PM PDT 24
Peak memory 205944 kb
Host smart-09c9e40d-70bd-4831-835a-f06b50b0c1ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128074816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3128074816
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3373189553
Short name T235
Test name
Test status
Simulation time 43458920 ps
CPU time 3.32 seconds
Started Aug 02 05:13:49 PM PDT 24
Finished Aug 02 05:13:52 PM PDT 24
Peak memory 214352 kb
Host smart-f51f7e2b-45c4-42aa-a65b-c71ba2583978
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3373189553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3373189553
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.4011062992
Short name T475
Test name
Test status
Simulation time 175482748 ps
CPU time 2.17 seconds
Started Aug 02 05:13:41 PM PDT 24
Finished Aug 02 05:13:43 PM PDT 24
Peak memory 217600 kb
Host smart-0ca2964d-7d14-42dd-a5d6-457ef89640cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011062992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.4011062992
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2219484589
Short name T608
Test name
Test status
Simulation time 873485957 ps
CPU time 3.87 seconds
Started Aug 02 05:13:49 PM PDT 24
Finished Aug 02 05:13:53 PM PDT 24
Peak memory 209104 kb
Host smart-fe57e5a2-5ce2-406f-934a-1d24c5b967c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219484589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2219484589
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1642638062
Short name T853
Test name
Test status
Simulation time 121966659 ps
CPU time 4.88 seconds
Started Aug 02 05:13:44 PM PDT 24
Finished Aug 02 05:13:49 PM PDT 24
Peak memory 209284 kb
Host smart-a1630bbb-0a25-4e0b-9f6b-ad53c898e707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642638062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1642638062
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.302371888
Short name T612
Test name
Test status
Simulation time 77807176 ps
CPU time 3.85 seconds
Started Aug 02 05:13:24 PM PDT 24
Finished Aug 02 05:13:28 PM PDT 24
Peak memory 210040 kb
Host smart-1f1de799-c8d7-43c4-9a0b-619f8168a466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302371888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.302371888
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.125055521
Short name T78
Test name
Test status
Simulation time 82132660 ps
CPU time 3.69 seconds
Started Aug 02 05:13:31 PM PDT 24
Finished Aug 02 05:13:34 PM PDT 24
Peak memory 208968 kb
Host smart-81c54bc4-b8a9-4473-bc77-0098950683ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125055521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.125055521
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1165813543
Short name T790
Test name
Test status
Simulation time 93696971 ps
CPU time 2.05 seconds
Started Aug 02 05:13:26 PM PDT 24
Finished Aug 02 05:13:29 PM PDT 24
Peak memory 208760 kb
Host smart-ccc47fde-70be-4941-a971-6cc8b4e88483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165813543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1165813543
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.1493108357
Short name T514
Test name
Test status
Simulation time 851936225 ps
CPU time 6.81 seconds
Started Aug 02 05:13:23 PM PDT 24
Finished Aug 02 05:13:30 PM PDT 24
Peak memory 208136 kb
Host smart-35fba9cb-5849-468d-9941-02774c903697
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493108357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1493108357
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2526515720
Short name T491
Test name
Test status
Simulation time 82613078 ps
CPU time 1.92 seconds
Started Aug 02 05:13:42 PM PDT 24
Finished Aug 02 05:13:44 PM PDT 24
Peak memory 206988 kb
Host smart-b1612d76-5bd6-4bd1-a64d-09b352821e6d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526515720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2526515720
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.976452976
Short name T520
Test name
Test status
Simulation time 61173050 ps
CPU time 3.03 seconds
Started Aug 02 05:13:19 PM PDT 24
Finished Aug 02 05:13:22 PM PDT 24
Peak memory 207276 kb
Host smart-a31a8112-fd32-4d12-9dea-89a5890ace24
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976452976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.976452976
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1281895480
Short name T512
Test name
Test status
Simulation time 43693912 ps
CPU time 2.43 seconds
Started Aug 02 05:13:22 PM PDT 24
Finished Aug 02 05:13:24 PM PDT 24
Peak memory 209336 kb
Host smart-65636a18-20b2-4ea4-9f66-038a00c5346b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281895480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1281895480
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1226236628
Short name T884
Test name
Test status
Simulation time 145553939 ps
CPU time 3.62 seconds
Started Aug 02 05:13:44 PM PDT 24
Finished Aug 02 05:13:48 PM PDT 24
Peak memory 208272 kb
Host smart-055c2e0b-0490-409f-a800-9b99cf0b248d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226236628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1226236628
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1252241859
Short name T701
Test name
Test status
Simulation time 1763672864 ps
CPU time 14.71 seconds
Started Aug 02 05:13:29 PM PDT 24
Finished Aug 02 05:13:44 PM PDT 24
Peak memory 216340 kb
Host smart-a4334486-306a-484c-b2f0-5e9aae600a53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252241859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1252241859
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.135197808
Short name T836
Test name
Test status
Simulation time 105595788 ps
CPU time 4.95 seconds
Started Aug 02 05:13:53 PM PDT 24
Finished Aug 02 05:13:58 PM PDT 24
Peak memory 218420 kb
Host smart-9f2e64ab-62eb-4ab0-a676-8792653e30f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135197808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.135197808
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2589807147
Short name T124
Test name
Test status
Simulation time 92381254 ps
CPU time 2.37 seconds
Started Aug 02 05:13:22 PM PDT 24
Finished Aug 02 05:13:24 PM PDT 24
Peak memory 210364 kb
Host smart-cd838a99-5fb6-4bf1-a6ff-932a884d8539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589807147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2589807147
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.559780217
Short name T892
Test name
Test status
Simulation time 51602469 ps
CPU time 0.7 seconds
Started Aug 02 05:13:23 PM PDT 24
Finished Aug 02 05:13:24 PM PDT 24
Peak memory 205896 kb
Host smart-cc34a6e6-2c37-445f-acd0-0d103725cf8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559780217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.559780217
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3219857294
Short name T418
Test name
Test status
Simulation time 206439480 ps
CPU time 10.98 seconds
Started Aug 02 05:13:51 PM PDT 24
Finished Aug 02 05:14:02 PM PDT 24
Peak memory 214364 kb
Host smart-66d8b60f-715a-48ad-bcf5-f15910ce8709
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3219857294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3219857294
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.313905766
Short name T662
Test name
Test status
Simulation time 78568415 ps
CPU time 3.28 seconds
Started Aug 02 05:13:42 PM PDT 24
Finished Aug 02 05:13:46 PM PDT 24
Peak memory 214304 kb
Host smart-8aeccfb5-a4e4-438f-8cff-5b34193281a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313905766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.313905766
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.4186677469
Short name T315
Test name
Test status
Simulation time 545691815 ps
CPU time 4.61 seconds
Started Aug 02 05:13:43 PM PDT 24
Finished Aug 02 05:13:47 PM PDT 24
Peak memory 214240 kb
Host smart-e9a5c763-a2d0-4a9b-b58a-3a5b5e23778a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186677469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.4186677469
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.160931982
Short name T287
Test name
Test status
Simulation time 60249160 ps
CPU time 2.44 seconds
Started Aug 02 05:13:27 PM PDT 24
Finished Aug 02 05:13:34 PM PDT 24
Peak memory 214156 kb
Host smart-a1c56b20-2695-4c31-a243-9efa41cba8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160931982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.160931982
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2744977846
Short name T686
Test name
Test status
Simulation time 127533344 ps
CPU time 3.78 seconds
Started Aug 02 05:13:35 PM PDT 24
Finished Aug 02 05:13:39 PM PDT 24
Peak memory 220060 kb
Host smart-f69bc6b6-07ae-4f73-83b2-db96d1defee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744977846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2744977846
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1482863100
Short name T405
Test name
Test status
Simulation time 254882068 ps
CPU time 5.48 seconds
Started Aug 02 05:13:32 PM PDT 24
Finished Aug 02 05:13:37 PM PDT 24
Peak memory 209056 kb
Host smart-e962d62a-75b7-4647-92d7-1892e5aed9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482863100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1482863100
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.428355222
Short name T723
Test name
Test status
Simulation time 3455865384 ps
CPU time 44.72 seconds
Started Aug 02 05:13:29 PM PDT 24
Finished Aug 02 05:14:14 PM PDT 24
Peak memory 209192 kb
Host smart-2c376305-9ea2-485e-b97e-2a04017e787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428355222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.428355222
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1135964529
Short name T480
Test name
Test status
Simulation time 84798247 ps
CPU time 2.46 seconds
Started Aug 02 05:13:22 PM PDT 24
Finished Aug 02 05:13:25 PM PDT 24
Peak memory 206908 kb
Host smart-95b743ff-b54a-44f5-bb57-72856b24b89a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135964529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1135964529
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.444931840
Short name T689
Test name
Test status
Simulation time 36617142 ps
CPU time 2.57 seconds
Started Aug 02 05:13:36 PM PDT 24
Finished Aug 02 05:13:38 PM PDT 24
Peak memory 208760 kb
Host smart-cf24b3d0-82c3-4d4f-a7d2-5db00df894ce
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444931840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.444931840
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3899288719
Short name T636
Test name
Test status
Simulation time 368446160 ps
CPU time 3.28 seconds
Started Aug 02 05:13:32 PM PDT 24
Finished Aug 02 05:13:35 PM PDT 24
Peak memory 208652 kb
Host smart-c1701848-11d1-48bc-ba6e-8ca90dc15634
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899288719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3899288719
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2469143674
Short name T838
Test name
Test status
Simulation time 444554555 ps
CPU time 2.62 seconds
Started Aug 02 05:13:24 PM PDT 24
Finished Aug 02 05:13:27 PM PDT 24
Peak memory 209248 kb
Host smart-26396ede-ddf9-46fd-a427-4692bb6290d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469143674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2469143674
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2873791011
Short name T190
Test name
Test status
Simulation time 481573655 ps
CPU time 3.36 seconds
Started Aug 02 05:13:35 PM PDT 24
Finished Aug 02 05:13:39 PM PDT 24
Peak memory 206828 kb
Host smart-25d01b1e-29ae-41a4-aa38-0f6626cf26f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873791011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2873791011
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.790081750
Short name T754
Test name
Test status
Simulation time 1056217404 ps
CPU time 29.59 seconds
Started Aug 02 05:13:24 PM PDT 24
Finished Aug 02 05:13:53 PM PDT 24
Peak memory 222600 kb
Host smart-d3400976-f05f-473a-85ce-606efa1092c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790081750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.790081750
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.2267284534
Short name T175
Test name
Test status
Simulation time 484039104 ps
CPU time 17.11 seconds
Started Aug 02 05:13:20 PM PDT 24
Finished Aug 02 05:13:37 PM PDT 24
Peak memory 219940 kb
Host smart-52382618-abff-4759-8d83-658a2bf39ecd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267284534 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.2267284534
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1288623288
Short name T182
Test name
Test status
Simulation time 464765540 ps
CPU time 5.87 seconds
Started Aug 02 05:13:23 PM PDT 24
Finished Aug 02 05:13:29 PM PDT 24
Peak memory 208832 kb
Host smart-42e968a7-e31d-4433-ab3c-2ccd4f3a6955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288623288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1288623288
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3834381095
Short name T402
Test name
Test status
Simulation time 80391439 ps
CPU time 2.32 seconds
Started Aug 02 05:13:23 PM PDT 24
Finished Aug 02 05:13:25 PM PDT 24
Peak memory 210104 kb
Host smart-9fd35d0e-6384-436b-86dc-99d24068fca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834381095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3834381095
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1124555406
Short name T767
Test name
Test status
Simulation time 19508109 ps
CPU time 0.74 seconds
Started Aug 02 05:13:55 PM PDT 24
Finished Aug 02 05:13:56 PM PDT 24
Peak memory 206012 kb
Host smart-741e6ba3-e9f5-402b-81db-bf24c5ece2e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124555406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1124555406
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2321341563
Short name T437
Test name
Test status
Simulation time 28988438 ps
CPU time 2.21 seconds
Started Aug 02 05:13:29 PM PDT 24
Finished Aug 02 05:13:31 PM PDT 24
Peak memory 214340 kb
Host smart-77bff5be-b68b-4439-bf0f-52f0e37cef02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2321341563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2321341563
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2290283218
Short name T68
Test name
Test status
Simulation time 64158779 ps
CPU time 2.39 seconds
Started Aug 02 05:13:24 PM PDT 24
Finished Aug 02 05:13:26 PM PDT 24
Peak memory 207368 kb
Host smart-5deaa911-96b2-4afe-912c-b51bfa04f353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290283218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2290283218
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1044689573
Short name T792
Test name
Test status
Simulation time 357181212 ps
CPU time 3.65 seconds
Started Aug 02 05:13:21 PM PDT 24
Finished Aug 02 05:13:25 PM PDT 24
Peak memory 214236 kb
Host smart-10d6b077-e12e-48f8-a5dc-b64e7242ce8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044689573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1044689573
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1763606742
Short name T43
Test name
Test status
Simulation time 43505814 ps
CPU time 1.99 seconds
Started Aug 02 05:13:27 PM PDT 24
Finished Aug 02 05:13:29 PM PDT 24
Peak memory 220104 kb
Host smart-255c8cd2-326b-4b20-a99e-e59761ab9667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763606742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1763606742
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.4059138150
Short name T600
Test name
Test status
Simulation time 555493322 ps
CPU time 5.54 seconds
Started Aug 02 05:13:39 PM PDT 24
Finished Aug 02 05:13:44 PM PDT 24
Peak memory 214336 kb
Host smart-6396b62f-4388-4d29-ab9c-bc296d5e6fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059138150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.4059138150
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1817265110
Short name T765
Test name
Test status
Simulation time 1491030210 ps
CPU time 15.44 seconds
Started Aug 02 05:13:48 PM PDT 24
Finished Aug 02 05:14:03 PM PDT 24
Peak memory 208104 kb
Host smart-92f2535b-7ea2-43ec-ac45-87e1320c2aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817265110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1817265110
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2278095878
Short name T819
Test name
Test status
Simulation time 218201192 ps
CPU time 3.07 seconds
Started Aug 02 05:13:32 PM PDT 24
Finished Aug 02 05:13:35 PM PDT 24
Peak memory 208580 kb
Host smart-587fc9a2-70d6-4a4f-9343-efcb64048bea
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278095878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2278095878
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.969202029
Short name T604
Test name
Test status
Simulation time 332914626 ps
CPU time 3.56 seconds
Started Aug 02 05:13:42 PM PDT 24
Finished Aug 02 05:13:46 PM PDT 24
Peak memory 208856 kb
Host smart-2abc2405-f8ae-486d-8c7b-292c0914876b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969202029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.969202029
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1843901532
Short name T776
Test name
Test status
Simulation time 157054477 ps
CPU time 4.38 seconds
Started Aug 02 05:13:23 PM PDT 24
Finished Aug 02 05:13:28 PM PDT 24
Peak memory 208008 kb
Host smart-a98ae4b7-8932-4f0e-9e69-81e579869693
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843901532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1843901532
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1127934357
Short name T663
Test name
Test status
Simulation time 686108845 ps
CPU time 2.96 seconds
Started Aug 02 05:13:27 PM PDT 24
Finished Aug 02 05:13:30 PM PDT 24
Peak memory 208596 kb
Host smart-104e19a2-4fd9-434f-8465-5db610f5eb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127934357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1127934357
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.760410453
Short name T463
Test name
Test status
Simulation time 70512063 ps
CPU time 2.85 seconds
Started Aug 02 05:13:56 PM PDT 24
Finished Aug 02 05:13:59 PM PDT 24
Peak memory 208380 kb
Host smart-8671bc33-efb6-4a5d-852b-0477ae94bd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760410453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.760410453
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.1248740423
Short name T222
Test name
Test status
Simulation time 702837494 ps
CPU time 18.55 seconds
Started Aug 02 05:13:39 PM PDT 24
Finished Aug 02 05:13:58 PM PDT 24
Peak memory 220424 kb
Host smart-246f061f-f3cb-49d6-b72b-d08bf4d6f134
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248740423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1248740423
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.944587027
Short name T262
Test name
Test status
Simulation time 1340176809 ps
CPU time 15.46 seconds
Started Aug 02 05:13:59 PM PDT 24
Finished Aug 02 05:14:15 PM PDT 24
Peak memory 222468 kb
Host smart-3dba794a-d8e5-4ddc-8e2e-84d528416013
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944587027 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.944587027
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.4266544297
Short name T346
Test name
Test status
Simulation time 1006723915 ps
CPU time 6.95 seconds
Started Aug 02 05:13:43 PM PDT 24
Finished Aug 02 05:13:50 PM PDT 24
Peak memory 207456 kb
Host smart-3e770784-f29e-484b-b583-3c1a5e376e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266544297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.4266544297
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2815607005
Short name T590
Test name
Test status
Simulation time 43901250 ps
CPU time 1.89 seconds
Started Aug 02 05:13:24 PM PDT 24
Finished Aug 02 05:13:26 PM PDT 24
Peak memory 209868 kb
Host smart-adf0003d-069f-4731-a37b-e4211c3e86ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815607005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2815607005
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2361946922
Short name T773
Test name
Test status
Simulation time 46608004 ps
CPU time 0.82 seconds
Started Aug 02 05:13:56 PM PDT 24
Finished Aug 02 05:13:57 PM PDT 24
Peak memory 206032 kb
Host smart-0045af31-e10c-4907-84b9-0c5c1069890c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361946922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2361946922
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.174699064
Short name T848
Test name
Test status
Simulation time 45047931 ps
CPU time 3.04 seconds
Started Aug 02 05:13:55 PM PDT 24
Finished Aug 02 05:13:58 PM PDT 24
Peak memory 214168 kb
Host smart-7982d9cc-2b71-45d4-abdf-39901836a122
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=174699064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.174699064
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3928396079
Short name T547
Test name
Test status
Simulation time 46940344 ps
CPU time 2.15 seconds
Started Aug 02 05:13:42 PM PDT 24
Finished Aug 02 05:13:44 PM PDT 24
Peak memory 208272 kb
Host smart-0155554e-073b-4c7f-b935-a03976ec87cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928396079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3928396079
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.610353791
Short name T717
Test name
Test status
Simulation time 138569664 ps
CPU time 2.64 seconds
Started Aug 02 05:14:04 PM PDT 24
Finished Aug 02 05:14:07 PM PDT 24
Peak memory 209188 kb
Host smart-83a5c7bf-6ff4-4565-b8f7-e889d68fc108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610353791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.610353791
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2389830921
Short name T877
Test name
Test status
Simulation time 123776519 ps
CPU time 3.07 seconds
Started Aug 02 05:13:55 PM PDT 24
Finished Aug 02 05:13:58 PM PDT 24
Peak memory 208664 kb
Host smart-aabda386-f419-4bb8-894a-577a314c93eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389830921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2389830921
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3047680174
Short name T330
Test name
Test status
Simulation time 121751379 ps
CPU time 2.36 seconds
Started Aug 02 05:13:55 PM PDT 24
Finished Aug 02 05:13:57 PM PDT 24
Peak memory 214288 kb
Host smart-1190710f-3898-4274-af10-47ee6f467676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047680174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3047680174
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.86081724
Short name T607
Test name
Test status
Simulation time 72964693 ps
CPU time 1.79 seconds
Started Aug 02 05:13:43 PM PDT 24
Finished Aug 02 05:13:45 PM PDT 24
Peak memory 208452 kb
Host smart-d412f129-5e71-40cd-b902-915528624ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86081724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.86081724
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3558809834
Short name T862
Test name
Test status
Simulation time 519929105 ps
CPU time 6.65 seconds
Started Aug 02 05:13:41 PM PDT 24
Finished Aug 02 05:13:48 PM PDT 24
Peak memory 209240 kb
Host smart-7c321230-5282-4a2a-9a34-4ccf64869992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558809834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3558809834
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.247412985
Short name T821
Test name
Test status
Simulation time 92851895 ps
CPU time 3.34 seconds
Started Aug 02 05:13:55 PM PDT 24
Finished Aug 02 05:13:58 PM PDT 24
Peak memory 206820 kb
Host smart-767f9681-6dd3-4dc8-a1c2-6f819660a30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247412985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.247412985
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3449238015
Short name T339
Test name
Test status
Simulation time 2552109155 ps
CPU time 18.54 seconds
Started Aug 02 05:13:47 PM PDT 24
Finished Aug 02 05:14:05 PM PDT 24
Peak memory 209136 kb
Host smart-ee7a5121-4322-495a-b70f-37b7ae032652
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449238015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3449238015
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1354118763
Short name T619
Test name
Test status
Simulation time 209497415 ps
CPU time 2.91 seconds
Started Aug 02 05:13:48 PM PDT 24
Finished Aug 02 05:13:51 PM PDT 24
Peak memory 208628 kb
Host smart-d578d34f-7e0d-4603-bf92-b34546357869
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354118763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1354118763
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1358197701
Short name T386
Test name
Test status
Simulation time 268138577 ps
CPU time 6.37 seconds
Started Aug 02 05:13:46 PM PDT 24
Finished Aug 02 05:13:52 PM PDT 24
Peak memory 207148 kb
Host smart-68c290df-8329-48f6-bced-081056c5fbcd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358197701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1358197701
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.842509101
Short name T411
Test name
Test status
Simulation time 144705574 ps
CPU time 5.23 seconds
Started Aug 02 05:13:45 PM PDT 24
Finished Aug 02 05:13:51 PM PDT 24
Peak memory 207916 kb
Host smart-d7486ff0-0491-48c5-b760-cc4578e038f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842509101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.842509101
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1713209495
Short name T859
Test name
Test status
Simulation time 273712800 ps
CPU time 2.63 seconds
Started Aug 02 05:13:54 PM PDT 24
Finished Aug 02 05:13:57 PM PDT 24
Peak memory 206852 kb
Host smart-54ae7b72-6951-4ec9-84e2-3aa7adf57486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713209495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1713209495
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3254370884
Short name T360
Test name
Test status
Simulation time 358111228 ps
CPU time 13.78 seconds
Started Aug 02 05:13:56 PM PDT 24
Finished Aug 02 05:14:10 PM PDT 24
Peak memory 219200 kb
Host smart-d8a54581-fb91-41dd-9903-a20444c36920
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254370884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3254370884
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.1033318522
Short name T174
Test name
Test status
Simulation time 3453816487 ps
CPU time 24.87 seconds
Started Aug 02 05:13:50 PM PDT 24
Finished Aug 02 05:14:15 PM PDT 24
Peak memory 222544 kb
Host smart-66bd44b5-3154-440a-baf4-474931a4c2f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033318522 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.1033318522
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3962406538
Short name T199
Test name
Test status
Simulation time 467457432 ps
CPU time 4.98 seconds
Started Aug 02 05:13:55 PM PDT 24
Finished Aug 02 05:14:00 PM PDT 24
Peak memory 210292 kb
Host smart-da44340f-07c7-4220-a087-631822a69901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962406538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3962406538
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2942323348
Short name T602
Test name
Test status
Simulation time 6859178229 ps
CPU time 41.87 seconds
Started Aug 02 05:13:48 PM PDT 24
Finished Aug 02 05:14:30 PM PDT 24
Peak memory 211712 kb
Host smart-e1cdb040-89cb-46e6-90b9-5b9227b2434c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942323348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2942323348
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.28880497
Short name T695
Test name
Test status
Simulation time 12290725 ps
CPU time 0.76 seconds
Started Aug 02 05:12:10 PM PDT 24
Finished Aug 02 05:12:11 PM PDT 24
Peak memory 206000 kb
Host smart-edf5490c-68ee-4753-8ebc-a19303d7cf94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28880497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.28880497
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2901218509
Short name T105
Test name
Test status
Simulation time 101881116 ps
CPU time 3.99 seconds
Started Aug 02 05:12:10 PM PDT 24
Finished Aug 02 05:12:14 PM PDT 24
Peak memory 215704 kb
Host smart-90ba2e77-d9dc-44b5-a3a2-9d449370c7a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2901218509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2901218509
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.584122803
Short name T27
Test name
Test status
Simulation time 846331525 ps
CPU time 11.41 seconds
Started Aug 02 05:12:13 PM PDT 24
Finished Aug 02 05:12:25 PM PDT 24
Peak memory 209956 kb
Host smart-01e5c05d-4b3f-4387-9461-fa8ed8adae26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584122803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.584122803
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2345303926
Short name T76
Test name
Test status
Simulation time 81365467 ps
CPU time 1.81 seconds
Started Aug 02 05:12:14 PM PDT 24
Finished Aug 02 05:12:16 PM PDT 24
Peak memory 208544 kb
Host smart-4385c0ed-a602-4f63-8918-756259521f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345303926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2345303926
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3659676341
Short name T266
Test name
Test status
Simulation time 26138037 ps
CPU time 2 seconds
Started Aug 02 05:12:15 PM PDT 24
Finished Aug 02 05:12:17 PM PDT 24
Peak memory 214348 kb
Host smart-2b870adf-ffd7-4fe3-adfb-b36262f878e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659676341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3659676341
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3237626216
Short name T249
Test name
Test status
Simulation time 29268599 ps
CPU time 1.88 seconds
Started Aug 02 05:12:14 PM PDT 24
Finished Aug 02 05:12:16 PM PDT 24
Peak memory 214260 kb
Host smart-613b6667-dcff-4010-99fa-ddd3ab97e19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237626216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3237626216
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1197997721
Short name T64
Test name
Test status
Simulation time 152857297 ps
CPU time 5.2 seconds
Started Aug 02 05:12:11 PM PDT 24
Finished Aug 02 05:12:22 PM PDT 24
Peak memory 220208 kb
Host smart-3c1f28b5-7996-49ad-9e26-ea01d8371be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197997721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1197997721
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.1207668432
Short name T653
Test name
Test status
Simulation time 982656337 ps
CPU time 4.86 seconds
Started Aug 02 05:12:08 PM PDT 24
Finished Aug 02 05:12:13 PM PDT 24
Peak memory 208620 kb
Host smart-00d0dc75-c82c-4b7e-9259-8ef3319e9024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207668432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1207668432
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.406356551
Short name T10
Test name
Test status
Simulation time 1917626466 ps
CPU time 13.38 seconds
Started Aug 02 05:12:19 PM PDT 24
Finished Aug 02 05:12:32 PM PDT 24
Peak memory 234020 kb
Host smart-397a8a92-b64c-4087-8727-5f98f66bd207
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406356551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.406356551
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.4200328257
Short name T314
Test name
Test status
Simulation time 1015037611 ps
CPU time 3.5 seconds
Started Aug 02 05:12:15 PM PDT 24
Finished Aug 02 05:12:19 PM PDT 24
Peak memory 208552 kb
Host smart-fcab5352-0500-4164-82c3-7da28f136962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200328257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.4200328257
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2435583917
Short name T721
Test name
Test status
Simulation time 903477386 ps
CPU time 11.03 seconds
Started Aug 02 05:12:13 PM PDT 24
Finished Aug 02 05:12:24 PM PDT 24
Peak memory 206948 kb
Host smart-22ce1801-ef30-498b-aa39-aa1441e01338
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435583917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2435583917
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.928029988
Short name T465
Test name
Test status
Simulation time 50998101 ps
CPU time 2.61 seconds
Started Aug 02 05:12:16 PM PDT 24
Finished Aug 02 05:12:19 PM PDT 24
Peak memory 208080 kb
Host smart-a72b0098-7b5f-4f45-b792-3db0d7972ad4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928029988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.928029988
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2769444900
Short name T185
Test name
Test status
Simulation time 694680339 ps
CPU time 5.61 seconds
Started Aug 02 05:12:15 PM PDT 24
Finished Aug 02 05:12:21 PM PDT 24
Peak memory 208080 kb
Host smart-e143dc92-0e70-465e-a765-ed5470dcfe7f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769444900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2769444900
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2075526945
Short name T796
Test name
Test status
Simulation time 296452492 ps
CPU time 7.45 seconds
Started Aug 02 05:12:13 PM PDT 24
Finished Aug 02 05:12:20 PM PDT 24
Peak memory 218456 kb
Host smart-e37a424c-ca7d-45e3-bba9-e715bdf8e64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075526945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2075526945
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.729675946
Short name T486
Test name
Test status
Simulation time 81033442 ps
CPU time 3.48 seconds
Started Aug 02 05:12:10 PM PDT 24
Finished Aug 02 05:12:13 PM PDT 24
Peak memory 207856 kb
Host smart-802c3c2e-4223-44de-b2d6-bf1c6c8dbcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729675946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.729675946
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.3531569639
Short name T413
Test name
Test status
Simulation time 2173338567 ps
CPU time 49.7 seconds
Started Aug 02 05:12:14 PM PDT 24
Finished Aug 02 05:13:04 PM PDT 24
Peak memory 222680 kb
Host smart-fa088630-a79c-4982-9a5b-aec52bf4e989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531569639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3531569639
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2937295954
Short name T763
Test name
Test status
Simulation time 91995030 ps
CPU time 2.59 seconds
Started Aug 02 05:12:11 PM PDT 24
Finished Aug 02 05:12:14 PM PDT 24
Peak memory 218252 kb
Host smart-b19f3a8b-f903-4267-8e79-df5fbb936160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937295954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2937295954
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1287830904
Short name T658
Test name
Test status
Simulation time 959895311 ps
CPU time 2.8 seconds
Started Aug 02 05:12:07 PM PDT 24
Finished Aug 02 05:12:09 PM PDT 24
Peak memory 210408 kb
Host smart-1525361e-ebce-4e98-9dd5-e306ebd66caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287830904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1287830904
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.4070757470
Short name T569
Test name
Test status
Simulation time 197389359 ps
CPU time 0.87 seconds
Started Aug 02 05:13:45 PM PDT 24
Finished Aug 02 05:13:46 PM PDT 24
Peak memory 205860 kb
Host smart-e7442a8e-c4ba-4f08-b635-a53b4d8df36b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070757470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.4070757470
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1786349
Short name T256
Test name
Test status
Simulation time 6384876471 ps
CPU time 20.65 seconds
Started Aug 02 05:13:58 PM PDT 24
Finished Aug 02 05:14:19 PM PDT 24
Peak memory 214424 kb
Host smart-3367d381-e472-40a7-b4b5-9114eb582be9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1786349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1786349
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.567363052
Short name T227
Test name
Test status
Simulation time 784131486 ps
CPU time 3.79 seconds
Started Aug 02 05:13:58 PM PDT 24
Finished Aug 02 05:14:02 PM PDT 24
Peak memory 209864 kb
Host smart-a33be56b-53b2-4869-b8f9-63107a284d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567363052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.567363052
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3675605872
Short name T45
Test name
Test status
Simulation time 64311800 ps
CPU time 2.47 seconds
Started Aug 02 05:13:39 PM PDT 24
Finished Aug 02 05:13:42 PM PDT 24
Peak memory 214244 kb
Host smart-c7a63308-11a4-4499-8f75-0bb83a3eda83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675605872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3675605872
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2587919280
Short name T886
Test name
Test status
Simulation time 26849861 ps
CPU time 1.76 seconds
Started Aug 02 05:13:48 PM PDT 24
Finished Aug 02 05:13:50 PM PDT 24
Peak memory 214312 kb
Host smart-8a131eb9-d535-40cc-8199-7468f9e923d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587919280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2587919280
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2677493404
Short name T566
Test name
Test status
Simulation time 53975615 ps
CPU time 3.72 seconds
Started Aug 02 05:13:55 PM PDT 24
Finished Aug 02 05:13:59 PM PDT 24
Peak memory 214320 kb
Host smart-54914cc7-7fa7-4ca9-8ac7-7629c9328382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677493404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2677493404
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1491682315
Short name T563
Test name
Test status
Simulation time 156715267 ps
CPU time 3.06 seconds
Started Aug 02 05:13:40 PM PDT 24
Finished Aug 02 05:13:43 PM PDT 24
Peak memory 209384 kb
Host smart-3e1e32bf-946c-452a-9e8b-0db5bf467868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491682315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1491682315
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2403986977
Short name T13
Test name
Test status
Simulation time 688859210 ps
CPU time 5.99 seconds
Started Aug 02 05:13:59 PM PDT 24
Finished Aug 02 05:14:06 PM PDT 24
Peak memory 207272 kb
Host smart-6099c3b6-f1d7-4256-8fc6-9c2d9fcf9464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403986977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2403986977
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3266071
Short name T453
Test name
Test status
Simulation time 498014874 ps
CPU time 3.96 seconds
Started Aug 02 05:13:50 PM PDT 24
Finished Aug 02 05:13:54 PM PDT 24
Peak memory 208548 kb
Host smart-35727824-9d3d-42c8-9ca5-68e255bbd738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3266071
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.9454652
Short name T364
Test name
Test status
Simulation time 60177321 ps
CPU time 3.14 seconds
Started Aug 02 05:13:58 PM PDT 24
Finished Aug 02 05:14:01 PM PDT 24
Peak memory 206912 kb
Host smart-7a749149-0d85-46f4-95c9-7e34106c53e2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9454652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.9454652
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2021271445
Short name T490
Test name
Test status
Simulation time 102714257 ps
CPU time 2.9 seconds
Started Aug 02 05:13:44 PM PDT 24
Finished Aug 02 05:13:47 PM PDT 24
Peak memory 207004 kb
Host smart-ecf9dc9e-4128-4bb8-8b0d-35342e2e9109
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021271445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2021271445
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.3523974309
Short name T556
Test name
Test status
Simulation time 625949912 ps
CPU time 3.03 seconds
Started Aug 02 05:13:55 PM PDT 24
Finished Aug 02 05:13:58 PM PDT 24
Peak memory 206980 kb
Host smart-3347e4be-0e27-4c9e-8d68-6929b64be796
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523974309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.3523974309
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1668523540
Short name T32
Test name
Test status
Simulation time 886081788 ps
CPU time 5.14 seconds
Started Aug 02 05:14:08 PM PDT 24
Finished Aug 02 05:14:13 PM PDT 24
Peak memory 209304 kb
Host smart-cf007d05-8b5a-4442-9512-19e26012cc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668523540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1668523540
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3836572320
Short name T532
Test name
Test status
Simulation time 126311601 ps
CPU time 3.97 seconds
Started Aug 02 05:13:57 PM PDT 24
Finished Aug 02 05:14:02 PM PDT 24
Peak memory 207912 kb
Host smart-67473fee-4edb-440f-82c0-d1aab530150f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836572320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3836572320
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.75795870
Short name T205
Test name
Test status
Simulation time 1046997071 ps
CPU time 5.55 seconds
Started Aug 02 05:13:53 PM PDT 24
Finished Aug 02 05:13:59 PM PDT 24
Peak memory 214252 kb
Host smart-433a5e38-5a1f-490b-b3d5-50cb95631d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75795870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.75795870
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.417383598
Short name T844
Test name
Test status
Simulation time 28454776 ps
CPU time 0.79 seconds
Started Aug 02 05:13:57 PM PDT 24
Finished Aug 02 05:13:58 PM PDT 24
Peak memory 206000 kb
Host smart-3dfdd473-156f-4bae-8ba3-a67a8c2fd588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417383598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.417383598
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.4219475047
Short name T417
Test name
Test status
Simulation time 223609775 ps
CPU time 4.3 seconds
Started Aug 02 05:13:50 PM PDT 24
Finished Aug 02 05:13:55 PM PDT 24
Peak memory 214960 kb
Host smart-56ba8eea-8507-4311-80ad-3ab2079cffe3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4219475047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.4219475047
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.484498587
Short name T18
Test name
Test status
Simulation time 157810550 ps
CPU time 3.26 seconds
Started Aug 02 05:13:52 PM PDT 24
Finished Aug 02 05:13:55 PM PDT 24
Peak memory 210028 kb
Host smart-5155da6b-f051-4fe2-ba72-ff2715f8a9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484498587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.484498587
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2181988257
Short name T831
Test name
Test status
Simulation time 309243790 ps
CPU time 1.99 seconds
Started Aug 02 05:13:44 PM PDT 24
Finished Aug 02 05:13:46 PM PDT 24
Peak memory 207028 kb
Host smart-c0587fb2-761a-4822-8dbd-69d46f88a5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181988257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2181988257
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1361197798
Short name T854
Test name
Test status
Simulation time 53523703 ps
CPU time 1.94 seconds
Started Aug 02 05:13:46 PM PDT 24
Finished Aug 02 05:13:48 PM PDT 24
Peak memory 214328 kb
Host smart-4634bef1-5c17-4b88-baee-a74c7153a6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361197798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1361197798
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1159819
Short name T286
Test name
Test status
Simulation time 39114807 ps
CPU time 2.26 seconds
Started Aug 02 05:13:54 PM PDT 24
Finished Aug 02 05:13:57 PM PDT 24
Peak memory 214244 kb
Host smart-6410228c-cbe0-4aa8-b8ca-c699a36af040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1159819
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.90678893
Short name T273
Test name
Test status
Simulation time 207667569 ps
CPU time 3.75 seconds
Started Aug 02 05:13:54 PM PDT 24
Finished Aug 02 05:13:58 PM PDT 24
Peak memory 210236 kb
Host smart-07ece3f1-61e9-443b-8b9f-69481ec9b1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90678893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.90678893
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1668420367
Short name T726
Test name
Test status
Simulation time 160149119 ps
CPU time 4.79 seconds
Started Aug 02 05:13:58 PM PDT 24
Finished Aug 02 05:14:03 PM PDT 24
Peak memory 214460 kb
Host smart-dc661fe7-7004-4bbd-a0a0-ae2007aef0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668420367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1668420367
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2424084747
Short name T693
Test name
Test status
Simulation time 63640833 ps
CPU time 2.76 seconds
Started Aug 02 05:13:59 PM PDT 24
Finished Aug 02 05:14:02 PM PDT 24
Peak memory 208100 kb
Host smart-63b64147-d421-48f1-9db7-85da3d04c43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424084747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2424084747
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1396044628
Short name T772
Test name
Test status
Simulation time 264221517 ps
CPU time 4.18 seconds
Started Aug 02 05:13:53 PM PDT 24
Finished Aug 02 05:13:57 PM PDT 24
Peak memory 206896 kb
Host smart-bfa61837-c30d-40c2-95a3-0e616a053658
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396044628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1396044628
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1227184198
Short name T544
Test name
Test status
Simulation time 33250019 ps
CPU time 2.29 seconds
Started Aug 02 05:13:54 PM PDT 24
Finished Aug 02 05:13:56 PM PDT 24
Peak memory 207372 kb
Host smart-60331de4-342f-4483-b598-209c7a83d4cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227184198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1227184198
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.4037869319
Short name T548
Test name
Test status
Simulation time 39530325 ps
CPU time 2.4 seconds
Started Aug 02 05:13:49 PM PDT 24
Finished Aug 02 05:13:52 PM PDT 24
Peak memory 207088 kb
Host smart-bac76433-3823-4bf7-b233-872099221c65
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037869319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.4037869319
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2238006139
Short name T398
Test name
Test status
Simulation time 28099020 ps
CPU time 2.12 seconds
Started Aug 02 05:13:53 PM PDT 24
Finished Aug 02 05:13:55 PM PDT 24
Peak memory 208364 kb
Host smart-d45e7c44-e535-40da-81c7-d3a50731bd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238006139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2238006139
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2396329185
Short name T485
Test name
Test status
Simulation time 63775190 ps
CPU time 2.02 seconds
Started Aug 02 05:13:57 PM PDT 24
Finished Aug 02 05:14:00 PM PDT 24
Peak memory 206780 kb
Host smart-ed4a070a-adbe-4596-b12f-c09135f44d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396329185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2396329185
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.291970169
Short name T3
Test name
Test status
Simulation time 152699617 ps
CPU time 6.08 seconds
Started Aug 02 05:13:56 PM PDT 24
Finished Aug 02 05:14:03 PM PDT 24
Peak memory 209992 kb
Host smart-61bed2f1-7b2d-4da7-9f62-0899a777a3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291970169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.291970169
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1662491607
Short name T414
Test name
Test status
Simulation time 82517163 ps
CPU time 2.17 seconds
Started Aug 02 05:13:54 PM PDT 24
Finished Aug 02 05:13:56 PM PDT 24
Peak memory 209860 kb
Host smart-ce29ee9c-a354-4eab-92c2-6e416a76b2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662491607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1662491607
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.119136511
Short name T638
Test name
Test status
Simulation time 42973903 ps
CPU time 0.69 seconds
Started Aug 02 05:14:00 PM PDT 24
Finished Aug 02 05:14:01 PM PDT 24
Peak memory 205972 kb
Host smart-00369b8e-40e8-4942-8996-6ad6baad9067
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119136511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.119136511
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.775531542
Short name T135
Test name
Test status
Simulation time 48891793 ps
CPU time 3.49 seconds
Started Aug 02 05:13:56 PM PDT 24
Finished Aug 02 05:13:59 PM PDT 24
Peak memory 222404 kb
Host smart-541eb48e-d598-4a2e-9cbb-28c04720e917
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=775531542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.775531542
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.697213724
Short name T594
Test name
Test status
Simulation time 60530873 ps
CPU time 3.25 seconds
Started Aug 02 05:13:59 PM PDT 24
Finished Aug 02 05:14:02 PM PDT 24
Peak memory 221296 kb
Host smart-4ed2c6a8-aa5d-4c93-911d-a0f2b2747fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697213724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.697213724
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3564565048
Short name T343
Test name
Test status
Simulation time 4033722359 ps
CPU time 21.01 seconds
Started Aug 02 05:13:51 PM PDT 24
Finished Aug 02 05:14:18 PM PDT 24
Peak memory 208620 kb
Host smart-aae6b753-a5e1-411e-9d5c-f90ffe9cc116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564565048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3564565048
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.4226287798
Short name T94
Test name
Test status
Simulation time 74469911 ps
CPU time 2.52 seconds
Started Aug 02 05:14:04 PM PDT 24
Finished Aug 02 05:14:06 PM PDT 24
Peak memory 209332 kb
Host smart-e9b17053-9ab3-4fdd-8471-3d41a34b1440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226287798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.4226287798
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.2271085127
Short name T374
Test name
Test status
Simulation time 129529479 ps
CPU time 5.15 seconds
Started Aug 02 05:13:57 PM PDT 24
Finished Aug 02 05:14:02 PM PDT 24
Peak memory 221528 kb
Host smart-db31f89f-e255-4887-9612-2ea08344f42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271085127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2271085127
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2024861801
Short name T481
Test name
Test status
Simulation time 43707222 ps
CPU time 2.71 seconds
Started Aug 02 05:13:56 PM PDT 24
Finished Aug 02 05:13:58 PM PDT 24
Peak memory 219880 kb
Host smart-35eb382d-c4ec-4bf3-84a3-55870f4df234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024861801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2024861801
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3284706714
Short name T397
Test name
Test status
Simulation time 6918700663 ps
CPU time 29.64 seconds
Started Aug 02 05:13:54 PM PDT 24
Finished Aug 02 05:14:24 PM PDT 24
Peak memory 209388 kb
Host smart-5f4f5114-4002-49ef-8d5d-fc9b937667ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284706714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3284706714
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2904146379
Short name T889
Test name
Test status
Simulation time 5320160791 ps
CPU time 33.06 seconds
Started Aug 02 05:13:59 PM PDT 24
Finished Aug 02 05:14:32 PM PDT 24
Peak memory 208824 kb
Host smart-8e37113f-674f-4e0f-b5b4-0ff98b6b1fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904146379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2904146379
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2271755853
Short name T213
Test name
Test status
Simulation time 489271207 ps
CPU time 4.33 seconds
Started Aug 02 05:13:45 PM PDT 24
Finished Aug 02 05:13:49 PM PDT 24
Peak memory 208924 kb
Host smart-eb589fae-d70a-4870-bc44-5133442bed4b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271755853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2271755853
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.836268610
Short name T814
Test name
Test status
Simulation time 20479266 ps
CPU time 1.74 seconds
Started Aug 02 05:13:58 PM PDT 24
Finished Aug 02 05:14:00 PM PDT 24
Peak memory 206988 kb
Host smart-b6cf6929-0478-4a0b-b973-c98eea79363c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836268610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.836268610
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3742415276
Short name T412
Test name
Test status
Simulation time 439441854 ps
CPU time 14.69 seconds
Started Aug 02 05:13:50 PM PDT 24
Finished Aug 02 05:14:05 PM PDT 24
Peak memory 208796 kb
Host smart-19c6f6ce-b6ff-4504-9979-d7d9537b5052
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742415276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3742415276
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2171113255
Short name T598
Test name
Test status
Simulation time 92521215 ps
CPU time 2.25 seconds
Started Aug 02 05:13:51 PM PDT 24
Finished Aug 02 05:13:54 PM PDT 24
Peak memory 208168 kb
Host smart-0738137d-48a6-4777-984a-2404b12665b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171113255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2171113255
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2739402085
Short name T768
Test name
Test status
Simulation time 224191736 ps
CPU time 4.31 seconds
Started Aug 02 05:14:01 PM PDT 24
Finished Aug 02 05:14:06 PM PDT 24
Peak memory 206732 kb
Host smart-9955d6bd-dc10-42b1-bf20-451af099833e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739402085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2739402085
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.616530366
Short name T71
Test name
Test status
Simulation time 168752688 ps
CPU time 6.74 seconds
Started Aug 02 05:14:01 PM PDT 24
Finished Aug 02 05:14:08 PM PDT 24
Peak memory 220124 kb
Host smart-37fc6c6f-da53-4e2c-a7ef-491e63de36b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616530366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.616530366
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.750641784
Short name T243
Test name
Test status
Simulation time 182837566 ps
CPU time 3.5 seconds
Started Aug 02 05:13:47 PM PDT 24
Finished Aug 02 05:13:51 PM PDT 24
Peak memory 207020 kb
Host smart-68f480cd-c02e-445b-9500-0faa311a079f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750641784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.750641784
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.631857162
Short name T155
Test name
Test status
Simulation time 326454314 ps
CPU time 8.15 seconds
Started Aug 02 05:14:00 PM PDT 24
Finished Aug 02 05:14:08 PM PDT 24
Peak memory 210892 kb
Host smart-bd8151a0-1ea8-4efe-b2cb-cb46ba9fd985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631857162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.631857162
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3465748871
Short name T879
Test name
Test status
Simulation time 31338246 ps
CPU time 0.82 seconds
Started Aug 02 05:13:51 PM PDT 24
Finished Aug 02 05:13:52 PM PDT 24
Peak memory 205796 kb
Host smart-986b5cb9-9422-4358-8e84-68d7cef11f28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465748871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3465748871
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2612351921
Short name T716
Test name
Test status
Simulation time 62475394 ps
CPU time 2.25 seconds
Started Aug 02 05:14:01 PM PDT 24
Finished Aug 02 05:14:03 PM PDT 24
Peak memory 208332 kb
Host smart-c590f65b-3138-4d46-b8fe-bfea1f91f3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612351921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2612351921
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1853936968
Short name T73
Test name
Test status
Simulation time 50432021 ps
CPU time 1.99 seconds
Started Aug 02 05:14:11 PM PDT 24
Finished Aug 02 05:14:13 PM PDT 24
Peak memory 209344 kb
Host smart-8ac9a63b-4532-43c7-86dd-91e7c5d87a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853936968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1853936968
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2475511050
Short name T337
Test name
Test status
Simulation time 91838718 ps
CPU time 3.14 seconds
Started Aug 02 05:14:02 PM PDT 24
Finished Aug 02 05:14:06 PM PDT 24
Peak memory 208840 kb
Host smart-03b953aa-2dc4-4fd3-9b96-e549f59368a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475511050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2475511050
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3795546816
Short name T332
Test name
Test status
Simulation time 125330278 ps
CPU time 2.33 seconds
Started Aug 02 05:13:56 PM PDT 24
Finished Aug 02 05:13:58 PM PDT 24
Peak memory 214316 kb
Host smart-62ca1d26-aedc-4957-bf85-f08a676572f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795546816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3795546816
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1703273300
Short name T215
Test name
Test status
Simulation time 74457273 ps
CPU time 2.85 seconds
Started Aug 02 05:13:58 PM PDT 24
Finished Aug 02 05:14:01 PM PDT 24
Peak memory 214248 kb
Host smart-f2bd5957-aa16-43a7-9251-f88b9714ad8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703273300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1703273300
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1539401413
Short name T292
Test name
Test status
Simulation time 169977499 ps
CPU time 4.34 seconds
Started Aug 02 05:14:04 PM PDT 24
Finished Aug 02 05:14:08 PM PDT 24
Peak memory 210396 kb
Host smart-c725be79-f134-4047-b52b-16cd5e9afbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539401413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1539401413
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3675647423
Short name T443
Test name
Test status
Simulation time 568101863 ps
CPU time 3.9 seconds
Started Aug 02 05:13:54 PM PDT 24
Finished Aug 02 05:13:58 PM PDT 24
Peak memory 208044 kb
Host smart-f80bf538-6cfe-44b4-8593-9d711198355a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675647423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3675647423
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1422400434
Short name T359
Test name
Test status
Simulation time 119918753 ps
CPU time 5.15 seconds
Started Aug 02 05:13:54 PM PDT 24
Finished Aug 02 05:14:00 PM PDT 24
Peak memory 209092 kb
Host smart-d1bf67ce-79f8-4e19-b469-7ccb79988442
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422400434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1422400434
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.3615386365
Short name T282
Test name
Test status
Simulation time 62526520 ps
CPU time 2.96 seconds
Started Aug 02 05:14:01 PM PDT 24
Finished Aug 02 05:14:04 PM PDT 24
Peak memory 207040 kb
Host smart-831b5875-e5a4-4dbd-9b05-8739ab46339a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615386365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3615386365
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1773438627
Short name T639
Test name
Test status
Simulation time 120523332 ps
CPU time 3.4 seconds
Started Aug 02 05:14:06 PM PDT 24
Finished Aug 02 05:14:10 PM PDT 24
Peak memory 209412 kb
Host smart-08d2821e-cc53-458c-a62b-2186cc30c0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773438627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1773438627
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1501585503
Short name T201
Test name
Test status
Simulation time 436729010 ps
CPU time 4.65 seconds
Started Aug 02 05:14:02 PM PDT 24
Finished Aug 02 05:14:06 PM PDT 24
Peak memory 208644 kb
Host smart-8415c419-5498-43de-90ce-f364d1f37b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501585503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1501585503
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.915255077
Short name T769
Test name
Test status
Simulation time 801692892 ps
CPU time 13.92 seconds
Started Aug 02 05:13:54 PM PDT 24
Finished Aug 02 05:14:08 PM PDT 24
Peak memory 215896 kb
Host smart-f79fc6e6-fbd9-4905-8753-e6a5f9858e54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915255077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.915255077
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2387861376
Short name T324
Test name
Test status
Simulation time 94858190 ps
CPU time 4.47 seconds
Started Aug 02 05:13:55 PM PDT 24
Finished Aug 02 05:14:00 PM PDT 24
Peak memory 207780 kb
Host smart-1e9f6aa8-dcd4-4a87-9349-c4221673d932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387861376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2387861376
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.1166009110
Short name T444
Test name
Test status
Simulation time 35115026 ps
CPU time 0.84 seconds
Started Aug 02 05:13:59 PM PDT 24
Finished Aug 02 05:14:00 PM PDT 24
Peak memory 206016 kb
Host smart-53cc26f8-ee00-423c-aec8-08e2b22d4e34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166009110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1166009110
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1442665052
Short name T434
Test name
Test status
Simulation time 76151908 ps
CPU time 4.71 seconds
Started Aug 02 05:13:58 PM PDT 24
Finished Aug 02 05:14:03 PM PDT 24
Peak memory 222516 kb
Host smart-a4698b3e-4af8-44df-80b2-d04a05cf06cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1442665052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1442665052
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.431481938
Short name T675
Test name
Test status
Simulation time 93791077 ps
CPU time 1.77 seconds
Started Aug 02 05:14:13 PM PDT 24
Finished Aug 02 05:14:15 PM PDT 24
Peak memory 208420 kb
Host smart-74d8a296-a21b-446e-82d6-f656be14b995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431481938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.431481938
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1809826559
Short name T84
Test name
Test status
Simulation time 368518927 ps
CPU time 2.83 seconds
Started Aug 02 05:14:04 PM PDT 24
Finished Aug 02 05:14:07 PM PDT 24
Peak memory 214328 kb
Host smart-162de6e5-5696-4a8c-8b83-9ddef4065579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809826559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1809826559
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1555300237
Short name T399
Test name
Test status
Simulation time 206003628 ps
CPU time 5.02 seconds
Started Aug 02 05:14:01 PM PDT 24
Finished Aug 02 05:14:06 PM PDT 24
Peak memory 214280 kb
Host smart-477875ea-dd4e-4c0c-b2c6-62c7de6149ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555300237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1555300237
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1996128282
Short name T428
Test name
Test status
Simulation time 120586975 ps
CPU time 3.54 seconds
Started Aug 02 05:13:57 PM PDT 24
Finished Aug 02 05:14:00 PM PDT 24
Peak memory 209516 kb
Host smart-2c1d3665-51a7-449b-85ef-b063207dafd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996128282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1996128282
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1450359239
Short name T557
Test name
Test status
Simulation time 116916385 ps
CPU time 4.04 seconds
Started Aug 02 05:13:57 PM PDT 24
Finished Aug 02 05:14:01 PM PDT 24
Peak memory 214344 kb
Host smart-ecc0e718-e692-46f6-9185-63876a54eae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450359239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1450359239
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2599260452
Short name T746
Test name
Test status
Simulation time 21776101 ps
CPU time 1.83 seconds
Started Aug 02 05:13:58 PM PDT 24
Finished Aug 02 05:14:00 PM PDT 24
Peak memory 206884 kb
Host smart-a96a9d4f-9f89-4a3a-98b0-1390a53b3dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599260452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2599260452
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1562694785
Short name T525
Test name
Test status
Simulation time 125376683 ps
CPU time 3.5 seconds
Started Aug 02 05:14:04 PM PDT 24
Finished Aug 02 05:14:08 PM PDT 24
Peak memory 208584 kb
Host smart-26cf3634-cf8b-43b6-be91-6d52cee329d3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562694785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1562694785
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1990312168
Short name T571
Test name
Test status
Simulation time 67866319 ps
CPU time 3.35 seconds
Started Aug 02 05:14:06 PM PDT 24
Finished Aug 02 05:14:10 PM PDT 24
Peak memory 209120 kb
Host smart-a563d33d-a686-4bee-9613-a6c31cf83e55
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990312168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1990312168
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3184674905
Short name T659
Test name
Test status
Simulation time 166800973 ps
CPU time 2.61 seconds
Started Aug 02 05:13:56 PM PDT 24
Finished Aug 02 05:13:59 PM PDT 24
Peak memory 208856 kb
Host smart-7780a076-379d-41cb-b999-d70a9350763e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184674905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3184674905
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.258013735
Short name T899
Test name
Test status
Simulation time 40695418 ps
CPU time 1.74 seconds
Started Aug 02 05:13:50 PM PDT 24
Finished Aug 02 05:13:52 PM PDT 24
Peak memory 209496 kb
Host smart-689f0652-8708-41aa-a471-db9adfc50cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258013735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.258013735
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3025342959
Short name T751
Test name
Test status
Simulation time 2993142724 ps
CPU time 27.08 seconds
Started Aug 02 05:14:07 PM PDT 24
Finished Aug 02 05:14:34 PM PDT 24
Peak memory 208712 kb
Host smart-3465f853-a2bc-4fcb-8ff9-70143c04c1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025342959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3025342959
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1666173919
Short name T125
Test name
Test status
Simulation time 680442255 ps
CPU time 10.27 seconds
Started Aug 02 05:13:53 PM PDT 24
Finished Aug 02 05:14:03 PM PDT 24
Peak memory 222528 kb
Host smart-0f673e53-56d5-4452-8181-422e77ec1d15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666173919 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.1666173919
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1963206902
Short name T829
Test name
Test status
Simulation time 345215550 ps
CPU time 4.78 seconds
Started Aug 02 05:14:09 PM PDT 24
Finished Aug 02 05:14:15 PM PDT 24
Peak memory 210380 kb
Host smart-c7be630a-8a6f-46a0-941a-990016f89e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963206902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1963206902
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3565139129
Short name T33
Test name
Test status
Simulation time 40036235 ps
CPU time 1.98 seconds
Started Aug 02 05:14:01 PM PDT 24
Finished Aug 02 05:14:03 PM PDT 24
Peak memory 209720 kb
Host smart-912aa9dd-553a-4fa8-9aec-257c6583a890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565139129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3565139129
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2475508690
Short name T99
Test name
Test status
Simulation time 85231429 ps
CPU time 0.8 seconds
Started Aug 02 05:14:03 PM PDT 24
Finished Aug 02 05:14:03 PM PDT 24
Peak memory 205968 kb
Host smart-e5c71220-f1bf-4eb3-8a15-8ad502c47f5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475508690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2475508690
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3298542143
Short name T289
Test name
Test status
Simulation time 40119427 ps
CPU time 3.06 seconds
Started Aug 02 05:14:01 PM PDT 24
Finished Aug 02 05:14:04 PM PDT 24
Peak memory 215652 kb
Host smart-4dfda875-35b0-4638-8ebd-d42f18b83e30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3298542143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3298542143
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1828653477
Short name T252
Test name
Test status
Simulation time 240375471 ps
CPU time 2.93 seconds
Started Aug 02 05:13:54 PM PDT 24
Finished Aug 02 05:13:57 PM PDT 24
Peak memory 206128 kb
Host smart-64013290-0b10-4fa0-8d42-ae9ec025405f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828653477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1828653477
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2337480231
Short name T246
Test name
Test status
Simulation time 144266570 ps
CPU time 2.08 seconds
Started Aug 02 05:13:56 PM PDT 24
Finished Aug 02 05:13:59 PM PDT 24
Peak memory 207776 kb
Host smart-37d18b25-4a7f-4679-9d18-c18df69b12fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337480231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2337480231
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2567719692
Short name T333
Test name
Test status
Simulation time 61185106 ps
CPU time 2.46 seconds
Started Aug 02 05:14:13 PM PDT 24
Finished Aug 02 05:14:15 PM PDT 24
Peak memory 214480 kb
Host smart-87952658-8022-47f5-af27-9d13527d6d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567719692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2567719692
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.2369063968
Short name T354
Test name
Test status
Simulation time 87138230 ps
CPU time 2.54 seconds
Started Aug 02 05:14:03 PM PDT 24
Finished Aug 02 05:14:06 PM PDT 24
Peak memory 214264 kb
Host smart-22691ac5-c497-4248-beb6-6acc7eec98e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369063968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2369063968
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3521537515
Short name T673
Test name
Test status
Simulation time 99692537 ps
CPU time 3.1 seconds
Started Aug 02 05:13:57 PM PDT 24
Finished Aug 02 05:14:00 PM PDT 24
Peak memory 215164 kb
Host smart-21fc6120-872d-4e0b-b7aa-736896882040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521537515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3521537515
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.3595072225
Short name T253
Test name
Test status
Simulation time 274273792 ps
CPU time 7.7 seconds
Started Aug 02 05:13:51 PM PDT 24
Finished Aug 02 05:13:59 PM PDT 24
Peak memory 218324 kb
Host smart-61a95b6e-209d-46fb-b97f-d35df4b25299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595072225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3595072225
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2218009993
Short name T469
Test name
Test status
Simulation time 87196417 ps
CPU time 2.39 seconds
Started Aug 02 05:14:05 PM PDT 24
Finished Aug 02 05:14:08 PM PDT 24
Peak memory 207032 kb
Host smart-662e2e82-186c-476a-a432-c56fa80a52ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218009993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2218009993
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3593920756
Short name T906
Test name
Test status
Simulation time 3669298854 ps
CPU time 33.99 seconds
Started Aug 02 05:14:00 PM PDT 24
Finished Aug 02 05:14:34 PM PDT 24
Peak memory 209184 kb
Host smart-933d8fc9-24fd-43bc-ad74-764f909934ec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593920756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3593920756
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.488673594
Short name T459
Test name
Test status
Simulation time 456124950 ps
CPU time 3.43 seconds
Started Aug 02 05:13:50 PM PDT 24
Finished Aug 02 05:13:53 PM PDT 24
Peak memory 206980 kb
Host smart-fc469e04-9ca0-49ee-800e-51c541053e4f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488673594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.488673594
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3711736763
Short name T704
Test name
Test status
Simulation time 879185536 ps
CPU time 5.95 seconds
Started Aug 02 05:13:56 PM PDT 24
Finished Aug 02 05:14:02 PM PDT 24
Peak memory 208860 kb
Host smart-a221bfb5-0fcb-4dd3-8c72-a3e6b6b53607
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711736763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3711736763
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.542605339
Short name T318
Test name
Test status
Simulation time 253680752 ps
CPU time 2.79 seconds
Started Aug 02 05:13:54 PM PDT 24
Finished Aug 02 05:13:57 PM PDT 24
Peak memory 209056 kb
Host smart-46b9e4ea-4412-49df-a7d2-f6f8699254bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542605339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.542605339
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3487540987
Short name T644
Test name
Test status
Simulation time 119447818 ps
CPU time 3.22 seconds
Started Aug 02 05:13:59 PM PDT 24
Finished Aug 02 05:14:02 PM PDT 24
Peak memory 206932 kb
Host smart-f8e88120-a1fe-4ab9-911b-c1fc1c65ad0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487540987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3487540987
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3772345524
Short name T226
Test name
Test status
Simulation time 2855850946 ps
CPU time 84.47 seconds
Started Aug 02 05:13:58 PM PDT 24
Finished Aug 02 05:15:23 PM PDT 24
Peak memory 222528 kb
Host smart-468b2157-4080-4a16-98f8-3448d59a3b60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772345524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3772345524
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3950475423
Short name T340
Test name
Test status
Simulation time 54522056 ps
CPU time 3.39 seconds
Started Aug 02 05:14:01 PM PDT 24
Finished Aug 02 05:14:04 PM PDT 24
Peak memory 209980 kb
Host smart-aa858552-bbb8-4587-97d7-fd6340ffd5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950475423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3950475423
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1120307787
Short name T537
Test name
Test status
Simulation time 10500146 ps
CPU time 0.86 seconds
Started Aug 02 05:14:02 PM PDT 24
Finished Aug 02 05:14:03 PM PDT 24
Peak memory 206024 kb
Host smart-e96b38e2-4f49-407c-ae56-bad65b9d87bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120307787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1120307787
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.925664204
Short name T438
Test name
Test status
Simulation time 153173455 ps
CPU time 3.45 seconds
Started Aug 02 05:14:02 PM PDT 24
Finished Aug 02 05:14:15 PM PDT 24
Peak memory 215480 kb
Host smart-6e09b022-26bc-4780-88a3-e760a781af4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=925664204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.925664204
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.90113800
Short name T635
Test name
Test status
Simulation time 40048440 ps
CPU time 2.62 seconds
Started Aug 02 05:14:00 PM PDT 24
Finished Aug 02 05:14:03 PM PDT 24
Peak memory 207888 kb
Host smart-3b0b29e3-c1fd-40b9-8901-00cd656a70e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90113800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.90113800
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.4258381477
Short name T48
Test name
Test status
Simulation time 673941085 ps
CPU time 4.24 seconds
Started Aug 02 05:14:10 PM PDT 24
Finished Aug 02 05:14:14 PM PDT 24
Peak memory 214248 kb
Host smart-cf8d64dd-f9ed-43a1-b7e0-6b543ddfa4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258381477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.4258381477
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_random.2375394718
Short name T101
Test name
Test status
Simulation time 856483098 ps
CPU time 4.65 seconds
Started Aug 02 05:13:58 PM PDT 24
Finished Aug 02 05:14:03 PM PDT 24
Peak memory 207600 kb
Host smart-07eb3a28-6adc-4362-80db-9c998fa4f8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375394718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2375394718
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3929584042
Short name T103
Test name
Test status
Simulation time 1841746033 ps
CPU time 34.84 seconds
Started Aug 02 05:13:59 PM PDT 24
Finished Aug 02 05:14:34 PM PDT 24
Peak memory 207744 kb
Host smart-79bba70a-24d2-4211-93cc-0e4a46f5f133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929584042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3929584042
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1383387216
Short name T471
Test name
Test status
Simulation time 37140131 ps
CPU time 2.38 seconds
Started Aug 02 05:14:08 PM PDT 24
Finished Aug 02 05:14:11 PM PDT 24
Peak memory 208756 kb
Host smart-ef5cfe86-35e8-4565-87c7-c470ee28df57
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383387216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1383387216
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2854050827
Short name T462
Test name
Test status
Simulation time 87700506 ps
CPU time 3.67 seconds
Started Aug 02 05:14:03 PM PDT 24
Finished Aug 02 05:14:06 PM PDT 24
Peak memory 206952 kb
Host smart-3d4fc30a-7ad4-4742-bd62-67dfe35fb135
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854050827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2854050827
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3242140442
Short name T492
Test name
Test status
Simulation time 135917235 ps
CPU time 2.54 seconds
Started Aug 02 05:14:05 PM PDT 24
Finished Aug 02 05:14:07 PM PDT 24
Peak memory 208832 kb
Host smart-7fdbca32-25b9-4c1b-8a6b-373ab0600593
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242140442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3242140442
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3494528367
Short name T365
Test name
Test status
Simulation time 145275085 ps
CPU time 3.22 seconds
Started Aug 02 05:14:06 PM PDT 24
Finished Aug 02 05:14:09 PM PDT 24
Peak memory 209116 kb
Host smart-0474daab-f785-4195-a0bc-d168de4033c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494528367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3494528367
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1594531249
Short name T705
Test name
Test status
Simulation time 124924523 ps
CPU time 3.53 seconds
Started Aug 02 05:13:58 PM PDT 24
Finished Aug 02 05:14:02 PM PDT 24
Peak memory 208196 kb
Host smart-f922272f-c134-46ed-b049-005754fc7987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594531249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1594531249
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2526428914
Short name T500
Test name
Test status
Simulation time 874161773 ps
CPU time 19.92 seconds
Started Aug 02 05:14:09 PM PDT 24
Finished Aug 02 05:14:29 PM PDT 24
Peak memory 209376 kb
Host smart-ecd9e80e-915d-40a8-82ee-f4ac4f88765e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526428914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2526428914
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1411692099
Short name T403
Test name
Test status
Simulation time 322835424 ps
CPU time 2.44 seconds
Started Aug 02 05:14:07 PM PDT 24
Finished Aug 02 05:14:09 PM PDT 24
Peak memory 209812 kb
Host smart-7034f3c1-39f9-458a-983a-bca6ebdb280a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411692099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1411692099
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1598028608
Short name T502
Test name
Test status
Simulation time 12639657 ps
CPU time 0.79 seconds
Started Aug 02 05:14:09 PM PDT 24
Finished Aug 02 05:14:10 PM PDT 24
Peak memory 206008 kb
Host smart-e8734e3e-c235-4926-9362-a81cbc663fe1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598028608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1598028608
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.940441647
Short name T424
Test name
Test status
Simulation time 199632002 ps
CPU time 3.73 seconds
Started Aug 02 05:13:59 PM PDT 24
Finished Aug 02 05:14:03 PM PDT 24
Peak memory 214660 kb
Host smart-48a0e484-9019-46d1-9562-ee78a87961e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=940441647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.940441647
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.201635956
Short name T37
Test name
Test status
Simulation time 52305190 ps
CPU time 2.9 seconds
Started Aug 02 05:14:00 PM PDT 24
Finished Aug 02 05:14:03 PM PDT 24
Peak memory 209884 kb
Host smart-47fe2251-4251-4155-8917-1b390ea31e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201635956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.201635956
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.516386273
Short name T106
Test name
Test status
Simulation time 120309486 ps
CPU time 1.86 seconds
Started Aug 02 05:14:18 PM PDT 24
Finished Aug 02 05:14:20 PM PDT 24
Peak memory 207328 kb
Host smart-6be107ba-c4b8-4088-92c0-6d673854a074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516386273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.516386273
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1860615168
Short name T555
Test name
Test status
Simulation time 292638999 ps
CPU time 2.88 seconds
Started Aug 02 05:14:02 PM PDT 24
Finished Aug 02 05:14:05 PM PDT 24
Peak memory 214328 kb
Host smart-5df1b577-5f10-4a34-b190-5558a15d1c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860615168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1860615168
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.2467729715
Short name T858
Test name
Test status
Simulation time 98681763 ps
CPU time 4.37 seconds
Started Aug 02 05:14:08 PM PDT 24
Finished Aug 02 05:14:13 PM PDT 24
Peak memory 222540 kb
Host smart-7a6850f9-47e5-4c31-9fdb-421f13cfc72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467729715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.2467729715
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.4231145770
Short name T589
Test name
Test status
Simulation time 191826083 ps
CPU time 2.64 seconds
Started Aug 02 05:14:10 PM PDT 24
Finished Aug 02 05:14:13 PM PDT 24
Peak memory 208996 kb
Host smart-3d742396-bd86-43d0-8bdc-d247d3fe2e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231145770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.4231145770
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1689590995
Short name T258
Test name
Test status
Simulation time 88530503 ps
CPU time 2.66 seconds
Started Aug 02 05:14:00 PM PDT 24
Finished Aug 02 05:14:03 PM PDT 24
Peak memory 208368 kb
Host smart-674249fd-9c80-49c1-a5a0-e01d9f7e0238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689590995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1689590995
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1358151012
Short name T878
Test name
Test status
Simulation time 86981638 ps
CPU time 3.79 seconds
Started Aug 02 05:14:23 PM PDT 24
Finished Aug 02 05:14:27 PM PDT 24
Peak memory 208540 kb
Host smart-b5c9a1e1-ec8f-400e-a13a-568cb185056a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358151012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1358151012
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.724321738
Short name T250
Test name
Test status
Simulation time 1583800820 ps
CPU time 7.49 seconds
Started Aug 02 05:14:07 PM PDT 24
Finished Aug 02 05:14:14 PM PDT 24
Peak memory 208848 kb
Host smart-b6d0ebb5-f116-4cc3-bfbd-f85542ab88a9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724321738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.724321738
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2895691539
Short name T624
Test name
Test status
Simulation time 244613274 ps
CPU time 3.04 seconds
Started Aug 02 05:14:01 PM PDT 24
Finished Aug 02 05:14:04 PM PDT 24
Peak memory 208788 kb
Host smart-732a97af-110e-4604-a679-cccb4914fb2e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895691539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2895691539
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2067918611
Short name T576
Test name
Test status
Simulation time 216841557 ps
CPU time 5.61 seconds
Started Aug 02 05:14:11 PM PDT 24
Finished Aug 02 05:14:17 PM PDT 24
Peak memory 208724 kb
Host smart-4c5914a3-463b-448e-937e-55f440bcb84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067918611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2067918611
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3432667571
Short name T795
Test name
Test status
Simulation time 243088421 ps
CPU time 3.34 seconds
Started Aug 02 05:14:09 PM PDT 24
Finished Aug 02 05:14:12 PM PDT 24
Peak memory 208636 kb
Host smart-3b7d8d24-e1cf-4707-ae81-6cd32a305dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432667571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3432667571
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.769770522
Short name T290
Test name
Test status
Simulation time 391475558 ps
CPU time 15.32 seconds
Started Aug 02 05:14:04 PM PDT 24
Finished Aug 02 05:14:20 PM PDT 24
Peak memory 220380 kb
Host smart-6e8d113a-9846-4342-b66b-40538dba9dd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769770522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.769770522
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.3468100438
Short name T785
Test name
Test status
Simulation time 425407110 ps
CPU time 5.36 seconds
Started Aug 02 05:14:08 PM PDT 24
Finished Aug 02 05:14:19 PM PDT 24
Peak memory 208576 kb
Host smart-4ddf501b-b4aa-482f-983a-15dac2082018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468100438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3468100438
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1859872224
Short name T577
Test name
Test status
Simulation time 70627965 ps
CPU time 1.81 seconds
Started Aug 02 05:14:08 PM PDT 24
Finished Aug 02 05:14:10 PM PDT 24
Peak memory 209700 kb
Host smart-2b4bdeac-e32e-42c6-abbc-0e7bef086c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859872224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1859872224
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2092724706
Short name T725
Test name
Test status
Simulation time 25138966 ps
CPU time 0.9 seconds
Started Aug 02 05:14:30 PM PDT 24
Finished Aug 02 05:14:31 PM PDT 24
Peak memory 205972 kb
Host smart-4d594ee2-30d1-4b05-94b5-a38bbabe0bc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092724706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2092724706
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3111653465
Short name T824
Test name
Test status
Simulation time 233825346 ps
CPU time 11.85 seconds
Started Aug 02 05:14:10 PM PDT 24
Finished Aug 02 05:14:22 PM PDT 24
Peak memory 214960 kb
Host smart-370671d3-45a7-4672-a6ae-21980cf05e2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3111653465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3111653465
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3697164509
Short name T664
Test name
Test status
Simulation time 410199312 ps
CPU time 6.58 seconds
Started Aug 02 05:14:12 PM PDT 24
Finished Aug 02 05:14:19 PM PDT 24
Peak memory 208196 kb
Host smart-4f8d0ed0-42ce-4b71-aa82-c4d931e047f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697164509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3697164509
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.4210231998
Short name T357
Test name
Test status
Simulation time 757010794 ps
CPU time 4.46 seconds
Started Aug 02 05:14:08 PM PDT 24
Finished Aug 02 05:14:13 PM PDT 24
Peak memory 218060 kb
Host smart-82c395ea-f7ce-4ed6-94bc-efa719777df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210231998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.4210231998
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3307861640
Short name T684
Test name
Test status
Simulation time 400959059 ps
CPU time 3.37 seconds
Started Aug 02 05:14:21 PM PDT 24
Finished Aug 02 05:14:25 PM PDT 24
Peak memory 214588 kb
Host smart-f9c5e5f6-81db-40b1-ac24-ac46861bca8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307861640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3307861640
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.426849824
Short name T329
Test name
Test status
Simulation time 272094571 ps
CPU time 6.14 seconds
Started Aug 02 05:14:22 PM PDT 24
Finished Aug 02 05:14:29 PM PDT 24
Peak memory 221316 kb
Host smart-74f13eec-0808-485e-acf1-168f8cc93030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426849824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.426849824
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2896990257
Short name T231
Test name
Test status
Simulation time 640861085 ps
CPU time 3.23 seconds
Started Aug 02 05:14:09 PM PDT 24
Finished Aug 02 05:14:13 PM PDT 24
Peak memory 209484 kb
Host smart-1a300fe5-bc95-4766-a6b6-32844a535147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896990257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2896990257
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1039015774
Short name T406
Test name
Test status
Simulation time 77201042 ps
CPU time 3.51 seconds
Started Aug 02 05:14:07 PM PDT 24
Finished Aug 02 05:14:11 PM PDT 24
Peak memory 207640 kb
Host smart-59960384-406b-411f-87f3-f7940cb9aecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039015774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1039015774
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.3763368989
Short name T452
Test name
Test status
Simulation time 83510432 ps
CPU time 2.63 seconds
Started Aug 02 05:14:03 PM PDT 24
Finished Aug 02 05:14:06 PM PDT 24
Peak memory 208472 kb
Host smart-5b31e5bf-506e-452a-a458-4581dd05d626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763368989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.3763368989
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3402237423
Short name T579
Test name
Test status
Simulation time 319582585 ps
CPU time 10.17 seconds
Started Aug 02 05:14:01 PM PDT 24
Finished Aug 02 05:14:11 PM PDT 24
Peak memory 208524 kb
Host smart-173c6ade-b6f2-4ebe-b951-6164ec317afd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402237423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3402237423
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3091758486
Short name T911
Test name
Test status
Simulation time 260277495 ps
CPU time 3.58 seconds
Started Aug 02 05:13:57 PM PDT 24
Finished Aug 02 05:14:01 PM PDT 24
Peak memory 208664 kb
Host smart-c8c91304-1ad1-443b-a7d7-d5e54cfd5328
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091758486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3091758486
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.2574055133
Short name T909
Test name
Test status
Simulation time 198638016 ps
CPU time 1.91 seconds
Started Aug 02 05:14:12 PM PDT 24
Finished Aug 02 05:14:14 PM PDT 24
Peak memory 208956 kb
Host smart-18c37a43-ec2b-4a0d-9c67-07d6dcb36b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574055133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2574055133
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.872944958
Short name T445
Test name
Test status
Simulation time 122491190 ps
CPU time 4.05 seconds
Started Aug 02 05:14:13 PM PDT 24
Finished Aug 02 05:14:17 PM PDT 24
Peak memory 208468 kb
Host smart-58ccc3c5-7642-411a-9d2c-3715578e3cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872944958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.872944958
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.4289096627
Short name T390
Test name
Test status
Simulation time 6912908321 ps
CPU time 44.75 seconds
Started Aug 02 05:14:07 PM PDT 24
Finished Aug 02 05:14:52 PM PDT 24
Peak memory 216344 kb
Host smart-b874e891-95f9-4824-bb5f-3de420e75441
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289096627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.4289096627
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.939373690
Short name T553
Test name
Test status
Simulation time 6113309890 ps
CPU time 52.51 seconds
Started Aug 02 05:14:21 PM PDT 24
Finished Aug 02 05:15:14 PM PDT 24
Peak memory 209604 kb
Host smart-e604d2a2-3d8a-447f-998e-bf946eb25763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939373690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.939373690
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3873763823
Short name T195
Test name
Test status
Simulation time 2162864939 ps
CPU time 8.96 seconds
Started Aug 02 05:14:24 PM PDT 24
Finished Aug 02 05:14:33 PM PDT 24
Peak memory 210112 kb
Host smart-155eca3f-af6e-4a59-8657-dc13936eddce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873763823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3873763823
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2111071602
Short name T510
Test name
Test status
Simulation time 29006799 ps
CPU time 0.72 seconds
Started Aug 02 05:14:09 PM PDT 24
Finished Aug 02 05:14:10 PM PDT 24
Peak memory 205952 kb
Host smart-233ef199-762f-4ed5-96d8-337b823192a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111071602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2111071602
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1610833776
Short name T102
Test name
Test status
Simulation time 122881058 ps
CPU time 2.66 seconds
Started Aug 02 05:14:08 PM PDT 24
Finished Aug 02 05:14:11 PM PDT 24
Peak memory 214352 kb
Host smart-7178b3d2-a655-4293-b86d-ad33bc86c00c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1610833776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1610833776
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.974601983
Short name T885
Test name
Test status
Simulation time 38083512 ps
CPU time 2.17 seconds
Started Aug 02 05:14:24 PM PDT 24
Finished Aug 02 05:14:27 PM PDT 24
Peak memory 215980 kb
Host smart-7178c040-ec79-49ec-b1fc-195493b0a4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974601983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.974601983
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2221005653
Short name T564
Test name
Test status
Simulation time 136854652 ps
CPU time 2.39 seconds
Started Aug 02 05:14:09 PM PDT 24
Finished Aug 02 05:14:12 PM PDT 24
Peak memory 209544 kb
Host smart-16539736-3d92-4c13-a257-2b790cf6aca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221005653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2221005653
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2066986746
Short name T827
Test name
Test status
Simulation time 386661874 ps
CPU time 2.88 seconds
Started Aug 02 05:14:06 PM PDT 24
Finished Aug 02 05:14:09 PM PDT 24
Peak memory 222544 kb
Host smart-64708f5e-a0cd-4b47-bcbe-3838c5cb311a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066986746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2066986746
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.4023929694
Short name T309
Test name
Test status
Simulation time 135279155 ps
CPU time 3.33 seconds
Started Aug 02 05:14:02 PM PDT 24
Finished Aug 02 05:14:05 PM PDT 24
Peak memory 214244 kb
Host smart-f84d89dc-d195-4854-994c-464f0dc678d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023929694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.4023929694
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.984594908
Short name T810
Test name
Test status
Simulation time 623176272 ps
CPU time 5.11 seconds
Started Aug 02 05:14:22 PM PDT 24
Finished Aug 02 05:14:27 PM PDT 24
Peak memory 222440 kb
Host smart-d54b1785-009a-4158-bd50-9aa6891d5bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984594908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.984594908
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1040083831
Short name T655
Test name
Test status
Simulation time 189915598 ps
CPU time 6.17 seconds
Started Aug 02 05:14:14 PM PDT 24
Finished Aug 02 05:14:21 PM PDT 24
Peak memory 208296 kb
Host smart-473b0eb3-17f1-4953-95d9-9f817d66fb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040083831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1040083831
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1904480985
Short name T206
Test name
Test status
Simulation time 294780505 ps
CPU time 7.13 seconds
Started Aug 02 05:14:10 PM PDT 24
Finished Aug 02 05:14:23 PM PDT 24
Peak memory 208060 kb
Host smart-5b8d4f71-07ac-488e-8f62-035d11326703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904480985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1904480985
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1311156897
Short name T181
Test name
Test status
Simulation time 123791767 ps
CPU time 3.9 seconds
Started Aug 02 05:14:28 PM PDT 24
Finished Aug 02 05:14:32 PM PDT 24
Peak memory 206788 kb
Host smart-5e594450-4025-472c-8f31-28c437fed8e4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311156897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1311156897
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2999933803
Short name T641
Test name
Test status
Simulation time 315176706 ps
CPU time 4.11 seconds
Started Aug 02 05:14:51 PM PDT 24
Finished Aug 02 05:14:55 PM PDT 24
Peak memory 206956 kb
Host smart-81e515c8-02fc-476c-905f-d22dbf8e3b51
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999933803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2999933803
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.1777239527
Short name T448
Test name
Test status
Simulation time 36779865 ps
CPU time 2.19 seconds
Started Aug 02 05:14:28 PM PDT 24
Finished Aug 02 05:14:30 PM PDT 24
Peak memory 206892 kb
Host smart-a01da4f7-1bc4-4a2f-83a3-2731ff8f7026
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777239527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1777239527
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1910184828
Short name T487
Test name
Test status
Simulation time 64532659 ps
CPU time 2.66 seconds
Started Aug 02 05:14:30 PM PDT 24
Finished Aug 02 05:14:33 PM PDT 24
Peak memory 215684 kb
Host smart-3e39270b-f2a1-4342-97ed-4fbfcea71d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910184828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1910184828
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.371030508
Short name T470
Test name
Test status
Simulation time 1257220205 ps
CPU time 10.89 seconds
Started Aug 02 05:14:17 PM PDT 24
Finished Aug 02 05:14:28 PM PDT 24
Peak memory 208024 kb
Host smart-5d70cdb4-015e-4f9e-8ace-924e34eb1579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371030508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.371030508
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.15192638
Short name T62
Test name
Test status
Simulation time 12109723989 ps
CPU time 29.25 seconds
Started Aug 02 05:14:11 PM PDT 24
Finished Aug 02 05:14:40 PM PDT 24
Peak memory 215568 kb
Host smart-65289855-cff8-4985-9805-547209344626
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15192638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.15192638
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1509063534
Short name T280
Test name
Test status
Simulation time 28809401 ps
CPU time 2.32 seconds
Started Aug 02 05:14:24 PM PDT 24
Finished Aug 02 05:14:27 PM PDT 24
Peak memory 207724 kb
Host smart-4876fb5f-331e-4d8b-9702-b37e0478ed79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509063534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1509063534
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.642312198
Short name T55
Test name
Test status
Simulation time 39351383 ps
CPU time 2.08 seconds
Started Aug 02 05:14:09 PM PDT 24
Finished Aug 02 05:14:11 PM PDT 24
Peak memory 209504 kb
Host smart-0527455c-d6c0-47cf-8290-a862eef8f13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642312198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.642312198
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2036125243
Short name T649
Test name
Test status
Simulation time 18488956 ps
CPU time 0.74 seconds
Started Aug 02 05:12:11 PM PDT 24
Finished Aug 02 05:12:12 PM PDT 24
Peak memory 205956 kb
Host smart-653d87de-f860-4300-8bb5-575e2a4cb75b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036125243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2036125243
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2902429937
Short name T436
Test name
Test status
Simulation time 945599137 ps
CPU time 7.16 seconds
Started Aug 02 05:12:19 PM PDT 24
Finished Aug 02 05:12:27 PM PDT 24
Peak memory 214704 kb
Host smart-5f4aa4ff-b55c-40b2-8478-eaf5dedb4143
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2902429937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2902429937
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1738121715
Short name T432
Test name
Test status
Simulation time 53367738 ps
CPU time 2.78 seconds
Started Aug 02 05:12:17 PM PDT 24
Finished Aug 02 05:12:20 PM PDT 24
Peak memory 221180 kb
Host smart-8bc59d4b-46ca-468e-a843-7bf14962d038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738121715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1738121715
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.572380995
Short name T74
Test name
Test status
Simulation time 117271054 ps
CPU time 3.03 seconds
Started Aug 02 05:12:12 PM PDT 24
Finished Aug 02 05:12:15 PM PDT 24
Peak memory 210132 kb
Host smart-217c32cd-ca12-40eb-a952-827d2a227131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572380995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.572380995
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1487814071
Short name T554
Test name
Test status
Simulation time 465936100 ps
CPU time 6.11 seconds
Started Aug 02 05:12:04 PM PDT 24
Finished Aug 02 05:12:10 PM PDT 24
Peak memory 214348 kb
Host smart-1f4b7514-3a7b-40fa-8882-92c0b8a7d313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487814071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1487814071
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2694675635
Short name T762
Test name
Test status
Simulation time 73010626 ps
CPU time 1.79 seconds
Started Aug 02 05:12:16 PM PDT 24
Finished Aug 02 05:12:18 PM PDT 24
Peak memory 214320 kb
Host smart-7009d8b8-82d3-4499-a8f6-c846a3e87ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694675635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2694675635
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.939817423
Short name T221
Test name
Test status
Simulation time 137708424 ps
CPU time 2.91 seconds
Started Aug 02 05:12:13 PM PDT 24
Finished Aug 02 05:12:21 PM PDT 24
Peak memory 214220 kb
Host smart-fa2e4ac7-ee5c-4386-b9ec-c6c57a73ee75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939817423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.939817423
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.1247052929
Short name T499
Test name
Test status
Simulation time 56009087 ps
CPU time 3.24 seconds
Started Aug 02 05:12:17 PM PDT 24
Finished Aug 02 05:12:21 PM PDT 24
Peak memory 208012 kb
Host smart-c38ee577-7582-42d9-8728-ba4723c010d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247052929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1247052929
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.6665389
Short name T591
Test name
Test status
Simulation time 90756937 ps
CPU time 3.67 seconds
Started Aug 02 05:12:11 PM PDT 24
Finished Aug 02 05:12:15 PM PDT 24
Peak memory 207988 kb
Host smart-01a293a7-0e7c-4410-8581-70ba8c1da921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6665389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.6665389
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3428254493
Short name T894
Test name
Test status
Simulation time 153435618 ps
CPU time 3.19 seconds
Started Aug 02 05:12:21 PM PDT 24
Finished Aug 02 05:12:25 PM PDT 24
Peak memory 208668 kb
Host smart-21bcbf38-7c81-4337-8075-e0213bd5d888
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428254493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3428254493
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.445907382
Short name T789
Test name
Test status
Simulation time 200705842 ps
CPU time 2.73 seconds
Started Aug 02 05:12:23 PM PDT 24
Finished Aug 02 05:12:26 PM PDT 24
Peak memory 206988 kb
Host smart-96ecb9e4-eb3d-4104-aff1-55ba9b7be780
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445907382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.445907382
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2209468354
Short name T211
Test name
Test status
Simulation time 175933083 ps
CPU time 2.57 seconds
Started Aug 02 05:12:14 PM PDT 24
Finished Aug 02 05:12:16 PM PDT 24
Peak memory 206980 kb
Host smart-ff6f4966-6e9b-4478-b437-0cba16a7ace5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209468354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2209468354
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3352173687
Short name T303
Test name
Test status
Simulation time 41082986 ps
CPU time 2.2 seconds
Started Aug 02 05:12:13 PM PDT 24
Finished Aug 02 05:12:15 PM PDT 24
Peak memory 215992 kb
Host smart-e1c9582c-c422-4b90-85e7-ae3e1039f49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352173687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3352173687
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1590574980
Short name T450
Test name
Test status
Simulation time 583112776 ps
CPU time 5.85 seconds
Started Aug 02 05:12:03 PM PDT 24
Finished Aug 02 05:12:09 PM PDT 24
Peak memory 207924 kb
Host smart-4deb7feb-92e5-4430-a6b0-4b91af510e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590574980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1590574980
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.155582281
Short name T194
Test name
Test status
Simulation time 2560941221 ps
CPU time 17.31 seconds
Started Aug 02 05:12:15 PM PDT 24
Finished Aug 02 05:12:32 PM PDT 24
Peak memory 216320 kb
Host smart-71f82f05-5b7f-41e8-bf35-25fab82586ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155582281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.155582281
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2429690695
Short name T580
Test name
Test status
Simulation time 394119210 ps
CPU time 4.68 seconds
Started Aug 02 05:12:16 PM PDT 24
Finished Aug 02 05:12:21 PM PDT 24
Peak memory 214332 kb
Host smart-882cafed-6430-4a78-a4f7-dc1892772982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429690695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2429690695
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1089956869
Short name T817
Test name
Test status
Simulation time 882466764 ps
CPU time 3.87 seconds
Started Aug 02 05:12:17 PM PDT 24
Finished Aug 02 05:12:21 PM PDT 24
Peak memory 210236 kb
Host smart-3d6a42da-2671-4a7b-b712-e48e1f2bc913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089956869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1089956869
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2686319074
Short name T449
Test name
Test status
Simulation time 96375264 ps
CPU time 0.76 seconds
Started Aug 02 05:12:18 PM PDT 24
Finished Aug 02 05:12:19 PM PDT 24
Peak memory 205960 kb
Host smart-126c9d9a-00fa-48f3-bdff-a34a6f8e12ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686319074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2686319074
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1211661421
Short name T389
Test name
Test status
Simulation time 1006843022 ps
CPU time 26.96 seconds
Started Aug 02 05:12:17 PM PDT 24
Finished Aug 02 05:12:44 PM PDT 24
Peak memory 215572 kb
Host smart-167bfd94-25af-4d10-919f-f5b774cf0507
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1211661421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1211661421
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1513074421
Short name T764
Test name
Test status
Simulation time 125706195 ps
CPU time 2.42 seconds
Started Aug 02 05:12:08 PM PDT 24
Finished Aug 02 05:12:11 PM PDT 24
Peak memory 219704 kb
Host smart-74c62a99-7b22-4e3e-9511-bacef55cee99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513074421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1513074421
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1521834196
Short name T802
Test name
Test status
Simulation time 81641955 ps
CPU time 3.76 seconds
Started Aug 02 05:12:16 PM PDT 24
Finished Aug 02 05:12:20 PM PDT 24
Peak memory 214268 kb
Host smart-f7c9c4b5-b4ca-4c8f-9927-734dc5317bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521834196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1521834196
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.951750095
Short name T53
Test name
Test status
Simulation time 609992690 ps
CPU time 4.44 seconds
Started Aug 02 05:12:22 PM PDT 24
Finished Aug 02 05:12:27 PM PDT 24
Peak memory 219884 kb
Host smart-2af50867-50a9-4ccf-8c76-4cf0b184fb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951750095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.951750095
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_sideload.874577416
Short name T109
Test name
Test status
Simulation time 3841205423 ps
CPU time 21.11 seconds
Started Aug 02 05:12:18 PM PDT 24
Finished Aug 02 05:12:39 PM PDT 24
Peak memory 208560 kb
Host smart-8a98fb58-bcca-4c97-92e6-8df23a3a1225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874577416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.874577416
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.2197640446
Short name T668
Test name
Test status
Simulation time 41386101 ps
CPU time 2.46 seconds
Started Aug 02 05:12:14 PM PDT 24
Finished Aug 02 05:12:17 PM PDT 24
Peak memory 207044 kb
Host smart-162ffb2e-7bb4-4ed0-bf94-fe03d6f67317
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197640446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2197640446
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3260207496
Short name T730
Test name
Test status
Simulation time 140484092 ps
CPU time 5.24 seconds
Started Aug 02 05:12:14 PM PDT 24
Finished Aug 02 05:12:19 PM PDT 24
Peak memory 208284 kb
Host smart-e38fc98d-caff-40a6-88cc-72ea986178d8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260207496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3260207496
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.1295640209
Short name T541
Test name
Test status
Simulation time 7622802979 ps
CPU time 34.82 seconds
Started Aug 02 05:12:10 PM PDT 24
Finished Aug 02 05:12:45 PM PDT 24
Peak memory 208852 kb
Host smart-b30fc757-4692-4338-b05f-990270cb1ef3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295640209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1295640209
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2651787974
Short name T382
Test name
Test status
Simulation time 289318250 ps
CPU time 2.74 seconds
Started Aug 02 05:12:18 PM PDT 24
Finished Aug 02 05:12:20 PM PDT 24
Peak memory 209864 kb
Host smart-12d39eff-2686-4717-bb22-7325235331f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651787974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2651787974
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2647529993
Short name T578
Test name
Test status
Simulation time 26372845 ps
CPU time 2.12 seconds
Started Aug 02 05:12:15 PM PDT 24
Finished Aug 02 05:12:18 PM PDT 24
Peak memory 208656 kb
Host smart-23aeae82-22e6-4abb-ab58-be554bab3ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647529993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2647529993
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2003267925
Short name T2
Test name
Test status
Simulation time 62340335 ps
CPU time 3.73 seconds
Started Aug 02 05:12:16 PM PDT 24
Finished Aug 02 05:12:20 PM PDT 24
Peak memory 207240 kb
Host smart-5af6d252-5535-4077-82a0-b36f9bb38cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003267925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2003267925
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3383499768
Short name T407
Test name
Test status
Simulation time 296822479 ps
CPU time 2.52 seconds
Started Aug 02 05:12:10 PM PDT 24
Finished Aug 02 05:12:13 PM PDT 24
Peak memory 210052 kb
Host smart-737c47d2-1ff2-4acd-9d88-22fdea6e0630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383499768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3383499768
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.457122117
Short name T601
Test name
Test status
Simulation time 19960431 ps
CPU time 0.75 seconds
Started Aug 02 05:12:24 PM PDT 24
Finished Aug 02 05:12:24 PM PDT 24
Peak memory 205148 kb
Host smart-018226de-34b7-409e-a4aa-d7a0ad4785c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457122117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.457122117
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.4286957193
Short name T560
Test name
Test status
Simulation time 259570578 ps
CPU time 2.5 seconds
Started Aug 02 05:12:26 PM PDT 24
Finished Aug 02 05:12:28 PM PDT 24
Peak memory 217800 kb
Host smart-a259e6b2-f75e-43c5-8626-b184809e2cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286957193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.4286957193
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.211063656
Short name T799
Test name
Test status
Simulation time 73272801 ps
CPU time 3 seconds
Started Aug 02 05:12:36 PM PDT 24
Finished Aug 02 05:12:39 PM PDT 24
Peak memory 218112 kb
Host smart-f26eb875-1405-4721-bc6c-ff1023869dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211063656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.211063656
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1640636438
Short name T861
Test name
Test status
Simulation time 48980241 ps
CPU time 1.68 seconds
Started Aug 02 05:12:24 PM PDT 24
Finished Aug 02 05:12:26 PM PDT 24
Peak memory 214364 kb
Host smart-14d76c2d-4134-4dc2-b892-5019aadeeb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640636438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1640636438
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3732281150
Short name T247
Test name
Test status
Simulation time 214718494 ps
CPU time 2.32 seconds
Started Aug 02 05:12:23 PM PDT 24
Finished Aug 02 05:12:25 PM PDT 24
Peak memory 214260 kb
Host smart-3abcd066-49ac-4a61-9676-612b5ee67f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732281150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3732281150
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_random.947235345
Short name T696
Test name
Test status
Simulation time 255658800 ps
CPU time 5.67 seconds
Started Aug 02 05:12:04 PM PDT 24
Finished Aug 02 05:12:10 PM PDT 24
Peak memory 222452 kb
Host smart-1b62a478-312d-45f1-98da-ca3a31d8bd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947235345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.947235345
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.331487111
Short name T311
Test name
Test status
Simulation time 700643380 ps
CPU time 9.13 seconds
Started Aug 02 05:12:13 PM PDT 24
Finished Aug 02 05:12:22 PM PDT 24
Peak memory 208620 kb
Host smart-4cfb6de7-5058-426b-bb8c-c3d07293370c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331487111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.331487111
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2726033909
Short name T597
Test name
Test status
Simulation time 1600653407 ps
CPU time 7.02 seconds
Started Aug 02 05:12:12 PM PDT 24
Finished Aug 02 05:12:19 PM PDT 24
Peak memory 208096 kb
Host smart-b3927aa7-eb57-4acf-9196-0c5d60801e3a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726033909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2726033909
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2083971932
Short name T467
Test name
Test status
Simulation time 37476582 ps
CPU time 2.16 seconds
Started Aug 02 05:12:23 PM PDT 24
Finished Aug 02 05:12:25 PM PDT 24
Peak memory 206928 kb
Host smart-29c349e8-3c45-45cd-83fb-c33454bbe721
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083971932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2083971932
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2606514072
Short name T711
Test name
Test status
Simulation time 62115348 ps
CPU time 2.35 seconds
Started Aug 02 05:12:18 PM PDT 24
Finished Aug 02 05:12:20 PM PDT 24
Peak memory 207008 kb
Host smart-d100f89d-9701-4939-8648-647a5e159238
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606514072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2606514072
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.2387481930
Short name T595
Test name
Test status
Simulation time 1862641361 ps
CPU time 11.77 seconds
Started Aug 02 05:12:24 PM PDT 24
Finished Aug 02 05:12:36 PM PDT 24
Peak memory 208756 kb
Host smart-b17118b2-866b-4721-a096-cb277a61ae9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387481930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.2387481930
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2362343890
Short name T881
Test name
Test status
Simulation time 296120193 ps
CPU time 3.37 seconds
Started Aug 02 05:12:10 PM PDT 24
Finished Aug 02 05:12:14 PM PDT 24
Peak memory 206744 kb
Host smart-970dae3c-2c2a-44a2-9fbe-2b39ee1a8183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362343890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2362343890
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1508712216
Short name T857
Test name
Test status
Simulation time 867234176 ps
CPU time 22.75 seconds
Started Aug 02 05:12:28 PM PDT 24
Finished Aug 02 05:12:51 PM PDT 24
Peak memory 222508 kb
Host smart-ed26bb6e-2614-4a00-b112-485f8f2a22e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508712216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1508712216
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.773934816
Short name T534
Test name
Test status
Simulation time 4970046627 ps
CPU time 34.95 seconds
Started Aug 02 05:12:25 PM PDT 24
Finished Aug 02 05:13:00 PM PDT 24
Peak memory 218212 kb
Host smart-53fb70c9-c7b3-4b0e-a8de-e5593881f8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773934816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.773934816
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2116485880
Short name T648
Test name
Test status
Simulation time 341112327 ps
CPU time 3.82 seconds
Started Aug 02 05:12:29 PM PDT 24
Finished Aug 02 05:12:33 PM PDT 24
Peak memory 209740 kb
Host smart-13d30709-83a4-41e8-9955-62251acd1fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116485880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2116485880
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.978391541
Short name T882
Test name
Test status
Simulation time 147129269 ps
CPU time 0.81 seconds
Started Aug 02 05:12:43 PM PDT 24
Finished Aug 02 05:12:44 PM PDT 24
Peak memory 205988 kb
Host smart-8aae9b5a-c3b3-4a6c-9a3e-fa866959b05c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978391541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.978391541
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3823965704
Short name T423
Test name
Test status
Simulation time 167665294 ps
CPU time 8.81 seconds
Started Aug 02 05:12:28 PM PDT 24
Finished Aug 02 05:12:37 PM PDT 24
Peak memory 214460 kb
Host smart-172b8b35-1691-4648-b22d-295f80a5c48c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3823965704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3823965704
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.321808187
Short name T456
Test name
Test status
Simulation time 488776259 ps
CPU time 12.07 seconds
Started Aug 02 05:12:29 PM PDT 24
Finished Aug 02 05:12:42 PM PDT 24
Peak memory 208236 kb
Host smart-351220c4-91c0-4f3b-894f-37f3e456de28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321808187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.321808187
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1720411082
Short name T586
Test name
Test status
Simulation time 1690400977 ps
CPU time 43.3 seconds
Started Aug 02 05:12:34 PM PDT 24
Finished Aug 02 05:13:17 PM PDT 24
Peak memory 214348 kb
Host smart-f7bc7ecf-0474-4ecb-b95d-5955e3510784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720411082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1720411082
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.218907715
Short name T715
Test name
Test status
Simulation time 40865443 ps
CPU time 1.52 seconds
Started Aug 02 05:12:41 PM PDT 24
Finished Aug 02 05:12:42 PM PDT 24
Peak memory 214304 kb
Host smart-218fa412-aa3a-40bc-ad83-27746a53af54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218907715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.218907715
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1480045323
Short name T708
Test name
Test status
Simulation time 95634440 ps
CPU time 2.76 seconds
Started Aug 02 05:12:26 PM PDT 24
Finished Aug 02 05:12:34 PM PDT 24
Peak memory 216104 kb
Host smart-0ee49315-9165-46fd-825e-9f12ea466f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480045323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1480045323
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3106803314
Short name T652
Test name
Test status
Simulation time 4768116780 ps
CPU time 8.43 seconds
Started Aug 02 05:12:25 PM PDT 24
Finished Aug 02 05:12:33 PM PDT 24
Peak memory 207724 kb
Host smart-632357ad-45ba-4245-bd4b-f66564049fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106803314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3106803314
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3412266742
Short name T358
Test name
Test status
Simulation time 3656703953 ps
CPU time 8.75 seconds
Started Aug 02 05:12:30 PM PDT 24
Finished Aug 02 05:12:39 PM PDT 24
Peak memory 208676 kb
Host smart-cd4238d0-4c57-456a-892b-e682c63efd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412266742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3412266742
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2127997542
Short name T774
Test name
Test status
Simulation time 110600126 ps
CPU time 2.11 seconds
Started Aug 02 05:12:19 PM PDT 24
Finished Aug 02 05:12:22 PM PDT 24
Peak memory 208508 kb
Host smart-97eff76d-f029-49c4-81ca-adfb12ff8c5a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127997542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2127997542
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2979077584
Short name T296
Test name
Test status
Simulation time 71324251 ps
CPU time 3.11 seconds
Started Aug 02 05:12:22 PM PDT 24
Finished Aug 02 05:12:25 PM PDT 24
Peak memory 206956 kb
Host smart-e2f755ff-29da-4c80-8937-cac5963247d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979077584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2979077584
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2427164114
Short name T81
Test name
Test status
Simulation time 6414901067 ps
CPU time 60.22 seconds
Started Aug 02 05:12:15 PM PDT 24
Finished Aug 02 05:13:15 PM PDT 24
Peak memory 209060 kb
Host smart-359bd4fd-517d-4d5b-a30c-aeef7af6d8fd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427164114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2427164114
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1660343214
Short name T515
Test name
Test status
Simulation time 1294052063 ps
CPU time 11.78 seconds
Started Aug 02 05:12:39 PM PDT 24
Finished Aug 02 05:12:51 PM PDT 24
Peak memory 208784 kb
Host smart-6e1b6ba9-8f8e-4d32-9732-a8ab6f722a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660343214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1660343214
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.859798689
Short name T558
Test name
Test status
Simulation time 283438353 ps
CPU time 1.82 seconds
Started Aug 02 05:12:38 PM PDT 24
Finished Aug 02 05:12:40 PM PDT 24
Peak memory 206984 kb
Host smart-5590e443-7b7c-440e-850b-39f597615e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859798689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.859798689
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.107540409
Short name T629
Test name
Test status
Simulation time 228246174 ps
CPU time 7.76 seconds
Started Aug 02 05:12:22 PM PDT 24
Finished Aug 02 05:12:30 PM PDT 24
Peak memory 222444 kb
Host smart-61716371-ed88-41ee-9463-ded408d55ef7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107540409 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.107540409
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.1337737472
Short name T242
Test name
Test status
Simulation time 1205260313 ps
CPU time 4.26 seconds
Started Aug 02 05:12:31 PM PDT 24
Finished Aug 02 05:12:35 PM PDT 24
Peak memory 208044 kb
Host smart-675a76fb-b0b6-44ef-ba3f-f79ccd8de036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337737472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1337737472
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.4111997215
Short name T645
Test name
Test status
Simulation time 150220621 ps
CPU time 1.68 seconds
Started Aug 02 05:12:25 PM PDT 24
Finished Aug 02 05:12:27 PM PDT 24
Peak memory 210260 kb
Host smart-73544c0f-f7b6-40ad-a0e3-5000dc224346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111997215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.4111997215
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.567594827
Short name T743
Test name
Test status
Simulation time 14150953 ps
CPU time 0.74 seconds
Started Aug 02 05:12:32 PM PDT 24
Finished Aug 02 05:12:33 PM PDT 24
Peak memory 205996 kb
Host smart-3af230c5-137c-4d81-92fd-bb89e56f169f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567594827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.567594827
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3940541096
Short name T888
Test name
Test status
Simulation time 204130932 ps
CPU time 4.65 seconds
Started Aug 02 05:12:18 PM PDT 24
Finished Aug 02 05:12:23 PM PDT 24
Peak memory 221184 kb
Host smart-9a42b92d-98d4-407c-9acb-4d2fb69cc1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940541096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3940541096
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3678427108
Short name T869
Test name
Test status
Simulation time 328375399 ps
CPU time 3.2 seconds
Started Aug 02 05:12:16 PM PDT 24
Finished Aug 02 05:12:20 PM PDT 24
Peak memory 210232 kb
Host smart-cf64c0d2-1ad5-450c-94e7-8d21d734f996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678427108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3678427108
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.20980848
Short name T86
Test name
Test status
Simulation time 316450131 ps
CPU time 2.82 seconds
Started Aug 02 05:12:17 PM PDT 24
Finished Aug 02 05:12:20 PM PDT 24
Peak memory 222404 kb
Host smart-e8d7d422-8075-40fa-a7af-d826f2758e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20980848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.20980848
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.575670981
Short name T749
Test name
Test status
Simulation time 124951605 ps
CPU time 3.44 seconds
Started Aug 02 05:12:28 PM PDT 24
Finished Aug 02 05:12:32 PM PDT 24
Peak memory 220280 kb
Host smart-d20d46a4-ac4e-41a1-94bf-c26a5d8bb208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575670981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.575670981
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.595993780
Short name T344
Test name
Test status
Simulation time 578060599 ps
CPU time 5.34 seconds
Started Aug 02 05:12:29 PM PDT 24
Finished Aug 02 05:12:35 PM PDT 24
Peak memory 210044 kb
Host smart-0c759142-74ba-4374-9045-6963d2ef7a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595993780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.595993780
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3744105305
Short name T254
Test name
Test status
Simulation time 199688956 ps
CPU time 3.71 seconds
Started Aug 02 05:12:35 PM PDT 24
Finished Aug 02 05:12:39 PM PDT 24
Peak memory 214388 kb
Host smart-e4466234-45c2-41af-98d8-9f1154032203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744105305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3744105305
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1886699041
Short name T338
Test name
Test status
Simulation time 40383323 ps
CPU time 2.31 seconds
Started Aug 02 05:12:25 PM PDT 24
Finished Aug 02 05:12:28 PM PDT 24
Peak memory 208844 kb
Host smart-49b84800-0ccc-41d8-8da5-28d1d0d5a7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886699041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1886699041
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2220795152
Short name T334
Test name
Test status
Simulation time 115761464 ps
CPU time 4.86 seconds
Started Aug 02 05:12:33 PM PDT 24
Finished Aug 02 05:12:38 PM PDT 24
Peak memory 209044 kb
Host smart-09743c70-e146-4649-9dc3-24e5927b10b0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220795152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2220795152
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.335418108
Short name T255
Test name
Test status
Simulation time 104749772 ps
CPU time 4.13 seconds
Started Aug 02 05:12:33 PM PDT 24
Finished Aug 02 05:12:38 PM PDT 24
Peak memory 208728 kb
Host smart-d8ff848b-d6da-4419-80c0-6b9a5140e57f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335418108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.335418108
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.2782034082
Short name T870
Test name
Test status
Simulation time 190070706 ps
CPU time 2.72 seconds
Started Aug 02 05:12:23 PM PDT 24
Finished Aug 02 05:12:26 PM PDT 24
Peak memory 207688 kb
Host smart-c6baf52c-4420-47d1-b840-e17e06924c4b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782034082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2782034082
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.4280453123
Short name T336
Test name
Test status
Simulation time 99992723 ps
CPU time 3.03 seconds
Started Aug 02 05:12:21 PM PDT 24
Finished Aug 02 05:12:24 PM PDT 24
Peak memory 214316 kb
Host smart-0bc05a78-6cfa-4c8a-8247-e7737dd48bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280453123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.4280453123
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3940546969
Short name T458
Test name
Test status
Simulation time 427218787 ps
CPU time 4.27 seconds
Started Aug 02 05:12:28 PM PDT 24
Finished Aug 02 05:12:32 PM PDT 24
Peak memory 206884 kb
Host smart-51fd1b2e-d631-499f-a5e2-edfabb321913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940546969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3940546969
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.4029534806
Short name T779
Test name
Test status
Simulation time 1696780941 ps
CPU time 34.98 seconds
Started Aug 02 05:12:21 PM PDT 24
Finished Aug 02 05:12:56 PM PDT 24
Peak memory 214836 kb
Host smart-5ba76892-d5e9-4d39-b966-ca6946059feb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029534806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.4029534806
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1785958037
Short name T890
Test name
Test status
Simulation time 2968868132 ps
CPU time 8.48 seconds
Started Aug 02 05:12:31 PM PDT 24
Finished Aug 02 05:12:40 PM PDT 24
Peak memory 209104 kb
Host smart-4682eae8-90b3-4eb9-a120-bfb05d9847f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785958037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1785958037
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1004681645
Short name T496
Test name
Test status
Simulation time 116679870 ps
CPU time 2.16 seconds
Started Aug 02 05:12:21 PM PDT 24
Finished Aug 02 05:12:23 PM PDT 24
Peak memory 209920 kb
Host smart-b893fea1-999c-4689-9460-be35441ecd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004681645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1004681645
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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