Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
71.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	17	32	65.31

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	16	19	54.29	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	48	1			T46	1		T47	1		T48	1
auto[OpGenId]	13	1			T59	1		T209	1		T66	1
auto[OpGenSwOut]	17	1			T54	1		T7	1		T210	1
auto[OpGenHwOut]	11	1			T6	1		T7	1		T8	2

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1481	1			T44	1		T26	2		T55	2
auto[StInit]	90	1			T54	1		T46	1		T47	1
auto[StCreatorRootKey]	51	1			T81	2		T48	1		T6	1
auto[StOwnerIntKey]	41	1			T44	1		T7	1		T59	1
auto[StOwnerKey]	42	1			T5	1		T44	1		T37	1
auto[StDisabled]	465	1			T44	2		T131	1		T26	1
auto[StInvalid]	50	1			T35	1		T50	1		T211	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3215

1

T1

1

T2

1

T3

1

auto[1]

89

1

T54

1

T46

1

T47

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1477	1			T44	1		T26	2		T55	2
auto[StReset]	auto[1]	4	1			T51	1		T52	1		T53	1
auto[StInit]	auto[0]	47	1			T60	1		T61	1		T121	1
auto[StInit]	auto[1]	43	1			T54	1		T46	1		T47	1
auto[StCreatorRootKey]	auto[0]	34	1			T81	2		T7	1		T41	1
auto[StCreatorRootKey]	auto[1]	17	1			T48	1		T6	1		T8	1
auto[StOwnerIntKey]	auto[0]	30	1			T44	1		T19	1		T43	1
auto[StOwnerIntKey]	auto[1]	11	1			T7	1		T59	1		T66	1
auto[StOwnerKey]	auto[0]	34	1			T5	1		T44	1		T37	1
auto[StOwnerKey]	auto[1]	8	1			T28	1		T66	1		T185	1
auto[StDisabled]	auto[0]	459	1			T44	2		T131	1		T26	1
auto[StDisabled]	auto[1]	6	1			T7	1		T185	1		T212	1
auto[StInvalid]	auto[0]	50	1			T35	1		T50	1		T211	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	16	19	54.29	16

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	4
[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[StOwnerIntKey]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpGenSwOut]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	4	1			T51	1		T52	1		T53	1
auto[StInit]	auto[OpAdvance]	23	1			T46	1		T47	1		T6	1
auto[StInit]	auto[OpGenId]	4	1			T209	1		T69	1		T213	1
auto[StInit]	auto[OpGenSwOut]	10	1			T54	1		T210	1		T214	1
auto[StInit]	auto[OpGenHwOut]	6	1			T8	2		T70	1		T215	1
auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T48	1		T8	1		T216	1
auto[StCreatorRootKey]	auto[OpGenId]	4	1			T217	1		T218	1		T77	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	2	1			T57	1		T213	1		-	-
auto[StCreatorRootKey]	auto[OpGenHwOut]	2	1			T6	1		T53	1		-	-
auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T53	1		T219	1		T220	1
auto[StOwnerIntKey]	auto[OpGenId]	2	1			T59	1		T66	1		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T7	1		T53	1		T221	1
auto[StOwnerKey]	auto[OpAdvance]	3	1			T66	1		T222	1		T173	1
auto[StOwnerKey]	auto[OpGenId]	2	1			T185	1		T223	1		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T224	1		T225	1		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	1	1			T28	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	3	1			T185	1		T226	1		T227	1
auto[StDisabled]	auto[OpGenId]	1	1			T228	1		-	-		-	-
auto[StDisabled]	auto[OpGenHwOut]	2	1			T7	1		T212	1		-	-