Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.05	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	76	254	76.97

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	57	223	79.64	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4776

1

T1

13

T2

9

T3

8

auto[1]

597

1

T17

2

T18

1

T86

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4776

1

T1

13

T2

9

T3

8

auto[1]

597

1

T17

2

T18

1

T86

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4814

1

T1

5

T2

9

T3

8

auto[1]

559

1

T1

8

T14

3

T18

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4814

1

T1

5

T2

9

T3

8

auto[1]

559

1

T1

8

T14

3

T18

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	427	1			T1	4		T4	1		T16	1
auto[OpGenId]	1152	1			T1	2		T4	2		T18	1
auto[OpGenSwOut]	1110	1			T1	1		T4	5		T15	1
auto[OpGenHwOut]	2623	1			T1	6		T2	9		T3	8
auto[OpDisable]	61	1			T55	2		T60	1		T7	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	427	1			T1	4		T4	1		T16	1
auto[OpGenId]	1152	1			T1	2		T4	2		T18	1
auto[OpGenSwOut]	1110	1			T1	1		T4	5		T15	1
auto[OpGenHwOut]	2623	1			T1	6		T2	9		T3	8
auto[OpDisable]	61	1			T55	2		T60	1		T7	2

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4800

1

T1

13

T2

6

T3

5

auto[1]

573

1

T2

3

T3

3

T44

2

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4800

1

T1

13

T2

6

T3

5

auto[1]

573

1

T2

3

T3

3

T44

2

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5089

1

T1

5

T2

9

T3

8

auto[1]

284

1

T1

8

T79

1

T144

1

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1852	1			T1	3		T2	1		T3	1
auto[1]	670	1			T1	10		T2	1		T3	2
auto[2]	776	1			T2	2		T3	1		T4	1
auto[3]	681	1			T2	3		T4	1		T14	1
auto[4]	355	1			T4	1		T17	2		T44	1
auto[5]	336	1			T2	1		T3	2		T4	1
auto[6]	355	1			T3	2		T14	4		T17	2
auto[7]	348	1			T2	1		T4	3		T17	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1394	1			T2	2		T3	4		T4	5
clear_one[1]	670	1			T1	10		T2	1		T3	2
clear_one[2]	776	1			T2	2		T3	1		T4	1
clear_one[3]	681	1			T2	3		T4	1		T14	1
clear_none	1852	1			T1	3		T2	1		T3	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1012	1			T2	1		T4	3		T14	3
auto[StInit]	640	1			T1	4		T2	1		T3	1
auto[StCreatorRootKey]	577	1			T1	3		T2	1		T3	1
auto[StOwnerIntKey]	537	1			T1	2		T2	1		T3	1
auto[StOwnerKey]	490	1			T2	1		T3	1		T14	1
auto[StDisabled]	1857	1			T1	4		T2	4		T3	4
auto[StInvalid]	260	1			T35	1		T36	4		T50	5

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1012	1			T2	1		T4	3		T14	3
auto[StInit]	640	1			T1	4		T2	1		T3	1
auto[StCreatorRootKey]	577	1			T1	3		T2	1		T3	1
auto[StOwnerIntKey]	537	1			T1	2		T2	1		T3	1
auto[StOwnerKey]	490	1			T2	1		T3	1		T14	1
auto[StDisabled]	1857	1			T1	4		T2	4		T3	4
auto[StInvalid]	260	1			T35	1		T36	4		T50	5

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	57	223	79.64	57

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[1] - auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[1] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[4]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[5]]	[auto[StOwnerIntKey]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[6] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[6] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	8	1			T230	2		T231	1		T232	1
auto[0]	auto[StReset]	auto[OpGenId]	173	1			T44	1		T35	2		T197	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	143	1			T4	1		T44	1		T25	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	257	1			T2	1		T14	1		T17	1
auto[0]	auto[StInit]	auto[OpAdvance]	37	1			T144	1		T6	1		T8	1
auto[0]	auto[StInit]	auto[OpGenId]	115	1			T44	2		T195	1		T55	2
auto[0]	auto[StInit]	auto[OpGenSwOut]	81	1			T18	1		T81	1		T83	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	176	1			T1	1		T3	1		T44	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	20	1			T4	1		T16	1		T190	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	53	1			T81	1		T83	1		T144	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	51	1			T15	1		T108	1		T188	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	91	1			T233	1		T203	1		T60	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	16	1			T192	1		T234	1		T235	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	37	1			T1	1		T25	1		T68	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	44	1			T18	1		T81	1		T196	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	67	1			T1	1		T130	1		T131	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	11	1			T231	2		T236	1		T178	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	13	1			T86	1		T110	1		T7	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	29	1			T44	1		T55	1		T201	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	51	1			T44	1		T205	1		T198	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	28	1			T198	1		T237	2		T238	1
auto[0]	auto[StDisabled]	auto[OpGenId]	61	1			T131	1		T208	2		T60	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	49	1			T190	1		T60	1		T61	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	152	1			T86	1		T204	1		T207	1
auto[0]	auto[StDisabled]	auto[OpDisable]	14	1			T55	1		T239	1		T72	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	10	1			T240	1		T89	1		T241	1
auto[0]	auto[StInvalid]	auto[OpGenId]	21	1			T36	1		T242	2		T243	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	22	1			T38	1		T88	1		T244	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	22	1			T50	1		T88	1		T245	2
auto[1]	auto[StReset]	auto[OpGenId]	19	1			T7	1		T246	1		T210	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	12	1			T25	1		T247	1		T248	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	44	1			T14	1		T130	1		T249	2
auto[1]	auto[StInit]	auto[OpAdvance]	10	1			T1	3		T135	2		T250	3
auto[1]	auto[StInit]	auto[OpGenId]	6	1			T121	1		T185	1		T251	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	6	1			T8	1		T252	1		T253	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	15	1			T14	1		T254	1		T255	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T256	1		T53	1		T257	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T55	1		T135	2		T182	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T1	1		T78	1		T7	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	29	1			T1	2		T205	1		T61	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T60	1		T135	2		T258	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T26	1		T200	1		T259	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T135	1		T260	1		T261	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	46	1			T3	1		T87	1		T262	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T235	1		T247	1		T102	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	19	1			T55	1		T6	1		T237	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T61	1		T263	1		T264	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	28	1			T2	1		T207	1		T7	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	29	1			T1	1		T199	1		T90	1
auto[1]	auto[StDisabled]	auto[OpGenId]	45	1			T1	1		T25	1		T208	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	52	1			T60	1		T265	1		T266	2
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	175	1			T1	2		T3	1		T14	2
auto[1]	auto[StDisabled]	auto[OpDisable]	7	1			T206	1		T216	1		T183	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	6	1			T36	1		T245	1		T267	1
auto[1]	auto[StInvalid]	auto[OpGenId]	14	1			T268	1		T89	2		T269	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	16	1			T38	1		T88	1		T244	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T38	1		T88	1		T245	1
auto[2]	auto[StReset]	auto[OpGenId]	19	1			T68	1		T64	1		T268	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	14	1			T189	1		T19	1		T270	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	51	1			T25	1		T35	1		T262	2
auto[2]	auto[StInit]	auto[OpAdvance]	6	1			T271	1		T272	1		T273	1
auto[2]	auto[StInit]	auto[OpGenId]	10	1			T55	1		T270	1		T64	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	14	1			T4	1		T274	1		T210	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	31	1			T87	1		T204	1		T207	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T275	1		T276	1		T277	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T55	1		T113	1		T265	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T49	1		T7	1		T193	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	38	1			T130	1		T204	1		T84	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T276	1		T186	1		T278	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T108	1		T7	1		T51	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	21	1			T55	3		T116	1		T7	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	46	1			T205	1		T201	1		T111	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T279	1		T276	1		T280	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	13	1			T7	2		T184	1		T281	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	20	1			T202	1		T238	3		T66	2
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	50	1			T87	1		T282	1		T238	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	27	1			T117	1		T235	1		T283	1
auto[2]	auto[StDisabled]	auto[OpGenId]	63	1			T25	1		T131	1		T197	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	66	1			T44	1		T55	1		T193	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	182	1			T2	2		T3	1		T17	1
auto[2]	auto[StDisabled]	auto[OpDisable]	13	1			T8	1		T284	1		T64	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	7	1			T50	1		T211	1		T89	1
auto[2]	auto[StInvalid]	auto[OpGenId]	6	1			T285	1		T286	1		T287	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T92	1		T288	1		T289	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T35	1		T290	2		T89	1
auto[3]	auto[StReset]	auto[OpGenId]	15	1			T114	1		T117	1		T121	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	26	1			T60	1		T254	2		T182	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	45	1			T204	1		T205	1		T249	1
auto[3]	auto[StInit]	auto[OpAdvance]	3	1			T291	1		T292	1		T293	1
auto[3]	auto[StInit]	auto[OpGenId]	9	1			T7	1		T206	1		T185	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	8	1			T189	1		T154	1		T294	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	15	1			T130	1		T26	1		T295	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	13	1			T7	1		T216	1		T281	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	17	1			T194	1		T7	1		T8	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T7	1		T206	1		T296	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	47	1			T87	1		T207	1		T249	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T65	1		T297	2		T298	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T60	1		T296	1		T155	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T83	1		T254	1		T128	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	56	1			T2	1		T17	1		T204	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T216	1		T227	1		T299	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	12	1			T184	1		T300	1		T297	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T25	1		T190	1		T301	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	43	1			T262	1		T249	1		T111	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	14	1			T26	1		T91	1		T302	1
auto[3]	auto[StDisabled]	auto[OpGenId]	57	1			T26	1		T61	1		T7	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	44	1			T4	1		T201	1		T60	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	147	1			T2	2		T14	1		T44	1
auto[3]	auto[StDisabled]	auto[OpDisable]	6	1			T303	1		T71	1		T185	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	6	1			T50	1		T211	1		T288	1
auto[3]	auto[StInvalid]	auto[OpGenId]	13	1			T92	1		T211	1		T288	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T290	1		T304	2		T305	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T306	1		T285	1		T307	1
auto[4]	auto[StReset]	auto[OpGenId]	15	1			T55	1		T121	1		T8	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	13	1			T281	1		T285	1		T298	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	24	1			T87	1		T204	1		T207	1
auto[4]	auto[StInit]	auto[OpAdvance]	2	1			T216	1		T308	1		-	-
auto[4]	auto[StInit]	auto[OpGenId]	5	1			T55	1		T309	1		T221	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	6	1			T4	1		T61	1		T216	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	9	1			T17	1		T310	1		T185	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T44	1		T186	1		T53	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T55	1		T311	1		T312	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T270	1		T281	1		T313	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	25	1			T55	1		T255	1		T314	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T60	1		T315	1		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T7	1		T279	1		T316	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T317	1		T318	1		T219	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	10	1			T207	1		T319	1		T314	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T250	1		-	-		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	5	1			T316	1		T74	2		T320	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T291	1		T321	1		T322	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T84	1		T319	1		T115	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	17	1			T55	1		T79	1		T198	1
auto[4]	auto[StDisabled]	auto[OpGenId]	24	1			T202	1		T7	1		T66	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	31	1			T86	1		T25	1		T195	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	81	1			T17	1		T205	1		T68	1
auto[4]	auto[StDisabled]	auto[OpDisable]	8	1			T55	1		T7	1		T73	1
auto[4]	auto[StInvalid]	auto[OpGenId]	5	1			T92	1		T240	1		T323	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T36	1		T287	1		T324	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	1	1			T325	1		-	-		-	-
auto[5]	auto[StReset]	auto[OpGenId]	10	1			T216	1		T326	1		T298	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	11	1			T196	2		T19	1		T91	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	25	1			T130	1		T36	1		T206	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T253	1		T229	1		-	-
auto[5]	auto[StInit]	auto[OpGenId]	8	1			T182	1		T298	1		T253	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	6	1			T183	1		T327	1		T53	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	14	1			T249	1		T328	1		T329	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T330	1		T331	1		T332	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T80	1		T333	1		T90	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T184	1		T334	1		T221	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T2	1		T3	1		T117	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T97	1		T335	1		T336	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T203	1		T337	1		T338	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	17	1			T4	1		T14	1		T61	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T53	1		T339	1		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenId]	2	1			T340	1		T53	1		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T55	1		T254	1		T266	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T204	1		T61	1		T295	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	12	1			T321	1		T231	1		T341	1
auto[5]	auto[StDisabled]	auto[OpGenId]	28	1			T85	1		T6	1		T8	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	30	1			T189	1		T81	1		T85	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	69	1			T3	1		T130	2		T204	1
auto[5]	auto[StDisabled]	auto[OpDisable]	4	1			T8	1		T342	1		T343	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	5	1			T290	1		T344	1		T345	1
auto[5]	auto[StInvalid]	auto[OpGenId]	8	1			T50	1		T89	1		T241	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T290	1		T248	1		T346	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T211	1		T268	1		T347	1
auto[6]	auto[StReset]	auto[OpGenId]	5	1			T313	1		T320	1		T348	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	7	1			T254	1		T91	1		T349	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	25	1			T14	1		T262	1		T117	1
auto[6]	auto[StInit]	auto[OpAdvance]	4	1			T93	1		T350	1		T351	1
auto[6]	auto[StInit]	auto[OpGenId]	4	1			T6	1		T326	2		T352	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	1	1			T353	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenHwOut]	10	1			T197	1		T205	1		T314	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T7	1		T354	1		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T18	1		T171	1		T355	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T136	1		T356	1		T357	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T14	1		T17	1		T115	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T55	1		T250	1		T358	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T183	1		T281	1		T53	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T266	1		T327	1		T359	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T115	1		T360	1		T71	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T361	1		T250	2		T275	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	14	1			T116	1		T254	1		T128	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T85	1		T271	2		T362	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T3	1		T14	1		T17	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	17	1			T116	2		T235	1		T300	1
auto[6]	auto[StDisabled]	auto[OpGenId]	32	1			T44	1		T25	1		T333	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	30	1			T85	1		T113	1		T7	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	87	1			T3	1		T14	1		T44	1
auto[6]	auto[StDisabled]	auto[OpDisable]	6	1			T60	1		T7	1		T359	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	2	1			T36	1		T363	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	3	1			T364	1		T365	1		T366	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T367	1		T345	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T38	1		T241	1		T365	1
auto[7]	auto[StReset]	auto[OpGenId]	24	1			T4	2		T55	1		T7	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	5	1			T60	1		T64	1		T75	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	22	1			T130	1		T205	1		T7	1
auto[7]	auto[StInit]	auto[OpAdvance]	1	1			T318	1		-	-		-	-
auto[7]	auto[StInit]	auto[OpGenId]	4	1			T281	1		T93	1		T212	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	8	1			T238	3		T368	1		T129	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	14	1			T2	1		T369	1		T238	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T197	1		T370	1		T326	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T371	1		T372	1		T373	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T60	1		T28	1		T183	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	14	1			T262	1		T60	1		T127	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T374	1		-	-		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T238	1		T252	1		T375	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T136	1		T238	1		T376	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	17	1			T6	1		T377	1		T206	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T7	1		T134	2		T378	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	4	1			T333	1		T379	2		T213	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T192	1		T7	1		T154	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T360	1		T380	1		T381	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	14	1			T382	1		T184	2		T66	1
auto[7]	auto[StDisabled]	auto[OpGenId]	33	1			T83	1		T192	1		T7	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	29	1			T4	1		T26	1		T134	2
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	71	1			T17	1		T87	1		T262	2
auto[7]	auto[StDisabled]	auto[OpDisable]	3	1			T322	1		T383	1		T384	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	4	1			T385	1		T386	1		T307	1
auto[7]	auto[StInvalid]	auto[OpGenId]	5	1			T50	1		T243	1		T324	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T245	1		T240	1		T387	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T38	1		T88	1		T242	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1394

1

T2

2

T3

4

T4

5

clear_one[1]

auto[0]

auto[0]

auto[0]

374

1

T1

4

T14

2

T17

1

clear_one[1]

auto[0]

auto[0]

auto[1]

130

1

T2

1

T3

2

T205

2

clear_one[1]

auto[0]

auto[1]

auto[0]

132

1

T1

6

T14

2

T87

1

clear_one[1]

auto[0]

auto[1]

auto[1]

34

1

T117

1

T60

1

T63

1

clear_one[2]

auto[0]

auto[0]

auto[0]

452

1

T4

1

T87

4

T25

2

clear_one[2]

auto[0]

auto[0]

auto[1]

123

1

T2

2

T3

1

T44

1

clear_one[2]

auto[1]

auto[0]

auto[0]

140

1

T17

1

T131

1

T204

3

clear_one[2]

auto[1]

auto[0]

auto[1]

61

1

T55

3

T112

1

T116

1

clear_one[3]

auto[0]

auto[0]

auto[0]

367

1

T2

3

T4

1

T130

1

clear_one[3]

auto[0]

auto[1]

auto[0]

134

1

T14

1

T44

1

T87

2

clear_one[3]

auto[1]

auto[0]

auto[0]

135

1

T17

1

T204

1

T207

2

clear_one[3]

auto[1]

auto[1]

auto[0]

45

1

T25

1

T60

1

T6

1

clear_none

auto[0]

auto[0]

auto[0]

1333

1

T1

1

T2

1

T3

1

clear_none

auto[0]

auto[0]

auto[1]

133

1

T108

1

T86

1

T205

3

clear_none

auto[0]

auto[1]

auto[0]

135

1

T1

2

T44

1

T25

1

clear_none

auto[0]

auto[1]

auto[1]

35

1

T44

1

T144

1

T194

1

clear_none

auto[1]

auto[0]

auto[0]

133

1

T131

1

T204

1

T207

1

clear_none

auto[1]

auto[0]

auto[1]

39

1

T121

1

T252

1

T210

1

clear_none

auto[1]

auto[1]

auto[0]

26

1

T18

1

T86

1

T131

1

clear_none

auto[1]

auto[1]

auto[1]

18

1

T26

1

T208

1

T71

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1324	1			T2	2		T3	4		T4	5
clear_all	auto[1]	70	1			T79	1		T116	6		T134	4
clear_one[1]	auto[0]	634	1			T1	3		T2	1		T3	2
clear_one[1]	auto[1]	36	1			T1	7		T134	2		T135	6
clear_one[2]	auto[0]	710	1			T2	2		T3	1		T4	1
clear_one[2]	auto[1]	66	1			T144	1		T116	5		T135	4
clear_one[3]	auto[0]	652	1			T2	3		T4	1		T14	1
clear_one[3]	auto[1]	29	1			T297	2		T232	5		T331	2
clear_none	auto[0]	1769	1			T1	2		T2	1		T3	1
clear_none	auto[1]	83	1			T1	1		T134	2		T235	5