Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11068

1

T1

16

T2

8

T3

5

auto[Attestation]

7610

1

T1

5

T2

3

T3

3

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2555	1			T1	5		T4	11		T5	1
auto[Aes]	3414	1			T1	4		T4	4		T5	2
auto[Kmac]	3389	1			T1	3		T4	5		T5	5
auto[Otbn]	3435	1			T1	1		T2	11		T3	8

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7812	1			T1	8		T2	8		T3	8
auto[OpGenId]	5885	1			T1	8		T4	9		T5	4
auto[OpGenSwOut]	5842	1			T1	5		T4	17		T5	6
auto[OpGenHwOut]	6951	1			T1	8		T2	11		T3	8
auto[OpDisable]	140	1			T18	1		T26	1		T49	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10825

1

T1

17

T2

8

T3

8

auto[OpDoneFail]

15805

1

T1

12

T2

11

T3

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6415	1			T1	1		T2	4		T3	1
auto[StInit]	3658	1			T1	3		T2	2		T3	2
auto[StCreatorRootKey]	3190	1			T1	5		T2	2		T3	2
auto[StOwnerIntKey]	2869	1			T1	5		T2	2		T3	2
auto[StOwnerKey]	2533	1			T1	5		T2	2		T3	2
auto[StDisabled]	7965	1			T1	10		T2	7		T3	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	316	1			T4	2		T5	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	87	1			T26	2		T188	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	71	1			T1	1		T189	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	71	1			T190	1		T60	1		T191	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	56	1			T85	2		T192	1		T193	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	198	1			T4	1		T18	1		T86	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	305	1			T4	1		T5	1		T18	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	103	1			T4	1		T189	1		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	74	1			T108	1		T194	1		T63	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	88	1			T85	1		T194	1		T110	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	75	1			T1	1		T44	1		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	214	1			T44	1		T190	1		T195	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	270	1			T4	2		T5	2		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	92	1			T4	1		T5	1		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	98	1			T86	1		T195	1		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	78	1			T108	1		T83	1		T196	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	60	1			T131	1		T112	2		T121	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	214	1			T1	1		T4	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	325	1			T18	1		T44	1		T25	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	103	1			T86	1		T117	1		T61	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	88	1			T15	1		T131	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	58	1			T5	1		T15	1		T108	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	65	1			T4	1		T197	1		T194	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	233	1			T1	1		T4	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	59	1			T60	2		T6	1		T7	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	88	1			T18	1		T110	1		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	91	1			T25	1		T189	1		T55	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	88	1			T197	1		T189	1		T78	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	50	1			T86	1		T190	3		T55	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	206	1			T44	1		T131	1		T195	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	80	1			T121	2		T6	1		T7	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	115	1			T55	2		T81	1		T82	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	84	1			T198	1		T199	1		T200	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	73	1			T18	1		T197	1		T189	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	79	1			T1	1		T44	1		T25	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	243	1			T4	2		T15	1		T55	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	79	1			T60	2		T7	1		T8	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	108	1			T44	1		T131	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	91	1			T188	1		T55	1		T78	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	74	1			T201	1		T202	1		T203	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	59	1			T44	1		T55	1		T68	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	224	1			T86	2		T25	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	86	1			T60	2		T121	3		T7	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	85	1			T4	2		T189	1		T117	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	77	1			T26	1		T68	1		T61	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	84	1			T86	1		T26	1		T55	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	65	1			T44	1		T55	1		T201	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	212	1			T4	2		T197	1		T55	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	252	1			T4	3		T18	3		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	84	1			T1	1		T15	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	85	1			T26	1		T81	1		T114	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	55	1			T1	1		T4	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	57	1			T44	1		T112	1		T113	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	178	1			T1	1		T86	1		T195	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	485	1			T5	1		T17	3		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	112	1			T17	1		T195	1		T204	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	106	1			T16	2		T26	1		T188	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	85	1			T17	1		T108	1		T189	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	93	1			T1	1		T25	1		T204	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	305	1			T1	1		T17	1		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	488	1			T4	1		T14	6		T18	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	115	1			T14	1		T26	3		T190	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	111	1			T130	1		T55	1		T81	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	104	1			T108	1		T130	1		T78	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	83	1			T14	1		T130	1		T55	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	283	1			T14	2		T44	1		T87	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	505	1			T2	3		T5	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	122	1			T44	2		T25	1		T205	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	114	1			T2	1		T108	1		T189	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	95	1			T2	1		T108	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	101	1			T2	1		T3	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	272	1			T2	2		T3	4		T195	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	50	1			T7	2		T182	1		T206	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	91	1			T4	1		T197	1		T114	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	70	1			T131	1		T195	1		T188	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	61	1			T1	1		T4	2		T55	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	37	1			T4	1		T86	1		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	154	1			T197	1		T55	1		T79	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	64	1			T60	2		T121	3		T7	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	110	1			T190	1		T207	1		T188	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	103	1			T16	1		T17	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	86	1			T18	1		T131	1		T204	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	88	1			T17	1		T55	1		T208	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	244	1			T17	3		T44	1		T190	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	61	1			T44	1		T60	1		T7	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	108	1			T5	1		T87	1		T130	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	114	1			T1	2		T14	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	103	1			T5	1		T14	1		T18	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	97	1			T44	1		T87	1		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	275	1			T14	2		T86	1		T87	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	65	1			T60	2		T121	2		T7	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	115	1			T2	1		T3	1		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	97	1			T3	1		T108	1		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	91	1			T3	1		T205	1		T55	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	95	1			T44	1		T189	1		T205	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	282	1			T2	2		T195	2		T197	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	188	1			T1	1		T190	1		T189	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	611	1			T4	3		T5	1		T18	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	218	1			T1	1		T44	1		T108	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	641	1			T4	2		T5	1		T18	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	216	1			T108	1		T86	1		T131	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	596	1			T1	1		T4	4		T5	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	197	1			T4	1		T5	1		T15	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	675	1			T1	1		T4	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	216	1			T86	1		T25	1		T190	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	366	1			T18	1		T44	1		T131	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	217	1			T1	1		T18	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	457	1			T4	2		T15	1		T55	4
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	204	1			T44	1		T188	1		T55	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	431	1			T44	1		T86	2		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	209	1			T44	1		T86	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	400	1			T4	4		T26	1		T197	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	182	1			T1	1		T4	1		T44	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	529	1			T1	2		T4	3		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	264	1			T1	1		T16	2		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	922	1			T1	1		T5	1		T17	5
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	282	1			T14	1		T108	1		T130	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	902	1			T4	1		T14	9		T18	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	295	1			T2	3		T3	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	914	1			T2	5		T3	4		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	155	1			T1	1		T4	2		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	308	1			T4	2		T197	2		T55	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	263	1			T16	1		T17	2		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	432	1			T17	3		T44	1		T190	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	296	1			T1	2		T5	1		T14	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	462	1			T5	1		T14	2		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	269	1			T3	2		T44	1		T108	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	476	1			T2	3		T3	1		T25	1