Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32714

1

T1

31

T2

25

T3

18

auto[1]

313

1

T1

10

T144

4

T116

11

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32723	1			T1	33		T2	25		T3	18
auto[134217728:268435455]	12	1			T1	1		T116	1		T238	1
auto[268435456:402653183]	9	1			T116	3		T134	2		T135	1
auto[402653184:536870911]	10	1			T1	1		T135	1		T235	1
auto[536870912:671088639]	8	1			T1	2		T407	1		T297	1
auto[671088640:805306367]	10	1			T117	1		T356	1		T232	1
auto[805306368:939524095]	16	1			T144	1		T238	2		T326	2
auto[939524096:1073741823]	18	1			T117	1		T252	2		T326	1
auto[1073741824:1207959551]	2	1			T231	1		T408	1		-	-
auto[1207959552:1342177279]	14	1			T135	1		T252	1		T231	1
auto[1342177280:1476395007]	5	1			T134	1		T397	1		T280	1
auto[1476395008:1610612735]	13	1			T1	2		T116	2		T321	1
auto[1610612736:1744830463]	10	1			T134	1		T321	1		T231	1
auto[1744830464:1879048191]	9	1			T144	1		T135	1		T231	1
auto[1879048192:2013265919]	11	1			T116	2		T231	1		T250	1
auto[2013265920:2147483647]	7	1			T252	1		T231	1		T280	1
auto[2147483648:2281701375]	16	1			T135	1		T230	1		T321	1
auto[2281701376:2415919103]	10	1			T135	1		T321	1		T407	1
auto[2415919104:2550136831]	9	1			T1	1		T326	1		T407	1
auto[2550136832:2684354559]	3	1			T231	1		T326	1		T271	1
auto[2684354560:2818572287]	8	1			T134	2		T321	1		T231	1
auto[2818572288:2952790015]	8	1			T135	1		T230	1		T321	1
auto[2952790016:3087007743]	6	1			T238	1		T407	1		T276	1
auto[3087007744:3221225471]	10	1			T397	1		T231	1		T250	1
auto[3221225472:3355443199]	9	1			T116	1		T135	1		T238	3
auto[3355443200:3489660927]	14	1			T117	1		T252	1		T231	1
auto[3489660928:3623878655]	9	1			T116	1		T397	1		T276	1
auto[3623878656:3758096383]	9	1			T135	1		T231	1		T356	1
auto[3758096384:3892314111]	13	1			T1	1		T144	1		T135	1
auto[3892314112:4026531839]	10	1			T116	1		T136	1		T252	1
auto[4026531840:4160749567]	8	1			T144	1		T321	1		T250	2
auto[4160749568:4294967295]	8	1			T409	1		T410	1		T411	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32714	1			T1	31		T2	25		T3	18
auto[0:134217727]	auto[1]	9	1			T1	2		T135	1		T356	1
auto[134217728:268435455]	auto[1]	12	1			T1	1		T116	1		T238	1
auto[268435456:402653183]	auto[1]	9	1			T116	3		T134	2		T135	1
auto[402653184:536870911]	auto[1]	10	1			T1	1		T135	1		T235	1
auto[536870912:671088639]	auto[1]	8	1			T1	2		T407	1		T297	1
auto[671088640:805306367]	auto[1]	10	1			T117	1		T356	1		T232	1
auto[805306368:939524095]	auto[1]	16	1			T144	1		T238	2		T326	2
auto[939524096:1073741823]	auto[1]	18	1			T117	1		T252	2		T326	1
auto[1073741824:1207959551]	auto[1]	2	1			T231	1		T408	1		-	-
auto[1207959552:1342177279]	auto[1]	14	1			T135	1		T252	1		T231	1
auto[1342177280:1476395007]	auto[1]	5	1			T134	1		T397	1		T280	1
auto[1476395008:1610612735]	auto[1]	13	1			T1	2		T116	2		T321	1
auto[1610612736:1744830463]	auto[1]	10	1			T134	1		T321	1		T231	1
auto[1744830464:1879048191]	auto[1]	9	1			T144	1		T135	1		T231	1
auto[1879048192:2013265919]	auto[1]	11	1			T116	2		T231	1		T250	1
auto[2013265920:2147483647]	auto[1]	7	1			T252	1		T231	1		T280	1
auto[2147483648:2281701375]	auto[1]	16	1			T135	1		T230	1		T321	1
auto[2281701376:2415919103]	auto[1]	10	1			T135	1		T321	1		T407	1
auto[2415919104:2550136831]	auto[1]	9	1			T1	1		T326	1		T407	1
auto[2550136832:2684354559]	auto[1]	3	1			T231	1		T326	1		T271	1
auto[2684354560:2818572287]	auto[1]	8	1			T134	2		T321	1		T231	1
auto[2818572288:2952790015]	auto[1]	8	1			T135	1		T230	1		T321	1
auto[2952790016:3087007743]	auto[1]	6	1			T238	1		T407	1		T276	1
auto[3087007744:3221225471]	auto[1]	10	1			T397	1		T231	1		T250	1
auto[3221225472:3355443199]	auto[1]	9	1			T116	1		T135	1		T238	3
auto[3355443200:3489660927]	auto[1]	14	1			T117	1		T252	1		T231	1
auto[3489660928:3623878655]	auto[1]	9	1			T116	1		T397	1		T276	1
auto[3623878656:3758096383]	auto[1]	9	1			T135	1		T231	1		T356	1
auto[3758096384:3892314111]	auto[1]	13	1			T1	1		T144	1		T135	1
auto[3892314112:4026531839]	auto[1]	10	1			T116	1		T136	1		T252	1
auto[4026531840:4160749567]	auto[1]	8	1			T144	1		T321	1		T250	2
auto[4160749568:4294967295]	auto[1]	8	1			T409	1		T410	1		T411	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1503

1

T4

3

T18

3

T44

5

auto[1]

1723

1

T1

4

T4

5

T16

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	88	1			T25	1		T190	1		T49	1
auto[134217728:268435455]	95	1			T35	2		T26	1		T36	1
auto[268435456:402653183]	101	1			T108	1		T190	1		T36	1
auto[402653184:536870911]	78	1			T25	1		T194	1		T117	1
auto[536870912:671088639]	95	1			T44	1		T195	1		T54	1
auto[671088640:805306367]	94	1			T18	1		T189	2		T55	1
auto[805306368:939524095]	113	1			T55	2		T208	1		T203	1
auto[939524096:1073741823]	109	1			T54	1		T197	1		T189	1
auto[1073741824:1207959551]	90	1			T4	1		T44	1		T197	1
auto[1207959552:1342177279]	104	1			T86	1		T190	1		T36	1
auto[1342177280:1476395007]	93	1			T1	1		T25	1		T195	1
auto[1476395008:1610612735]	92	1			T4	1		T44	1		T35	1
auto[1610612736:1744830463]	108	1			T26	2		T197	1		T55	1
auto[1744830464:1879048191]	115	1			T44	1		T25	1		T190	2
auto[1879048192:2013265919]	111	1			T1	1		T4	1		T18	2
auto[2013265920:2147483647]	103	1			T26	1		T55	3		T60	2
auto[2147483648:2281701375]	103	1			T54	1		T79	1		T85	1
auto[2281701376:2415919103]	83	1			T16	1		T54	1		T36	1
auto[2415919104:2550136831]	100	1			T4	1		T36	1		T189	1
auto[2550136832:2684354559]	119	1			T18	2		T44	1		T26	1
auto[2684354560:2818572287]	107	1			T4	1		T35	2		T26	1
auto[2818572288:2952790015]	105	1			T35	1		T55	1		T79	1
auto[2952790016:3087007743]	96	1			T44	1		T26	1		T54	1
auto[3087007744:3221225471]	96	1			T197	1		T55	1		T199	1
auto[3221225472:3355443199]	93	1			T1	1		T25	1		T35	1
auto[3355443200:3489660927]	113	1			T4	1		T79	1		T50	1
auto[3489660928:3623878655]	113	1			T4	1		T55	1		T114	1
auto[3623878656:3758096383]	104	1			T18	1		T44	1		T108	1
auto[3758096384:3892314111]	105	1			T4	1		T44	1		T26	1
auto[3892314112:4026531839]	105	1			T1	1		T55	1		T208	1
auto[4026531840:4160749567]	108	1			T25	1		T201	1		T117	1
auto[4160749568:4294967295]	87	1			T44	1		T195	1		T54	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	41	1			T49	1		T55	1		T68	1
auto[0:134217727]	auto[1]	47	1			T25	1		T190	1		T116	1
auto[134217728:268435455]	auto[0]	43	1			T35	2		T36	1		T55	1
auto[134217728:268435455]	auto[1]	52	1			T26	1		T68	1		T201	1
auto[268435456:402653183]	auto[0]	34	1			T36	1		T7	1		T8	1
auto[268435456:402653183]	auto[1]	67	1			T108	1		T190	1		T81	1
auto[402653184:536870911]	auto[0]	37	1			T237	1		T401	1		T8	2
auto[402653184:536870911]	auto[1]	41	1			T25	1		T194	1		T117	1
auto[536870912:671088639]	auto[0]	51	1			T54	1		T80	1		T117	1
auto[536870912:671088639]	auto[1]	44	1			T44	1		T195	1		T85	1
auto[671088640:805306367]	auto[0]	50	1			T189	1		T198	1		T6	1
auto[671088640:805306367]	auto[1]	44	1			T18	1		T189	1		T55	1
auto[805306368:939524095]	auto[0]	49	1			T55	1		T208	1		T7	2
auto[805306368:939524095]	auto[1]	64	1			T55	1		T203	1		T121	1
auto[939524096:1073741823]	auto[0]	54	1			T197	1		T55	1		T47	1
auto[939524096:1073741823]	auto[1]	55	1			T54	1		T189	1		T55	1
auto[1073741824:1207959551]	auto[0]	40	1			T44	1		T189	1		T116	1
auto[1073741824:1207959551]	auto[1]	50	1			T4	1		T197	1		T49	1
auto[1207959552:1342177279]	auto[0]	48	1			T36	1		T55	1		T46	1
auto[1207959552:1342177279]	auto[1]	56	1			T86	1		T190	1		T113	1
auto[1342177280:1476395007]	auto[0]	41	1			T25	1		T195	1		T114	1
auto[1342177280:1476395007]	auto[1]	52	1			T1	1		T49	1		T55	1
auto[1476395008:1610612735]	auto[0]	40	1			T4	1		T44	1		T35	1
auto[1476395008:1610612735]	auto[1]	52	1			T189	1		T78	1		T81	1
auto[1610612736:1744830463]	auto[0]	53	1			T26	2		T197	1		T55	1
auto[1610612736:1744830463]	auto[1]	55	1			T144	1		T7	2		T412	1
auto[1744830464:1879048191]	auto[0]	62	1			T190	1		T68	2		T194	1
auto[1744830464:1879048191]	auto[1]	53	1			T44	1		T25	1		T190	1
auto[1879048192:2013265919]	auto[0]	51	1			T18	1		T86	1		T35	2
auto[1879048192:2013265919]	auto[1]	60	1			T1	1		T4	1		T18	1
auto[2013265920:2147483647]	auto[0]	49	1			T26	1		T55	2		T60	1
auto[2013265920:2147483647]	auto[1]	54	1			T55	1		T60	1		T192	1
auto[2147483648:2281701375]	auto[0]	54	1			T54	1		T60	1		T191	1
auto[2147483648:2281701375]	auto[1]	49	1			T79	1		T85	1		T113	1
auto[2281701376:2415919103]	auto[0]	39	1			T54	1		T36	1		T55	1
auto[2281701376:2415919103]	auto[1]	44	1			T16	1		T197	1		T113	1
auto[2415919104:2550136831]	auto[0]	48	1			T189	1		T55	1		T92	2
auto[2415919104:2550136831]	auto[1]	52	1			T4	1		T36	1		T55	1
auto[2550136832:2684354559]	auto[0]	65	1			T18	1		T44	1		T36	1
auto[2550136832:2684354559]	auto[1]	54	1			T18	1		T26	1		T79	1
auto[2684354560:2818572287]	auto[0]	48	1			T4	1		T35	1		T26	1
auto[2684354560:2818572287]	auto[1]	59	1			T35	1		T60	1		T121	1
auto[2818572288:2952790015]	auto[0]	50	1			T55	1		T46	1		T144	1
auto[2818572288:2952790015]	auto[1]	55	1			T35	1		T79	1		T68	1
auto[2952790016:3087007743]	auto[0]	46	1			T44	1		T54	1		T114	1
auto[2952790016:3087007743]	auto[1]	50	1			T26	1		T85	1		T199	1
auto[3087007744:3221225471]	auto[0]	43	1			T88	1		T135	1		T266	1
auto[3087007744:3221225471]	auto[1]	53	1			T197	1		T55	1		T199	1
auto[3221225472:3355443199]	auto[0]	36	1			T35	1		T54	1		T60	1
auto[3221225472:3355443199]	auto[1]	57	1			T1	1		T25	1		T81	1
auto[3355443200:3489660927]	auto[0]	53	1			T4	1		T79	1		T121	1
auto[3355443200:3489660927]	auto[1]	60	1			T50	1		T117	1		T199	1
auto[3489660928:3623878655]	auto[0]	53	1			T7	3		T413	1		T8	1
auto[3489660928:3623878655]	auto[1]	60	1			T4	1		T55	1		T114	1
auto[3623878656:3758096383]	auto[0]	49	1			T18	1		T44	1		T36	1
auto[3623878656:3758096383]	auto[1]	55	1			T108	1		T81	1		T208	1
auto[3758096384:3892314111]	auto[0]	49	1			T26	1		T49	1		T55	2
auto[3758096384:3892314111]	auto[1]	56	1			T4	1		T44	1		T49	1
auto[3892314112:4026531839]	auto[0]	44	1			T55	1		T7	1		T413	1
auto[3892314112:4026531839]	auto[1]	61	1			T1	1		T208	1		T194	1
auto[4026531840:4160749567]	auto[0]	46	1			T25	1		T201	1		T92	1
auto[4026531840:4160749567]	auto[1]	62	1			T117	1		T60	1		T6	1
auto[4160749568:4294967295]	auto[0]	37	1			T54	1		T55	1		T116	1
auto[4160749568:4294967295]	auto[1]	50	1			T44	1		T195	1		T80	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1493

1

T4

4

T18

3

T44

5

auto[1]

1732

1

T1

4

T4

4

T16

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T195	1		T197	2		T55	2
auto[134217728:268435455]	100	1			T16	1		T18	1		T44	2
auto[268435456:402653183]	97	1			T194	2		T198	1		T92	1
auto[402653184:536870911]	104	1			T18	1		T190	1		T36	1
auto[536870912:671088639]	109	1			T86	1		T190	1		T36	1
auto[671088640:805306367]	106	1			T197	1		T55	1		T79	1
auto[805306368:939524095]	88	1			T18	1		T25	1		T113	1
auto[939524096:1073741823]	97	1			T1	1		T197	1		T55	1
auto[1073741824:1207959551]	101	1			T55	1		T201	1		T92	2
auto[1207959552:1342177279]	83	1			T1	1		T54	1		T189	1
auto[1342177280:1476395007]	97	1			T25	2		T55	1		T85	2
auto[1476395008:1610612735]	100	1			T35	1		T68	1		T208	1
auto[1610612736:1744830463]	94	1			T4	1		T54	1		T144	2
auto[1744830464:1879048191]	94	1			T4	1		T18	1		T44	1
auto[1879048192:2013265919]	108	1			T4	1		T18	1		T108	1
auto[2013265920:2147483647]	101	1			T1	1		T35	1		T121	2
auto[2147483648:2281701375]	105	1			T35	1		T55	2		T79	1
auto[2281701376:2415919103]	81	1			T60	1		T127	1		T182	1
auto[2415919104:2550136831]	89	1			T4	1		T54	1		T112	1
auto[2550136832:2684354559]	101	1			T4	1		T26	2		T55	1
auto[2684354560:2818572287]	95	1			T54	1		T49	1		T55	2
auto[2818572288:2952790015]	86	1			T44	1		T26	1		T197	1
auto[2952790016:3087007743]	98	1			T18	1		T25	3		T35	1
auto[3087007744:3221225471]	96	1			T4	1		T44	1		T190	1
auto[3221225472:3355443199]	110	1			T86	1		T54	1		T49	1
auto[3355443200:3489660927]	116	1			T44	1		T35	1		T36	1
auto[3489660928:3623878655]	90	1			T35	1		T54	2		T189	2
auto[3623878656:3758096383]	110	1			T1	1		T108	1		T26	1
auto[3758096384:3892314111]	113	1			T4	1		T26	2		T36	1
auto[3892314112:4026531839]	118	1			T35	1		T36	1		T55	1
auto[4026531840:4160749567]	119	1			T44	1		T35	1		T189	2
auto[4160749568:4294967295]	116	1			T4	1		T44	2		T26	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	50	1			T197	1		T55	2		T8	1
auto[0:134217727]	auto[1]	53	1			T195	1		T197	1		T116	1
auto[134217728:268435455]	auto[0]	47	1			T18	1		T44	2		T86	1
auto[134217728:268435455]	auto[1]	53	1			T16	1		T197	1		T49	1
auto[268435456:402653183]	auto[0]	48	1			T194	2		T198	1		T7	5
auto[268435456:402653183]	auto[1]	49	1			T92	1		T192	1		T6	1
auto[402653184:536870911]	auto[0]	50	1			T190	1		T36	1		T55	1
auto[402653184:536870911]	auto[1]	54	1			T18	1		T68	1		T208	1
auto[536870912:671088639]	auto[0]	49	1			T190	1		T36	1		T49	1
auto[536870912:671088639]	auto[1]	60	1			T86	1		T81	1		T68	1
auto[671088640:805306367]	auto[0]	51	1			T197	1		T55	1		T198	1
auto[671088640:805306367]	auto[1]	55	1			T79	1		T81	1		T113	1
auto[805306368:939524095]	auto[0]	35	1			T25	1		T113	1		T7	1
auto[805306368:939524095]	auto[1]	53	1			T18	1		T121	1		T412	1
auto[939524096:1073741823]	auto[0]	38	1			T197	1		T68	1		T7	2
auto[939524096:1073741823]	auto[1]	59	1			T1	1		T55	1		T50	1
auto[1073741824:1207959551]	auto[0]	37	1			T55	1		T92	2		T211	1
auto[1073741824:1207959551]	auto[1]	64	1			T201	1		T121	1		T6	1
auto[1207959552:1342177279]	auto[0]	38	1			T54	1		T7	1		T8	1
auto[1207959552:1342177279]	auto[1]	45	1			T1	1		T189	1		T113	1
auto[1342177280:1476395007]	auto[0]	46	1			T25	1		T191	1		T7	1
auto[1342177280:1476395007]	auto[1]	51	1			T25	1		T55	1		T85	2
auto[1476395008:1610612735]	auto[0]	52	1			T35	1		T68	1		T117	1
auto[1476395008:1610612735]	auto[1]	48	1			T208	1		T198	1		T114	1
auto[1610612736:1744830463]	auto[0]	39	1			T54	1		T144	1		T92	1
auto[1610612736:1744830463]	auto[1]	55	1			T4	1		T144	1		T47	1
auto[1744830464:1879048191]	auto[0]	47	1			T18	1		T44	1		T35	1
auto[1744830464:1879048191]	auto[1]	47	1			T4	1		T55	1		T121	1
auto[1879048192:2013265919]	auto[0]	43	1			T18	1		T108	1		T55	1
auto[1879048192:2013265919]	auto[1]	65	1			T4	1		T195	1		T79	1
auto[2013265920:2147483647]	auto[0]	44	1			T121	2		T301	1		T401	1
auto[2013265920:2147483647]	auto[1]	57	1			T1	1		T35	1		T192	1
auto[2147483648:2281701375]	auto[0]	50	1			T35	1		T55	1		T79	1
auto[2147483648:2281701375]	auto[1]	55	1			T55	1		T144	1		T208	1
auto[2281701376:2415919103]	auto[0]	38	1			T60	1		T182	1		T240	1
auto[2281701376:2415919103]	auto[1]	43	1			T127	1		T283	1		T210	1
auto[2415919104:2550136831]	auto[0]	36	1			T4	1		T413	1		T8	2
auto[2415919104:2550136831]	auto[1]	53	1			T54	1		T112	1		T7	1
auto[2550136832:2684354559]	auto[0]	48	1			T4	1		T26	2		T201	1
auto[2550136832:2684354559]	auto[1]	53	1			T55	1		T194	1		T60	1
auto[2684354560:2818572287]	auto[0]	47	1			T54	1		T49	1		T55	1
auto[2684354560:2818572287]	auto[1]	48	1			T55	1		T112	1		T114	1
auto[2818572288:2952790015]	auto[0]	35	1			T44	1		T26	1		T189	1
auto[2818572288:2952790015]	auto[1]	51	1			T197	1		T85	1		T60	1
auto[2952790016:3087007743]	auto[0]	51	1			T25	1		T35	1		T195	1
auto[2952790016:3087007743]	auto[1]	47	1			T18	1		T25	2		T7	1
auto[3087007744:3221225471]	auto[0]	44	1			T4	1		T68	1		T61	1
auto[3087007744:3221225471]	auto[1]	52	1			T44	1		T190	1		T55	2
auto[3221225472:3355443199]	auto[0]	52	1			T54	1		T49	1		T68	1
auto[3221225472:3355443199]	auto[1]	58	1			T86	1		T80	1		T201	1
auto[3355443200:3489660927]	auto[0]	59	1			T35	1		T36	1		T47	1
auto[3355443200:3489660927]	auto[1]	57	1			T44	1		T55	1		T79	1
auto[3489660928:3623878655]	auto[0]	35	1			T54	2		T189	2		T55	1
auto[3489660928:3623878655]	auto[1]	55	1			T35	1		T198	1		T113	2
auto[3623878656:3758096383]	auto[0]	49	1			T36	1		T49	1		T55	2
auto[3623878656:3758096383]	auto[1]	61	1			T1	1		T108	1		T26	1
auto[3758096384:3892314111]	auto[0]	63	1			T4	1		T26	1		T36	1
auto[3758096384:3892314111]	auto[1]	50	1			T26	1		T144	1		T203	1
auto[3892314112:4026531839]	auto[0]	66	1			T36	1		T201	1		T200	1
auto[3892314112:4026531839]	auto[1]	52	1			T35	1		T55	1		T199	1
auto[4026531840:4160749567]	auto[0]	56	1			T35	1		T55	1		T46	1
auto[4026531840:4160749567]	auto[1]	63	1			T44	1		T189	2		T55	1
auto[4160749568:4294967295]	auto[0]	50	1			T44	1		T26	1		T68	1
auto[4160749568:4294967295]	auto[1]	66	1			T4	1		T44	1		T190	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1480

1

T4

3

T18

2

T44

5

auto[1]

1746

1

T1

4

T4

5

T16

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	102	1			T35	1		T55	1		T80	1
auto[134217728:268435455]	100	1			T25	1		T36	2		T197	2
auto[268435456:402653183]	91	1			T44	1		T55	1		T46	1
auto[402653184:536870911]	104	1			T25	1		T49	2		T55	1
auto[536870912:671088639]	120	1			T4	2		T35	1		T190	1
auto[671088640:805306367]	86	1			T1	1		T26	1		T195	1
auto[805306368:939524095]	137	1			T44	2		T195	1		T189	1
auto[939524096:1073741823]	97	1			T35	1		T26	1		T54	1
auto[1073741824:1207959551]	103	1			T4	1		T25	1		T54	1
auto[1207959552:1342177279]	110	1			T4	1		T55	1		T68	1
auto[1342177280:1476395007]	99	1			T1	1		T4	1		T55	2
auto[1476395008:1610612735]	89	1			T16	1		T44	3		T86	1
auto[1610612736:1744830463]	95	1			T4	1		T190	1		T189	1
auto[1744830464:1879048191]	108	1			T26	2		T198	2		T117	1
auto[1879048192:2013265919]	96	1			T18	1		T189	1		T68	1
auto[2013265920:2147483647]	109	1			T25	1		T54	1		T36	1
auto[2147483648:2281701375]	87	1			T26	1		T190	1		T55	1
auto[2281701376:2415919103]	96	1			T18	1		T55	1		T81	1
auto[2415919104:2550136831]	101	1			T55	2		T85	1		T208	1
auto[2550136832:2684354559]	99	1			T18	1		T26	1		T54	2
auto[2684354560:2818572287]	97	1			T86	1		T35	1		T26	1
auto[2818572288:2952790015]	84	1			T44	2		T26	1		T197	1
auto[2952790016:3087007743]	109	1			T18	1		T25	1		T35	1
auto[3087007744:3221225471]	98	1			T1	1		T18	1		T197	2
auto[3221225472:3355443199]	117	1			T190	1		T80	1		T144	2
auto[3355443200:3489660927]	104	1			T18	1		T108	2		T35	1
auto[3489660928:3623878655]	94	1			T44	1		T55	1		T81	1
auto[3623878656:3758096383]	89	1			T1	1		T86	1		T25	1
auto[3758096384:3892314111]	106	1			T4	1		T55	1		T47	1
auto[3892314112:4026531839]	106	1			T4	1		T35	1		T190	1
auto[4026531840:4160749567]	100	1			T36	1		T189	2		T55	2
auto[4160749568:4294967295]	93	1			T35	1		T55	2		T116	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T35	1		T55	1		T144	1
auto[0:134217727]	auto[1]	49	1			T80	1		T199	1		T121	1
auto[134217728:268435455]	auto[0]	49	1			T36	2		T197	1		T80	1
auto[134217728:268435455]	auto[1]	51	1			T25	1		T197	1		T7	1
auto[268435456:402653183]	auto[0]	34	1			T55	1		T46	1		T7	1
auto[268435456:402653183]	auto[1]	57	1			T44	1		T208	1		T117	1
auto[402653184:536870911]	auto[0]	46	1			T49	1		T68	1		T201	1
auto[402653184:536870911]	auto[1]	58	1			T25	1		T49	1		T55	1
auto[536870912:671088639]	auto[0]	68	1			T190	1		T54	1		T117	1
auto[536870912:671088639]	auto[1]	52	1			T4	2		T35	1		T50	1
auto[671088640:805306367]	auto[0]	37	1			T26	1		T36	1		T55	1
auto[671088640:805306367]	auto[1]	49	1			T1	1		T195	1		T49	1
auto[805306368:939524095]	auto[0]	68	1			T44	2		T189	1		T55	1
auto[805306368:939524095]	auto[1]	69	1			T195	1		T201	1		T117	2
auto[939524096:1073741823]	auto[0]	45	1			T35	1		T54	1		T197	1
auto[939524096:1073741823]	auto[1]	52	1			T26	1		T55	1		T47	1
auto[1073741824:1207959551]	auto[0]	39	1			T54	1		T55	2		T68	1
auto[1073741824:1207959551]	auto[1]	64	1			T4	1		T25	1		T49	1
auto[1207959552:1342177279]	auto[0]	47	1			T4	1		T55	1		T68	1
auto[1207959552:1342177279]	auto[1]	63	1			T85	1		T199	1		T48	1
auto[1342177280:1476395007]	auto[0]	45	1			T4	1		T55	2		T85	1
auto[1342177280:1476395007]	auto[1]	54	1			T1	1		T81	1		T60	1
auto[1476395008:1610612735]	auto[0]	41	1			T44	1		T36	1		T116	1
auto[1476395008:1610612735]	auto[1]	48	1			T16	1		T44	2		T86	1
auto[1610612736:1744830463]	auto[0]	43	1			T198	1		T114	1		T60	1
auto[1610612736:1744830463]	auto[1]	52	1			T4	1		T190	1		T189	1
auto[1744830464:1879048191]	auto[0]	47	1			T198	2		T117	1		T38	1
auto[1744830464:1879048191]	auto[1]	61	1			T26	2		T237	1		T7	1
auto[1879048192:2013265919]	auto[0]	47	1			T189	1		T68	1		T194	1
auto[1879048192:2013265919]	auto[1]	49	1			T18	1		T144	1		T116	1
auto[2013265920:2147483647]	auto[0]	48	1			T54	1		T36	1		T55	1
auto[2013265920:2147483647]	auto[1]	61	1			T25	1		T127	2		T8	1
auto[2147483648:2281701375]	auto[0]	38	1			T26	1		T55	1		T121	1
auto[2147483648:2281701375]	auto[1]	49	1			T190	1		T85	2		T60	1
auto[2281701376:2415919103]	auto[0]	36	1			T18	1		T8	2		T246	1
auto[2281701376:2415919103]	auto[1]	60	1			T55	1		T81	1		T201	1
auto[2415919104:2550136831]	auto[0]	57	1			T55	2		T208	1		T60	1
auto[2415919104:2550136831]	auto[1]	44	1			T85	1		T114	1		T92	1
auto[2550136832:2684354559]	auto[0]	40	1			T26	1		T54	2		T49	1
auto[2550136832:2684354559]	auto[1]	59	1			T18	1		T36	1		T121	1
auto[2684354560:2818572287]	auto[0]	52	1			T35	1		T26	1		T7	1
auto[2684354560:2818572287]	auto[1]	45	1			T86	1		T55	1		T79	1
auto[2818572288:2952790015]	auto[0]	40	1			T44	2		T26	1		T211	1
auto[2818572288:2952790015]	auto[1]	44	1			T197	1		T78	1		T47	1
auto[2952790016:3087007743]	auto[0]	45	1			T25	1		T35	1		T46	1
auto[2952790016:3087007743]	auto[1]	64	1			T18	1		T55	1		T114	1
auto[3087007744:3221225471]	auto[0]	46	1			T197	1		T198	1		T60	1
auto[3087007744:3221225471]	auto[1]	52	1			T1	1		T18	1		T197	1
auto[3221225472:3355443199]	auto[0]	58	1			T80	1		T144	1		T121	1
auto[3221225472:3355443199]	auto[1]	59	1			T190	1		T144	1		T60	1
auto[3355443200:3489660927]	auto[0]	51	1			T18	1		T108	1		T35	1
auto[3355443200:3489660927]	auto[1]	53	1			T108	1		T208	1		T194	1
auto[3489660928:3623878655]	auto[0]	42	1			T46	1		T112	1		T7	1
auto[3489660928:3623878655]	auto[1]	52	1			T44	1		T55	1		T81	1
auto[3623878656:3758096383]	auto[0]	46	1			T86	1		T35	1		T54	1
auto[3623878656:3758096383]	auto[1]	43	1			T1	1		T25	1		T121	1
auto[3758096384:3892314111]	auto[0]	47	1			T47	1		T8	1		T135	2
auto[3758096384:3892314111]	auto[1]	59	1			T4	1		T55	1		T113	1
auto[3892314112:4026531839]	auto[0]	44	1			T4	1		T46	1		T60	1
auto[3892314112:4026531839]	auto[1]	62	1			T35	1		T190	1		T81	1
auto[4026531840:4160749567]	auto[0]	42	1			T36	1		T189	2		T414	1
auto[4026531840:4160749567]	auto[1]	58	1			T55	2		T6	2		T7	6
auto[4160749568:4294967295]	auto[0]	39	1			T35	1		T7	2		T38	1
auto[4160749568:4294967295]	auto[1]	54	1			T55	2		T116	1		T7	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1492

1

T4

3

T18

2

T44

5

auto[1]

1735

1

T1

4

T4

5

T16

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T36	2		T85	1		T208	1
auto[134217728:268435455]	104	1			T4	1		T44	2		T25	1
auto[268435456:402653183]	102	1			T25	1		T54	1		T36	1
auto[402653184:536870911]	74	1			T35	1		T26	1		T54	1
auto[536870912:671088639]	109	1			T4	1		T18	1		T35	1
auto[671088640:805306367]	101	1			T1	1		T25	1		T36	1
auto[805306368:939524095]	109	1			T35	1		T189	1		T55	1
auto[939524096:1073741823]	111	1			T44	1		T35	1		T26	1
auto[1073741824:1207959551]	107	1			T44	2		T189	1		T55	1
auto[1207959552:1342177279]	121	1			T197	1		T55	2		T81	1
auto[1342177280:1476395007]	100	1			T35	2		T54	1		T49	1
auto[1476395008:1610612735]	89	1			T79	1		T144	1		T208	1
auto[1610612736:1744830463]	108	1			T44	1		T55	1		T85	1
auto[1744830464:1879048191]	94	1			T1	2		T4	1		T35	1
auto[1879048192:2013265919]	103	1			T4	1		T55	3		T46	1
auto[2013265920:2147483647]	102	1			T4	1		T190	1		T55	1
auto[2147483648:2281701375]	110	1			T86	1		T25	1		T197	1
auto[2281701376:2415919103]	91	1			T18	1		T108	1		T26	1
auto[2415919104:2550136831]	103	1			T35	1		T54	1		T197	1
auto[2550136832:2684354559]	90	1			T86	1		T190	1		T189	1
auto[2684354560:2818572287]	96	1			T36	1		T189	1		T55	2
auto[2818572288:2952790015]	104	1			T25	1		T26	1		T195	1
auto[2952790016:3087007743]	121	1			T1	1		T18	1		T55	1
auto[3087007744:3221225471]	107	1			T16	1		T108	1		T86	1
auto[3221225472:3355443199]	75	1			T4	1		T18	1		T26	1
auto[3355443200:3489660927]	102	1			T195	1		T49	1		T68	1
auto[3489660928:3623878655]	100	1			T44	1		T55	1		T46	1
auto[3623878656:3758096383]	106	1			T44	1		T26	2		T195	1
auto[3758096384:3892314111]	115	1			T18	1		T44	1		T189	1
auto[3892314112:4026531839]	82	1			T4	2		T36	1		T112	1
auto[4026531840:4160749567]	99	1			T36	1		T201	1		T113	1
auto[4160749568:4294967295]	92	1			T18	1		T197	1		T46	1