Unified Coverage Report :: Group Instance : salt_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2868

1

T1

4

T4

8

T16

1

auto[1]

268

1

T1

10

T79

1

T144

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	107	1			T1	1		T4	1		T18	1
auto[134217728:268435455]	100	1			T25	1		T190	1		T144	1
auto[268435456:402653183]	103	1			T35	1		T197	1		T55	1
auto[402653184:536870911]	106	1			T44	1		T36	1		T49	1
auto[536870912:671088639]	98	1			T25	2		T195	1		T85	1
auto[671088640:805306367]	97	1			T35	1		T195	1		T197	1
auto[805306368:939524095]	103	1			T86	1		T36	2		T189	1
auto[939524096:1073741823]	115	1			T26	1		T189	1		T49	2
auto[1073741824:1207959551]	91	1			T4	1		T16	1		T44	1
auto[1207959552:1342177279]	105	1			T18	1		T44	1		T197	1
auto[1342177280:1476395007]	86	1			T26	2		T190	1		T55	1
auto[1476395008:1610612735]	100	1			T44	1		T78	1		T68	1
auto[1610612736:1744830463]	105	1			T1	2		T44	1		T35	1
auto[1744830464:1879048191]	97	1			T55	2		T113	1		T117	1
auto[1879048192:2013265919]	96	1			T4	1		T18	1		T55	2
auto[2013265920:2147483647]	84	1			T1	1		T4	1		T49	1
auto[2147483648:2281701375]	112	1			T35	2		T26	1		T197	1
auto[2281701376:2415919103]	103	1			T1	1		T18	1		T26	1
auto[2415919104:2550136831]	85	1			T55	1		T144	1		T116	1
auto[2550136832:2684354559]	94	1			T1	1		T55	1		T81	1
auto[2684354560:2818572287]	93	1			T55	2		T79	1		T81	1
auto[2818572288:2952790015]	114	1			T44	1		T189	1		T55	1
auto[2952790016:3087007743]	85	1			T1	2		T44	1		T108	1
auto[3087007744:3221225471]	79	1			T1	1		T25	1		T35	1
auto[3221225472:3355443199]	117	1			T1	2		T25	1		T36	1
auto[3355443200:3489660927]	106	1			T18	1		T86	1		T35	1
auto[3489660928:3623878655]	95	1			T1	1		T35	1		T26	1
auto[3623878656:3758096383]	104	1			T1	1		T4	1		T108	1
auto[3758096384:3892314111]	91	1			T4	1		T55	1		T144	1
auto[3892314112:4026531839]	85	1			T4	1		T18	1		T60	1
auto[4026531840:4160749567]	100	1			T1	1		T36	1		T49	1
auto[4160749568:4294967295]	80	1			T4	1		T44	1		T86	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	100	1			T4	1		T18	1		T26	1
auto[0:134217727]	auto[1]	7	1			T1	1		T116	1		T135	1
auto[134217728:268435455]	auto[0]	85	1			T25	1		T190	1		T144	1
auto[134217728:268435455]	auto[1]	15	1			T116	1		T135	1		T136	1
auto[268435456:402653183]	auto[0]	93	1			T35	1		T197	1		T55	1
auto[268435456:402653183]	auto[1]	10	1			T116	1		T235	1		T252	1
auto[402653184:536870911]	auto[0]	95	1			T44	1		T36	1		T49	1
auto[402653184:536870911]	auto[1]	11	1			T135	1		T238	1		T407	1
auto[536870912:671088639]	auto[0]	91	1			T25	2		T195	1		T85	1
auto[536870912:671088639]	auto[1]	7	1			T252	1		T407	1		T331	1
auto[671088640:805306367]	auto[0]	89	1			T35	1		T195	1		T197	1
auto[671088640:805306367]	auto[1]	8	1			T135	1		T252	1		T231	1
auto[805306368:939524095]	auto[0]	96	1			T86	1		T36	2		T189	1
auto[805306368:939524095]	auto[1]	7	1			T326	3		T232	1		T280	1
auto[939524096:1073741823]	auto[0]	103	1			T26	1		T189	1		T49	2
auto[939524096:1073741823]	auto[1]	12	1			T134	1		T252	1		T321	1
auto[1073741824:1207959551]	auto[0]	83	1			T4	1		T16	1		T44	1
auto[1073741824:1207959551]	auto[1]	8	1			T116	1		T238	1		T397	3
auto[1207959552:1342177279]	auto[0]	91	1			T18	1		T44	1		T197	1
auto[1207959552:1342177279]	auto[1]	14	1			T116	2		T135	1		T397	1
auto[1342177280:1476395007]	auto[0]	80	1			T26	2		T190	1		T55	1
auto[1342177280:1476395007]	auto[1]	6	1			T79	1		T379	1		T331	2
auto[1476395008:1610612735]	auto[0]	93	1			T44	1		T78	1		T68	1
auto[1476395008:1610612735]	auto[1]	7	1			T116	1		T238	1		T252	1
auto[1610612736:1744830463]	auto[0]	100	1			T1	1		T44	1		T35	1
auto[1610612736:1744830463]	auto[1]	5	1			T1	1		T134	1		T407	1
auto[1744830464:1879048191]	auto[0]	90	1			T55	2		T113	1		T117	1
auto[1744830464:1879048191]	auto[1]	7	1			T321	1		T407	1		T297	1
auto[1879048192:2013265919]	auto[0]	90	1			T4	1		T18	1		T55	2
auto[1879048192:2013265919]	auto[1]	6	1			T135	1		T230	1		T232	1
auto[2013265920:2147483647]	auto[0]	73	1			T4	1		T49	1		T55	1
auto[2013265920:2147483647]	auto[1]	11	1			T1	1		T235	1		T252	1
auto[2147483648:2281701375]	auto[0]	105	1			T35	2		T26	1		T197	1
auto[2147483648:2281701375]	auto[1]	7	1			T116	1		T252	1		T407	1
auto[2281701376:2415919103]	auto[0]	94	1			T18	1		T26	1		T190	1
auto[2281701376:2415919103]	auto[1]	9	1			T1	1		T231	1		T276	1
auto[2415919104:2550136831]	auto[0]	76	1			T55	1		T116	1		T121	1
auto[2415919104:2550136831]	auto[1]	9	1			T144	1		T136	1		T238	1
auto[2550136832:2684354559]	auto[0]	93	1			T1	1		T55	1		T81	1
auto[2550136832:2684354559]	auto[1]	1	1			T326	1		-	-		-	-
auto[2684354560:2818572287]	auto[0]	85	1			T55	2		T79	1		T81	1
auto[2684354560:2818572287]	auto[1]	8	1			T230	1		T231	1		T250	1
auto[2818572288:2952790015]	auto[0]	105	1			T44	1		T189	1		T55	1
auto[2818572288:2952790015]	auto[1]	9	1			T136	1		T231	1		T326	1
auto[2952790016:3087007743]	auto[0]	76	1			T44	1		T108	1		T36	2
auto[2952790016:3087007743]	auto[1]	9	1			T1	2		T235	1		T397	1
auto[3087007744:3221225471]	auto[0]	76	1			T1	1		T25	1		T35	1
auto[3087007744:3221225471]	auto[1]	3	1			T397	1		T232	1		T410	1
auto[3221225472:3355443199]	auto[0]	107	1			T25	1		T36	1		T197	1
auto[3221225472:3355443199]	auto[1]	10	1			T1	2		T231	1		T407	1
auto[3355443200:3489660927]	auto[0]	96	1			T18	1		T86	1		T35	1
auto[3355443200:3489660927]	auto[1]	10	1			T252	1		T231	1		T250	1
auto[3489660928:3623878655]	auto[0]	83	1			T35	1		T26	1		T55	3
auto[3489660928:3623878655]	auto[1]	12	1			T1	1		T397	1		T321	1
auto[3623878656:3758096383]	auto[0]	94	1			T4	1		T108	1		T25	1
auto[3623878656:3758096383]	auto[1]	10	1			T1	1		T252	1		T231	1
auto[3758096384:3892314111]	auto[0]	86	1			T4	1		T55	1		T144	1
auto[3758096384:3892314111]	auto[1]	5	1			T252	1		T397	1		T271	1
auto[3892314112:4026531839]	auto[0]	79	1			T4	1		T18	1		T60	1
auto[3892314112:4026531839]	auto[1]	6	1			T134	1		T136	1		T250	1
auto[4026531840:4160749567]	auto[0]	87	1			T1	1		T36	1		T49	1
auto[4026531840:4160749567]	auto[1]	13	1			T136	1		T238	1		T326	1
auto[4160749568:4294967295]	auto[0]	74	1			T4	1		T44	1		T86	1
auto[4160749568:4294967295]	auto[1]	6	1			T116	1		T134	1		T135	1