Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.71 99.04 98.11 98.32 100.00 99.02 98.41 91.09


Total test records in report: 1084
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T1006 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3466407825 Aug 03 04:29:31 PM PDT 24 Aug 03 04:29:33 PM PDT 24 110848446 ps
T1007 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2814903657 Aug 03 04:29:42 PM PDT 24 Aug 03 04:29:43 PM PDT 24 15373086 ps
T1008 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2994625247 Aug 03 04:30:02 PM PDT 24 Aug 03 04:30:03 PM PDT 24 8591971 ps
T1009 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3741614470 Aug 03 04:29:32 PM PDT 24 Aug 03 04:29:44 PM PDT 24 257996460 ps
T1010 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.876145275 Aug 03 04:29:58 PM PDT 24 Aug 03 04:29:59 PM PDT 24 63722210 ps
T1011 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.403891757 Aug 03 04:29:49 PM PDT 24 Aug 03 04:29:57 PM PDT 24 342608476 ps
T1012 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.7196410 Aug 03 04:30:25 PM PDT 24 Aug 03 04:30:27 PM PDT 24 89950969 ps
T1013 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.446088143 Aug 03 04:30:05 PM PDT 24 Aug 03 04:30:06 PM PDT 24 9612372 ps
T1014 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.830135787 Aug 03 04:30:00 PM PDT 24 Aug 03 04:30:01 PM PDT 24 91158350 ps
T153 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1553887411 Aug 03 04:29:35 PM PDT 24 Aug 03 04:29:44 PM PDT 24 322943837 ps
T1015 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3075956111 Aug 03 04:29:54 PM PDT 24 Aug 03 04:29:55 PM PDT 24 25584372 ps
T1016 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3263534920 Aug 03 04:29:51 PM PDT 24 Aug 03 04:29:51 PM PDT 24 9370741 ps
T1017 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.19361861 Aug 03 04:29:42 PM PDT 24 Aug 03 04:29:45 PM PDT 24 172395291 ps
T1018 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.137264943 Aug 03 04:29:34 PM PDT 24 Aug 03 04:29:36 PM PDT 24 23581963 ps
T1019 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1646753253 Aug 03 04:29:50 PM PDT 24 Aug 03 04:29:53 PM PDT 24 46830399 ps
T1020 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1579941329 Aug 03 04:29:26 PM PDT 24 Aug 03 04:29:34 PM PDT 24 331291207 ps
T1021 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2172128031 Aug 03 04:29:21 PM PDT 24 Aug 03 04:29:22 PM PDT 24 27308673 ps
T1022 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2650773970 Aug 03 04:29:59 PM PDT 24 Aug 03 04:30:02 PM PDT 24 146691094 ps
T1023 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3739662612 Aug 03 04:29:51 PM PDT 24 Aug 03 04:29:57 PM PDT 24 1440077497 ps
T1024 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3276890334 Aug 03 04:29:57 PM PDT 24 Aug 03 04:30:00 PM PDT 24 80339276 ps
T1025 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3134532637 Aug 03 04:30:01 PM PDT 24 Aug 03 04:30:03 PM PDT 24 50892169 ps
T1026 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2549698663 Aug 03 04:29:55 PM PDT 24 Aug 03 04:29:56 PM PDT 24 20794806 ps
T1027 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2674627388 Aug 03 04:29:49 PM PDT 24 Aug 03 04:29:50 PM PDT 24 49434886 ps
T1028 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2522369200 Aug 03 04:30:06 PM PDT 24 Aug 03 04:30:07 PM PDT 24 41818665 ps
T1029 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1644769878 Aug 03 04:29:40 PM PDT 24 Aug 03 04:29:42 PM PDT 24 97557413 ps
T1030 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.162682501 Aug 03 04:29:42 PM PDT 24 Aug 03 04:29:45 PM PDT 24 140482114 ps
T1031 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.567494091 Aug 03 04:29:40 PM PDT 24 Aug 03 04:29:42 PM PDT 24 172688910 ps
T1032 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2375969937 Aug 03 04:29:41 PM PDT 24 Aug 03 04:29:42 PM PDT 24 25189179 ps
T157 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2129623493 Aug 03 04:29:48 PM PDT 24 Aug 03 04:29:53 PM PDT 24 358809713 ps
T1033 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3172077914 Aug 03 04:29:31 PM PDT 24 Aug 03 04:29:42 PM PDT 24 269014244 ps
T1034 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.4187307453 Aug 03 04:30:01 PM PDT 24 Aug 03 04:30:02 PM PDT 24 18715020 ps
T1035 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2973024069 Aug 03 04:29:50 PM PDT 24 Aug 03 04:29:52 PM PDT 24 16639814 ps
T158 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1014527268 Aug 03 04:29:47 PM PDT 24 Aug 03 04:29:52 PM PDT 24 144441577 ps
T1036 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3119243376 Aug 03 04:29:42 PM PDT 24 Aug 03 04:29:50 PM PDT 24 2987222758 ps
T149 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.911662296 Aug 03 04:29:59 PM PDT 24 Aug 03 04:30:02 PM PDT 24 167297115 ps
T1037 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.4163871919 Aug 03 04:29:42 PM PDT 24 Aug 03 04:29:45 PM PDT 24 158549371 ps
T1038 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3794722792 Aug 03 04:30:04 PM PDT 24 Aug 03 04:30:04 PM PDT 24 12381454 ps
T1039 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2634923103 Aug 03 04:29:35 PM PDT 24 Aug 03 04:29:43 PM PDT 24 274280302 ps
T1040 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2722306830 Aug 03 04:29:57 PM PDT 24 Aug 03 04:29:57 PM PDT 24 18274825 ps
T1041 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.161551611 Aug 03 04:29:42 PM PDT 24 Aug 03 04:29:45 PM PDT 24 147947927 ps
T1042 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.708515544 Aug 03 04:30:00 PM PDT 24 Aug 03 04:30:01 PM PDT 24 31099827 ps
T1043 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2927449980 Aug 03 04:29:52 PM PDT 24 Aug 03 04:29:54 PM PDT 24 13639324 ps
T1044 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1798181503 Aug 03 04:29:53 PM PDT 24 Aug 03 04:29:54 PM PDT 24 58425756 ps
T1045 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2289005675 Aug 03 04:29:49 PM PDT 24 Aug 03 04:29:51 PM PDT 24 85575051 ps
T1046 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1812056032 Aug 03 04:29:50 PM PDT 24 Aug 03 04:29:51 PM PDT 24 182946081 ps
T1047 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.4066816193 Aug 03 04:29:29 PM PDT 24 Aug 03 04:29:30 PM PDT 24 72056407 ps
T1048 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3167121241 Aug 03 04:29:55 PM PDT 24 Aug 03 04:29:56 PM PDT 24 21840120 ps
T1049 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.4035303576 Aug 03 04:29:51 PM PDT 24 Aug 03 04:29:53 PM PDT 24 53408904 ps
T1050 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1211885277 Aug 03 04:29:29 PM PDT 24 Aug 03 04:29:31 PM PDT 24 160685391 ps
T1051 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3182352036 Aug 03 04:29:57 PM PDT 24 Aug 03 04:29:58 PM PDT 24 12154412 ps
T1052 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2186683696 Aug 03 04:29:47 PM PDT 24 Aug 03 04:29:50 PM PDT 24 108157532 ps
T1053 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.572556653 Aug 03 04:29:26 PM PDT 24 Aug 03 04:29:27 PM PDT 24 16434719 ps
T1054 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.860509631 Aug 03 04:29:36 PM PDT 24 Aug 03 04:29:37 PM PDT 24 34299222 ps
T1055 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2846337504 Aug 03 04:29:47 PM PDT 24 Aug 03 04:29:48 PM PDT 24 20468403 ps
T1056 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3189306274 Aug 03 04:29:33 PM PDT 24 Aug 03 04:29:48 PM PDT 24 1003372188 ps
T1057 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3572283468 Aug 03 04:29:55 PM PDT 24 Aug 03 04:30:01 PM PDT 24 388198860 ps
T1058 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.214605271 Aug 03 04:29:51 PM PDT 24 Aug 03 04:29:55 PM PDT 24 179717400 ps
T1059 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1549260794 Aug 03 04:29:58 PM PDT 24 Aug 03 04:29:59 PM PDT 24 147090359 ps
T1060 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1182953532 Aug 03 04:29:34 PM PDT 24 Aug 03 04:29:36 PM PDT 24 657703554 ps
T1061 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3694216999 Aug 03 04:29:43 PM PDT 24 Aug 03 04:29:46 PM PDT 24 188071698 ps
T1062 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.573172696 Aug 03 04:29:52 PM PDT 24 Aug 03 04:29:54 PM PDT 24 88516106 ps
T1063 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1565992215 Aug 03 04:29:31 PM PDT 24 Aug 03 04:29:40 PM PDT 24 360968184 ps
T1064 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3536749563 Aug 03 04:30:00 PM PDT 24 Aug 03 04:30:01 PM PDT 24 22334818 ps
T1065 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3116457192 Aug 03 04:29:52 PM PDT 24 Aug 03 04:29:54 PM PDT 24 188767206 ps
T1066 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.359496499 Aug 03 04:29:48 PM PDT 24 Aug 03 04:29:49 PM PDT 24 12872874 ps
T1067 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2012359529 Aug 03 04:29:47 PM PDT 24 Aug 03 04:29:54 PM PDT 24 208613403 ps
T1068 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1066073633 Aug 03 04:29:32 PM PDT 24 Aug 03 04:29:33 PM PDT 24 23257565 ps
T1069 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3515977858 Aug 03 04:29:53 PM PDT 24 Aug 03 04:29:56 PM PDT 24 61593629 ps
T169 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3359785602 Aug 03 04:29:49 PM PDT 24 Aug 03 04:29:52 PM PDT 24 169287992 ps
T1070 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.125894268 Aug 03 04:29:56 PM PDT 24 Aug 03 04:29:57 PM PDT 24 97389779 ps
T1071 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1357731147 Aug 03 04:29:51 PM PDT 24 Aug 03 04:29:54 PM PDT 24 693046296 ps
T1072 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3595661820 Aug 03 04:29:42 PM PDT 24 Aug 03 04:29:42 PM PDT 24 40581146 ps
T1073 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.4098825820 Aug 03 04:29:37 PM PDT 24 Aug 03 04:29:38 PM PDT 24 11350824 ps
T1074 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1284416995 Aug 03 04:29:55 PM PDT 24 Aug 03 04:29:56 PM PDT 24 16757197 ps
T1075 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1366639824 Aug 03 04:30:04 PM PDT 24 Aug 03 04:30:05 PM PDT 24 149354687 ps
T1076 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2829840804 Aug 03 04:29:49 PM PDT 24 Aug 03 04:29:51 PM PDT 24 87998163 ps
T1077 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.50743281 Aug 03 04:29:58 PM PDT 24 Aug 03 04:29:59 PM PDT 24 42296890 ps
T1078 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3703780346 Aug 03 04:29:37 PM PDT 24 Aug 03 04:29:38 PM PDT 24 28456006 ps
T1079 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3577244884 Aug 03 04:29:36 PM PDT 24 Aug 03 04:29:36 PM PDT 24 13879266 ps
T1080 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2395709710 Aug 03 04:29:37 PM PDT 24 Aug 03 04:29:41 PM PDT 24 497411804 ps
T1081 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.4169994310 Aug 03 04:29:35 PM PDT 24 Aug 03 04:29:37 PM PDT 24 72353228 ps
T1082 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2164650209 Aug 03 04:29:52 PM PDT 24 Aug 03 04:29:54 PM PDT 24 137436253 ps
T1083 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2155268433 Aug 03 04:29:48 PM PDT 24 Aug 03 04:29:50 PM PDT 24 155898482 ps
T1084 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1252616919 Aug 03 04:29:57 PM PDT 24 Aug 03 04:30:01 PM PDT 24 74976583 ps

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2945478795
Short name T4
Test name
Test status
Simulation time 425954897 ps
CPU time 9.07 seconds
Started Aug 03 05:25:18 PM PDT 24
Finished Aug 03 05:25:27 PM PDT 24
Peak memory 214408 kb
Host smart-aad3b77b-4db1-4d4e-9ba4-0804f3d3177b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945478795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2945478795
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1864769241
Short name T7
Test name
Test status
Simulation time 2483084193 ps
CPU time 34.27 seconds
Started Aug 03 05:25:26 PM PDT 24
Finished Aug 03 05:26:00 PM PDT 24
Peak memory 215148 kb
Host smart-c7e4249d-a075-428d-b162-e65ac13c60f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864769241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1864769241
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.2861036140
Short name T44
Test name
Test status
Simulation time 492110579 ps
CPU time 9.94 seconds
Started Aug 03 05:24:02 PM PDT 24
Finished Aug 03 05:24:12 PM PDT 24
Peak memory 219548 kb
Host smart-7e64856d-cd60-4f3a-a546-01b3560aeaa9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861036140 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.2861036140
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1995447155
Short name T12
Test name
Test status
Simulation time 397338288 ps
CPU time 11.1 seconds
Started Aug 03 05:23:25 PM PDT 24
Finished Aug 03 05:23:36 PM PDT 24
Peak memory 230724 kb
Host smart-eb271198-02c5-43c7-95f7-d8ee14bf5a29
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995447155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1995447155
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3250506782
Short name T55
Test name
Test status
Simulation time 609662803 ps
CPU time 17.79 seconds
Started Aug 03 05:25:35 PM PDT 24
Finished Aug 03 05:25:53 PM PDT 24
Peak memory 216580 kb
Host smart-f22931ec-357d-4f16-a6a0-fb7978a9d8b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250506782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3250506782
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.2366610181
Short name T64
Test name
Test status
Simulation time 111267110 ps
CPU time 7.48 seconds
Started Aug 03 05:25:34 PM PDT 24
Finished Aug 03 05:25:42 PM PDT 24
Peak memory 222400 kb
Host smart-6fadb742-27e7-42a0-b7ce-ec1cc85be842
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366610181 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.2366610181
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.301644278
Short name T35
Test name
Test status
Simulation time 154783509 ps
CPU time 3.8 seconds
Started Aug 03 05:23:09 PM PDT 24
Finished Aug 03 05:23:13 PM PDT 24
Peak memory 215168 kb
Host smart-b722d969-cd42-4c35-a47d-da7fb3b07c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301644278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.301644278
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2951277688
Short name T135
Test name
Test status
Simulation time 96656379 ps
CPU time 5.43 seconds
Started Aug 03 05:24:29 PM PDT 24
Finished Aug 03 05:24:34 PM PDT 24
Peak memory 215504 kb
Host smart-99ae3354-269a-4c24-bebb-1ca7cf3c7694
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2951277688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2951277688
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.783395271
Short name T118
Test name
Test status
Simulation time 548656300 ps
CPU time 17.02 seconds
Started Aug 03 04:29:50 PM PDT 24
Finished Aug 03 04:30:07 PM PDT 24
Peak memory 214600 kb
Host smart-d10c66bb-9ae4-4306-98f1-bd3558655020
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783395271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.783395271
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.580154677
Short name T8
Test name
Test status
Simulation time 900708019 ps
CPU time 30.11 seconds
Started Aug 03 05:25:41 PM PDT 24
Finished Aug 03 05:26:11 PM PDT 24
Peak memory 222396 kb
Host smart-f4be86bf-b569-479e-a586-ea9a57680582
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580154677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.580154677
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.143067236
Short name T9
Test name
Test status
Simulation time 3051922406 ps
CPU time 15.93 seconds
Started Aug 03 05:25:20 PM PDT 24
Finished Aug 03 05:25:36 PM PDT 24
Peak memory 221592 kb
Host smart-59d8f6d5-3189-4422-8cb9-91faaee62a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143067236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.143067236
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3941413857
Short name T1
Test name
Test status
Simulation time 156189300 ps
CPU time 8.32 seconds
Started Aug 03 05:23:33 PM PDT 24
Finished Aug 03 05:23:41 PM PDT 24
Peak memory 214408 kb
Host smart-5616bae4-33b7-42c5-adc2-3e46b3649cd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3941413857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3941413857
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3067574933
Short name T116
Test name
Test status
Simulation time 131315945 ps
CPU time 7.27 seconds
Started Aug 03 05:24:57 PM PDT 24
Finished Aug 03 05:25:05 PM PDT 24
Peak memory 214296 kb
Host smart-3ef2701f-a19f-4e2e-80f1-0ccf0a67995a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3067574933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3067574933
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2344559721
Short name T41
Test name
Test status
Simulation time 285688378 ps
CPU time 2.06 seconds
Started Aug 03 05:24:49 PM PDT 24
Finished Aug 03 05:24:52 PM PDT 24
Peak memory 210204 kb
Host smart-dde3e04f-751c-414c-8d87-00d55dbbabd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344559721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2344559721
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.1193409816
Short name T121
Test name
Test status
Simulation time 398304600 ps
CPU time 14.58 seconds
Started Aug 03 05:24:39 PM PDT 24
Finished Aug 03 05:24:53 PM PDT 24
Peak memory 222660 kb
Host smart-c412a4b7-0c0e-4df8-ab9f-751220f9edad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193409816 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.1193409816
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.4223075877
Short name T231
Test name
Test status
Simulation time 200053705 ps
CPU time 10.14 seconds
Started Aug 03 05:25:02 PM PDT 24
Finished Aug 03 05:25:12 PM PDT 24
Peak memory 214300 kb
Host smart-b9854cdc-dc0b-4aab-aa5d-db90744c241b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4223075877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.4223075877
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3946040682
Short name T216
Test name
Test status
Simulation time 946655201 ps
CPU time 34.4 seconds
Started Aug 03 05:24:08 PM PDT 24
Finished Aug 03 05:24:42 PM PDT 24
Peak memory 215472 kb
Host smart-d4ce64c5-a69f-44e7-90da-462d2fb3e479
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946040682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3946040682
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.4081301860
Short name T21
Test name
Test status
Simulation time 139313229 ps
CPU time 2.54 seconds
Started Aug 03 05:24:20 PM PDT 24
Finished Aug 03 05:24:23 PM PDT 24
Peak memory 222332 kb
Host smart-b2d13972-0e75-421f-8226-cf5fbe1156c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081301860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.4081301860
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.215312052
Short name T93
Test name
Test status
Simulation time 19655093663 ps
CPU time 53.94 seconds
Started Aug 03 05:23:09 PM PDT 24
Finished Aug 03 05:24:03 PM PDT 24
Peak memory 218564 kb
Host smart-d9863424-9b63-400b-855d-1bfcef0a35cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215312052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.215312052
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.58799427
Short name T326
Test name
Test status
Simulation time 914705065 ps
CPU time 49.13 seconds
Started Aug 03 05:24:13 PM PDT 24
Finished Aug 03 05:25:03 PM PDT 24
Peak memory 215420 kb
Host smart-ee4fc8c2-4377-4842-a883-55f57aadb647
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58799427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.58799427
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.718839569
Short name T331
Test name
Test status
Simulation time 1070128917 ps
CPU time 14.98 seconds
Started Aug 03 05:24:20 PM PDT 24
Finished Aug 03 05:24:35 PM PDT 24
Peak memory 214248 kb
Host smart-88619cc3-c08a-462b-bb38-9febc212b973
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=718839569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.718839569
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1677503432
Short name T66
Test name
Test status
Simulation time 2401398229 ps
CPU time 55.46 seconds
Started Aug 03 05:25:21 PM PDT 24
Finished Aug 03 05:26:16 PM PDT 24
Peak memory 216272 kb
Host smart-e0348c2e-279a-48de-ab3a-7b1ce7e7cb8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677503432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1677503432
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.183729420
Short name T63
Test name
Test status
Simulation time 44409318 ps
CPU time 3.41 seconds
Started Aug 03 05:25:30 PM PDT 24
Finished Aug 03 05:25:34 PM PDT 24
Peak memory 218416 kb
Host smart-0e339b55-8f42-4f60-b1f8-26a2c285a02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183729420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.183729420
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1269269288
Short name T60
Test name
Test status
Simulation time 911079619 ps
CPU time 13.66 seconds
Started Aug 03 05:23:54 PM PDT 24
Finished Aug 03 05:24:08 PM PDT 24
Peak memory 217048 kb
Host smart-15a5090f-1535-40f0-90e2-357cc3fe8077
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269269288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1269269288
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.236744427
Short name T122
Test name
Test status
Simulation time 185029533 ps
CPU time 1.69 seconds
Started Aug 03 04:29:51 PM PDT 24
Finished Aug 03 04:29:52 PM PDT 24
Peak memory 214508 kb
Host smart-79448fd7-508a-4eaa-a828-e3298a590d6c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236744427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.236744427
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.3704219393
Short name T40
Test name
Test status
Simulation time 4493560697 ps
CPU time 36.06 seconds
Started Aug 03 05:25:03 PM PDT 24
Finished Aug 03 05:25:39 PM PDT 24
Peak memory 214308 kb
Host smart-373735c1-6dd2-4456-91cf-0108e5fce939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704219393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3704219393
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1606649016
Short name T238
Test name
Test status
Simulation time 207778089 ps
CPU time 6.38 seconds
Started Aug 03 05:24:06 PM PDT 24
Finished Aug 03 05:24:12 PM PDT 24
Peak memory 222360 kb
Host smart-42733541-ebcc-453f-b56f-9829786519c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1606649016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1606649016
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3248299507
Short name T184
Test name
Test status
Simulation time 9472745126 ps
CPU time 56.96 seconds
Started Aug 03 05:24:13 PM PDT 24
Finished Aug 03 05:25:11 PM PDT 24
Peak memory 222556 kb
Host smart-dd1411f9-4d97-47aa-8356-863e6b0d46e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248299507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3248299507
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.3697598766
Short name T97
Test name
Test status
Simulation time 614209336 ps
CPU time 5.24 seconds
Started Aug 03 05:25:30 PM PDT 24
Finished Aug 03 05:25:35 PM PDT 24
Peak memory 214232 kb
Host smart-c5da4e58-a927-4755-aabf-ec168dda88df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697598766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3697598766
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.38432692
Short name T53
Test name
Test status
Simulation time 8791037710 ps
CPU time 53.92 seconds
Started Aug 03 05:23:14 PM PDT 24
Finished Aug 03 05:24:08 PM PDT 24
Peak memory 216108 kb
Host smart-0e527f27-2934-4f64-91b1-9f6a8c1ce548
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38432692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.38432692
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3149734330
Short name T910
Test name
Test status
Simulation time 418630486 ps
CPU time 3.73 seconds
Started Aug 03 05:24:13 PM PDT 24
Finished Aug 03 05:24:16 PM PDT 24
Peak memory 208668 kb
Host smart-70d18d30-fbd1-4a60-b1b5-20b146934fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149734330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3149734330
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.927916969
Short name T851
Test name
Test status
Simulation time 288209206 ps
CPU time 7.5 seconds
Started Aug 03 05:24:38 PM PDT 24
Finished Aug 03 05:24:45 PM PDT 24
Peak memory 215664 kb
Host smart-1cda304e-ecd7-4313-b174-43e45b890e23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=927916969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.927916969
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.4125109872
Short name T253
Test name
Test status
Simulation time 69622907348 ps
CPU time 398.31 seconds
Started Aug 03 05:24:39 PM PDT 24
Finished Aug 03 05:31:17 PM PDT 24
Peak memory 219280 kb
Host smart-fc8947a7-942a-4e3e-a31d-ffd9f9e2bc79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125109872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.4125109872
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2401956047
Short name T291
Test name
Test status
Simulation time 5733611633 ps
CPU time 48.51 seconds
Started Aug 03 05:25:18 PM PDT 24
Finished Aug 03 05:26:07 PM PDT 24
Peak memory 222572 kb
Host smart-595b7c9c-cab7-468d-9e5d-800575b1f19b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401956047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2401956047
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.63603712
Short name T425
Test name
Test status
Simulation time 144944447 ps
CPU time 0.85 seconds
Started Aug 03 05:23:56 PM PDT 24
Finished Aug 03 05:23:57 PM PDT 24
Peak memory 205872 kb
Host smart-7476b295-b0b1-4d84-998a-fa56f5759d29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63603712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.63603712
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2129623493
Short name T157
Test name
Test status
Simulation time 358809713 ps
CPU time 4.42 seconds
Started Aug 03 04:29:48 PM PDT 24
Finished Aug 03 04:29:53 PM PDT 24
Peak memory 214220 kb
Host smart-95fb0209-ad81-4eab-a3fc-0c739b660f9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129623493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2129623493
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.1143463520
Short name T17
Test name
Test status
Simulation time 38817181 ps
CPU time 2.28 seconds
Started Aug 03 05:24:44 PM PDT 24
Finished Aug 03 05:24:46 PM PDT 24
Peak memory 208360 kb
Host smart-2d52b305-88ac-44d5-881d-131b62ac023b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143463520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1143463520
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3603956710
Short name T280
Test name
Test status
Simulation time 1066613383 ps
CPU time 56.33 seconds
Started Aug 03 05:24:49 PM PDT 24
Finished Aug 03 05:25:46 PM PDT 24
Peak memory 222460 kb
Host smart-b1d77b22-5f5c-4616-9334-a427db2dbc41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3603956710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3603956710
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.882817878
Short name T297
Test name
Test status
Simulation time 147658630 ps
CPU time 2.67 seconds
Started Aug 03 05:23:48 PM PDT 24
Finished Aug 03 05:23:51 PM PDT 24
Peak memory 214504 kb
Host smart-25cf81f5-66c8-4472-b7b9-2e10c875c0dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=882817878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.882817878
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2421069778
Short name T145
Test name
Test status
Simulation time 188844489 ps
CPU time 2.66 seconds
Started Aug 03 04:29:41 PM PDT 24
Finished Aug 03 04:29:44 PM PDT 24
Peak memory 214160 kb
Host smart-b115b2ab-054f-4fbe-a829-05e6a92bafe9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421069778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2421069778
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2168879880
Short name T38
Test name
Test status
Simulation time 43642437 ps
CPU time 3.07 seconds
Started Aug 03 05:23:37 PM PDT 24
Finished Aug 03 05:23:40 PM PDT 24
Peak memory 215016 kb
Host smart-dd7a2075-3ad6-4031-8162-221eabd2101b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168879880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2168879880
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.4158381799
Short name T6
Test name
Test status
Simulation time 53970016861 ps
CPU time 488.23 seconds
Started Aug 03 05:24:55 PM PDT 24
Finished Aug 03 05:33:04 PM PDT 24
Peak memory 222540 kb
Host smart-496392da-1164-467a-a1cf-b7ba9495929a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158381799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.4158381799
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1794258021
Short name T171
Test name
Test status
Simulation time 61256667 ps
CPU time 3.48 seconds
Started Aug 03 05:23:45 PM PDT 24
Finished Aug 03 05:23:48 PM PDT 24
Peak memory 222632 kb
Host smart-1a218fcb-b63e-4c35-99ee-8c9ac6c3c6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794258021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1794258021
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.3304532149
Short name T248
Test name
Test status
Simulation time 120933831 ps
CPU time 2.35 seconds
Started Aug 03 05:25:05 PM PDT 24
Finished Aug 03 05:25:08 PM PDT 24
Peak memory 214272 kb
Host smart-8e3d27e8-d93b-4e68-a007-7d750e16606f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304532149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3304532149
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.117646722
Short name T152
Test name
Test status
Simulation time 366139167 ps
CPU time 6.79 seconds
Started Aug 03 04:29:52 PM PDT 24
Finished Aug 03 04:29:59 PM PDT 24
Peak memory 206132 kb
Host smart-496f5060-4c15-48e1-aa35-a8eeb366033d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117646722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.117646722
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2435411905
Short name T221
Test name
Test status
Simulation time 1793207182 ps
CPU time 48.04 seconds
Started Aug 03 05:24:28 PM PDT 24
Finished Aug 03 05:25:16 PM PDT 24
Peak memory 222444 kb
Host smart-ddaf065f-f054-4bdc-a75b-ae9fee827059
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435411905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2435411905
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3292656353
Short name T250
Test name
Test status
Simulation time 1072454546 ps
CPU time 15.57 seconds
Started Aug 03 05:24:33 PM PDT 24
Finished Aug 03 05:24:48 PM PDT 24
Peak memory 214404 kb
Host smart-748da112-0316-4ec4-a7b1-64e33e931279
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3292656353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3292656353
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2041148304
Short name T36
Test name
Test status
Simulation time 124854515 ps
CPU time 2.18 seconds
Started Aug 03 05:25:11 PM PDT 24
Finished Aug 03 05:25:13 PM PDT 24
Peak memory 214368 kb
Host smart-78fd2746-fb1e-466a-a11b-03b1966feb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041148304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2041148304
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.557252085
Short name T69
Test name
Test status
Simulation time 491832819 ps
CPU time 2.49 seconds
Started Aug 03 05:23:26 PM PDT 24
Finished Aug 03 05:23:28 PM PDT 24
Peak memory 221484 kb
Host smart-82520cb7-29d2-42b2-aea4-445b6046345f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557252085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.557252085
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3183427176
Short name T211
Test name
Test status
Simulation time 331715467 ps
CPU time 2.82 seconds
Started Aug 03 05:23:54 PM PDT 24
Finished Aug 03 05:23:57 PM PDT 24
Peak memory 214184 kb
Host smart-5b0d24d8-2d54-4ff1-8719-70215c398bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183427176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3183427176
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1266195020
Short name T136
Test name
Test status
Simulation time 54207134 ps
CPU time 2.44 seconds
Started Aug 03 05:23:20 PM PDT 24
Finished Aug 03 05:23:23 PM PDT 24
Peak memory 214368 kb
Host smart-bbb8cf59-b35b-4dde-99d0-77fb51401a62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1266195020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1266195020
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.197664352
Short name T186
Test name
Test status
Simulation time 8579886089 ps
CPU time 48.94 seconds
Started Aug 03 05:25:30 PM PDT 24
Finished Aug 03 05:26:19 PM PDT 24
Peak memory 221376 kb
Host smart-3ec3f201-515a-4dcf-afe8-1fb3366685b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197664352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.197664352
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.1931284703
Short name T829
Test name
Test status
Simulation time 439140426 ps
CPU time 22.36 seconds
Started Aug 03 05:24:31 PM PDT 24
Finished Aug 03 05:24:54 PM PDT 24
Peak memory 222524 kb
Host smart-d5d502ed-585d-450c-b2a8-c8b83c07c490
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931284703 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.1931284703
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2330713919
Short name T167
Test name
Test status
Simulation time 179546270 ps
CPU time 2.38 seconds
Started Aug 03 05:25:06 PM PDT 24
Finished Aug 03 05:25:09 PM PDT 24
Peak memory 210568 kb
Host smart-6d5a5ee5-6b67-49a8-b6a0-c806eace6bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330713919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2330713919
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.4042525380
Short name T938
Test name
Test status
Simulation time 2016425064 ps
CPU time 6.56 seconds
Started Aug 03 04:29:31 PM PDT 24
Finished Aug 03 04:29:38 PM PDT 24
Peak memory 214444 kb
Host smart-34991d5a-5a9b-47cf-aac3-b356bbe75290
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042525380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.4042525380
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3194751600
Short name T164
Test name
Test status
Simulation time 118078086 ps
CPU time 4.68 seconds
Started Aug 03 04:30:08 PM PDT 24
Finished Aug 03 04:30:13 PM PDT 24
Peak memory 214224 kb
Host smart-c10bfbee-1289-47e9-af1e-afed59f24525
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194751600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3194751600
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1553887411
Short name T153
Test name
Test status
Simulation time 322943837 ps
CPU time 9.48 seconds
Started Aug 03 04:29:35 PM PDT 24
Finished Aug 03 04:29:44 PM PDT 24
Peak memory 214200 kb
Host smart-1d159081-7f9a-44fe-b92b-8c501e8d207a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553887411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1553887411
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.565035236
Short name T175
Test name
Test status
Simulation time 71790873 ps
CPU time 2.07 seconds
Started Aug 03 05:24:51 PM PDT 24
Finished Aug 03 05:24:53 PM PDT 24
Peak memory 216336 kb
Host smart-343f1c8e-3871-433f-87b3-b66b0a2091d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565035236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.565035236
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.545146439
Short name T345
Test name
Test status
Simulation time 65234212 ps
CPU time 2.51 seconds
Started Aug 03 05:23:43 PM PDT 24
Finished Aug 03 05:23:46 PM PDT 24
Peak memory 214332 kb
Host smart-0390eb9f-52bf-49da-8db3-8b48f648bd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545146439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.545146439
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3770809360
Short name T548
Test name
Test status
Simulation time 32325446 ps
CPU time 2.18 seconds
Started Aug 03 05:23:15 PM PDT 24
Finished Aug 03 05:23:17 PM PDT 24
Peak memory 214348 kb
Host smart-1a782378-6d13-41b7-bf1c-edd133c15f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770809360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3770809360
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.235338673
Short name T207
Test name
Test status
Simulation time 1712151872 ps
CPU time 41.19 seconds
Started Aug 03 05:24:28 PM PDT 24
Finished Aug 03 05:25:09 PM PDT 24
Peak memory 208476 kb
Host smart-518c63a3-6e90-48dd-8332-72a3d6809535
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235338673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.235338673
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2895730783
Short name T117
Test name
Test status
Simulation time 136034262 ps
CPU time 3.26 seconds
Started Aug 03 05:24:38 PM PDT 24
Finished Aug 03 05:24:42 PM PDT 24
Peak memory 215524 kb
Host smart-b9743b6c-9bf4-4bf4-a7b5-c47e6986200d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2895730783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2895730783
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2285056711
Short name T252
Test name
Test status
Simulation time 261875299 ps
CPU time 5.13 seconds
Started Aug 03 05:25:24 PM PDT 24
Finished Aug 03 05:25:29 PM PDT 24
Peak memory 215476 kb
Host smart-fe85a813-b158-439a-bcee-2cc374ea6ecc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2285056711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2285056711
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1071655846
Short name T159
Test name
Test status
Simulation time 405540251 ps
CPU time 2.58 seconds
Started Aug 03 05:24:26 PM PDT 24
Finished Aug 03 05:24:29 PM PDT 24
Peak memory 209924 kb
Host smart-fe12e46e-06b8-4a21-8c7f-8110492d8c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071655846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1071655846
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1750051448
Short name T90
Test name
Test status
Simulation time 204565903 ps
CPU time 3.78 seconds
Started Aug 03 05:25:36 PM PDT 24
Finished Aug 03 05:25:40 PM PDT 24
Peak memory 222448 kb
Host smart-ca95d9f8-ef93-4122-9be6-d8c1af16d0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750051448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1750051448
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.191371300
Short name T172
Test name
Test status
Simulation time 334541948 ps
CPU time 4.52 seconds
Started Aug 03 05:24:01 PM PDT 24
Finished Aug 03 05:24:06 PM PDT 24
Peak memory 217800 kb
Host smart-5cb6ff0d-b045-4177-8ceb-77902e228b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191371300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.191371300
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1566532082
Short name T174
Test name
Test status
Simulation time 152321951 ps
CPU time 3.81 seconds
Started Aug 03 05:24:26 PM PDT 24
Finished Aug 03 05:24:30 PM PDT 24
Peak memory 217992 kb
Host smart-1f485df9-2a3e-43a8-874f-e12bfac26a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566532082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1566532082
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3013099476
Short name T173
Test name
Test status
Simulation time 546516093 ps
CPU time 5.72 seconds
Started Aug 03 05:24:29 PM PDT 24
Finished Aug 03 05:24:35 PM PDT 24
Peak memory 217940 kb
Host smart-27de6fbe-035b-4cb1-a48d-d8e231949ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013099476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3013099476
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1138326089
Short name T320
Test name
Test status
Simulation time 1406033656 ps
CPU time 46.9 seconds
Started Aug 03 05:23:54 PM PDT 24
Finished Aug 03 05:24:41 PM PDT 24
Peak memory 221280 kb
Host smart-cb785c37-dc80-4bf7-8aa2-b271e8d6c1a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138326089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1138326089
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1728583379
Short name T229
Test name
Test status
Simulation time 642854541 ps
CPU time 7.63 seconds
Started Aug 03 05:23:55 PM PDT 24
Finished Aug 03 05:24:02 PM PDT 24
Peak memory 214312 kb
Host smart-5d1b4ab0-8939-4b42-8cf3-3d3eebf20518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728583379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1728583379
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3154094912
Short name T385
Test name
Test status
Simulation time 64500672 ps
CPU time 1.85 seconds
Started Aug 03 05:24:07 PM PDT 24
Finished Aug 03 05:24:09 PM PDT 24
Peak memory 214340 kb
Host smart-7c661726-d3ee-4933-b100-4f14b1ac64e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154094912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3154094912
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_random.3693469159
Short name T114
Test name
Test status
Simulation time 700692129 ps
CPU time 6.21 seconds
Started Aug 03 05:24:06 PM PDT 24
Finished Aug 03 05:24:12 PM PDT 24
Peak memory 214284 kb
Host smart-6814cc21-a0db-4af9-bbe0-fdbac4d0904b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693469159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3693469159
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.291028703
Short name T185
Test name
Test status
Simulation time 1485770389 ps
CPU time 40.22 seconds
Started Aug 03 05:24:29 PM PDT 24
Finished Aug 03 05:25:09 PM PDT 24
Peak memory 222480 kb
Host smart-1c65e002-ceb9-47c6-bf56-e176c35def4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291028703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.291028703
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.4069371377
Short name T528
Test name
Test status
Simulation time 324794228 ps
CPU time 3.01 seconds
Started Aug 03 05:24:40 PM PDT 24
Finished Aug 03 05:24:44 PM PDT 24
Peak memory 214252 kb
Host smart-af407683-fe19-4ec7-9e5e-8fc358079374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069371377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.4069371377
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3502326969
Short name T213
Test name
Test status
Simulation time 9990602219 ps
CPU time 62.31 seconds
Started Aug 03 05:24:46 PM PDT 24
Finished Aug 03 05:25:48 PM PDT 24
Peak memory 216588 kb
Host smart-58dc26dc-4d9b-460c-869a-3fa0a800bba9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502326969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3502326969
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3758624074
Short name T352
Test name
Test status
Simulation time 331636751 ps
CPU time 4.44 seconds
Started Aug 03 05:25:09 PM PDT 24
Finished Aug 03 05:25:14 PM PDT 24
Peak memory 215540 kb
Host smart-6944d5c3-2afd-4234-adf0-e1948eed68a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3758624074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3758624074
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1611543486
Short name T388
Test name
Test status
Simulation time 332115845 ps
CPU time 3.5 seconds
Started Aug 03 05:25:16 PM PDT 24
Finished Aug 03 05:25:20 PM PDT 24
Peak memory 210104 kb
Host smart-4962e0d6-2bd1-4f42-8b5f-7485eb7db437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611543486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1611543486
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.652972882
Short name T318
Test name
Test status
Simulation time 790719901 ps
CPU time 18.17 seconds
Started Aug 03 05:23:31 PM PDT 24
Finished Aug 03 05:23:49 PM PDT 24
Peak memory 222404 kb
Host smart-52c93237-d4ad-4860-b115-8a2caeb0848f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652972882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.652972882
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.195015508
Short name T147
Test name
Test status
Simulation time 212728437 ps
CPU time 4.86 seconds
Started Aug 03 04:29:25 PM PDT 24
Finished Aug 03 04:29:30 PM PDT 24
Peak memory 206000 kb
Host smart-5ee3d8a8-dbde-4dcc-a338-428030e2c837
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195015508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
195015508
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.911662296
Short name T149
Test name
Test status
Simulation time 167297115 ps
CPU time 3 seconds
Started Aug 03 04:29:59 PM PDT 24
Finished Aug 03 04:30:02 PM PDT 24
Peak memory 214200 kb
Host smart-fc7c59df-7cde-4d79-82c0-ed239108600c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911662296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err
.911662296
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2890012010
Short name T161
Test name
Test status
Simulation time 260652224 ps
CPU time 6.38 seconds
Started Aug 03 05:23:28 PM PDT 24
Finished Aug 03 05:23:35 PM PDT 24
Peak memory 210824 kb
Host smart-f6ee2048-26df-4cd9-9ed3-f746e18bcb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890012010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2890012010
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.945896915
Short name T166
Test name
Test status
Simulation time 159999350 ps
CPU time 2.2 seconds
Started Aug 03 05:23:35 PM PDT 24
Finished Aug 03 05:23:38 PM PDT 24
Peak memory 209572 kb
Host smart-24a2f395-5d60-4447-b9a5-7910e0850829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945896915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.945896915
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_random.1158430324
Short name T353
Test name
Test status
Simulation time 203880641 ps
CPU time 3.49 seconds
Started Aug 03 05:23:14 PM PDT 24
Finished Aug 03 05:23:17 PM PDT 24
Peak memory 209304 kb
Host smart-af2a1aaa-dc0c-4164-87af-1c333b7a95fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158430324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1158430324
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3861685049
Short name T371
Test name
Test status
Simulation time 60379620 ps
CPU time 2.2 seconds
Started Aug 03 05:23:42 PM PDT 24
Finished Aug 03 05:23:45 PM PDT 24
Peak memory 215748 kb
Host smart-7d7cc750-b462-4f04-9c82-e7968695f461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861685049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3861685049
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1109185947
Short name T645
Test name
Test status
Simulation time 603112564 ps
CPU time 3.57 seconds
Started Aug 03 05:23:48 PM PDT 24
Finished Aug 03 05:23:52 PM PDT 24
Peak memory 209812 kb
Host smart-59c1be6e-904e-4346-a6bd-559b7a02145a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109185947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1109185947
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.690146264
Short name T777
Test name
Test status
Simulation time 87413463 ps
CPU time 4.53 seconds
Started Aug 03 05:23:50 PM PDT 24
Finished Aug 03 05:23:54 PM PDT 24
Peak memory 220272 kb
Host smart-41c05007-1d5b-4b48-96a5-95858a58fdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690146264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.690146264
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1450519999
Short name T256
Test name
Test status
Simulation time 211683634 ps
CPU time 5.69 seconds
Started Aug 03 05:23:59 PM PDT 24
Finished Aug 03 05:24:05 PM PDT 24
Peak memory 214244 kb
Host smart-16bcc92e-b2d3-48e0-a8ef-be38ed797df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450519999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1450519999
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3876806953
Short name T224
Test name
Test status
Simulation time 670606325 ps
CPU time 32.16 seconds
Started Aug 03 05:23:55 PM PDT 24
Finished Aug 03 05:24:27 PM PDT 24
Peak memory 214404 kb
Host smart-3c85e8e7-49d9-4001-aaa8-1794ef391a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876806953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3876806953
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3672648487
Short name T627
Test name
Test status
Simulation time 2691828851 ps
CPU time 10.94 seconds
Started Aug 03 05:24:00 PM PDT 24
Finished Aug 03 05:24:11 PM PDT 24
Peak memory 214292 kb
Host smart-d327617c-998a-43bc-b4d5-b171ff88de67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672648487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3672648487
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1919599741
Short name T763
Test name
Test status
Simulation time 30409246 ps
CPU time 2.28 seconds
Started Aug 03 05:24:07 PM PDT 24
Finished Aug 03 05:24:09 PM PDT 24
Peak memory 214320 kb
Host smart-94d89e44-c0ac-41a4-8cb3-6dad76dd47c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919599741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1919599741
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.598258504
Short name T322
Test name
Test status
Simulation time 223807136 ps
CPU time 3.1 seconds
Started Aug 03 05:23:14 PM PDT 24
Finished Aug 03 05:23:17 PM PDT 24
Peak memory 218400 kb
Host smart-d870c484-787e-464c-adeb-31e95d38e050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598258504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.598258504
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.3977014577
Short name T442
Test name
Test status
Simulation time 127879427 ps
CPU time 4.23 seconds
Started Aug 03 05:23:15 PM PDT 24
Finished Aug 03 05:23:19 PM PDT 24
Peak memory 206992 kb
Host smart-f44cf02a-0a36-48e2-80a8-42570d4eab48
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977014577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3977014577
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3348613265
Short name T365
Test name
Test status
Simulation time 343624237 ps
CPU time 4.66 seconds
Started Aug 03 05:24:32 PM PDT 24
Finished Aug 03 05:24:37 PM PDT 24
Peak memory 214280 kb
Host smart-52a0f7a1-5733-4a08-86e4-77bbec9138be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348613265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3348613265
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.267815417
Short name T228
Test name
Test status
Simulation time 214656425 ps
CPU time 2.56 seconds
Started Aug 03 05:24:33 PM PDT 24
Finished Aug 03 05:24:36 PM PDT 24
Peak memory 215488 kb
Host smart-1570f0c6-d823-41fe-91e8-b2de8a75f094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267815417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.267815417
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3424131136
Short name T410
Test name
Test status
Simulation time 1687958764 ps
CPU time 6.68 seconds
Started Aug 03 05:24:45 PM PDT 24
Finished Aug 03 05:24:52 PM PDT 24
Peak memory 215560 kb
Host smart-4bd09579-2b33-4705-b21f-e74a7d92323c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3424131136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3424131136
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.310821531
Short name T100
Test name
Test status
Simulation time 375758987 ps
CPU time 4.32 seconds
Started Aug 03 05:24:45 PM PDT 24
Finished Aug 03 05:24:50 PM PDT 24
Peak memory 214232 kb
Host smart-3be7fe89-f341-406f-b80a-986505c2a4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310821531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.310821531
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.579723624
Short name T420
Test name
Test status
Simulation time 114260068 ps
CPU time 5.73 seconds
Started Aug 03 05:24:46 PM PDT 24
Finished Aug 03 05:24:52 PM PDT 24
Peak memory 214564 kb
Host smart-79005be8-0381-49d5-a2f5-60aea3b6f813
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=579723624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.579723624
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.345977389
Short name T325
Test name
Test status
Simulation time 440268905 ps
CPU time 3.86 seconds
Started Aug 03 05:25:34 PM PDT 24
Finished Aug 03 05:25:38 PM PDT 24
Peak memory 214244 kb
Host smart-5c77c442-bc05-49d3-86d4-855b8a0ae7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345977389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.345977389
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_random.2691345583
Short name T374
Test name
Test status
Simulation time 440281014 ps
CPU time 6.6 seconds
Started Aug 03 05:25:36 PM PDT 24
Finished Aug 03 05:25:43 PM PDT 24
Peak memory 209944 kb
Host smart-73bbf18e-58a1-4c2b-ab35-746590197199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691345583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2691345583
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2277068589
Short name T28
Test name
Test status
Simulation time 1476423670 ps
CPU time 24.89 seconds
Started Aug 03 05:23:30 PM PDT 24
Finished Aug 03 05:23:55 PM PDT 24
Peak memory 222652 kb
Host smart-d05ff618-a8c7-4936-9888-de0ab6b0d0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277068589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2277068589
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1565992215
Short name T1063
Test name
Test status
Simulation time 360968184 ps
CPU time 9.64 seconds
Started Aug 03 04:29:31 PM PDT 24
Finished Aug 03 04:29:40 PM PDT 24
Peak memory 206004 kb
Host smart-f6d764e2-fd54-46b4-8c0d-42ece62ea227
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565992215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
565992215
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3172077914
Short name T1033
Test name
Test status
Simulation time 269014244 ps
CPU time 11.21 seconds
Started Aug 03 04:29:31 PM PDT 24
Finished Aug 03 04:29:42 PM PDT 24
Peak memory 206084 kb
Host smart-ef8d28c7-be99-4d56-b99e-1a11fb442d6e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172077914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
172077914
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.841163026
Short name T963
Test name
Test status
Simulation time 33442766 ps
CPU time 0.96 seconds
Started Aug 03 04:29:20 PM PDT 24
Finished Aug 03 04:29:21 PM PDT 24
Peak memory 205756 kb
Host smart-193fad69-48a0-4583-9ee1-b911e3dbf37b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841163026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.841163026
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3675116552
Short name T949
Test name
Test status
Simulation time 88810949 ps
CPU time 1.89 seconds
Started Aug 03 04:29:19 PM PDT 24
Finished Aug 03 04:29:21 PM PDT 24
Peak memory 214208 kb
Host smart-d98406c0-72e8-42ec-ad09-55847300698f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675116552 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3675116552
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.173399227
Short name T142
Test name
Test status
Simulation time 52192603 ps
CPU time 1.14 seconds
Started Aug 03 04:29:19 PM PDT 24
Finished Aug 03 04:29:20 PM PDT 24
Peak memory 206020 kb
Host smart-1756e5eb-8798-445e-9c59-7bd1bb5044c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173399227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.173399227
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3703046160
Short name T967
Test name
Test status
Simulation time 51690541 ps
CPU time 0.85 seconds
Started Aug 03 04:29:21 PM PDT 24
Finished Aug 03 04:29:22 PM PDT 24
Peak memory 205988 kb
Host smart-c696b639-b56e-453a-8c52-fb1c0fe91efc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703046160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3703046160
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2415683343
Short name T998
Test name
Test status
Simulation time 447751794 ps
CPU time 2.37 seconds
Started Aug 03 04:29:19 PM PDT 24
Finished Aug 03 04:29:22 PM PDT 24
Peak memory 205996 kb
Host smart-380a1df0-7b76-4223-a0ee-c2a0ef821bd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415683343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2415683343
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.416776066
Short name T924
Test name
Test status
Simulation time 910418407 ps
CPU time 2.5 seconds
Started Aug 03 04:29:31 PM PDT 24
Finished Aug 03 04:29:34 PM PDT 24
Peak memory 214492 kb
Host smart-39370fc3-3a44-4ccb-962e-83d51be7a6ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416776066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.416776066
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1211885277
Short name T1050
Test name
Test status
Simulation time 160685391 ps
CPU time 2.62 seconds
Started Aug 03 04:29:29 PM PDT 24
Finished Aug 03 04:29:31 PM PDT 24
Peak memory 217524 kb
Host smart-1830f3f1-bfb8-4391-b57c-f64e34426877
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211885277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1211885277
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2333182661
Short name T944
Test name
Test status
Simulation time 566385850 ps
CPU time 11.94 seconds
Started Aug 03 04:29:33 PM PDT 24
Finished Aug 03 04:29:45 PM PDT 24
Peak memory 206076 kb
Host smart-6bb9224a-3c3f-4c7a-9a47-cf8aa936bb82
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333182661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
333182661
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3741614470
Short name T1009
Test name
Test status
Simulation time 257996460 ps
CPU time 11.51 seconds
Started Aug 03 04:29:32 PM PDT 24
Finished Aug 03 04:29:44 PM PDT 24
Peak memory 206072 kb
Host smart-76b32517-a10f-4462-b2da-de39dea14f60
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741614470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
741614470
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1066073633
Short name T1068
Test name
Test status
Simulation time 23257565 ps
CPU time 0.96 seconds
Started Aug 03 04:29:32 PM PDT 24
Finished Aug 03 04:29:33 PM PDT 24
Peak memory 205936 kb
Host smart-c14dda99-f2a8-494f-afda-b4f5f7b2e0e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066073633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
066073633
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.877825049
Short name T993
Test name
Test status
Simulation time 30889419 ps
CPU time 1.6 seconds
Started Aug 03 04:29:27 PM PDT 24
Finished Aug 03 04:29:29 PM PDT 24
Peak memory 214276 kb
Host smart-e0f1a081-5df6-4a4c-8555-775c244bb945
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877825049 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.877825049
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.4066816193
Short name T1047
Test name
Test status
Simulation time 72056407 ps
CPU time 0.96 seconds
Started Aug 03 04:29:29 PM PDT 24
Finished Aug 03 04:29:30 PM PDT 24
Peak memory 205844 kb
Host smart-f67a3b04-b2d2-48c4-b324-ba6631469dfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066816193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.4066816193
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2172128031
Short name T1021
Test name
Test status
Simulation time 27308673 ps
CPU time 0.69 seconds
Started Aug 03 04:29:21 PM PDT 24
Finished Aug 03 04:29:22 PM PDT 24
Peak memory 205808 kb
Host smart-d58e6762-afae-4f58-9c86-6a81c9652576
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172128031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2172128031
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3486919646
Short name T920
Test name
Test status
Simulation time 51036866 ps
CPU time 1.66 seconds
Started Aug 03 04:29:41 PM PDT 24
Finished Aug 03 04:29:43 PM PDT 24
Peak memory 205980 kb
Host smart-fe26b74a-0ff3-4d1c-af23-9b7ec335b374
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486919646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.3486919646
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3851041132
Short name T942
Test name
Test status
Simulation time 161514300 ps
CPU time 1.82 seconds
Started Aug 03 04:29:23 PM PDT 24
Finished Aug 03 04:29:25 PM PDT 24
Peak memory 214508 kb
Host smart-c2a61f05-8340-429b-8406-ab600e827630
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851041132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3851041132
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1478348866
Short name T995
Test name
Test status
Simulation time 690716061 ps
CPU time 4.81 seconds
Started Aug 03 04:29:31 PM PDT 24
Finished Aug 03 04:29:35 PM PDT 24
Peak memory 214592 kb
Host smart-91acb185-7c03-4611-b514-85a7e380e1a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478348866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.1478348866
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1332233081
Short name T999
Test name
Test status
Simulation time 92566645 ps
CPU time 2.77 seconds
Started Aug 03 04:29:23 PM PDT 24
Finished Aug 03 04:29:25 PM PDT 24
Peak memory 214324 kb
Host smart-3bcb157d-c58d-402d-8176-7c0cc6941ca2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332233081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1332233081
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.4244194392
Short name T151
Test name
Test status
Simulation time 117962847 ps
CPU time 4.91 seconds
Started Aug 03 04:29:27 PM PDT 24
Finished Aug 03 04:29:32 PM PDT 24
Peak memory 214288 kb
Host smart-a437e19b-611d-4c49-a93a-05f34ae73bcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244194392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.4244194392
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1492316336
Short name T916
Test name
Test status
Simulation time 30220316 ps
CPU time 1.1 seconds
Started Aug 03 04:29:43 PM PDT 24
Finished Aug 03 04:29:44 PM PDT 24
Peak memory 206128 kb
Host smart-6e958535-42a6-4679-9138-f323170d3456
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492316336 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1492316336
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3375523729
Short name T141
Test name
Test status
Simulation time 34642480 ps
CPU time 0.94 seconds
Started Aug 03 04:29:52 PM PDT 24
Finished Aug 03 04:29:54 PM PDT 24
Peak memory 205764 kb
Host smart-0647ae3c-bdcf-4ddc-b476-6f86550a0369
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375523729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3375523729
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3859376492
Short name T958
Test name
Test status
Simulation time 35756559 ps
CPU time 0.85 seconds
Started Aug 03 04:29:48 PM PDT 24
Finished Aug 03 04:29:49 PM PDT 24
Peak memory 205720 kb
Host smart-955de00d-9b45-4340-aaea-0c648e0b9537
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859376492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3859376492
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.351527508
Short name T996
Test name
Test status
Simulation time 234342331 ps
CPU time 2.43 seconds
Started Aug 03 04:30:01 PM PDT 24
Finished Aug 03 04:30:03 PM PDT 24
Peak memory 206024 kb
Host smart-8ac0b575-04b6-4403-a7d0-f157773c2ae9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351527508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.351527508
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.4163871919
Short name T1037
Test name
Test status
Simulation time 158549371 ps
CPU time 2.59 seconds
Started Aug 03 04:29:42 PM PDT 24
Finished Aug 03 04:29:45 PM PDT 24
Peak memory 214560 kb
Host smart-cd598f98-7c66-4055-a19b-e3a6db747cc8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163871919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.4163871919
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2610500102
Short name T980
Test name
Test status
Simulation time 373350149 ps
CPU time 4.33 seconds
Started Aug 03 04:29:42 PM PDT 24
Finished Aug 03 04:29:47 PM PDT 24
Peak memory 216728 kb
Host smart-a7fb731a-e903-4b74-b830-1ea4fd9d6c8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610500102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2610500102
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1014527268
Short name T158
Test name
Test status
Simulation time 144441577 ps
CPU time 5.35 seconds
Started Aug 03 04:29:47 PM PDT 24
Finished Aug 03 04:29:52 PM PDT 24
Peak memory 214276 kb
Host smart-5d51d348-4a87-4621-92bd-6367e0d80cc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014527268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1014527268
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1560444789
Short name T935
Test name
Test status
Simulation time 50326229 ps
CPU time 1.24 seconds
Started Aug 03 04:29:50 PM PDT 24
Finished Aug 03 04:29:52 PM PDT 24
Peak memory 214432 kb
Host smart-bc94d848-8822-4957-984f-89da5c0ef0d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560444789 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1560444789
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2973024069
Short name T1035
Test name
Test status
Simulation time 16639814 ps
CPU time 0.91 seconds
Started Aug 03 04:29:50 PM PDT 24
Finished Aug 03 04:29:52 PM PDT 24
Peak memory 205724 kb
Host smart-390ecc91-e07f-4d0b-8b0e-ccd9b1cb14ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973024069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2973024069
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2814903657
Short name T1007
Test name
Test status
Simulation time 15373086 ps
CPU time 0.9 seconds
Started Aug 03 04:29:42 PM PDT 24
Finished Aug 03 04:29:43 PM PDT 24
Peak memory 205872 kb
Host smart-5cd6fe29-94e7-4ace-b928-42b9c6f87cb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814903657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2814903657
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.487294747
Short name T982
Test name
Test status
Simulation time 464705028 ps
CPU time 2.32 seconds
Started Aug 03 04:29:53 PM PDT 24
Finished Aug 03 04:29:55 PM PDT 24
Peak memory 206064 kb
Host smart-d2c3eaf5-2309-441b-a18d-331c8f0e9005
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487294747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.487294747
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.162682501
Short name T1030
Test name
Test status
Simulation time 140482114 ps
CPU time 2.75 seconds
Started Aug 03 04:29:42 PM PDT 24
Finished Aug 03 04:29:45 PM PDT 24
Peak memory 214536 kb
Host smart-098421d9-6941-4f32-80c0-c4077e1a7743
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162682501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.162682501
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3369958142
Short name T991
Test name
Test status
Simulation time 273315038 ps
CPU time 4.28 seconds
Started Aug 03 04:29:41 PM PDT 24
Finished Aug 03 04:29:46 PM PDT 24
Peak memory 220456 kb
Host smart-bfd4324c-84d8-4eea-96f0-19dd6051de5d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369958142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3369958142
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3548202635
Short name T917
Test name
Test status
Simulation time 52881507 ps
CPU time 1.64 seconds
Started Aug 03 04:29:41 PM PDT 24
Finished Aug 03 04:29:43 PM PDT 24
Peak memory 214172 kb
Host smart-f4117d7b-c302-40ef-a52c-6a61a91c4002
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548202635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3548202635
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.161551611
Short name T1041
Test name
Test status
Simulation time 147947927 ps
CPU time 3.45 seconds
Started Aug 03 04:29:42 PM PDT 24
Finished Aug 03 04:29:45 PM PDT 24
Peak memory 206380 kb
Host smart-4c4606fc-2031-47f1-af33-7759b952e464
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161551611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.161551611
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.726737239
Short name T922
Test name
Test status
Simulation time 30019137 ps
CPU time 1.56 seconds
Started Aug 03 04:29:41 PM PDT 24
Finished Aug 03 04:29:43 PM PDT 24
Peak memory 206064 kb
Host smart-951a2684-10e5-4215-845b-73e20814ccea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726737239 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.726737239
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3266451295
Short name T997
Test name
Test status
Simulation time 8957007 ps
CPU time 0.86 seconds
Started Aug 03 04:29:43 PM PDT 24
Finished Aug 03 04:29:44 PM PDT 24
Peak memory 205976 kb
Host smart-4e44ad3c-e7ab-46ad-8e93-5732e769b19a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266451295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3266451295
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3263534920
Short name T1016
Test name
Test status
Simulation time 9370741 ps
CPU time 0.69 seconds
Started Aug 03 04:29:51 PM PDT 24
Finished Aug 03 04:29:51 PM PDT 24
Peak memory 205848 kb
Host smart-4d495fcc-cbdc-4638-83b4-80810b0fdcbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263534920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3263534920
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.19361861
Short name T1017
Test name
Test status
Simulation time 172395291 ps
CPU time 3.34 seconds
Started Aug 03 04:29:42 PM PDT 24
Finished Aug 03 04:29:45 PM PDT 24
Peak memory 206064 kb
Host smart-07c61eda-564a-42d7-8a1e-d58fe363d6ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19361861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sam
e_csr_outstanding.19361861
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.7196410
Short name T1012
Test name
Test status
Simulation time 89950969 ps
CPU time 2.66 seconds
Started Aug 03 04:30:25 PM PDT 24
Finished Aug 03 04:30:27 PM PDT 24
Peak memory 214436 kb
Host smart-23fa0c56-ce07-44b0-96bd-ddd83a343e67
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7196410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_
reg_errors.7196410
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1958093023
Short name T990
Test name
Test status
Simulation time 1865633413 ps
CPU time 9.8 seconds
Started Aug 03 04:29:42 PM PDT 24
Finished Aug 03 04:29:52 PM PDT 24
Peak memory 221464 kb
Host smart-86f42912-551b-4e1e-af96-f0f40b124fe6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958093023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1958093023
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.4035303576
Short name T1049
Test name
Test status
Simulation time 53408904 ps
CPU time 1.85 seconds
Started Aug 03 04:29:51 PM PDT 24
Finished Aug 03 04:29:53 PM PDT 24
Peak memory 222084 kb
Host smart-56ced328-a6a8-4bd4-8f8d-9b53bd7bc641
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035303576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.4035303576
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.757194291
Short name T150
Test name
Test status
Simulation time 554844035 ps
CPU time 3.94 seconds
Started Aug 03 04:29:51 PM PDT 24
Finished Aug 03 04:29:55 PM PDT 24
Peak memory 215416 kb
Host smart-9f8a11fe-db83-4ad3-b1a3-c20d693cf789
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757194291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err
.757194291
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3940109281
Short name T957
Test name
Test status
Simulation time 47248952 ps
CPU time 2.26 seconds
Started Aug 03 04:29:42 PM PDT 24
Finished Aug 03 04:29:45 PM PDT 24
Peak memory 214232 kb
Host smart-3be3b493-322a-43d1-9e88-f6d75c823799
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940109281 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3940109281
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1366639824
Short name T1075
Test name
Test status
Simulation time 149354687 ps
CPU time 1.02 seconds
Started Aug 03 04:30:04 PM PDT 24
Finished Aug 03 04:30:05 PM PDT 24
Peak memory 206044 kb
Host smart-e0acf3f5-dbba-445c-adf4-fa9282d9224c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366639824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1366639824
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2375969937
Short name T1032
Test name
Test status
Simulation time 25189179 ps
CPU time 0.74 seconds
Started Aug 03 04:29:41 PM PDT 24
Finished Aug 03 04:29:42 PM PDT 24
Peak memory 205764 kb
Host smart-b2305acb-9d29-4628-8927-f11b88a7c88c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375969937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2375969937
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2650773970
Short name T1022
Test name
Test status
Simulation time 146691094 ps
CPU time 3.02 seconds
Started Aug 03 04:29:59 PM PDT 24
Finished Aug 03 04:30:02 PM PDT 24
Peak memory 206020 kb
Host smart-c7d89d08-a1ca-4bac-bf43-3642c6f44ff6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650773970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2650773970
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.4147033307
Short name T119
Test name
Test status
Simulation time 87302464 ps
CPU time 1.63 seconds
Started Aug 03 04:29:43 PM PDT 24
Finished Aug 03 04:29:44 PM PDT 24
Peak memory 214456 kb
Host smart-3a9c1a0f-8f4a-4860-b4af-6c4420de3395
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147033307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.4147033307
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3119243376
Short name T1036
Test name
Test status
Simulation time 2987222758 ps
CPU time 6.9 seconds
Started Aug 03 04:29:42 PM PDT 24
Finished Aug 03 04:29:50 PM PDT 24
Peak memory 221748 kb
Host smart-36415609-2ea8-4bd4-8080-e69ece75d041
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119243376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3119243376
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3615149173
Short name T1003
Test name
Test status
Simulation time 29426245 ps
CPU time 2.07 seconds
Started Aug 03 04:29:48 PM PDT 24
Finished Aug 03 04:29:50 PM PDT 24
Peak memory 214248 kb
Host smart-7f85b431-c3b1-4e65-882e-dcd7aedaceb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615149173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3615149173
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3579223464
Short name T396
Test name
Test status
Simulation time 54019539 ps
CPU time 1.57 seconds
Started Aug 03 04:29:52 PM PDT 24
Finished Aug 03 04:29:54 PM PDT 24
Peak memory 214296 kb
Host smart-7113db5e-2e53-4e5b-9dae-e3996cb9a3f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579223464 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3579223464
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.359496499
Short name T1066
Test name
Test status
Simulation time 12872874 ps
CPU time 1.08 seconds
Started Aug 03 04:29:48 PM PDT 24
Finished Aug 03 04:29:49 PM PDT 24
Peak memory 206012 kb
Host smart-eda4b169-f19d-4c6f-b742-2fa7f4420485
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359496499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.359496499
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2324250735
Short name T945
Test name
Test status
Simulation time 37485604 ps
CPU time 0.76 seconds
Started Aug 03 04:29:48 PM PDT 24
Finished Aug 03 04:29:49 PM PDT 24
Peak memory 205692 kb
Host smart-16fbd793-3340-460d-a6fc-efbc9a691b42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324250735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2324250735
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2186683696
Short name T1052
Test name
Test status
Simulation time 108157532 ps
CPU time 2.61 seconds
Started Aug 03 04:29:47 PM PDT 24
Finished Aug 03 04:29:50 PM PDT 24
Peak memory 206012 kb
Host smart-751d44e9-d314-420f-b2b7-cee472e66b83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186683696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2186683696
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.829830153
Short name T975
Test name
Test status
Simulation time 856645410 ps
CPU time 1.79 seconds
Started Aug 03 04:29:57 PM PDT 24
Finished Aug 03 04:29:59 PM PDT 24
Peak memory 214516 kb
Host smart-53617ee2-5159-4fc8-930b-9001997db644
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829830153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.829830153
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1274063536
Short name T125
Test name
Test status
Simulation time 450289945 ps
CPU time 9.18 seconds
Started Aug 03 04:30:11 PM PDT 24
Finished Aug 03 04:30:21 PM PDT 24
Peak memory 220780 kb
Host smart-912c657e-125a-4f4c-bb40-98860c0304a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274063536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1274063536
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1812056032
Short name T1046
Test name
Test status
Simulation time 182946081 ps
CPU time 1.61 seconds
Started Aug 03 04:29:50 PM PDT 24
Finished Aug 03 04:29:51 PM PDT 24
Peak memory 214428 kb
Host smart-414abfa8-b3ae-4483-a3af-3579b2b7c901
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812056032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1812056032
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1979369701
Short name T160
Test name
Test status
Simulation time 1468085981 ps
CPU time 4.25 seconds
Started Aug 03 04:29:58 PM PDT 24
Finished Aug 03 04:30:03 PM PDT 24
Peak memory 214228 kb
Host smart-d5020104-c779-4968-ae9e-236658ca1f74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979369701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1979369701
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1131259258
Short name T1002
Test name
Test status
Simulation time 27451622 ps
CPU time 1.43 seconds
Started Aug 03 04:29:52 PM PDT 24
Finished Aug 03 04:29:54 PM PDT 24
Peak memory 214388 kb
Host smart-461ae8eb-efd9-4ebb-8c6c-16d971ee35dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131259258 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1131259258
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2927449980
Short name T1043
Test name
Test status
Simulation time 13639324 ps
CPU time 1.04 seconds
Started Aug 03 04:29:52 PM PDT 24
Finished Aug 03 04:29:54 PM PDT 24
Peak memory 206028 kb
Host smart-862aea8f-f390-4fd8-af2c-4dee348bef13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927449980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2927449980
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2298046726
Short name T932
Test name
Test status
Simulation time 12627697 ps
CPU time 0.72 seconds
Started Aug 03 04:29:50 PM PDT 24
Finished Aug 03 04:29:51 PM PDT 24
Peak memory 205808 kb
Host smart-a9cad1eb-fa47-4a9b-be67-edaaaf3852a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298046726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2298046726
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.573172696
Short name T1062
Test name
Test status
Simulation time 88516106 ps
CPU time 1.49 seconds
Started Aug 03 04:29:52 PM PDT 24
Finished Aug 03 04:29:54 PM PDT 24
Peak memory 205976 kb
Host smart-4d5e42c6-4999-4e55-b5ae-eeeb25142452
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573172696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.573172696
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2553968462
Short name T931
Test name
Test status
Simulation time 409798579 ps
CPU time 3.36 seconds
Started Aug 03 04:29:53 PM PDT 24
Finished Aug 03 04:29:57 PM PDT 24
Peak memory 222516 kb
Host smart-a2816def-67f3-408f-9dbb-6af12f7c5b34
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553968462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2553968462
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.403891757
Short name T1011
Test name
Test status
Simulation time 342608476 ps
CPU time 8.42 seconds
Started Aug 03 04:29:49 PM PDT 24
Finished Aug 03 04:29:57 PM PDT 24
Peak memory 214580 kb
Host smart-ee70f16e-2692-4341-b278-cac3f60f1303
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403891757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_shadow_reg_errors_with_csr_rw.403891757
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2164650209
Short name T1082
Test name
Test status
Simulation time 137436253 ps
CPU time 2.13 seconds
Started Aug 03 04:29:52 PM PDT 24
Finished Aug 03 04:29:54 PM PDT 24
Peak memory 214336 kb
Host smart-65213c84-1c47-4c9e-8f7e-ad27451b7052
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164650209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2164650209
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.410138324
Short name T961
Test name
Test status
Simulation time 18158087 ps
CPU time 1.34 seconds
Started Aug 03 04:29:53 PM PDT 24
Finished Aug 03 04:29:55 PM PDT 24
Peak memory 214244 kb
Host smart-4347891b-3095-43b4-8e58-b4cdddfe0c16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410138324 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.410138324
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3061251393
Short name T946
Test name
Test status
Simulation time 16923917 ps
CPU time 0.91 seconds
Started Aug 03 04:29:52 PM PDT 24
Finished Aug 03 04:29:54 PM PDT 24
Peak memory 205764 kb
Host smart-3260679c-3ae3-4ad6-a502-5343f510234f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061251393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3061251393
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.812135762
Short name T937
Test name
Test status
Simulation time 44250614 ps
CPU time 0.84 seconds
Started Aug 03 04:29:53 PM PDT 24
Finished Aug 03 04:29:54 PM PDT 24
Peak memory 205840 kb
Host smart-aa78d71a-75e3-4129-bf53-d33141525365
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812135762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.812135762
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2674627388
Short name T1027
Test name
Test status
Simulation time 49434886 ps
CPU time 1.54 seconds
Started Aug 03 04:29:49 PM PDT 24
Finished Aug 03 04:29:50 PM PDT 24
Peak memory 205928 kb
Host smart-1561f82b-82b4-473d-823c-7960514d1fd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674627388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2674627388
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.224208395
Short name T934
Test name
Test status
Simulation time 382717666 ps
CPU time 4.76 seconds
Started Aug 03 04:29:50 PM PDT 24
Finished Aug 03 04:29:55 PM PDT 24
Peak memory 220480 kb
Host smart-a4a49d05-5ec5-4170-96d2-a9dabe497c39
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224208395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.224208395
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3515977858
Short name T1069
Test name
Test status
Simulation time 61593629 ps
CPU time 2.29 seconds
Started Aug 03 04:29:53 PM PDT 24
Finished Aug 03 04:29:56 PM PDT 24
Peak memory 214316 kb
Host smart-78d89513-3716-4158-b737-e45fbe05dbb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515977858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3515977858
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2932008138
Short name T951
Test name
Test status
Simulation time 44025356 ps
CPU time 1.74 seconds
Started Aug 03 04:29:50 PM PDT 24
Finished Aug 03 04:29:52 PM PDT 24
Peak memory 214320 kb
Host smart-a02a23ef-5a37-4c30-a582-08e1dc5a8bfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932008138 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2932008138
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1798181503
Short name T1044
Test name
Test status
Simulation time 58425756 ps
CPU time 1.52 seconds
Started Aug 03 04:29:53 PM PDT 24
Finished Aug 03 04:29:54 PM PDT 24
Peak memory 206020 kb
Host smart-b69e80fe-ead7-44a8-a2ca-0140f8c4a4cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798181503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1798181503
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3167121241
Short name T1048
Test name
Test status
Simulation time 21840120 ps
CPU time 0.91 seconds
Started Aug 03 04:29:55 PM PDT 24
Finished Aug 03 04:29:56 PM PDT 24
Peak memory 205916 kb
Host smart-0b4b3a39-b3a8-48ea-8c73-fe2b73b5a8ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167121241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3167121241
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.496415689
Short name T941
Test name
Test status
Simulation time 195987858 ps
CPU time 2.58 seconds
Started Aug 03 04:29:51 PM PDT 24
Finished Aug 03 04:29:54 PM PDT 24
Peak memory 206060 kb
Host smart-e5705deb-33b1-4bfe-82a5-fea83b4e8e42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496415689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.496415689
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2335085346
Short name T988
Test name
Test status
Simulation time 365655607 ps
CPU time 2.54 seconds
Started Aug 03 04:29:56 PM PDT 24
Finished Aug 03 04:29:59 PM PDT 24
Peak memory 214492 kb
Host smart-6950a724-1a7d-4697-aa66-6871a74239b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335085346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2335085346
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3525716624
Short name T972
Test name
Test status
Simulation time 156459126 ps
CPU time 8.24 seconds
Started Aug 03 04:29:56 PM PDT 24
Finished Aug 03 04:30:05 PM PDT 24
Peak memory 214520 kb
Host smart-2dba5ef1-20fb-46e0-bf94-29ae798b1a61
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525716624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3525716624
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3116457192
Short name T1065
Test name
Test status
Simulation time 188767206 ps
CPU time 2.19 seconds
Started Aug 03 04:29:52 PM PDT 24
Finished Aug 03 04:29:54 PM PDT 24
Peak memory 214344 kb
Host smart-e9f97f39-00ec-4e79-99a7-a3668a75edaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116457192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3116457192
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.720411736
Short name T156
Test name
Test status
Simulation time 613346662 ps
CPU time 4.95 seconds
Started Aug 03 04:29:56 PM PDT 24
Finished Aug 03 04:30:01 PM PDT 24
Peak memory 214236 kb
Host smart-0a8b094e-ef7a-41f4-b41d-24929c9aaad8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720411736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err
.720411736
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1964457907
Short name T979
Test name
Test status
Simulation time 26145243 ps
CPU time 1.54 seconds
Started Aug 03 04:30:02 PM PDT 24
Finished Aug 03 04:30:04 PM PDT 24
Peak memory 214208 kb
Host smart-86193561-b157-4181-8ab0-44ed224cd803
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964457907 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1964457907
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1989467531
Short name T395
Test name
Test status
Simulation time 53329489 ps
CPU time 0.97 seconds
Started Aug 03 04:29:55 PM PDT 24
Finished Aug 03 04:29:56 PM PDT 24
Peak memory 205824 kb
Host smart-deffebdf-363c-4c5d-9c10-a9c61cb62d4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989467531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1989467531
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1219086438
Short name T940
Test name
Test status
Simulation time 46768848 ps
CPU time 0.91 seconds
Started Aug 03 04:30:01 PM PDT 24
Finished Aug 03 04:30:02 PM PDT 24
Peak memory 205756 kb
Host smart-74655020-d25b-4413-9263-dbe211f67bb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219086438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1219086438
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3375153880
Short name T140
Test name
Test status
Simulation time 42252806 ps
CPU time 2.09 seconds
Started Aug 03 04:29:56 PM PDT 24
Finished Aug 03 04:29:59 PM PDT 24
Peak memory 205876 kb
Host smart-379110d6-78d7-4eba-bded-d5aa27a466da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375153880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.3375153880
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.143681421
Short name T123
Test name
Test status
Simulation time 208944146 ps
CPU time 4.21 seconds
Started Aug 03 04:29:50 PM PDT 24
Finished Aug 03 04:29:54 PM PDT 24
Peak memory 214524 kb
Host smart-76f281a1-2be8-4592-9886-9f81fc040093
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143681421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.143681421
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3572283468
Short name T1057
Test name
Test status
Simulation time 388198860 ps
CPU time 6.27 seconds
Started Aug 03 04:29:55 PM PDT 24
Finished Aug 03 04:30:01 PM PDT 24
Peak memory 214520 kb
Host smart-e36c0b62-cd43-4b97-b634-120e1107cbe5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572283468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3572283468
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3276890334
Short name T1024
Test name
Test status
Simulation time 80339276 ps
CPU time 2.13 seconds
Started Aug 03 04:29:57 PM PDT 24
Finished Aug 03 04:30:00 PM PDT 24
Peak memory 214184 kb
Host smart-e8d706ab-d303-4f08-9053-a58283c93a09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276890334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3276890334
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.4201855372
Short name T163
Test name
Test status
Simulation time 158503685 ps
CPU time 4.79 seconds
Started Aug 03 04:30:00 PM PDT 24
Finished Aug 03 04:30:05 PM PDT 24
Peak memory 214212 kb
Host smart-4bd0e90d-491f-4cdc-928d-815f6431a459
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201855372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.4201855372
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3353811688
Short name T983
Test name
Test status
Simulation time 43553841 ps
CPU time 1.28 seconds
Started Aug 03 04:29:55 PM PDT 24
Finished Aug 03 04:29:57 PM PDT 24
Peak memory 205988 kb
Host smart-cf3b44b2-10ab-4b2c-adee-4e13a23d62de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353811688 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3353811688
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.185184060
Short name T138
Test name
Test status
Simulation time 206457881 ps
CPU time 1.06 seconds
Started Aug 03 04:29:56 PM PDT 24
Finished Aug 03 04:29:57 PM PDT 24
Peak memory 206216 kb
Host smart-07d275e2-4c6e-4253-8e4d-52f44f22d251
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185184060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.185184060
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.4233827226
Short name T994
Test name
Test status
Simulation time 8007648 ps
CPU time 0.71 seconds
Started Aug 03 04:30:01 PM PDT 24
Finished Aug 03 04:30:02 PM PDT 24
Peak memory 205704 kb
Host smart-5a7d2504-b322-4011-b78a-a0391f36a985
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233827226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.4233827226
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1846977892
Short name T985
Test name
Test status
Simulation time 292048750 ps
CPU time 3.19 seconds
Started Aug 03 04:30:01 PM PDT 24
Finished Aug 03 04:30:05 PM PDT 24
Peak memory 206104 kb
Host smart-5a53ab9e-7bea-4360-a0e7-5c2f60f158b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846977892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1846977892
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3087324847
Short name T925
Test name
Test status
Simulation time 158560935 ps
CPU time 1.58 seconds
Started Aug 03 04:30:01 PM PDT 24
Finished Aug 03 04:30:03 PM PDT 24
Peak memory 214576 kb
Host smart-9302583d-8eea-43e2-9fcb-f0561841a02e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087324847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3087324847
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1252616919
Short name T1084
Test name
Test status
Simulation time 74976583 ps
CPU time 3.64 seconds
Started Aug 03 04:29:57 PM PDT 24
Finished Aug 03 04:30:01 PM PDT 24
Peak memory 214548 kb
Host smart-4aa205ba-7ed6-4f9e-9b1a-608e8ca63b0d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252616919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1252616919
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2877312773
Short name T950
Test name
Test status
Simulation time 27652581 ps
CPU time 1.55 seconds
Started Aug 03 04:29:56 PM PDT 24
Finished Aug 03 04:29:57 PM PDT 24
Peak memory 214280 kb
Host smart-1806fab4-8d78-43b9-b235-1fdb01602e50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877312773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2877312773
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2036701132
Short name T929
Test name
Test status
Simulation time 378668522 ps
CPU time 9.97 seconds
Started Aug 03 04:29:26 PM PDT 24
Finished Aug 03 04:29:36 PM PDT 24
Peak memory 206048 kb
Host smart-94d862d3-9752-47bb-9a82-990d4b20d37f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036701132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2
036701132
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3189306274
Short name T1056
Test name
Test status
Simulation time 1003372188 ps
CPU time 14.6 seconds
Started Aug 03 04:29:33 PM PDT 24
Finished Aug 03 04:29:48 PM PDT 24
Peak memory 206080 kb
Host smart-fe8d1731-e96d-46cd-8fcf-82479be05510
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189306274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
189306274
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3399299733
Short name T969
Test name
Test status
Simulation time 58058584 ps
CPU time 1.16 seconds
Started Aug 03 04:29:35 PM PDT 24
Finished Aug 03 04:29:37 PM PDT 24
Peak memory 205952 kb
Host smart-3e81ef77-806d-45ae-909d-5f0f25800631
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399299733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
399299733
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.831177346
Short name T974
Test name
Test status
Simulation time 15650684 ps
CPU time 1.32 seconds
Started Aug 03 04:29:27 PM PDT 24
Finished Aug 03 04:29:28 PM PDT 24
Peak memory 214376 kb
Host smart-efef91a4-f8f6-4c1c-aedf-53a8c24140a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831177346 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.831177346
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.137264943
Short name T1018
Test name
Test status
Simulation time 23581963 ps
CPU time 1.09 seconds
Started Aug 03 04:29:34 PM PDT 24
Finished Aug 03 04:29:36 PM PDT 24
Peak memory 205952 kb
Host smart-6e8dca89-c16a-4b3d-a18b-62f67f4eaff7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137264943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.137264943
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.572556653
Short name T1053
Test name
Test status
Simulation time 16434719 ps
CPU time 0.73 seconds
Started Aug 03 04:29:26 PM PDT 24
Finished Aug 03 04:29:27 PM PDT 24
Peak memory 205776 kb
Host smart-dd37fe3b-806b-4a92-91f7-7bb9c3c61026
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572556653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.572556653
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1182953532
Short name T1060
Test name
Test status
Simulation time 657703554 ps
CPU time 1.89 seconds
Started Aug 03 04:29:34 PM PDT 24
Finished Aug 03 04:29:36 PM PDT 24
Peak memory 205956 kb
Host smart-fb50004a-d3b0-4104-9ce0-68932557954d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182953532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1182953532
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.459652425
Short name T992
Test name
Test status
Simulation time 157593476 ps
CPU time 2.52 seconds
Started Aug 03 04:29:29 PM PDT 24
Finished Aug 03 04:29:32 PM PDT 24
Peak memory 214576 kb
Host smart-a39be3ba-5301-4e97-bec2-b32379943a94
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459652425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.459652425
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1523930996
Short name T120
Test name
Test status
Simulation time 176417591 ps
CPU time 6.53 seconds
Started Aug 03 04:29:28 PM PDT 24
Finished Aug 03 04:29:34 PM PDT 24
Peak memory 214548 kb
Host smart-21d2b21f-aae3-48e8-9c87-28ab4ce75d2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523930996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1523930996
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.4040002017
Short name T981
Test name
Test status
Simulation time 472460316 ps
CPU time 2.44 seconds
Started Aug 03 04:29:27 PM PDT 24
Finished Aug 03 04:29:30 PM PDT 24
Peak memory 222380 kb
Host smart-e404eb8d-a02f-429d-96d4-9a2dae9729c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040002017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.4040002017
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2001387641
Short name T165
Test name
Test status
Simulation time 226850782 ps
CPU time 3.53 seconds
Started Aug 03 04:29:38 PM PDT 24
Finished Aug 03 04:29:41 PM PDT 24
Peak memory 214096 kb
Host smart-ff697c33-9abb-4570-be84-492270c64b7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001387641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2001387641
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.4140313914
Short name T952
Test name
Test status
Simulation time 28446118 ps
CPU time 0.72 seconds
Started Aug 03 04:29:53 PM PDT 24
Finished Aug 03 04:29:54 PM PDT 24
Peak memory 205792 kb
Host smart-72ed52f4-0518-4be1-a20c-5da093e6c38c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140313914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.4140313914
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2722306830
Short name T1040
Test name
Test status
Simulation time 18274825 ps
CPU time 0.74 seconds
Started Aug 03 04:29:57 PM PDT 24
Finished Aug 03 04:29:57 PM PDT 24
Peak memory 205756 kb
Host smart-a404c2ab-8a4a-415f-a61b-2d1a51897475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722306830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2722306830
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.446088143
Short name T1013
Test name
Test status
Simulation time 9612372 ps
CPU time 0.8 seconds
Started Aug 03 04:30:05 PM PDT 24
Finished Aug 03 04:30:06 PM PDT 24
Peak memory 205840 kb
Host smart-c675d4c6-f501-4cd0-967e-f07a9f765272
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446088143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.446088143
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3171976992
Short name T918
Test name
Test status
Simulation time 16669065 ps
CPU time 0.7 seconds
Started Aug 03 04:30:00 PM PDT 24
Finished Aug 03 04:30:01 PM PDT 24
Peak memory 205792 kb
Host smart-d729dd4f-e85a-4525-9b59-18318b2735f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171976992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3171976992
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3404694172
Short name T923
Test name
Test status
Simulation time 10908251 ps
CPU time 0.77 seconds
Started Aug 03 04:29:59 PM PDT 24
Finished Aug 03 04:29:59 PM PDT 24
Peak memory 205784 kb
Host smart-59f8a365-01e6-4899-9587-2e981d9d4829
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404694172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3404694172
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3075956111
Short name T1015
Test name
Test status
Simulation time 25584372 ps
CPU time 0.79 seconds
Started Aug 03 04:29:54 PM PDT 24
Finished Aug 03 04:29:55 PM PDT 24
Peak memory 205740 kb
Host smart-5a065916-d3df-4f8d-afd4-6d91dc082cd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075956111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3075956111
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1284416995
Short name T1074
Test name
Test status
Simulation time 16757197 ps
CPU time 0.7 seconds
Started Aug 03 04:29:55 PM PDT 24
Finished Aug 03 04:29:56 PM PDT 24
Peak memory 205800 kb
Host smart-3ff24932-4f72-40a4-b638-5b9922ca0199
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284416995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1284416995
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.720103464
Short name T914
Test name
Test status
Simulation time 11442025 ps
CPU time 0.71 seconds
Started Aug 03 04:29:55 PM PDT 24
Finished Aug 03 04:29:56 PM PDT 24
Peak memory 205696 kb
Host smart-ca23248f-b900-4c67-972d-851c87875865
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720103464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.720103464
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3712719360
Short name T915
Test name
Test status
Simulation time 21386989 ps
CPU time 0.76 seconds
Started Aug 03 04:29:55 PM PDT 24
Finished Aug 03 04:29:56 PM PDT 24
Peak memory 205756 kb
Host smart-86288b4b-bdec-4caa-bc2f-73105f60d543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712719360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3712719360
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3134532637
Short name T1025
Test name
Test status
Simulation time 50892169 ps
CPU time 0.81 seconds
Started Aug 03 04:30:01 PM PDT 24
Finished Aug 03 04:30:03 PM PDT 24
Peak memory 205780 kb
Host smart-b1f69661-02f9-4968-a49e-e0511c872603
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134532637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3134532637
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.4207740228
Short name T971
Test name
Test status
Simulation time 1890881469 ps
CPU time 14.34 seconds
Started Aug 03 04:29:49 PM PDT 24
Finished Aug 03 04:30:03 PM PDT 24
Peak memory 206016 kb
Host smart-58d2a89f-ea3c-4f13-b72b-4f57d1d2f63a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207740228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.4
207740228
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1546217488
Short name T1001
Test name
Test status
Simulation time 678524130 ps
CPU time 9.38 seconds
Started Aug 03 04:29:27 PM PDT 24
Finished Aug 03 04:29:36 PM PDT 24
Peak memory 206000 kb
Host smart-c6449a27-949e-4f3e-885a-0d80e2b15fb3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546217488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
546217488
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1644769878
Short name T1029
Test name
Test status
Simulation time 97557413 ps
CPU time 1.11 seconds
Started Aug 03 04:29:40 PM PDT 24
Finished Aug 03 04:29:42 PM PDT 24
Peak memory 206368 kb
Host smart-94118684-583b-455a-b46a-29d4885bdf49
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644769878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
644769878
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2155268433
Short name T1083
Test name
Test status
Simulation time 155898482 ps
CPU time 1.25 seconds
Started Aug 03 04:29:48 PM PDT 24
Finished Aug 03 04:29:50 PM PDT 24
Peak memory 214332 kb
Host smart-0d0acd22-c9b8-4203-9cca-c0a9471eac89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155268433 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2155268433
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3526252092
Short name T977
Test name
Test status
Simulation time 51456335 ps
CPU time 1.46 seconds
Started Aug 03 04:29:26 PM PDT 24
Finished Aug 03 04:29:27 PM PDT 24
Peak memory 206064 kb
Host smart-c07e9f00-083a-40fe-9ec6-806cfcdab6a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526252092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3526252092
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.161215036
Short name T954
Test name
Test status
Simulation time 48225832 ps
CPU time 0.83 seconds
Started Aug 03 04:29:30 PM PDT 24
Finished Aug 03 04:29:31 PM PDT 24
Peak memory 205796 kb
Host smart-2d9231a1-0933-46bc-b719-c55aa743e945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161215036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.161215036
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.400966299
Short name T139
Test name
Test status
Simulation time 108240325 ps
CPU time 3.68 seconds
Started Aug 03 04:29:26 PM PDT 24
Finished Aug 03 04:29:30 PM PDT 24
Peak memory 205920 kb
Host smart-6d857664-2679-4842-817a-640e52449e8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400966299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.400966299
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3466407825
Short name T1006
Test name
Test status
Simulation time 110848446 ps
CPU time 1.57 seconds
Started Aug 03 04:29:31 PM PDT 24
Finished Aug 03 04:29:33 PM PDT 24
Peak memory 214480 kb
Host smart-5ea990b8-c50b-4d0a-abd4-85f9880cbd71
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466407825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3466407825
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2012359529
Short name T1067
Test name
Test status
Simulation time 208613403 ps
CPU time 7.1 seconds
Started Aug 03 04:29:47 PM PDT 24
Finished Aug 03 04:29:54 PM PDT 24
Peak memory 214428 kb
Host smart-0a91cc45-038e-44fd-9bfa-60fa69c35d02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012359529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2012359529
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3739662612
Short name T1023
Test name
Test status
Simulation time 1440077497 ps
CPU time 6.04 seconds
Started Aug 03 04:29:51 PM PDT 24
Finished Aug 03 04:29:57 PM PDT 24
Peak memory 214324 kb
Host smart-b092e84a-ca63-40f7-a12e-e433996aaec5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739662612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3739662612
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.50743281
Short name T1077
Test name
Test status
Simulation time 42296890 ps
CPU time 0.75 seconds
Started Aug 03 04:29:58 PM PDT 24
Finished Aug 03 04:29:59 PM PDT 24
Peak memory 206084 kb
Host smart-c37c56e5-ae77-4854-b24a-47dad826dd46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50743281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.50743281
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.876145275
Short name T1010
Test name
Test status
Simulation time 63722210 ps
CPU time 0.7 seconds
Started Aug 03 04:29:58 PM PDT 24
Finished Aug 03 04:29:59 PM PDT 24
Peak memory 205760 kb
Host smart-822b9407-a843-4afd-994b-1a5d20156c4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876145275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.876145275
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2522369200
Short name T1028
Test name
Test status
Simulation time 41818665 ps
CPU time 0.69 seconds
Started Aug 03 04:30:06 PM PDT 24
Finished Aug 03 04:30:07 PM PDT 24
Peak memory 205720 kb
Host smart-1bee4f05-97bd-4942-9f6a-07c5795b7839
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522369200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2522369200
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2549698663
Short name T1026
Test name
Test status
Simulation time 20794806 ps
CPU time 0.86 seconds
Started Aug 03 04:29:55 PM PDT 24
Finished Aug 03 04:29:56 PM PDT 24
Peak memory 205764 kb
Host smart-ffc35b89-1481-45eb-bdfa-792ae91bd064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549698663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2549698663
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3794722792
Short name T1038
Test name
Test status
Simulation time 12381454 ps
CPU time 0.73 seconds
Started Aug 03 04:30:04 PM PDT 24
Finished Aug 03 04:30:04 PM PDT 24
Peak memory 205792 kb
Host smart-249f3a8b-139b-4fe1-bda7-0b7da8a5e0d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794722792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3794722792
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2983759876
Short name T913
Test name
Test status
Simulation time 22537589 ps
CPU time 0.74 seconds
Started Aug 03 04:29:58 PM PDT 24
Finished Aug 03 04:29:59 PM PDT 24
Peak memory 205820 kb
Host smart-643ea1dc-110e-4410-8a99-27b14237fea6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983759876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2983759876
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2023819861
Short name T933
Test name
Test status
Simulation time 13595541 ps
CPU time 0.71 seconds
Started Aug 03 04:30:01 PM PDT 24
Finished Aug 03 04:30:02 PM PDT 24
Peak memory 205780 kb
Host smart-f786ae50-06ef-4699-a4d8-2502800d42ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023819861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2023819861
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1549260794
Short name T1059
Test name
Test status
Simulation time 147090359 ps
CPU time 0.82 seconds
Started Aug 03 04:29:58 PM PDT 24
Finished Aug 03 04:29:59 PM PDT 24
Peak memory 205808 kb
Host smart-a2b6c215-1330-4514-b2f1-fd1116707efa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549260794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1549260794
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3182352036
Short name T1051
Test name
Test status
Simulation time 12154412 ps
CPU time 0.71 seconds
Started Aug 03 04:29:57 PM PDT 24
Finished Aug 03 04:29:58 PM PDT 24
Peak memory 205748 kb
Host smart-7b003703-90f5-4051-b506-19e35bf7787f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182352036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3182352036
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.125894268
Short name T1070
Test name
Test status
Simulation time 97389779 ps
CPU time 0.73 seconds
Started Aug 03 04:29:56 PM PDT 24
Finished Aug 03 04:29:57 PM PDT 24
Peak memory 205776 kb
Host smart-5d9d9695-11ed-47f1-83c7-e777405c848b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125894268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.125894268
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1567516810
Short name T959
Test name
Test status
Simulation time 1011253803 ps
CPU time 15.5 seconds
Started Aug 03 04:29:36 PM PDT 24
Finished Aug 03 04:29:52 PM PDT 24
Peak memory 205900 kb
Host smart-edcfdb84-3d4a-4e64-bfc6-1370db49e2d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567516810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
567516810
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2634923103
Short name T1039
Test name
Test status
Simulation time 274280302 ps
CPU time 7.31 seconds
Started Aug 03 04:29:35 PM PDT 24
Finished Aug 03 04:29:43 PM PDT 24
Peak memory 206016 kb
Host smart-0c31a847-e071-4b80-bd28-038845c11e7e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634923103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
634923103
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3309672142
Short name T930
Test name
Test status
Simulation time 14678843 ps
CPU time 1.17 seconds
Started Aug 03 04:29:39 PM PDT 24
Finished Aug 03 04:29:40 PM PDT 24
Peak memory 205928 kb
Host smart-38845a44-4422-4186-87cd-d0fdfa7c4430
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309672142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
309672142
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.4169994310
Short name T1081
Test name
Test status
Simulation time 72353228 ps
CPU time 1.88 seconds
Started Aug 03 04:29:35 PM PDT 24
Finished Aug 03 04:29:37 PM PDT 24
Peak memory 214260 kb
Host smart-7463214a-ef5d-4148-82d6-a3ba02a081ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169994310 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.4169994310
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2846337504
Short name T1055
Test name
Test status
Simulation time 20468403 ps
CPU time 0.89 seconds
Started Aug 03 04:29:47 PM PDT 24
Finished Aug 03 04:29:48 PM PDT 24
Peak memory 205844 kb
Host smart-8d306a8e-0f9a-4072-ab3d-fccb2cde3748
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846337504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2846337504
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.860509631
Short name T1054
Test name
Test status
Simulation time 34299222 ps
CPU time 0.81 seconds
Started Aug 03 04:29:36 PM PDT 24
Finished Aug 03 04:29:37 PM PDT 24
Peak memory 205668 kb
Host smart-34539631-07da-400d-b6b8-becf703c7f01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860509631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.860509631
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.493407491
Short name T137
Test name
Test status
Simulation time 61169783 ps
CPU time 2.49 seconds
Started Aug 03 04:29:37 PM PDT 24
Finished Aug 03 04:29:40 PM PDT 24
Peak memory 206040 kb
Host smart-72ebee89-1026-4669-a760-cdfbcac66dc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493407491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sam
e_csr_outstanding.493407491
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2744233449
Short name T124
Test name
Test status
Simulation time 184048837 ps
CPU time 3.3 seconds
Started Aug 03 04:29:25 PM PDT 24
Finished Aug 03 04:29:29 PM PDT 24
Peak memory 214500 kb
Host smart-8c563da0-9f65-4d44-b2db-309664551aaa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744233449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2744233449
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1579941329
Short name T1020
Test name
Test status
Simulation time 331291207 ps
CPU time 7.89 seconds
Started Aug 03 04:29:26 PM PDT 24
Finished Aug 03 04:29:34 PM PDT 24
Peak memory 214512 kb
Host smart-7eadce96-8bfa-4e36-83be-ff1bd1a48db5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579941329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1579941329
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.214605271
Short name T1058
Test name
Test status
Simulation time 179717400 ps
CPU time 3.3 seconds
Started Aug 03 04:29:51 PM PDT 24
Finished Aug 03 04:29:55 PM PDT 24
Peak memory 214304 kb
Host smart-4e5acbba-d869-46bc-95dc-5b14eab9bc5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214605271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.214605271
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3292515093
Short name T966
Test name
Test status
Simulation time 36490521 ps
CPU time 0.75 seconds
Started Aug 03 04:30:01 PM PDT 24
Finished Aug 03 04:30:02 PM PDT 24
Peak memory 205848 kb
Host smart-dd77ce57-02ed-4ac6-93b2-b3b779b5616a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292515093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3292515093
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.804660060
Short name T1005
Test name
Test status
Simulation time 37313104 ps
CPU time 0.69 seconds
Started Aug 03 04:29:55 PM PDT 24
Finished Aug 03 04:29:56 PM PDT 24
Peak memory 205824 kb
Host smart-72a74570-14d6-4efd-8285-5b53117750de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804660060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.804660060
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3536749563
Short name T1064
Test name
Test status
Simulation time 22334818 ps
CPU time 0.75 seconds
Started Aug 03 04:30:00 PM PDT 24
Finished Aug 03 04:30:01 PM PDT 24
Peak memory 205732 kb
Host smart-bdac6203-c25b-42fc-999f-8905a350393b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536749563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3536749563
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3016860153
Short name T947
Test name
Test status
Simulation time 10930725 ps
CPU time 0.7 seconds
Started Aug 03 04:30:02 PM PDT 24
Finished Aug 03 04:30:03 PM PDT 24
Peak memory 205844 kb
Host smart-425c9581-2f48-4560-af23-bbd0d7ceeccf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016860153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3016860153
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.4187307453
Short name T1034
Test name
Test status
Simulation time 18715020 ps
CPU time 0.66 seconds
Started Aug 03 04:30:01 PM PDT 24
Finished Aug 03 04:30:02 PM PDT 24
Peak memory 205816 kb
Host smart-c4bd9922-37dc-4094-9eab-33a45f1e3476
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187307453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.4187307453
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.51995010
Short name T968
Test name
Test status
Simulation time 12961146 ps
CPU time 0.79 seconds
Started Aug 03 04:30:02 PM PDT 24
Finished Aug 03 04:30:03 PM PDT 24
Peak memory 205804 kb
Host smart-0be3e95e-b18c-43c0-8779-f1b5923423b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51995010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.51995010
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.314084142
Short name T965
Test name
Test status
Simulation time 10204904 ps
CPU time 0.81 seconds
Started Aug 03 04:30:01 PM PDT 24
Finished Aug 03 04:30:02 PM PDT 24
Peak memory 205740 kb
Host smart-73eb6442-c491-4b7f-a062-a8be108b8a68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314084142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.314084142
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.160940320
Short name T939
Test name
Test status
Simulation time 14988250 ps
CPU time 0.89 seconds
Started Aug 03 04:29:59 PM PDT 24
Finished Aug 03 04:30:00 PM PDT 24
Peak memory 205976 kb
Host smart-fe10222e-5a8c-4af0-a15a-bf9621ab8414
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160940320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.160940320
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2994625247
Short name T1008
Test name
Test status
Simulation time 8591971 ps
CPU time 0.69 seconds
Started Aug 03 04:30:02 PM PDT 24
Finished Aug 03 04:30:03 PM PDT 24
Peak memory 205820 kb
Host smart-cf20fad0-1b8b-4c78-acdb-5ff0161d6715
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994625247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2994625247
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.708515544
Short name T1042
Test name
Test status
Simulation time 31099827 ps
CPU time 0.76 seconds
Started Aug 03 04:30:00 PM PDT 24
Finished Aug 03 04:30:01 PM PDT 24
Peak memory 205788 kb
Host smart-4b723b9a-24d6-47ef-8b13-194ac42d2fc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708515544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.708515544
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1514667898
Short name T987
Test name
Test status
Simulation time 69196634 ps
CPU time 2.49 seconds
Started Aug 03 04:29:42 PM PDT 24
Finished Aug 03 04:29:45 PM PDT 24
Peak memory 214216 kb
Host smart-ae68521a-a029-49af-9398-efc3d0501668
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514667898 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1514667898
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.516672067
Short name T143
Test name
Test status
Simulation time 31370563 ps
CPU time 1.63 seconds
Started Aug 03 04:29:48 PM PDT 24
Finished Aug 03 04:29:50 PM PDT 24
Peak memory 206024 kb
Host smart-b49287fc-9c4d-4231-a209-7bc13244b8be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516672067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.516672067
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3577244884
Short name T1079
Test name
Test status
Simulation time 13879266 ps
CPU time 0.85 seconds
Started Aug 03 04:29:36 PM PDT 24
Finished Aug 03 04:29:36 PM PDT 24
Peak memory 205720 kb
Host smart-4bff212a-58c3-4b66-80a7-e4542a0349b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577244884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3577244884
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1646753253
Short name T1019
Test name
Test status
Simulation time 46830399 ps
CPU time 2.53 seconds
Started Aug 03 04:29:50 PM PDT 24
Finished Aug 03 04:29:53 PM PDT 24
Peak memory 205948 kb
Host smart-34bf49d1-0431-403a-bdc6-155c7e22a2d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646753253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.1646753253
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.567494091
Short name T1031
Test name
Test status
Simulation time 172688910 ps
CPU time 2 seconds
Started Aug 03 04:29:40 PM PDT 24
Finished Aug 03 04:29:42 PM PDT 24
Peak memory 214540 kb
Host smart-e0931456-338c-4e8e-a8fe-cd551eaa9a1c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567494091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.567494091
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1357731147
Short name T1071
Test name
Test status
Simulation time 693046296 ps
CPU time 3.57 seconds
Started Aug 03 04:29:51 PM PDT 24
Finished Aug 03 04:29:54 PM PDT 24
Peak memory 214188 kb
Host smart-1d8eb270-44ed-4e09-adae-6156f4a78901
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357731147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1357731147
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3545206939
Short name T1004
Test name
Test status
Simulation time 250405800 ps
CPU time 2.59 seconds
Started Aug 03 04:29:40 PM PDT 24
Finished Aug 03 04:29:43 PM PDT 24
Peak memory 216368 kb
Host smart-00d3f1e8-b4e7-408e-bded-d99aa5e3d6fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545206939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3545206939
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3359785602
Short name T169
Test name
Test status
Simulation time 169287992 ps
CPU time 2.95 seconds
Started Aug 03 04:29:49 PM PDT 24
Finished Aug 03 04:29:52 PM PDT 24
Peak memory 214244 kb
Host smart-114b0ce4-a3ce-4a5b-a026-5707d324039d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359785602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3359785602
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.51705528
Short name T970
Test name
Test status
Simulation time 65482971 ps
CPU time 1.1 seconds
Started Aug 03 04:29:48 PM PDT 24
Finished Aug 03 04:29:49 PM PDT 24
Peak memory 206048 kb
Host smart-2cd9d9d8-99e5-48c9-b494-7e88ad1fa2f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51705528 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.51705528
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2468590812
Short name T960
Test name
Test status
Simulation time 29259132 ps
CPU time 1.34 seconds
Started Aug 03 04:29:34 PM PDT 24
Finished Aug 03 04:29:35 PM PDT 24
Peak memory 205996 kb
Host smart-750ef86e-b83e-4d3d-b212-d0c55c83c50a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468590812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.2468590812
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.158431470
Short name T978
Test name
Test status
Simulation time 23075090 ps
CPU time 0.85 seconds
Started Aug 03 04:29:45 PM PDT 24
Finished Aug 03 04:29:46 PM PDT 24
Peak memory 205812 kb
Host smart-8bdfa7ea-895a-48ee-876a-b60fa5494336
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158431470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.158431470
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1079775731
Short name T973
Test name
Test status
Simulation time 66507911 ps
CPU time 1.57 seconds
Started Aug 03 04:29:52 PM PDT 24
Finished Aug 03 04:29:54 PM PDT 24
Peak memory 206024 kb
Host smart-056371e3-b4ac-4ab2-b69e-cd6d09219f76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079775731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1079775731
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3464846051
Short name T955
Test name
Test status
Simulation time 231508381 ps
CPU time 1.7 seconds
Started Aug 03 04:29:35 PM PDT 24
Finished Aug 03 04:29:37 PM PDT 24
Peak memory 214416 kb
Host smart-473295ec-3154-45aa-a758-6e20c3203b00
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464846051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3464846051
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3648414660
Short name T956
Test name
Test status
Simulation time 463853837 ps
CPU time 9.92 seconds
Started Aug 03 04:29:35 PM PDT 24
Finished Aug 03 04:29:45 PM PDT 24
Peak memory 221064 kb
Host smart-7dd846f3-ff30-4199-a3ae-e3c22371ecaf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648414660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3648414660
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2049949648
Short name T948
Test name
Test status
Simulation time 160794542 ps
CPU time 5.21 seconds
Started Aug 03 04:29:44 PM PDT 24
Finished Aug 03 04:29:49 PM PDT 24
Peak memory 217384 kb
Host smart-f189a22b-218f-40cd-acf7-9b5c89be4ea5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049949648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2049949648
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2088639708
Short name T921
Test name
Test status
Simulation time 564765288 ps
CPU time 4.08 seconds
Started Aug 03 04:29:48 PM PDT 24
Finished Aug 03 04:29:52 PM PDT 24
Peak memory 205928 kb
Host smart-cd8b7bb0-de2e-4ec3-9535-03529d353ce9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088639708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2088639708
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3703780346
Short name T1078
Test name
Test status
Simulation time 28456006 ps
CPU time 1.06 seconds
Started Aug 03 04:29:37 PM PDT 24
Finished Aug 03 04:29:38 PM PDT 24
Peak memory 206156 kb
Host smart-59720b36-5564-422c-b70f-e7e01e703949
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703780346 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3703780346
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3429424303
Short name T919
Test name
Test status
Simulation time 28973968 ps
CPU time 1.65 seconds
Started Aug 03 04:29:49 PM PDT 24
Finished Aug 03 04:29:50 PM PDT 24
Peak memory 206020 kb
Host smart-99a51002-90b3-4474-b1d8-719da4cebe32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429424303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3429424303
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.4098825820
Short name T1073
Test name
Test status
Simulation time 11350824 ps
CPU time 0.8 seconds
Started Aug 03 04:29:37 PM PDT 24
Finished Aug 03 04:29:38 PM PDT 24
Peak memory 205820 kb
Host smart-6ad9c77a-45f9-4264-a591-f870843c0ec8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098825820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.4098825820
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2829840804
Short name T1076
Test name
Test status
Simulation time 87998163 ps
CPU time 2.02 seconds
Started Aug 03 04:29:49 PM PDT 24
Finished Aug 03 04:29:51 PM PDT 24
Peak memory 206028 kb
Host smart-9a607d6b-8cdb-4189-95fb-f75728cad10a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829840804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2829840804
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.4040122147
Short name T976
Test name
Test status
Simulation time 196583186 ps
CPU time 3.42 seconds
Started Aug 03 04:29:45 PM PDT 24
Finished Aug 03 04:29:49 PM PDT 24
Peak memory 214676 kb
Host smart-2d9a75c9-d484-422d-80ec-bb6b12308acd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040122147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.4040122147
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2607556189
Short name T126
Test name
Test status
Simulation time 589481247 ps
CPU time 6.28 seconds
Started Aug 03 04:29:46 PM PDT 24
Finished Aug 03 04:29:53 PM PDT 24
Peak memory 220680 kb
Host smart-890fd027-d55c-4db7-b621-f217bcd8b046
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607556189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2607556189
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.4042805137
Short name T984
Test name
Test status
Simulation time 274622404 ps
CPU time 2.8 seconds
Started Aug 03 04:29:35 PM PDT 24
Finished Aug 03 04:29:38 PM PDT 24
Peak memory 215460 kb
Host smart-aa307709-a6a4-490e-bb58-4e352af9b7fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042805137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.4042805137
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2395709710
Short name T1080
Test name
Test status
Simulation time 497411804 ps
CPU time 4.06 seconds
Started Aug 03 04:29:37 PM PDT 24
Finished Aug 03 04:29:41 PM PDT 24
Peak memory 214208 kb
Host smart-eb35f856-ce3f-4871-9de5-97cbe3103a00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395709710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2395709710
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2289005675
Short name T1045
Test name
Test status
Simulation time 85575051 ps
CPU time 2.02 seconds
Started Aug 03 04:29:49 PM PDT 24
Finished Aug 03 04:29:51 PM PDT 24
Peak memory 214312 kb
Host smart-685e4215-863f-4f98-a648-e4105b8f63a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289005675 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2289005675
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.830135787
Short name T1014
Test name
Test status
Simulation time 91158350 ps
CPU time 1.01 seconds
Started Aug 03 04:30:00 PM PDT 24
Finished Aug 03 04:30:01 PM PDT 24
Peak memory 205808 kb
Host smart-61f0e0f3-1f23-4bce-a580-7d2f7d128dcc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830135787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.830135787
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1198723987
Short name T927
Test name
Test status
Simulation time 36172644 ps
CPU time 0.83 seconds
Started Aug 03 04:29:41 PM PDT 24
Finished Aug 03 04:29:42 PM PDT 24
Peak memory 205792 kb
Host smart-d41806a8-577a-4620-8928-5f6fc47f325b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198723987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1198723987
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.201905657
Short name T989
Test name
Test status
Simulation time 139328896 ps
CPU time 1.98 seconds
Started Aug 03 04:29:41 PM PDT 24
Finished Aug 03 04:29:44 PM PDT 24
Peak memory 205944 kb
Host smart-1719c4ac-09bd-4206-b3e8-d4a7a96401fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201905657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.201905657
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.116206566
Short name T936
Test name
Test status
Simulation time 296733406 ps
CPU time 2.61 seconds
Started Aug 03 04:29:48 PM PDT 24
Finished Aug 03 04:29:51 PM PDT 24
Peak memory 214492 kb
Host smart-c62bbb53-dc1a-4f0d-a973-4521153dd577
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116206566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow
_reg_errors.116206566
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3006609197
Short name T964
Test name
Test status
Simulation time 146564371 ps
CPU time 3.67 seconds
Started Aug 03 04:29:35 PM PDT 24
Finished Aug 03 04:29:39 PM PDT 24
Peak memory 214680 kb
Host smart-9dfc9058-8714-425d-8b2a-2feaa21cf5da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006609197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3006609197
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3163181835
Short name T1000
Test name
Test status
Simulation time 379769461 ps
CPU time 2.58 seconds
Started Aug 03 04:29:37 PM PDT 24
Finished Aug 03 04:29:39 PM PDT 24
Peak memory 214268 kb
Host smart-77d00ce3-2ece-4501-a068-c27352db2fab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163181835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3163181835
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.783750050
Short name T168
Test name
Test status
Simulation time 166738199 ps
CPU time 2.59 seconds
Started Aug 03 04:29:38 PM PDT 24
Finished Aug 03 04:29:41 PM PDT 24
Peak memory 214200 kb
Host smart-11617be7-23fc-45bf-82a1-5da0bfff5722
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783750050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
783750050
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3353523930
Short name T926
Test name
Test status
Simulation time 20139326 ps
CPU time 1.23 seconds
Started Aug 03 04:29:43 PM PDT 24
Finished Aug 03 04:29:44 PM PDT 24
Peak memory 214320 kb
Host smart-f3fc158f-015b-4d7f-96bb-beb3bac5d0f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353523930 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.3353523930
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.178571924
Short name T953
Test name
Test status
Simulation time 112310074 ps
CPU time 0.86 seconds
Started Aug 03 04:29:44 PM PDT 24
Finished Aug 03 04:29:45 PM PDT 24
Peak memory 205848 kb
Host smart-31561fb9-6252-4b22-a68d-d294b4e5d0fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178571924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.178571924
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3595661820
Short name T1072
Test name
Test status
Simulation time 40581146 ps
CPU time 0.72 seconds
Started Aug 03 04:29:42 PM PDT 24
Finished Aug 03 04:29:42 PM PDT 24
Peak memory 205768 kb
Host smart-d6e41f93-5794-4d5b-acec-cc193dd193e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595661820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3595661820
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.4121679635
Short name T928
Test name
Test status
Simulation time 126489058 ps
CPU time 2.48 seconds
Started Aug 03 04:29:59 PM PDT 24
Finished Aug 03 04:30:02 PM PDT 24
Peak memory 206000 kb
Host smart-24f43b12-8e7e-47b1-b7c9-39161c8f6bab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121679635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.4121679635
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2983221248
Short name T986
Test name
Test status
Simulation time 288430003 ps
CPU time 1.77 seconds
Started Aug 03 04:29:51 PM PDT 24
Finished Aug 03 04:29:53 PM PDT 24
Peak memory 214004 kb
Host smart-d52b7d5c-fcda-4b0b-a295-c17149291375
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983221248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2983221248
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2597474175
Short name T962
Test name
Test status
Simulation time 1123974648 ps
CPU time 9.24 seconds
Started Aug 03 04:29:53 PM PDT 24
Finished Aug 03 04:30:02 PM PDT 24
Peak memory 214476 kb
Host smart-2d00959d-c009-4e20-9be9-4819ca181819
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597474175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2597474175
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1067925626
Short name T943
Test name
Test status
Simulation time 151113939 ps
CPU time 3.84 seconds
Started Aug 03 04:29:43 PM PDT 24
Finished Aug 03 04:29:47 PM PDT 24
Peak memory 214284 kb
Host smart-4c3c6084-5190-450c-ba13-5293c62dbe33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067925626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1067925626
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3694216999
Short name T1061
Test name
Test status
Simulation time 188071698 ps
CPU time 3.03 seconds
Started Aug 03 04:29:43 PM PDT 24
Finished Aug 03 04:29:46 PM PDT 24
Peak memory 214116 kb
Host smart-ef56b805-5ae4-44a8-9116-0aebbfff1cb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694216999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3694216999
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2247514920
Short name T454
Test name
Test status
Simulation time 35381902 ps
CPU time 0.86 seconds
Started Aug 03 05:23:08 PM PDT 24
Finished Aug 03 05:23:09 PM PDT 24
Peak memory 205924 kb
Host smart-c9428f7a-4aca-450a-8b77-f9c119a8e3a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247514920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2247514920
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2227148239
Short name T904
Test name
Test status
Simulation time 80522742 ps
CPU time 3.43 seconds
Started Aug 03 05:23:07 PM PDT 24
Finished Aug 03 05:23:11 PM PDT 24
Peak memory 215396 kb
Host smart-e930de88-f625-4001-a9b8-a9a45007dcf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2227148239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2227148239
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.215502397
Short name T39
Test name
Test status
Simulation time 182099829 ps
CPU time 1.38 seconds
Started Aug 03 05:23:10 PM PDT 24
Finished Aug 03 05:23:12 PM PDT 24
Peak memory 208588 kb
Host smart-33cefb59-0281-4166-9cdd-5b3cc2b41709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215502397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.215502397
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1593329044
Short name T463
Test name
Test status
Simulation time 45441160 ps
CPU time 2.41 seconds
Started Aug 03 05:23:08 PM PDT 24
Finished Aug 03 05:23:11 PM PDT 24
Peak memory 218364 kb
Host smart-149bc5d3-9de7-4056-958f-5c6c8a5f3a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593329044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1593329044
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2860239497
Short name T59
Test name
Test status
Simulation time 64404054 ps
CPU time 2.5 seconds
Started Aug 03 05:23:13 PM PDT 24
Finished Aug 03 05:23:16 PM PDT 24
Peak memory 208556 kb
Host smart-75709026-c5ec-42c8-bad1-36478a180643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860239497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2860239497
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.3454487786
Short name T647
Test name
Test status
Simulation time 69334022 ps
CPU time 3.39 seconds
Started Aug 03 05:23:08 PM PDT 24
Finished Aug 03 05:23:12 PM PDT 24
Peak memory 214340 kb
Host smart-087d3b7e-ed83-4f0b-b7d4-f4fc3f45ed77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454487786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3454487786
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1782572250
Short name T109
Test name
Test status
Simulation time 236780455 ps
CPU time 7.73 seconds
Started Aug 03 05:23:08 PM PDT 24
Finished Aug 03 05:23:16 PM PDT 24
Peak memory 233432 kb
Host smart-1719dde7-f4be-4dc9-8959-64b93fa26506
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782572250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1782572250
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1467661112
Short name T608
Test name
Test status
Simulation time 3366110926 ps
CPU time 66.09 seconds
Started Aug 03 05:23:07 PM PDT 24
Finished Aug 03 05:24:14 PM PDT 24
Peak memory 208160 kb
Host smart-a728cbaa-7735-41c6-923d-109050d1a117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467661112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1467661112
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.380436340
Short name T810
Test name
Test status
Simulation time 100233524 ps
CPU time 4.64 seconds
Started Aug 03 05:23:08 PM PDT 24
Finished Aug 03 05:23:13 PM PDT 24
Peak memory 208876 kb
Host smart-99ca271c-b96b-4290-929b-4b3c24a4aa1b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380436340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.380436340
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.911321726
Short name T329
Test name
Test status
Simulation time 54676956 ps
CPU time 2.93 seconds
Started Aug 03 05:23:08 PM PDT 24
Finished Aug 03 05:23:11 PM PDT 24
Peak memory 208744 kb
Host smart-b62c530d-54ea-4607-be6d-f5556812d290
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911321726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.911321726
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1481027130
Short name T532
Test name
Test status
Simulation time 361650523 ps
CPU time 8.07 seconds
Started Aug 03 05:23:10 PM PDT 24
Finished Aug 03 05:23:19 PM PDT 24
Peak memory 208756 kb
Host smart-6eb75b64-5486-4845-81af-a62ca155c113
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481027130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1481027130
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2132281578
Short name T828
Test name
Test status
Simulation time 1565989433 ps
CPU time 14.38 seconds
Started Aug 03 05:23:10 PM PDT 24
Finished Aug 03 05:23:24 PM PDT 24
Peak memory 209328 kb
Host smart-775411b4-7bc6-466a-b010-24e904f89685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132281578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2132281578
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.694392323
Short name T435
Test name
Test status
Simulation time 193918771 ps
CPU time 2.46 seconds
Started Aug 03 05:23:08 PM PDT 24
Finished Aug 03 05:23:11 PM PDT 24
Peak memory 208728 kb
Host smart-9ee72e40-54dd-430a-a2df-57cbc1dbe45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694392323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.694392323
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1199428962
Short name T336
Test name
Test status
Simulation time 2999031727 ps
CPU time 67.2 seconds
Started Aug 03 05:23:10 PM PDT 24
Finished Aug 03 05:24:18 PM PDT 24
Peak memory 222488 kb
Host smart-a9070e23-fcb1-454c-8657-3da89ce2877a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199428962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1199428962
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.1945095681
Short name T129
Test name
Test status
Simulation time 1313696561 ps
CPU time 14.01 seconds
Started Aug 03 05:23:10 PM PDT 24
Finished Aug 03 05:23:24 PM PDT 24
Peak memory 222616 kb
Host smart-2b035be6-4ce4-4f37-9775-5c2f649719b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945095681 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.1945095681
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2672774321
Short name T201
Test name
Test status
Simulation time 101652997 ps
CPU time 4.37 seconds
Started Aug 03 05:23:10 PM PDT 24
Finished Aug 03 05:23:14 PM PDT 24
Peak memory 209160 kb
Host smart-d1d81485-3609-440f-862d-50f9da8db4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672774321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2672774321
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2809316710
Short name T719
Test name
Test status
Simulation time 11366087 ps
CPU time 0.85 seconds
Started Aug 03 05:23:15 PM PDT 24
Finished Aug 03 05:23:16 PM PDT 24
Peak memory 205896 kb
Host smart-4e76bcc2-6651-485d-98d9-3e65c149963f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809316710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2809316710
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3386337666
Short name T419
Test name
Test status
Simulation time 31257289 ps
CPU time 2.63 seconds
Started Aug 03 05:23:17 PM PDT 24
Finished Aug 03 05:23:19 PM PDT 24
Peak memory 214264 kb
Host smart-ec3bb506-016b-4db8-8fca-9307ab793177
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3386337666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3386337666
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.643003906
Short name T29
Test name
Test status
Simulation time 193462297 ps
CPU time 3.47 seconds
Started Aug 03 05:23:17 PM PDT 24
Finished Aug 03 05:23:21 PM PDT 24
Peak memory 222696 kb
Host smart-2b623517-0a61-47a2-9bb3-645c1f87cea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643003906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.643003906
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3604194805
Short name T376
Test name
Test status
Simulation time 431298042 ps
CPU time 5.82 seconds
Started Aug 03 05:23:13 PM PDT 24
Finished Aug 03 05:23:19 PM PDT 24
Peak memory 218360 kb
Host smart-87f3d763-599f-43ba-8783-50467967cd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604194805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3604194805
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1248774235
Short name T89
Test name
Test status
Simulation time 85098252 ps
CPU time 3.71 seconds
Started Aug 03 05:23:13 PM PDT 24
Finished Aug 03 05:23:17 PM PDT 24
Peak memory 214420 kb
Host smart-985aac28-2cfe-4c4e-b842-e937b8d3b5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248774235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1248774235
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3942391382
Short name T367
Test name
Test status
Simulation time 37380376 ps
CPU time 2.21 seconds
Started Aug 03 05:23:15 PM PDT 24
Finished Aug 03 05:23:17 PM PDT 24
Peak memory 220968 kb
Host smart-e216080b-1c60-4c8c-87b0-be4ae5157ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942391382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3942391382
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1197626855
Short name T879
Test name
Test status
Simulation time 458077363 ps
CPU time 2.51 seconds
Started Aug 03 05:23:15 PM PDT 24
Finished Aug 03 05:23:17 PM PDT 24
Peak memory 216420 kb
Host smart-adda9d50-2753-4792-b97c-8571b9f711ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197626855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1197626855
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3395182817
Short name T13
Test name
Test status
Simulation time 1268515958 ps
CPU time 7.15 seconds
Started Aug 03 05:23:22 PM PDT 24
Finished Aug 03 05:23:30 PM PDT 24
Peak memory 229380 kb
Host smart-29d8e02d-9c45-4262-b73a-5e9e9fbb2ae1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395182817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3395182817
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3109697058
Short name T193
Test name
Test status
Simulation time 1865421802 ps
CPU time 21.85 seconds
Started Aug 03 05:23:07 PM PDT 24
Finished Aug 03 05:23:29 PM PDT 24
Peak memory 208924 kb
Host smart-d4add01c-5be1-44bf-bc80-f0a2b7a382db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109697058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3109697058
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.821249969
Short name T565
Test name
Test status
Simulation time 85135952 ps
CPU time 3.94 seconds
Started Aug 03 05:23:13 PM PDT 24
Finished Aug 03 05:23:18 PM PDT 24
Peak memory 208948 kb
Host smart-8ba4275d-230e-4848-86bb-57c2393519fd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821249969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.821249969
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1107558033
Short name T842
Test name
Test status
Simulation time 192457316 ps
CPU time 7.46 seconds
Started Aug 03 05:23:09 PM PDT 24
Finished Aug 03 05:23:16 PM PDT 24
Peak memory 208156 kb
Host smart-aa47988a-8850-4794-85aa-c5d5bad9d623
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107558033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1107558033
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2966695033
Short name T569
Test name
Test status
Simulation time 84534251 ps
CPU time 4 seconds
Started Aug 03 05:23:12 PM PDT 24
Finished Aug 03 05:23:16 PM PDT 24
Peak memory 208736 kb
Host smart-cb7fd7c5-2090-4e0c-8fa1-bf8131d67637
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966695033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2966695033
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.824417581
Short name T421
Test name
Test status
Simulation time 620573872 ps
CPU time 5.99 seconds
Started Aug 03 05:23:14 PM PDT 24
Finished Aug 03 05:23:20 PM PDT 24
Peak memory 209008 kb
Host smart-35224e62-c238-4597-8f0c-822d3bb1a093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824417581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.824417581
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2611874433
Short name T653
Test name
Test status
Simulation time 138232811 ps
CPU time 3.47 seconds
Started Aug 03 05:23:13 PM PDT 24
Finished Aug 03 05:23:17 PM PDT 24
Peak memory 208500 kb
Host smart-5ba8b8a4-0c3a-475f-b705-3e5c9a9f4824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611874433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2611874433
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3382382327
Short name T674
Test name
Test status
Simulation time 674436835 ps
CPU time 10.6 seconds
Started Aug 03 05:23:22 PM PDT 24
Finished Aug 03 05:23:33 PM PDT 24
Peak memory 219584 kb
Host smart-0a20d9bb-0401-4711-9081-617055220400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382382327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3382382327
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1723542258
Short name T648
Test name
Test status
Simulation time 83776911 ps
CPU time 3.1 seconds
Started Aug 03 05:23:22 PM PDT 24
Finished Aug 03 05:23:26 PM PDT 24
Peak memory 210036 kb
Host smart-ae44ff74-3177-4c18-a6af-bd6f7d3a4c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723542258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1723542258
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1219222070
Short name T502
Test name
Test status
Simulation time 45499475 ps
CPU time 0.87 seconds
Started Aug 03 05:23:48 PM PDT 24
Finished Aug 03 05:23:49 PM PDT 24
Peak memory 205920 kb
Host smart-124eb102-ebc5-4585-a825-0bb5f173f186
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219222070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1219222070
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1297254013
Short name T144
Test name
Test status
Simulation time 33682117 ps
CPU time 2.68 seconds
Started Aug 03 05:23:43 PM PDT 24
Finished Aug 03 05:23:46 PM PDT 24
Peak memory 215308 kb
Host smart-8e0817b7-a876-4ed1-bbc0-0a62f233489d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1297254013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1297254013
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1801823006
Short name T825
Test name
Test status
Simulation time 83524461 ps
CPU time 1.8 seconds
Started Aug 03 05:23:44 PM PDT 24
Finished Aug 03 05:23:46 PM PDT 24
Peak memory 216372 kb
Host smart-c7fac5bf-5f56-4745-a2e1-89003b890974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801823006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1801823006
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2550240902
Short name T713
Test name
Test status
Simulation time 42305867 ps
CPU time 2.02 seconds
Started Aug 03 05:23:46 PM PDT 24
Finished Aug 03 05:23:48 PM PDT 24
Peak memory 207620 kb
Host smart-c27200c6-01d4-4557-b6e8-98f624cb87cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550240902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2550240902
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1575376302
Short name T288
Test name
Test status
Simulation time 147398915 ps
CPU time 3.72 seconds
Started Aug 03 05:23:46 PM PDT 24
Finished Aug 03 05:23:49 PM PDT 24
Peak memory 214260 kb
Host smart-e0522d7e-a3aa-48d0-a1f3-7063e5f2d6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575376302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1575376302
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3940372154
Short name T668
Test name
Test status
Simulation time 174876694 ps
CPU time 2.78 seconds
Started Aug 03 05:23:42 PM PDT 24
Finished Aug 03 05:23:45 PM PDT 24
Peak memory 209408 kb
Host smart-20ab10bc-8407-4d4e-aa74-165291e23abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940372154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3940372154
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3423664201
Short name T898
Test name
Test status
Simulation time 397052414 ps
CPU time 5.02 seconds
Started Aug 03 05:23:45 PM PDT 24
Finished Aug 03 05:23:51 PM PDT 24
Peak memory 208964 kb
Host smart-e5256fa3-f4ce-45b0-b00c-4d82bb66b718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423664201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3423664201
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2025967658
Short name T721
Test name
Test status
Simulation time 5046951269 ps
CPU time 32.43 seconds
Started Aug 03 05:23:42 PM PDT 24
Finished Aug 03 05:24:15 PM PDT 24
Peak memory 208052 kb
Host smart-08b72fc9-c7a4-47e6-aadc-3fdb08f2331f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025967658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2025967658
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.1648765025
Short name T591
Test name
Test status
Simulation time 504978983 ps
CPU time 5.73 seconds
Started Aug 03 05:23:42 PM PDT 24
Finished Aug 03 05:23:48 PM PDT 24
Peak memory 208944 kb
Host smart-1ebed0db-30e3-435a-8c8c-fd89b0061caf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648765025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1648765025
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2721610323
Short name T624
Test name
Test status
Simulation time 915707841 ps
CPU time 6.79 seconds
Started Aug 03 05:23:42 PM PDT 24
Finished Aug 03 05:23:49 PM PDT 24
Peak memory 207712 kb
Host smart-75e24891-7f44-4379-b972-02c4abd22cf7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721610323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2721610323
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1166795182
Short name T538
Test name
Test status
Simulation time 57703575 ps
CPU time 2.94 seconds
Started Aug 03 05:23:48 PM PDT 24
Finished Aug 03 05:23:51 PM PDT 24
Peak memory 207080 kb
Host smart-3ab382c9-2e61-4f81-9aa3-6c607183746b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166795182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1166795182
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3105416489
Short name T449
Test name
Test status
Simulation time 88613558 ps
CPU time 2.13 seconds
Started Aug 03 05:23:42 PM PDT 24
Finished Aug 03 05:23:45 PM PDT 24
Peak memory 206920 kb
Host smart-7c8fd8cd-8097-400d-9a39-a238e1244638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105416489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3105416489
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1002853844
Short name T677
Test name
Test status
Simulation time 7268686082 ps
CPU time 49.12 seconds
Started Aug 03 05:23:50 PM PDT 24
Finished Aug 03 05:24:39 PM PDT 24
Peak memory 216664 kb
Host smart-f6981f22-00ba-4690-af17-c6b5caabeb15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002853844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1002853844
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.1025818640
Short name T236
Test name
Test status
Simulation time 681190511 ps
CPU time 23.04 seconds
Started Aug 03 05:23:48 PM PDT 24
Finished Aug 03 05:24:11 PM PDT 24
Peak memory 222724 kb
Host smart-eb2f5859-6c56-42b1-a9ae-a4f5878c03e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025818640 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.1025818640
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1519467022
Short name T661
Test name
Test status
Simulation time 1285923048 ps
CPU time 10.08 seconds
Started Aug 03 05:23:43 PM PDT 24
Finished Aug 03 05:23:53 PM PDT 24
Peak memory 218332 kb
Host smart-2d87373a-1a64-4cbf-b361-a9f97ff03d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519467022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1519467022
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.119664952
Short name T887
Test name
Test status
Simulation time 145451967 ps
CPU time 2.13 seconds
Started Aug 03 05:23:57 PM PDT 24
Finished Aug 03 05:23:59 PM PDT 24
Peak memory 210216 kb
Host smart-39862ae7-e349-47e7-9f6f-20a99ca422b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119664952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.119664952
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1135179027
Short name T637
Test name
Test status
Simulation time 30075168 ps
CPU time 0.74 seconds
Started Aug 03 05:23:49 PM PDT 24
Finished Aug 03 05:23:50 PM PDT 24
Peak memory 205924 kb
Host smart-2fbbc64f-c85d-4bf8-a401-13549be58ff5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135179027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1135179027
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.152272540
Short name T714
Test name
Test status
Simulation time 81722861 ps
CPU time 2.04 seconds
Started Aug 03 05:23:53 PM PDT 24
Finished Aug 03 05:23:55 PM PDT 24
Peak memory 208616 kb
Host smart-0bb0de1d-a814-4c8d-b7ee-cb861cdfec47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152272540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.152272540
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1238875931
Short name T846
Test name
Test status
Simulation time 1777459297 ps
CPU time 13.94 seconds
Started Aug 03 05:23:48 PM PDT 24
Finished Aug 03 05:24:02 PM PDT 24
Peak memory 209428 kb
Host smart-d3c276a6-693c-4497-9564-bad8078526a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238875931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1238875931
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.447682875
Short name T88
Test name
Test status
Simulation time 34788639 ps
CPU time 2.7 seconds
Started Aug 03 05:23:49 PM PDT 24
Finished Aug 03 05:23:52 PM PDT 24
Peak memory 222552 kb
Host smart-d22f964a-b9bb-4125-879b-661fa6217f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447682875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.447682875
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.92796198
Short name T707
Test name
Test status
Simulation time 144524579 ps
CPU time 2.98 seconds
Started Aug 03 05:23:49 PM PDT 24
Finished Aug 03 05:23:52 PM PDT 24
Peak memory 222308 kb
Host smart-6d7bf855-d102-4678-9bad-5170b2045999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92796198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.92796198
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3030321202
Short name T348
Test name
Test status
Simulation time 98622200 ps
CPU time 3.62 seconds
Started Aug 03 05:23:48 PM PDT 24
Finished Aug 03 05:23:52 PM PDT 24
Peak memory 214416 kb
Host smart-b790788a-ac42-4357-8b72-36087589bb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030321202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3030321202
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.440686925
Short name T806
Test name
Test status
Simulation time 330550921 ps
CPU time 5.55 seconds
Started Aug 03 05:23:48 PM PDT 24
Finished Aug 03 05:23:54 PM PDT 24
Peak memory 207440 kb
Host smart-8339bb2f-ca22-4c60-a1c6-57d2be38708f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440686925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.440686925
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1382653635
Short name T530
Test name
Test status
Simulation time 116113249 ps
CPU time 3.34 seconds
Started Aug 03 05:23:47 PM PDT 24
Finished Aug 03 05:23:50 PM PDT 24
Peak memory 206876 kb
Host smart-40394060-0fb3-421b-8a63-975ec2e3f07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382653635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1382653635
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3634952792
Short name T204
Test name
Test status
Simulation time 220283761 ps
CPU time 2 seconds
Started Aug 03 05:23:51 PM PDT 24
Finished Aug 03 05:23:53 PM PDT 24
Peak memory 208348 kb
Host smart-ac7b6730-7447-46bc-9b3c-f261b5ff8081
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634952792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3634952792
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.2830174705
Short name T328
Test name
Test status
Simulation time 2449228381 ps
CPU time 11.35 seconds
Started Aug 03 05:23:48 PM PDT 24
Finished Aug 03 05:24:00 PM PDT 24
Peak memory 208488 kb
Host smart-6b2ef5fb-4ef5-45aa-9c8d-0b6e588ee6b5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830174705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.2830174705
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2211641461
Short name T3
Test name
Test status
Simulation time 45508208 ps
CPU time 2.88 seconds
Started Aug 03 05:23:53 PM PDT 24
Finished Aug 03 05:23:56 PM PDT 24
Peak memory 206904 kb
Host smart-3c55f8a0-ed21-442b-a31f-47c22ab215c5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211641461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2211641461
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_smoke.2903874440
Short name T446
Test name
Test status
Simulation time 790693874 ps
CPU time 4.97 seconds
Started Aug 03 05:23:49 PM PDT 24
Finished Aug 03 05:23:54 PM PDT 24
Peak memory 207764 kb
Host smart-646c37bf-64e6-4068-91f9-86d2b8e4fe92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903874440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2903874440
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.2290992212
Short name T176
Test name
Test status
Simulation time 328075510 ps
CPU time 8.28 seconds
Started Aug 03 05:23:51 PM PDT 24
Finished Aug 03 05:23:59 PM PDT 24
Peak memory 219640 kb
Host smart-6bd5efba-b511-400f-b6d9-10c96dc86548
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290992212 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.2290992212
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3247537400
Short name T337
Test name
Test status
Simulation time 218375348 ps
CPU time 3.74 seconds
Started Aug 03 05:23:48 PM PDT 24
Finished Aug 03 05:23:52 PM PDT 24
Peak memory 214252 kb
Host smart-553cdd55-2d8c-42e4-bb52-e92dbe1a45b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247537400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3247537400
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3159206574
Short name T808
Test name
Test status
Simulation time 44550092 ps
CPU time 1.47 seconds
Started Aug 03 05:23:51 PM PDT 24
Finished Aug 03 05:23:52 PM PDT 24
Peak memory 209636 kb
Host smart-272a68b5-d35c-4660-9f67-68d02156d060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159206574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3159206574
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2108772863
Short name T812
Test name
Test status
Simulation time 10961563 ps
CPU time 0.73 seconds
Started Aug 03 05:23:56 PM PDT 24
Finished Aug 03 05:23:57 PM PDT 24
Peak memory 205952 kb
Host smart-9ef59448-a4f3-4ade-83c8-461653e6bd2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108772863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2108772863
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.192398042
Short name T351
Test name
Test status
Simulation time 111092954 ps
CPU time 3.78 seconds
Started Aug 03 05:23:48 PM PDT 24
Finished Aug 03 05:23:52 PM PDT 24
Peak memory 215196 kb
Host smart-10eac312-4c45-4e02-a068-ed04e2cc883f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=192398042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.192398042
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2900189391
Short name T215
Test name
Test status
Simulation time 571116049 ps
CPU time 10.73 seconds
Started Aug 03 05:24:00 PM PDT 24
Finished Aug 03 05:24:11 PM PDT 24
Peak memory 220036 kb
Host smart-04a07be1-ba01-4e38-9c07-03dfa4e4643e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900189391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2900189391
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.368652356
Short name T705
Test name
Test status
Simulation time 723255454 ps
CPU time 4.71 seconds
Started Aug 03 05:23:49 PM PDT 24
Finished Aug 03 05:23:54 PM PDT 24
Peak memory 218256 kb
Host smart-6fef6b94-a585-4517-902f-400262b1cf47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368652356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.368652356
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2523803509
Short name T804
Test name
Test status
Simulation time 158498430 ps
CPU time 4.55 seconds
Started Aug 03 05:23:53 PM PDT 24
Finished Aug 03 05:23:58 PM PDT 24
Peak memory 221108 kb
Host smart-3453a64b-e8bd-4c6d-a9ac-8495e160d79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523803509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2523803509
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1997200390
Short name T844
Test name
Test status
Simulation time 68538260 ps
CPU time 2.59 seconds
Started Aug 03 05:23:48 PM PDT 24
Finished Aug 03 05:23:50 PM PDT 24
Peak memory 221592 kb
Host smart-686cee13-d95b-4afe-acc2-27123612c93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997200390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1997200390
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_random.2651302127
Short name T459
Test name
Test status
Simulation time 191379363 ps
CPU time 3.99 seconds
Started Aug 03 05:23:53 PM PDT 24
Finished Aug 03 05:23:57 PM PDT 24
Peak memory 208004 kb
Host smart-eb45041b-2088-4a95-838b-f47c492ef68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651302127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2651302127
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3959525078
Short name T771
Test name
Test status
Simulation time 166688360 ps
CPU time 2.56 seconds
Started Aug 03 05:23:49 PM PDT 24
Finished Aug 03 05:23:52 PM PDT 24
Peak memory 207024 kb
Host smart-aae35d4f-1d53-4d0d-90f5-f91ddd5c3260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959525078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3959525078
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.564182922
Short name T676
Test name
Test status
Simulation time 92221287 ps
CPU time 3.05 seconds
Started Aug 03 05:23:54 PM PDT 24
Finished Aug 03 05:23:57 PM PDT 24
Peak memory 208744 kb
Host smart-3e30e68e-53e2-4f01-94ed-089652605fc3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564182922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.564182922
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2648986231
Short name T503
Test name
Test status
Simulation time 404906995 ps
CPU time 4.2 seconds
Started Aug 03 05:23:51 PM PDT 24
Finished Aug 03 05:23:56 PM PDT 24
Peak memory 206896 kb
Host smart-8c06d7b1-ad9c-49cf-9993-0a302220300b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648986231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2648986231
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.98091159
Short name T553
Test name
Test status
Simulation time 85386540 ps
CPU time 1.87 seconds
Started Aug 03 05:23:53 PM PDT 24
Finished Aug 03 05:23:55 PM PDT 24
Peak memory 206944 kb
Host smart-4ac71afb-d6dd-47be-a1fa-7205c128a884
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98091159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.98091159
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.126098611
Short name T515
Test name
Test status
Simulation time 1973256873 ps
CPU time 29.1 seconds
Started Aug 03 05:23:55 PM PDT 24
Finished Aug 03 05:24:24 PM PDT 24
Peak memory 219296 kb
Host smart-ca9093ea-5fbc-4e53-93c6-222024ba7188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126098611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.126098611
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.777156346
Short name T725
Test name
Test status
Simulation time 77694431 ps
CPU time 3.32 seconds
Started Aug 03 05:23:48 PM PDT 24
Finished Aug 03 05:23:52 PM PDT 24
Peak memory 208788 kb
Host smart-fe5e6d1d-801e-4b59-ad26-2a237600eb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777156346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.777156346
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3643701401
Short name T535
Test name
Test status
Simulation time 575151711 ps
CPU time 7.23 seconds
Started Aug 03 05:23:53 PM PDT 24
Finished Aug 03 05:24:00 PM PDT 24
Peak memory 209388 kb
Host smart-9fb7a22b-2089-42f3-bef3-abc2a8518857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643701401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3643701401
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1181491370
Short name T762
Test name
Test status
Simulation time 468191899 ps
CPU time 3.3 seconds
Started Aug 03 05:23:54 PM PDT 24
Finished Aug 03 05:23:57 PM PDT 24
Peak memory 210472 kb
Host smart-4ba66d79-2f0c-4f0b-8e49-f0eb6ffbf9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181491370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1181491370
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.691622541
Short name T742
Test name
Test status
Simulation time 52582660 ps
CPU time 0.94 seconds
Started Aug 03 05:23:57 PM PDT 24
Finished Aug 03 05:23:58 PM PDT 24
Peak memory 205948 kb
Host smart-1cd0ed46-a322-413f-89c8-d804d4c6b9bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691622541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.691622541
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3909577377
Short name T299
Test name
Test status
Simulation time 195141178 ps
CPU time 10.75 seconds
Started Aug 03 05:24:00 PM PDT 24
Finished Aug 03 05:24:11 PM PDT 24
Peak memory 214812 kb
Host smart-eb4d3b88-637a-412c-bf7a-a8ebfa2075c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3909577377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3909577377
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3894951436
Short name T483
Test name
Test status
Simulation time 80021074 ps
CPU time 3.06 seconds
Started Aug 03 05:23:55 PM PDT 24
Finished Aug 03 05:23:58 PM PDT 24
Peak memory 209464 kb
Host smart-f5fced66-9234-4fab-a2d3-96d61c3e0b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894951436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3894951436
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3447746562
Short name T693
Test name
Test status
Simulation time 81994735 ps
CPU time 3.94 seconds
Started Aug 03 05:23:59 PM PDT 24
Finished Aug 03 05:24:03 PM PDT 24
Peak memory 210352 kb
Host smart-59ca794c-b22e-4100-8dc4-da3f087db84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447746562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3447746562
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2601857171
Short name T23
Test name
Test status
Simulation time 1494046391 ps
CPU time 34.29 seconds
Started Aug 03 05:23:56 PM PDT 24
Finished Aug 03 05:24:30 PM PDT 24
Peak memory 219160 kb
Host smart-a0ce138f-cc0a-43e5-baaa-d24bee697ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601857171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2601857171
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3152730261
Short name T289
Test name
Test status
Simulation time 194148909 ps
CPU time 4.8 seconds
Started Aug 03 05:24:00 PM PDT 24
Finished Aug 03 05:24:05 PM PDT 24
Peak memory 215388 kb
Host smart-7c38f279-4d54-4740-8a4d-42f4f27c1d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152730261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3152730261
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.565538766
Short name T650
Test name
Test status
Simulation time 147170900 ps
CPU time 3.21 seconds
Started Aug 03 05:24:00 PM PDT 24
Finished Aug 03 05:24:04 PM PDT 24
Peak memory 220368 kb
Host smart-a786aabb-ca2c-4c10-aeea-8a157510c6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565538766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.565538766
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_sideload.768127829
Short name T877
Test name
Test status
Simulation time 88248090 ps
CPU time 3.63 seconds
Started Aug 03 05:24:00 PM PDT 24
Finished Aug 03 05:24:04 PM PDT 24
Peak memory 207808 kb
Host smart-4b31b7bb-9602-41e6-a16c-d0c3de9b3bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768127829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.768127829
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3528160912
Short name T681
Test name
Test status
Simulation time 56702864 ps
CPU time 2.93 seconds
Started Aug 03 05:23:55 PM PDT 24
Finished Aug 03 05:23:58 PM PDT 24
Peak memory 206772 kb
Host smart-d597f2c8-3aa1-4f54-9377-5f79aaea3fbb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528160912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3528160912
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2622521392
Short name T863
Test name
Test status
Simulation time 241368485 ps
CPU time 5.54 seconds
Started Aug 03 05:23:56 PM PDT 24
Finished Aug 03 05:24:01 PM PDT 24
Peak memory 207060 kb
Host smart-8a7e7c40-a57a-4599-be72-4e6100cdb0db
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622521392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2622521392
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3853565961
Short name T588
Test name
Test status
Simulation time 278251088 ps
CPU time 4.37 seconds
Started Aug 03 05:23:55 PM PDT 24
Finished Aug 03 05:23:59 PM PDT 24
Peak memory 208860 kb
Host smart-1615e19b-fe22-4c5f-a0f2-3d749371aa28
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853565961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3853565961
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3516108683
Short name T912
Test name
Test status
Simulation time 324239971 ps
CPU time 3.06 seconds
Started Aug 03 05:23:57 PM PDT 24
Finished Aug 03 05:24:00 PM PDT 24
Peak memory 215512 kb
Host smart-c50940ef-3b00-47fd-925a-606e49a69cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516108683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3516108683
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.98743150
Short name T727
Test name
Test status
Simulation time 324266687 ps
CPU time 2.7 seconds
Started Aug 03 05:23:55 PM PDT 24
Finished Aug 03 05:23:58 PM PDT 24
Peak memory 208640 kb
Host smart-89836b14-870b-480b-abfb-c0e0c22fcd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98743150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.98743150
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3799384760
Short name T308
Test name
Test status
Simulation time 3503114777 ps
CPU time 24.47 seconds
Started Aug 03 05:23:59 PM PDT 24
Finished Aug 03 05:24:23 PM PDT 24
Peak memory 215812 kb
Host smart-9e81e09a-8215-43f6-9be0-13b6c8eee601
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799384760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3799384760
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3396843284
Short name T720
Test name
Test status
Simulation time 1065036125 ps
CPU time 8.48 seconds
Started Aug 03 05:24:00 PM PDT 24
Finished Aug 03 05:24:08 PM PDT 24
Peak memory 214428 kb
Host smart-265ce2e9-6dd3-4d98-b651-cdfce843b6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396843284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3396843284
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1418571359
Short name T356
Test name
Test status
Simulation time 467855840 ps
CPU time 7.08 seconds
Started Aug 03 05:23:56 PM PDT 24
Finished Aug 03 05:24:03 PM PDT 24
Peak memory 214424 kb
Host smart-414fab10-bea2-4e92-9f92-ea836dcecd78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1418571359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1418571359
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1396454755
Short name T500
Test name
Test status
Simulation time 81079822 ps
CPU time 1.8 seconds
Started Aug 03 05:23:58 PM PDT 24
Finished Aug 03 05:24:00 PM PDT 24
Peak memory 208688 kb
Host smart-fc9a726f-48cd-448f-8154-9dc56d601008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396454755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1396454755
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1159994267
Short name T474
Test name
Test status
Simulation time 149906611 ps
CPU time 1.64 seconds
Started Aug 03 05:23:53 PM PDT 24
Finished Aug 03 05:23:55 PM PDT 24
Peak memory 207728 kb
Host smart-641c996f-f347-46e5-93fa-3491a81d5af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159994267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1159994267
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_random.3648669819
Short name T621
Test name
Test status
Simulation time 442137280 ps
CPU time 4.73 seconds
Started Aug 03 05:23:55 PM PDT 24
Finished Aug 03 05:24:00 PM PDT 24
Peak memory 209492 kb
Host smart-1c3d4561-edd7-4bda-a5fb-17fccc95089a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648669819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3648669819
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3551080737
Short name T362
Test name
Test status
Simulation time 421977579 ps
CPU time 4.6 seconds
Started Aug 03 05:23:58 PM PDT 24
Finished Aug 03 05:24:03 PM PDT 24
Peak memory 207960 kb
Host smart-824acd64-13c4-4e6a-8744-2034d5cfeb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551080737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3551080737
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3387001935
Short name T508
Test name
Test status
Simulation time 60763088 ps
CPU time 2.81 seconds
Started Aug 03 05:24:00 PM PDT 24
Finished Aug 03 05:24:03 PM PDT 24
Peak memory 206852 kb
Host smart-c4c29c09-adab-4fbe-b26c-2dd74357ce03
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387001935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3387001935
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1822595555
Short name T620
Test name
Test status
Simulation time 1899683624 ps
CPU time 8.2 seconds
Started Aug 03 05:23:57 PM PDT 24
Finished Aug 03 05:24:05 PM PDT 24
Peak memory 208796 kb
Host smart-64fdd096-384f-4760-bfdf-3abfa8cf4736
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822595555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1822595555
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.256228537
Short name T816
Test name
Test status
Simulation time 3468168056 ps
CPU time 59.03 seconds
Started Aug 03 05:23:55 PM PDT 24
Finished Aug 03 05:24:54 PM PDT 24
Peak memory 208220 kb
Host smart-0d90405f-f989-4424-9c18-cfb4bac5d941
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256228537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.256228537
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3369276063
Short name T669
Test name
Test status
Simulation time 80880421 ps
CPU time 1.71 seconds
Started Aug 03 05:23:58 PM PDT 24
Finished Aug 03 05:24:00 PM PDT 24
Peak memory 214372 kb
Host smart-1af7de8b-800f-4074-a49e-5658f7eab6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369276063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3369276063
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1353873272
Short name T865
Test name
Test status
Simulation time 107194059 ps
CPU time 2.79 seconds
Started Aug 03 05:23:57 PM PDT 24
Finished Aug 03 05:24:00 PM PDT 24
Peak memory 208652 kb
Host smart-b4c3e61d-c8e8-457d-b4ee-5055ca75a4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353873272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1353873272
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.4090416798
Short name T292
Test name
Test status
Simulation time 1224505624 ps
CPU time 22.19 seconds
Started Aug 03 05:23:55 PM PDT 24
Finished Aug 03 05:24:18 PM PDT 24
Peak memory 220688 kb
Host smart-3607565f-6bb5-4366-8595-bd0e6fb29082
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090416798 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.4090416798
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.568780854
Short name T486
Test name
Test status
Simulation time 92245260 ps
CPU time 4.46 seconds
Started Aug 03 05:23:58 PM PDT 24
Finished Aug 03 05:24:03 PM PDT 24
Peak memory 209004 kb
Host smart-08533fa8-be1f-45db-8cdc-40c37581773b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568780854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.568780854
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3787572504
Short name T43
Test name
Test status
Simulation time 162241790 ps
CPU time 3.47 seconds
Started Aug 03 05:23:59 PM PDT 24
Finished Aug 03 05:24:03 PM PDT 24
Peak memory 210308 kb
Host smart-b1171ff9-9657-44ec-9877-ea8de4fbce74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787572504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3787572504
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3591317212
Short name T679
Test name
Test status
Simulation time 17885085 ps
CPU time 0.83 seconds
Started Aug 03 05:23:59 PM PDT 24
Finished Aug 03 05:24:00 PM PDT 24
Peak memory 205940 kb
Host smart-7dd91c7f-a246-451f-9392-4b0f7fd18795
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591317212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3591317212
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2648107226
Short name T79
Test name
Test status
Simulation time 66937924 ps
CPU time 2.87 seconds
Started Aug 03 05:24:02 PM PDT 24
Finished Aug 03 05:24:05 PM PDT 24
Peak memory 215120 kb
Host smart-0933acfd-e616-4f9a-87a0-c23ac3fc926a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2648107226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2648107226
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3857619223
Short name T22
Test name
Test status
Simulation time 126634682 ps
CPU time 2.74 seconds
Started Aug 03 05:23:59 PM PDT 24
Finished Aug 03 05:24:02 PM PDT 24
Peak memory 220608 kb
Host smart-aded4333-1621-4f2d-a99c-5f850e38943b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857619223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3857619223
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1865341849
Short name T905
Test name
Test status
Simulation time 1430640339 ps
CPU time 4.01 seconds
Started Aug 03 05:24:00 PM PDT 24
Finished Aug 03 05:24:04 PM PDT 24
Peak memory 209084 kb
Host smart-0ab16fb7-003c-4cb9-8d59-7b0a52141708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865341849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1865341849
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.633192946
Short name T728
Test name
Test status
Simulation time 92495676 ps
CPU time 3.09 seconds
Started Aug 03 05:24:01 PM PDT 24
Finished Aug 03 05:24:04 PM PDT 24
Peak memory 209684 kb
Host smart-b8b25583-c098-4fe5-9325-8da6860de05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633192946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.633192946
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3631380722
Short name T507
Test name
Test status
Simulation time 240162289 ps
CPU time 3.58 seconds
Started Aug 03 05:24:02 PM PDT 24
Finished Aug 03 05:24:05 PM PDT 24
Peak memory 208736 kb
Host smart-2cac7d2d-6d88-4bcc-be7d-d2c7c4f97809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631380722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3631380722
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.199234037
Short name T878
Test name
Test status
Simulation time 111742680 ps
CPU time 5.38 seconds
Started Aug 03 05:24:00 PM PDT 24
Finished Aug 03 05:24:05 PM PDT 24
Peak memory 214276 kb
Host smart-d33b17d7-96c5-4699-99af-d5f47a5e14a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199234037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.199234037
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.4243868268
Short name T876
Test name
Test status
Simulation time 221828847 ps
CPU time 3.86 seconds
Started Aug 03 05:23:56 PM PDT 24
Finished Aug 03 05:24:00 PM PDT 24
Peak memory 208792 kb
Host smart-495af6d8-dd30-49c9-978e-f0b3596416b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243868268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.4243868268
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1780645498
Short name T631
Test name
Test status
Simulation time 223833055 ps
CPU time 4.28 seconds
Started Aug 03 05:23:59 PM PDT 24
Finished Aug 03 05:24:03 PM PDT 24
Peak memory 208204 kb
Host smart-3430082d-ece2-4318-82bd-3be40525ef86
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780645498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1780645498
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.1737184972
Short name T640
Test name
Test status
Simulation time 466293626 ps
CPU time 5.88 seconds
Started Aug 03 05:23:55 PM PDT 24
Finished Aug 03 05:24:01 PM PDT 24
Peak memory 208980 kb
Host smart-7a24f017-26d1-4bdf-99c4-c7edcda52d06
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737184972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1737184972
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1734054399
Short name T399
Test name
Test status
Simulation time 582103228 ps
CPU time 4.67 seconds
Started Aug 03 05:23:59 PM PDT 24
Finished Aug 03 05:24:03 PM PDT 24
Peak memory 208424 kb
Host smart-9c25a25c-f57e-4ac8-b76b-bd19c63eeac4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734054399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1734054399
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2059751149
Short name T554
Test name
Test status
Simulation time 148863867 ps
CPU time 3.66 seconds
Started Aug 03 05:24:02 PM PDT 24
Finished Aug 03 05:24:06 PM PDT 24
Peak memory 208824 kb
Host smart-008faed6-2cf8-4925-8792-7359402e90ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059751149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2059751149
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.961122087
Short name T82
Test name
Test status
Simulation time 293293887 ps
CPU time 3.2 seconds
Started Aug 03 05:23:59 PM PDT 24
Finished Aug 03 05:24:02 PM PDT 24
Peak memory 208792 kb
Host smart-85cda273-2900-4f6f-964b-e023f02ecf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961122087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.961122087
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1267799144
Short name T254
Test name
Test status
Simulation time 2349540539 ps
CPU time 32.99 seconds
Started Aug 03 05:24:00 PM PDT 24
Finished Aug 03 05:24:33 PM PDT 24
Peak memory 219612 kb
Host smart-786e1348-c462-4ecf-a6f5-884932ecaa8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267799144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1267799144
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3271255426
Short name T259
Test name
Test status
Simulation time 168870198 ps
CPU time 2.49 seconds
Started Aug 03 05:23:58 PM PDT 24
Finished Aug 03 05:24:00 PM PDT 24
Peak memory 208132 kb
Host smart-476b712c-1eaa-4917-9d6f-326518181a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271255426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3271255426
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2052863640
Short name T133
Test name
Test status
Simulation time 243338809 ps
CPU time 2.91 seconds
Started Aug 03 05:23:59 PM PDT 24
Finished Aug 03 05:24:02 PM PDT 24
Peak memory 210300 kb
Host smart-4f27468b-3d5d-46d9-abec-df9ad39ababb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052863640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2052863640
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3631286395
Short name T433
Test name
Test status
Simulation time 18717305 ps
CPU time 0.8 seconds
Started Aug 03 05:24:03 PM PDT 24
Finished Aug 03 05:24:04 PM PDT 24
Peak memory 205872 kb
Host smart-063269c9-7235-4ed7-bd11-03a36c078616
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631286395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3631286395
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1069583383
Short name T230
Test name
Test status
Simulation time 186236363 ps
CPU time 3.29 seconds
Started Aug 03 05:24:00 PM PDT 24
Finished Aug 03 05:24:04 PM PDT 24
Peak memory 214312 kb
Host smart-8d4fbdd9-b37d-43b2-96e1-682805f3eeff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1069583383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1069583383
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.446227442
Short name T73
Test name
Test status
Simulation time 137903362 ps
CPU time 2.45 seconds
Started Aug 03 05:24:00 PM PDT 24
Finished Aug 03 05:24:03 PM PDT 24
Peak memory 208468 kb
Host smart-820301e3-1a51-4045-8e72-8dfb3afd1767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446227442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.446227442
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3124877987
Short name T817
Test name
Test status
Simulation time 106442592 ps
CPU time 3.89 seconds
Started Aug 03 05:24:01 PM PDT 24
Finished Aug 03 05:24:05 PM PDT 24
Peak memory 214348 kb
Host smart-4d9c7a67-995b-428c-a261-734534f59507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124877987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3124877987
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.4007122089
Short name T285
Test name
Test status
Simulation time 479777752 ps
CPU time 3.22 seconds
Started Aug 03 05:24:01 PM PDT 24
Finished Aug 03 05:24:04 PM PDT 24
Peak memory 214228 kb
Host smart-0f870581-b85f-4859-88f2-2c381a73955d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007122089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.4007122089
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2792856525
Short name T272
Test name
Test status
Simulation time 261498377 ps
CPU time 3.34 seconds
Started Aug 03 05:24:02 PM PDT 24
Finished Aug 03 05:24:06 PM PDT 24
Peak memory 219848 kb
Host smart-a176e67b-5e2c-4e24-b7ad-ccf8611ffcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792856525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2792856525
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.1731801818
Short name T743
Test name
Test status
Simulation time 38896512 ps
CPU time 2.73 seconds
Started Aug 03 05:23:59 PM PDT 24
Finished Aug 03 05:24:02 PM PDT 24
Peak memory 217732 kb
Host smart-84ca2541-6fe2-4a98-8abd-d8e026c91d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731801818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1731801818
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3558561992
Short name T664
Test name
Test status
Simulation time 33757465 ps
CPU time 2.34 seconds
Started Aug 03 05:24:00 PM PDT 24
Finished Aug 03 05:24:03 PM PDT 24
Peak memory 206940 kb
Host smart-27e4d0c2-7fbb-48e2-9f8f-de6218a0d6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558561992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3558561992
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2126565605
Short name T859
Test name
Test status
Simulation time 642563484 ps
CPU time 5.53 seconds
Started Aug 03 05:24:00 PM PDT 24
Finished Aug 03 05:24:06 PM PDT 24
Peak memory 208760 kb
Host smart-e2ce1047-7fd8-467d-b07a-9ff29aa5fb9a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126565605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2126565605
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.439552940
Short name T14
Test name
Test status
Simulation time 65640409 ps
CPU time 2.56 seconds
Started Aug 03 05:23:58 PM PDT 24
Finished Aug 03 05:24:01 PM PDT 24
Peak memory 208632 kb
Host smart-584bcf16-7911-420b-b4d5-bcd6e6258571
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439552940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.439552940
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2027271920
Short name T205
Test name
Test status
Simulation time 162090139 ps
CPU time 3.07 seconds
Started Aug 03 05:24:04 PM PDT 24
Finished Aug 03 05:24:07 PM PDT 24
Peak memory 208592 kb
Host smart-7625d7d2-acc1-4919-86d1-cea3513a4280
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027271920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2027271920
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1162686561
Short name T654
Test name
Test status
Simulation time 487918545 ps
CPU time 11.7 seconds
Started Aug 03 05:24:01 PM PDT 24
Finished Aug 03 05:24:12 PM PDT 24
Peak memory 208396 kb
Host smart-3a8f2eec-aea5-4e10-915c-344493a4d273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162686561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1162686561
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2010745298
Short name T423
Test name
Test status
Simulation time 61977186 ps
CPU time 2.63 seconds
Started Aug 03 05:24:03 PM PDT 24
Finished Aug 03 05:24:06 PM PDT 24
Peak memory 208620 kb
Host smart-abd0a6a5-34ed-4c71-a038-9e996cb924ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010745298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2010745298
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.805364460
Short name T77
Test name
Test status
Simulation time 3373555057 ps
CPU time 63.43 seconds
Started Aug 03 05:24:00 PM PDT 24
Finished Aug 03 05:25:04 PM PDT 24
Peak memory 216416 kb
Host smart-bb56e55e-07b1-4d36-9f37-e2e626bcd720
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805364460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.805364460
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.1094467403
Short name T261
Test name
Test status
Simulation time 427521182 ps
CPU time 8.82 seconds
Started Aug 03 05:24:02 PM PDT 24
Finished Aug 03 05:24:11 PM PDT 24
Peak memory 219304 kb
Host smart-d5092c9d-4994-4b1b-bd79-7a34848aaa15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094467403 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.1094467403
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1144988614
Short name T815
Test name
Test status
Simulation time 530170026 ps
CPU time 4.15 seconds
Started Aug 03 05:24:02 PM PDT 24
Finished Aug 03 05:24:07 PM PDT 24
Peak memory 214248 kb
Host smart-d20f9167-865c-49ef-b719-465cf9a071d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144988614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1144988614
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.1184791827
Short name T516
Test name
Test status
Simulation time 91409885 ps
CPU time 1.44 seconds
Started Aug 03 05:24:02 PM PDT 24
Finished Aug 03 05:24:03 PM PDT 24
Peak memory 209692 kb
Host smart-c80d33e9-b3eb-4e24-97a9-d3c9d9e57156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184791827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1184791827
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.737982559
Short name T434
Test name
Test status
Simulation time 42890678 ps
CPU time 0.92 seconds
Started Aug 03 05:24:05 PM PDT 24
Finished Aug 03 05:24:06 PM PDT 24
Peak memory 205936 kb
Host smart-95d61d54-55c5-4388-8aa4-9e5fdad06598
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737982559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.737982559
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1998288330
Short name T694
Test name
Test status
Simulation time 403399431 ps
CPU time 10.73 seconds
Started Aug 03 05:24:05 PM PDT 24
Finished Aug 03 05:24:16 PM PDT 24
Peak memory 214324 kb
Host smart-b6cdaf7c-5633-4595-96df-8d833db7898a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1998288330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1998288330
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.2236958359
Short name T729
Test name
Test status
Simulation time 243902289 ps
CPU time 2.18 seconds
Started Aug 03 05:24:07 PM PDT 24
Finished Aug 03 05:24:09 PM PDT 24
Peak memory 209048 kb
Host smart-8fb46e8e-5d46-4e5a-b579-70d349151060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236958359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2236958359
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2044995026
Short name T581
Test name
Test status
Simulation time 84870722 ps
CPU time 3.64 seconds
Started Aug 03 05:24:10 PM PDT 24
Finished Aug 03 05:24:14 PM PDT 24
Peak memory 219656 kb
Host smart-9c2b3fdb-e3c6-4e53-aa19-594efc03a34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044995026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2044995026
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1742203104
Short name T540
Test name
Test status
Simulation time 1142136940 ps
CPU time 2.84 seconds
Started Aug 03 05:24:06 PM PDT 24
Finished Aug 03 05:24:09 PM PDT 24
Peak memory 208772 kb
Host smart-3f08cedc-1aa0-4175-9201-ca818fc87f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742203104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1742203104
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1844971401
Short name T884
Test name
Test status
Simulation time 112189295 ps
CPU time 2.97 seconds
Started Aug 03 05:24:07 PM PDT 24
Finished Aug 03 05:24:10 PM PDT 24
Peak memory 208564 kb
Host smart-bcfffc1b-5e20-469a-a718-e445911bf5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844971401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1844971401
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3170067315
Short name T310
Test name
Test status
Simulation time 739134406 ps
CPU time 3.84 seconds
Started Aug 03 05:24:06 PM PDT 24
Finished Aug 03 05:24:10 PM PDT 24
Peak memory 208756 kb
Host smart-f1462287-3b1f-46b3-8ab1-61ff94ee888c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170067315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3170067315
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1081936721
Short name T380
Test name
Test status
Simulation time 198658306 ps
CPU time 2.53 seconds
Started Aug 03 05:24:08 PM PDT 24
Finished Aug 03 05:24:10 PM PDT 24
Peak memory 207860 kb
Host smart-8d2bf054-4bfc-4370-81b8-48a15f2dff97
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081936721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1081936721
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.3428490199
Short name T443
Test name
Test status
Simulation time 234915932 ps
CPU time 3.1 seconds
Started Aug 03 05:24:06 PM PDT 24
Finished Aug 03 05:24:09 PM PDT 24
Peak memory 206952 kb
Host smart-decc17d1-69da-4506-9ae2-1fc4994247e5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428490199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3428490199
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.33126457
Short name T573
Test name
Test status
Simulation time 58459393 ps
CPU time 2.52 seconds
Started Aug 03 05:24:04 PM PDT 24
Finished Aug 03 05:24:07 PM PDT 24
Peak memory 214280 kb
Host smart-3adf6adb-e77d-4794-884b-d31532c456be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33126457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.33126457
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3365056610
Short name T579
Test name
Test status
Simulation time 152760659 ps
CPU time 1.6 seconds
Started Aug 03 05:24:07 PM PDT 24
Finished Aug 03 05:24:08 PM PDT 24
Peak memory 206768 kb
Host smart-e33c4876-58d3-4aae-af5d-8eb8d9a2b57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365056610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3365056610
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.692544150
Short name T793
Test name
Test status
Simulation time 1054181431 ps
CPU time 22.07 seconds
Started Aug 03 05:24:09 PM PDT 24
Finished Aug 03 05:24:31 PM PDT 24
Peak memory 208600 kb
Host smart-10ee58f7-0391-4a96-af48-7381c9791cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692544150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.692544150
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.783616514
Short name T690
Test name
Test status
Simulation time 162977607 ps
CPU time 4.7 seconds
Started Aug 03 05:24:09 PM PDT 24
Finished Aug 03 05:24:14 PM PDT 24
Peak memory 210356 kb
Host smart-464ae3d8-13d8-487b-b092-b1bbc672c014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783616514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.783616514
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.377055073
Short name T772
Test name
Test status
Simulation time 19101570 ps
CPU time 0.87 seconds
Started Aug 03 05:24:07 PM PDT 24
Finished Aug 03 05:24:08 PM PDT 24
Peak memory 205948 kb
Host smart-f6536bc5-f432-46b4-8fde-3b6eb33d4364
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377055073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.377055073
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3808829958
Short name T795
Test name
Test status
Simulation time 53664811 ps
CPU time 3.75 seconds
Started Aug 03 05:24:05 PM PDT 24
Finished Aug 03 05:24:09 PM PDT 24
Peak memory 215440 kb
Host smart-7378db13-d51a-4b31-adb6-5a887f7c41b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3808829958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3808829958
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3431053208
Short name T734
Test name
Test status
Simulation time 181956255 ps
CPU time 2.43 seconds
Started Aug 03 05:24:08 PM PDT 24
Finished Aug 03 05:24:10 PM PDT 24
Peak memory 222580 kb
Host smart-76d7b629-30f5-46ae-868b-6c3acb9a3a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431053208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3431053208
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.589883263
Short name T368
Test name
Test status
Simulation time 194549593 ps
CPU time 2.46 seconds
Started Aug 03 05:24:05 PM PDT 24
Finished Aug 03 05:24:08 PM PDT 24
Peak memory 210196 kb
Host smart-c0f23479-9bc5-42f9-aac2-ca99524d740e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589883263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.589883263
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2906465892
Short name T363
Test name
Test status
Simulation time 68798694 ps
CPU time 1.46 seconds
Started Aug 03 05:24:13 PM PDT 24
Finished Aug 03 05:24:14 PM PDT 24
Peak memory 214264 kb
Host smart-9de67985-16fb-4c43-99cb-b761ba147c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906465892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2906465892
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.993614081
Short name T54
Test name
Test status
Simulation time 28121006 ps
CPU time 2.24 seconds
Started Aug 03 05:24:07 PM PDT 24
Finished Aug 03 05:24:09 PM PDT 24
Peak memory 214316 kb
Host smart-7741135e-1a36-494d-9f7a-4fdcde4cb5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993614081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.993614081
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3949319516
Short name T278
Test name
Test status
Simulation time 105249442 ps
CPU time 3.54 seconds
Started Aug 03 05:24:04 PM PDT 24
Finished Aug 03 05:24:08 PM PDT 24
Peak memory 214396 kb
Host smart-06324785-852b-430b-8488-27cbb18da30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949319516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3949319516
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.825437016
Short name T274
Test name
Test status
Simulation time 200503234 ps
CPU time 3.52 seconds
Started Aug 03 05:24:14 PM PDT 24
Finished Aug 03 05:24:18 PM PDT 24
Peak memory 208260 kb
Host smart-d1d5a73e-d658-49be-96f2-f7e1211d2c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825437016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.825437016
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.521439933
Short name T757
Test name
Test status
Simulation time 118779535 ps
CPU time 2.52 seconds
Started Aug 03 05:24:09 PM PDT 24
Finished Aug 03 05:24:12 PM PDT 24
Peak memory 206928 kb
Host smart-7848a02b-d2b0-4d65-b9df-6f3daf657142
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521439933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.521439933
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.269035721
Short name T255
Test name
Test status
Simulation time 89406373 ps
CPU time 4.04 seconds
Started Aug 03 05:24:09 PM PDT 24
Finished Aug 03 05:24:13 PM PDT 24
Peak memory 208580 kb
Host smart-de4bdf60-66cc-49fd-881f-6bb9fb96f265
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269035721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.269035721
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1735107388
Short name T575
Test name
Test status
Simulation time 196520505 ps
CPU time 5.82 seconds
Started Aug 03 05:24:07 PM PDT 24
Finished Aug 03 05:24:13 PM PDT 24
Peak memory 208864 kb
Host smart-253b710d-2004-46a6-82a4-d0666bc2bc65
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735107388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1735107388
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.116834929
Short name T662
Test name
Test status
Simulation time 814983673 ps
CPU time 23.65 seconds
Started Aug 03 05:24:06 PM PDT 24
Finished Aug 03 05:24:29 PM PDT 24
Peak memory 209804 kb
Host smart-407ddffe-8451-4194-a93d-093a8f5c4235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116834929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.116834929
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2840062231
Short name T684
Test name
Test status
Simulation time 58501059 ps
CPU time 2.63 seconds
Started Aug 03 05:24:05 PM PDT 24
Finished Aug 03 05:24:08 PM PDT 24
Peak memory 208184 kb
Host smart-aec045f5-d334-4f5f-ba1e-610fd0e9e8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840062231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2840062231
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3971905238
Short name T183
Test name
Test status
Simulation time 1652671892 ps
CPU time 15.63 seconds
Started Aug 03 05:24:10 PM PDT 24
Finished Aug 03 05:24:26 PM PDT 24
Peak memory 215016 kb
Host smart-9ae148af-5e68-442b-b563-6c4530735a65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971905238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3971905238
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.1145017524
Short name T61
Test name
Test status
Simulation time 431322674 ps
CPU time 9.85 seconds
Started Aug 03 05:24:06 PM PDT 24
Finished Aug 03 05:24:16 PM PDT 24
Peak memory 219640 kb
Host smart-c5736c23-7906-4dbd-827d-7e0e7aaf36da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145017524 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.1145017524
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1687694064
Short name T809
Test name
Test status
Simulation time 109717944 ps
CPU time 5.4 seconds
Started Aug 03 05:24:10 PM PDT 24
Finished Aug 03 05:24:15 PM PDT 24
Peak memory 209692 kb
Host smart-3a91c042-67cd-4c2b-8338-b8982c73f89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687694064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1687694064
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.4066785974
Short name T596
Test name
Test status
Simulation time 47769292 ps
CPU time 2.47 seconds
Started Aug 03 05:24:08 PM PDT 24
Finished Aug 03 05:24:10 PM PDT 24
Peak memory 209972 kb
Host smart-8051e599-75fd-4743-b2a3-0eefe11afb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066785974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.4066785974
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3820199104
Short name T629
Test name
Test status
Simulation time 19850373 ps
CPU time 0.88 seconds
Started Aug 03 05:24:12 PM PDT 24
Finished Aug 03 05:24:13 PM PDT 24
Peak memory 205944 kb
Host smart-78cd9e84-1999-4381-b8ca-daa0372e6e8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820199104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3820199104
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2207464503
Short name T30
Test name
Test status
Simulation time 107429968 ps
CPU time 2.53 seconds
Started Aug 03 05:24:13 PM PDT 24
Finished Aug 03 05:24:16 PM PDT 24
Peak memory 220704 kb
Host smart-3cb01e23-ebd7-490d-bb7e-0e7af400c2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207464503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2207464503
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.599428997
Short name T758
Test name
Test status
Simulation time 241008486 ps
CPU time 3.26 seconds
Started Aug 03 05:24:05 PM PDT 24
Finished Aug 03 05:24:09 PM PDT 24
Peak memory 214300 kb
Host smart-e3683575-8c5c-4ca1-8e51-14ef10018b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599428997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.599428997
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.903938372
Short name T101
Test name
Test status
Simulation time 113835039 ps
CPU time 4.97 seconds
Started Aug 03 05:24:16 PM PDT 24
Finished Aug 03 05:24:22 PM PDT 24
Peak memory 214296 kb
Host smart-58be81fa-2f78-4485-b4df-09e1aa22c3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903938372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.903938372
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.4102598211
Short name T243
Test name
Test status
Simulation time 526974228 ps
CPU time 3.89 seconds
Started Aug 03 05:24:12 PM PDT 24
Finished Aug 03 05:24:16 PM PDT 24
Peak memory 222400 kb
Host smart-125e0746-eefb-42df-b1ea-881ec74c6598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102598211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.4102598211
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_random.2146104858
Short name T841
Test name
Test status
Simulation time 883127642 ps
CPU time 6.7 seconds
Started Aug 03 05:24:07 PM PDT 24
Finished Aug 03 05:24:14 PM PDT 24
Peak memory 218160 kb
Host smart-b28fe015-61ec-470f-b599-bfec2d18ea96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146104858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2146104858
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3240391399
Short name T786
Test name
Test status
Simulation time 404378309 ps
CPU time 4.29 seconds
Started Aug 03 05:24:08 PM PDT 24
Finished Aug 03 05:24:13 PM PDT 24
Peak memory 208464 kb
Host smart-4c6a31f8-6c9d-4e30-b638-55d0e1207512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240391399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3240391399
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2902379264
Short name T115
Test name
Test status
Simulation time 68601188 ps
CPU time 3.31 seconds
Started Aug 03 05:24:09 PM PDT 24
Finished Aug 03 05:24:12 PM PDT 24
Peak memory 207064 kb
Host smart-acba1495-9e09-443e-952f-47b5907d781d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902379264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2902379264
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.2732798681
Short name T592
Test name
Test status
Simulation time 177168796 ps
CPU time 5.73 seconds
Started Aug 03 05:24:06 PM PDT 24
Finished Aug 03 05:24:12 PM PDT 24
Peak memory 208528 kb
Host smart-154167e9-1bf6-4265-8161-dc9d86aa8ace
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732798681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2732798681
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.78309187
Short name T542
Test name
Test status
Simulation time 168489128 ps
CPU time 2.4 seconds
Started Aug 03 05:24:08 PM PDT 24
Finished Aug 03 05:24:10 PM PDT 24
Peak memory 207364 kb
Host smart-8c2bb501-0d34-4950-bfe0-0c97b0db96c0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78309187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.78309187
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1180447366
Short name T672
Test name
Test status
Simulation time 115066938 ps
CPU time 4.36 seconds
Started Aug 03 05:24:12 PM PDT 24
Finished Aug 03 05:24:17 PM PDT 24
Peak memory 209812 kb
Host smart-ece4c9f1-299a-451d-a015-0258923a935b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180447366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1180447366
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1667996442
Short name T441
Test name
Test status
Simulation time 37729514 ps
CPU time 2.05 seconds
Started Aug 03 05:24:13 PM PDT 24
Finished Aug 03 05:24:15 PM PDT 24
Peak memory 206856 kb
Host smart-15229b4f-5c94-422b-afdb-b317f5dc6d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667996442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1667996442
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3037533583
Short name T316
Test name
Test status
Simulation time 509660075 ps
CPU time 5.92 seconds
Started Aug 03 05:24:14 PM PDT 24
Finished Aug 03 05:24:20 PM PDT 24
Peak memory 218308 kb
Host smart-465c2a2c-73a1-4d61-bfbf-d88b29e920c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037533583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3037533583
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1597266142
Short name T113
Test name
Test status
Simulation time 182284570 ps
CPU time 3.25 seconds
Started Aug 03 05:24:06 PM PDT 24
Finished Aug 03 05:24:09 PM PDT 24
Peak memory 218484 kb
Host smart-a69fdc8e-7533-4674-9d22-5402b929f9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597266142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1597266142
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.620708702
Short name T389
Test name
Test status
Simulation time 67653675 ps
CPU time 2.7 seconds
Started Aug 03 05:24:13 PM PDT 24
Finished Aug 03 05:24:16 PM PDT 24
Peak memory 210088 kb
Host smart-7532e25b-5a4a-41f8-b98b-a75368e76a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620708702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.620708702
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.622824966
Short name T577
Test name
Test status
Simulation time 63153971 ps
CPU time 0.71 seconds
Started Aug 03 05:23:18 PM PDT 24
Finished Aug 03 05:23:19 PM PDT 24
Peak memory 205956 kb
Host smart-3392016a-31d7-4a59-85bb-ee986c1535ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622824966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.622824966
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2650122252
Short name T787
Test name
Test status
Simulation time 77725640 ps
CPU time 4.32 seconds
Started Aug 03 05:23:22 PM PDT 24
Finished Aug 03 05:23:27 PM PDT 24
Peak memory 214876 kb
Host smart-c57d75ee-51b3-412b-9e87-0819d8c279f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2650122252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2650122252
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1346852274
Short name T564
Test name
Test status
Simulation time 128604601 ps
CPU time 2.6 seconds
Started Aug 03 05:23:14 PM PDT 24
Finished Aug 03 05:23:17 PM PDT 24
Peak memory 208260 kb
Host smart-9a589226-961b-442b-a0a3-0541f603e0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346852274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1346852274
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2713048485
Short name T868
Test name
Test status
Simulation time 1252206000 ps
CPU time 5.98 seconds
Started Aug 03 05:23:15 PM PDT 24
Finished Aug 03 05:23:21 PM PDT 24
Peak memory 222412 kb
Host smart-5d021f6b-2748-40af-914c-d941aca3b324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713048485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2713048485
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.4087926805
Short name T217
Test name
Test status
Simulation time 54536260 ps
CPU time 2.14 seconds
Started Aug 03 05:23:14 PM PDT 24
Finished Aug 03 05:23:16 PM PDT 24
Peak memory 218432 kb
Host smart-8f7eb254-4486-4f6e-a360-9ab158945cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087926805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.4087926805
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.992559594
Short name T861
Test name
Test status
Simulation time 190177282 ps
CPU time 3.4 seconds
Started Aug 03 05:23:16 PM PDT 24
Finished Aug 03 05:23:19 PM PDT 24
Peak memory 208172 kb
Host smart-479f8a8a-2cd3-4e36-8f5e-1a1fcca28f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992559594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.992559594
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.1626677211
Short name T45
Test name
Test status
Simulation time 518866250 ps
CPU time 15.35 seconds
Started Aug 03 05:23:17 PM PDT 24
Finished Aug 03 05:23:33 PM PDT 24
Peak memory 238008 kb
Host smart-15bfa8e6-057c-4c5b-b527-dd5e3376ef3a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626677211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1626677211
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2996517232
Short name T733
Test name
Test status
Simulation time 144699342 ps
CPU time 5.74 seconds
Started Aug 03 05:23:13 PM PDT 24
Finished Aug 03 05:23:19 PM PDT 24
Peak memory 206948 kb
Host smart-f80a3726-f236-4537-8e85-f8c3f7453f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996517232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2996517232
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2178312894
Short name T739
Test name
Test status
Simulation time 674489865 ps
CPU time 7.72 seconds
Started Aug 03 05:23:17 PM PDT 24
Finished Aug 03 05:23:25 PM PDT 24
Peak memory 208468 kb
Host smart-ecde35cc-a00c-45a0-9691-87d3ffb4da4a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178312894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2178312894
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2510218419
Short name T493
Test name
Test status
Simulation time 44772611 ps
CPU time 2.44 seconds
Started Aug 03 05:23:18 PM PDT 24
Finished Aug 03 05:23:21 PM PDT 24
Peak memory 207008 kb
Host smart-8197834c-290a-43c0-875b-8b601cdf55a1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510218419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2510218419
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.891306145
Short name T188
Test name
Test status
Simulation time 36853531 ps
CPU time 2.1 seconds
Started Aug 03 05:23:17 PM PDT 24
Finished Aug 03 05:23:19 PM PDT 24
Peak memory 206964 kb
Host smart-4b3684d4-7492-4150-981a-dccaf89e1732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891306145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.891306145
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.499081682
Short name T769
Test name
Test status
Simulation time 2485210819 ps
CPU time 37.32 seconds
Started Aug 03 05:23:14 PM PDT 24
Finished Aug 03 05:23:52 PM PDT 24
Peak memory 207924 kb
Host smart-d36d9c35-25b2-4fde-9294-674d3e9e04bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499081682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.499081682
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.3291888361
Short name T383
Test name
Test status
Simulation time 4981004739 ps
CPU time 20.4 seconds
Started Aug 03 05:23:15 PM PDT 24
Finished Aug 03 05:23:36 PM PDT 24
Peak memory 220464 kb
Host smart-5a6c26bf-5c60-4143-97c5-b18fe1872e3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291888361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3291888361
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.4275363352
Short name T251
Test name
Test status
Simulation time 564720108 ps
CPU time 9.75 seconds
Started Aug 03 05:23:17 PM PDT 24
Finished Aug 03 05:23:27 PM PDT 24
Peak memory 209980 kb
Host smart-dbffc7fc-2201-4033-add2-00f2bb0c766f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275363352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.4275363352
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.4148590687
Short name T549
Test name
Test status
Simulation time 637231339 ps
CPU time 11.36 seconds
Started Aug 03 05:23:13 PM PDT 24
Finished Aug 03 05:23:25 PM PDT 24
Peak memory 211084 kb
Host smart-215767d0-3e77-4874-8327-ce5e32e34071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148590687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.4148590687
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2581458725
Short name T519
Test name
Test status
Simulation time 74191197 ps
CPU time 0.83 seconds
Started Aug 03 05:24:14 PM PDT 24
Finished Aug 03 05:24:15 PM PDT 24
Peak memory 205952 kb
Host smart-1dc82815-8086-4527-9ea5-7832d1cebb6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581458725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2581458725
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3419222867
Short name T702
Test name
Test status
Simulation time 113810663 ps
CPU time 4.65 seconds
Started Aug 03 05:24:15 PM PDT 24
Finished Aug 03 05:24:19 PM PDT 24
Peak memory 221564 kb
Host smart-1159f247-a85d-47c1-aec5-ca78f1b5b808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419222867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3419222867
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.4096141944
Short name T303
Test name
Test status
Simulation time 122246405 ps
CPU time 3.26 seconds
Started Aug 03 05:24:17 PM PDT 24
Finished Aug 03 05:24:20 PM PDT 24
Peak memory 209068 kb
Host smart-d76d80ee-429e-453b-b538-bbe160041b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096141944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.4096141944
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3877862376
Short name T102
Test name
Test status
Simulation time 1068660177 ps
CPU time 10.97 seconds
Started Aug 03 05:24:13 PM PDT 24
Finished Aug 03 05:24:24 PM PDT 24
Peak memory 209848 kb
Host smart-ccc2520c-a224-4022-abe3-9331a5a9c6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877862376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3877862376
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2641430393
Short name T304
Test name
Test status
Simulation time 70017451 ps
CPU time 2.14 seconds
Started Aug 03 05:24:14 PM PDT 24
Finished Aug 03 05:24:16 PM PDT 24
Peak memory 214264 kb
Host smart-10587717-2a26-4040-a1de-e79a3b7faf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641430393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2641430393
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.120089544
Short name T332
Test name
Test status
Simulation time 60753511 ps
CPU time 3.78 seconds
Started Aug 03 05:24:17 PM PDT 24
Finished Aug 03 05:24:20 PM PDT 24
Peak memory 209640 kb
Host smart-4a7a293c-cf30-4b0f-a5ce-857d4bbadb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120089544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.120089544
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.854494812
Short name T494
Test name
Test status
Simulation time 101046659 ps
CPU time 4.16 seconds
Started Aug 03 05:24:13 PM PDT 24
Finished Aug 03 05:24:17 PM PDT 24
Peak memory 208000 kb
Host smart-f12185a1-4f17-44f0-ab73-be8c63b44cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854494812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.854494812
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2742400051
Short name T471
Test name
Test status
Simulation time 4165823287 ps
CPU time 43.78 seconds
Started Aug 03 05:24:14 PM PDT 24
Finished Aug 03 05:24:58 PM PDT 24
Peak memory 208492 kb
Host smart-bc867965-2d94-41a0-ace9-07bc0bdb27e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742400051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2742400051
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2519014595
Short name T760
Test name
Test status
Simulation time 60543663 ps
CPU time 1.76 seconds
Started Aug 03 05:24:14 PM PDT 24
Finished Aug 03 05:24:15 PM PDT 24
Peak memory 206984 kb
Host smart-dfe10a4b-91ae-4967-90f7-7f54a1ffea1a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519014595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2519014595
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.1289256803
Short name T909
Test name
Test status
Simulation time 4386981266 ps
CPU time 30.46 seconds
Started Aug 03 05:24:13 PM PDT 24
Finished Aug 03 05:24:43 PM PDT 24
Peak memory 208040 kb
Host smart-c278b006-7512-43fb-87b3-4168b53761f4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289256803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1289256803
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2017689578
Short name T510
Test name
Test status
Simulation time 221555662 ps
CPU time 2.98 seconds
Started Aug 03 05:24:16 PM PDT 24
Finished Aug 03 05:24:20 PM PDT 24
Peak memory 208708 kb
Host smart-baafafc3-cf5d-4daf-b03b-57ec0e7211a6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017689578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2017689578
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2402075377
Short name T194
Test name
Test status
Simulation time 96785305 ps
CPU time 3.27 seconds
Started Aug 03 05:24:13 PM PDT 24
Finished Aug 03 05:24:16 PM PDT 24
Peak memory 208936 kb
Host smart-25128901-6004-4c7e-8237-be524f11416d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402075377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2402075377
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1382987944
Short name T813
Test name
Test status
Simulation time 1186581750 ps
CPU time 4.86 seconds
Started Aug 03 05:24:14 PM PDT 24
Finished Aug 03 05:24:19 PM PDT 24
Peak memory 208488 kb
Host smart-9cd68745-4469-46e9-9727-d8365d505fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382987944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1382987944
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.4036838985
Short name T413
Test name
Test status
Simulation time 167759032 ps
CPU time 6.87 seconds
Started Aug 03 05:24:12 PM PDT 24
Finished Aug 03 05:24:19 PM PDT 24
Peak memory 214304 kb
Host smart-d9356bea-539f-419d-8616-33d25be23889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036838985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.4036838985
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1765325667
Short name T481
Test name
Test status
Simulation time 96754224 ps
CPU time 1.88 seconds
Started Aug 03 05:24:16 PM PDT 24
Finished Aug 03 05:24:18 PM PDT 24
Peak memory 214304 kb
Host smart-fece3164-1697-410c-8e1f-9b620cd82c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765325667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1765325667
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.82693568
Short name T422
Test name
Test status
Simulation time 12711865 ps
CPU time 0.82 seconds
Started Aug 03 05:24:22 PM PDT 24
Finished Aug 03 05:24:23 PM PDT 24
Peak memory 205928 kb
Host smart-33d9cc77-059d-4016-880b-23364f800229
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82693568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.82693568
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1154247316
Short name T749
Test name
Test status
Simulation time 243838240 ps
CPU time 3.03 seconds
Started Aug 03 05:24:23 PM PDT 24
Finished Aug 03 05:24:27 PM PDT 24
Peak memory 208244 kb
Host smart-e6dde46a-bd35-4513-9c51-59538d8cec50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154247316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1154247316
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1962306132
Short name T240
Test name
Test status
Simulation time 130625774 ps
CPU time 2.47 seconds
Started Aug 03 05:24:24 PM PDT 24
Finished Aug 03 05:24:27 PM PDT 24
Peak memory 222468 kb
Host smart-255d2dad-f6a3-4bda-8934-883220750cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962306132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1962306132
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2050307058
Short name T269
Test name
Test status
Simulation time 191782183 ps
CPU time 1.88 seconds
Started Aug 03 05:24:21 PM PDT 24
Finished Aug 03 05:24:23 PM PDT 24
Peak memory 214156 kb
Host smart-005948e0-f1bd-47e9-abed-7f91a44dcc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050307058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2050307058
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.875969276
Short name T52
Test name
Test status
Simulation time 28407245 ps
CPU time 2.04 seconds
Started Aug 03 05:24:28 PM PDT 24
Finished Aug 03 05:24:30 PM PDT 24
Peak memory 214272 kb
Host smart-c2ae3455-fed1-457f-a36f-0108bd950fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875969276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.875969276
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1945087723
Short name T300
Test name
Test status
Simulation time 818300140 ps
CPU time 6.1 seconds
Started Aug 03 05:24:18 PM PDT 24
Finished Aug 03 05:24:24 PM PDT 24
Peak memory 210036 kb
Host smart-bfe92bb5-eae6-4965-a383-e9fda541d89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945087723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1945087723
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2406475882
Short name T405
Test name
Test status
Simulation time 127066210 ps
CPU time 3.17 seconds
Started Aug 03 05:24:14 PM PDT 24
Finished Aug 03 05:24:17 PM PDT 24
Peak memory 206792 kb
Host smart-c7827946-f252-4966-8c06-145596f70155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406475882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2406475882
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1722048255
Short name T319
Test name
Test status
Simulation time 890498385 ps
CPU time 3.7 seconds
Started Aug 03 05:24:14 PM PDT 24
Finished Aug 03 05:24:18 PM PDT 24
Peak memory 206840 kb
Host smart-2e089e48-2957-42dc-a7ab-f9b2475a090f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722048255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1722048255
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1053625521
Short name T369
Test name
Test status
Simulation time 137512218 ps
CPU time 2.48 seconds
Started Aug 03 05:24:16 PM PDT 24
Finished Aug 03 05:24:18 PM PDT 24
Peak memory 207572 kb
Host smart-6ae21170-486b-46a5-8b8a-4c7a6a96aa82
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053625521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1053625521
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1219227262
Short name T484
Test name
Test status
Simulation time 196016826 ps
CPU time 5.37 seconds
Started Aug 03 05:24:19 PM PDT 24
Finished Aug 03 05:24:25 PM PDT 24
Peak memory 208084 kb
Host smart-c9f5c690-b796-4b18-90ec-18f71681d812
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219227262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1219227262
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3659948094
Short name T445
Test name
Test status
Simulation time 130809611 ps
CPU time 2.5 seconds
Started Aug 03 05:24:22 PM PDT 24
Finished Aug 03 05:24:25 PM PDT 24
Peak memory 218480 kb
Host smart-ab5b08a2-5822-45d2-80d1-33850287ff8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659948094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3659948094
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.2682596437
Short name T801
Test name
Test status
Simulation time 192089971 ps
CPU time 2.63 seconds
Started Aug 03 05:24:13 PM PDT 24
Finished Aug 03 05:24:15 PM PDT 24
Peak memory 208412 kb
Host smart-1555fbe1-12e5-4744-96b0-8d8e6bebf12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682596437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2682596437
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2434667455
Short name T566
Test name
Test status
Simulation time 1986768659 ps
CPU time 20.26 seconds
Started Aug 03 05:24:20 PM PDT 24
Finished Aug 03 05:24:41 PM PDT 24
Peak memory 222380 kb
Host smart-4998002d-36b5-4717-bb6b-ad796e154ddc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434667455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2434667455
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.3097689883
Short name T294
Test name
Test status
Simulation time 1244864102 ps
CPU time 13.65 seconds
Started Aug 03 05:24:20 PM PDT 24
Finished Aug 03 05:24:34 PM PDT 24
Peak memory 221656 kb
Host smart-cdf2870f-82e6-4c4f-ae22-c7bdca397a2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097689883 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.3097689883
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3073999355
Short name T191
Test name
Test status
Simulation time 346127435 ps
CPU time 7.22 seconds
Started Aug 03 05:24:20 PM PDT 24
Finished Aug 03 05:24:27 PM PDT 24
Peak memory 207444 kb
Host smart-37df2f00-91ef-4d65-be64-b6d23ee230f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073999355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3073999355
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1495938988
Short name T132
Test name
Test status
Simulation time 138939226 ps
CPU time 2.52 seconds
Started Aug 03 05:24:21 PM PDT 24
Finished Aug 03 05:24:24 PM PDT 24
Peak memory 210120 kb
Host smart-edb37dc7-e037-49be-9999-8650935f0357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495938988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1495938988
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3714575393
Short name T460
Test name
Test status
Simulation time 12482867 ps
CPU time 0.94 seconds
Started Aug 03 05:24:19 PM PDT 24
Finished Aug 03 05:24:21 PM PDT 24
Peak memory 205912 kb
Host smart-d21628c7-7894-4b76-8bb3-b5c0ac450a48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714575393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3714575393
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.3086542801
Short name T899
Test name
Test status
Simulation time 675604436 ps
CPU time 8.96 seconds
Started Aug 03 05:24:20 PM PDT 24
Finished Aug 03 05:24:29 PM PDT 24
Peak memory 214484 kb
Host smart-7b1f4107-dc33-4c82-a3d2-d563ee779724
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3086542801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3086542801
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1231501833
Short name T625
Test name
Test status
Simulation time 44198004 ps
CPU time 1.97 seconds
Started Aug 03 05:24:22 PM PDT 24
Finished Aug 03 05:24:24 PM PDT 24
Peak memory 208576 kb
Host smart-f6e3a77f-2175-49d1-b174-a6e01eb23fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231501833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1231501833
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2067660149
Short name T527
Test name
Test status
Simulation time 84593563 ps
CPU time 2.09 seconds
Started Aug 03 05:24:22 PM PDT 24
Finished Aug 03 05:24:25 PM PDT 24
Peak memory 214316 kb
Host smart-ee8c7513-7f59-4189-9804-803081d8d172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067660149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2067660149
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2572157445
Short name T245
Test name
Test status
Simulation time 76532309 ps
CPU time 3.74 seconds
Started Aug 03 05:24:23 PM PDT 24
Finished Aug 03 05:24:27 PM PDT 24
Peak memory 214244 kb
Host smart-caa0acfd-532b-4b96-9501-85b27ea6b947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572157445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2572157445
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3144662913
Short name T545
Test name
Test status
Simulation time 134785711 ps
CPU time 1.69 seconds
Started Aug 03 05:24:20 PM PDT 24
Finished Aug 03 05:24:22 PM PDT 24
Peak memory 206108 kb
Host smart-cb737609-1cdf-4ec7-8c21-1c5e4a51fd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144662913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3144662913
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3128818467
Short name T574
Test name
Test status
Simulation time 833333502 ps
CPU time 9.6 seconds
Started Aug 03 05:24:27 PM PDT 24
Finished Aug 03 05:24:37 PM PDT 24
Peak memory 207612 kb
Host smart-f4cee0ae-9fad-40ca-adf3-7b2aa606f204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128818467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3128818467
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.4149583901
Short name T440
Test name
Test status
Simulation time 32459077 ps
CPU time 2.14 seconds
Started Aug 03 05:24:25 PM PDT 24
Finished Aug 03 05:24:27 PM PDT 24
Peak memory 206820 kb
Host smart-fc5f1296-6efa-4179-bb8b-a70b68244a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149583901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.4149583901
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.850647788
Short name T282
Test name
Test status
Simulation time 264063853 ps
CPU time 2.94 seconds
Started Aug 03 05:24:21 PM PDT 24
Finished Aug 03 05:24:24 PM PDT 24
Peak memory 206840 kb
Host smart-add85962-9e11-4590-8eb6-153855d69e75
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850647788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.850647788
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3191934774
Short name T487
Test name
Test status
Simulation time 520140037 ps
CPU time 3.21 seconds
Started Aug 03 05:24:19 PM PDT 24
Finished Aug 03 05:24:22 PM PDT 24
Peak memory 206968 kb
Host smart-2ead82e2-edfe-4ce0-a6ca-18e16422de88
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191934774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3191934774
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2388626467
Short name T531
Test name
Test status
Simulation time 1144978622 ps
CPU time 3.15 seconds
Started Aug 03 05:24:28 PM PDT 24
Finished Aug 03 05:24:31 PM PDT 24
Peak memory 206972 kb
Host smart-23a649a6-4bfc-491f-84e2-0fdac40e8272
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388626467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2388626467
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1920028041
Short name T584
Test name
Test status
Simulation time 123704268 ps
CPU time 3.64 seconds
Started Aug 03 05:24:22 PM PDT 24
Finished Aug 03 05:24:26 PM PDT 24
Peak memory 209388 kb
Host smart-dfe8bbf1-e9ec-4d5a-be87-b5c2c101f7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920028041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1920028041
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2343701885
Short name T429
Test name
Test status
Simulation time 10079805501 ps
CPU time 11.5 seconds
Started Aug 03 05:24:22 PM PDT 24
Finished Aug 03 05:24:33 PM PDT 24
Peak memory 207924 kb
Host smart-520a36f0-9056-462a-8c12-30354d12e219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343701885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2343701885
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.287205223
Short name T293
Test name
Test status
Simulation time 450242063 ps
CPU time 10.05 seconds
Started Aug 03 05:24:20 PM PDT 24
Finished Aug 03 05:24:30 PM PDT 24
Peak memory 214388 kb
Host smart-6b37e9ce-079b-4865-a34b-101af6bb487b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287205223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.287205223
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.4270959355
Short name T146
Test name
Test status
Simulation time 220680581 ps
CPU time 2.16 seconds
Started Aug 03 05:24:24 PM PDT 24
Finished Aug 03 05:24:27 PM PDT 24
Peak memory 209984 kb
Host smart-0fbd70f0-0106-48a2-b7e8-03e37df681ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270959355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.4270959355
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2683051519
Short name T430
Test name
Test status
Simulation time 15066375 ps
CPU time 0.76 seconds
Started Aug 03 05:24:29 PM PDT 24
Finished Aug 03 05:24:30 PM PDT 24
Peak memory 205980 kb
Host smart-9d1a4233-8b0e-4142-a04e-034ad88f4dfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683051519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2683051519
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.104605487
Short name T791
Test name
Test status
Simulation time 38467067 ps
CPU time 2.92 seconds
Started Aug 03 05:24:25 PM PDT 24
Finished Aug 03 05:24:28 PM PDT 24
Peak memory 214332 kb
Host smart-08a5567e-86d6-4bac-8d11-8e0efe22a98f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104605487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.104605487
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2047488
Short name T260
Test name
Test status
Simulation time 204539046 ps
CPU time 2.79 seconds
Started Aug 03 05:24:26 PM PDT 24
Finished Aug 03 05:24:29 PM PDT 24
Peak memory 218508 kb
Host smart-c484479e-f829-4b66-b5fe-3dcf308cc60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2047488
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.199028950
Short name T797
Test name
Test status
Simulation time 140822007 ps
CPU time 4.14 seconds
Started Aug 03 05:24:25 PM PDT 24
Finished Aug 03 05:24:29 PM PDT 24
Peak memory 222396 kb
Host smart-dfd86d9c-dc56-4550-a3db-5130830627d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199028950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.199028950
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1698174306
Short name T286
Test name
Test status
Simulation time 163468121 ps
CPU time 3.08 seconds
Started Aug 03 05:24:25 PM PDT 24
Finished Aug 03 05:24:29 PM PDT 24
Peak memory 214164 kb
Host smart-d0d77dba-b646-4214-ac10-647850b8bcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698174306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1698174306
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1783167995
Short name T220
Test name
Test status
Simulation time 224812761 ps
CPU time 3.11 seconds
Started Aug 03 05:24:27 PM PDT 24
Finished Aug 03 05:24:30 PM PDT 24
Peak memory 217872 kb
Host smart-36e07b6b-d11e-4b20-8f60-89d68d5d3bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783167995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1783167995
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2415484849
Short name T511
Test name
Test status
Simulation time 287367939 ps
CPU time 3.36 seconds
Started Aug 03 05:24:26 PM PDT 24
Finished Aug 03 05:24:29 PM PDT 24
Peak memory 207712 kb
Host smart-4abd8482-ca42-46c5-8c9c-4a5afdb21a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415484849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2415484849
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.4130638571
Short name T755
Test name
Test status
Simulation time 157691820 ps
CPU time 2.32 seconds
Started Aug 03 05:24:27 PM PDT 24
Finished Aug 03 05:24:30 PM PDT 24
Peak memory 206876 kb
Host smart-97e5969e-0a19-4fc0-a9bc-7f27efc3fcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130638571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.4130638571
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1931560781
Short name T602
Test name
Test status
Simulation time 104801425 ps
CPU time 3.5 seconds
Started Aug 03 05:24:29 PM PDT 24
Finished Aug 03 05:24:33 PM PDT 24
Peak memory 208608 kb
Host smart-9aa568a7-d6d2-4115-838d-3eb6159161b3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931560781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1931560781
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3477214210
Short name T87
Test name
Test status
Simulation time 218437612 ps
CPU time 6.4 seconds
Started Aug 03 05:24:26 PM PDT 24
Finished Aug 03 05:24:32 PM PDT 24
Peak memory 208552 kb
Host smart-15fbc39a-9e59-4894-8131-de3343c9f09d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477214210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3477214210
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.2519384708
Short name T603
Test name
Test status
Simulation time 674436789 ps
CPU time 19.55 seconds
Started Aug 03 05:24:30 PM PDT 24
Finished Aug 03 05:24:50 PM PDT 24
Peak memory 208352 kb
Host smart-12b65da2-a540-44e7-aa1c-507a843fa03e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519384708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2519384708
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2765542193
Short name T78
Test name
Test status
Simulation time 53815629 ps
CPU time 2.78 seconds
Started Aug 03 05:24:29 PM PDT 24
Finished Aug 03 05:24:32 PM PDT 24
Peak memory 208956 kb
Host smart-b86727ff-adcb-4177-bbad-d6910de52e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765542193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2765542193
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2835647451
Short name T582
Test name
Test status
Simulation time 66564336 ps
CPU time 2.78 seconds
Started Aug 03 05:24:21 PM PDT 24
Finished Aug 03 05:24:23 PM PDT 24
Peak memory 208392 kb
Host smart-b1577754-b29d-44e7-a7bd-1e401133f4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835647451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2835647451
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2148061021
Short name T237
Test name
Test status
Simulation time 205294233 ps
CPU time 5.52 seconds
Started Aug 03 05:24:30 PM PDT 24
Finished Aug 03 05:24:36 PM PDT 24
Peak memory 208352 kb
Host smart-376e9264-e13a-422f-8106-60f3e315c663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148061021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2148061021
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2455573434
Short name T580
Test name
Test status
Simulation time 319583632 ps
CPU time 2.31 seconds
Started Aug 03 05:24:27 PM PDT 24
Finished Aug 03 05:24:30 PM PDT 24
Peak memory 209876 kb
Host smart-5adcbb6a-2f8d-4fe4-a8c8-63fefb155480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455573434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2455573434
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2466632241
Short name T649
Test name
Test status
Simulation time 45643380 ps
CPU time 0.87 seconds
Started Aug 03 05:24:32 PM PDT 24
Finished Aug 03 05:24:33 PM PDT 24
Peak memory 205936 kb
Host smart-e6c3e1cb-2d58-4d22-b6b4-ae18ca2222ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466632241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2466632241
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3757196742
Short name T70
Test name
Test status
Simulation time 39123470 ps
CPU time 2.65 seconds
Started Aug 03 05:24:24 PM PDT 24
Finished Aug 03 05:24:27 PM PDT 24
Peak memory 222704 kb
Host smart-220190a4-96cf-4b2f-8298-69deac0b0d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757196742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3757196742
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2555426072
Short name T384
Test name
Test status
Simulation time 154319964 ps
CPU time 1.98 seconds
Started Aug 03 05:24:26 PM PDT 24
Finished Aug 03 05:24:28 PM PDT 24
Peak memory 207240 kb
Host smart-95f5fa6a-0770-4d2c-85c4-b9fcc8a99528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555426072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2555426072
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1413253892
Short name T96
Test name
Test status
Simulation time 258778151 ps
CPU time 9.38 seconds
Started Aug 03 05:24:27 PM PDT 24
Finished Aug 03 05:24:37 PM PDT 24
Peak memory 221348 kb
Host smart-25c3bdbd-ed8e-4500-b8e9-7f51c5e26e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413253892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1413253892
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.4034250211
Short name T305
Test name
Test status
Simulation time 61192930 ps
CPU time 2.32 seconds
Started Aug 03 05:24:30 PM PDT 24
Finished Aug 03 05:24:32 PM PDT 24
Peak memory 214220 kb
Host smart-5496a5d4-e152-4742-9fc3-00b0570e63ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034250211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.4034250211
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3515026584
Short name T257
Test name
Test status
Simulation time 72265816 ps
CPU time 3.6 seconds
Started Aug 03 05:24:28 PM PDT 24
Finished Aug 03 05:24:32 PM PDT 24
Peak memory 217988 kb
Host smart-33273d21-fba7-4dcf-89e7-a50b718f8462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515026584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3515026584
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2318527679
Short name T375
Test name
Test status
Simulation time 83117159 ps
CPU time 4.51 seconds
Started Aug 03 05:24:26 PM PDT 24
Finished Aug 03 05:24:30 PM PDT 24
Peak memory 209516 kb
Host smart-6ff2b705-9a08-4fd4-b672-badeeb826436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318527679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2318527679
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2624481261
Short name T424
Test name
Test status
Simulation time 177167646 ps
CPU time 4.06 seconds
Started Aug 03 05:24:29 PM PDT 24
Finished Aug 03 05:24:33 PM PDT 24
Peak memory 208596 kb
Host smart-74147d47-ff42-43b5-ad68-035a2e8a55a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624481261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2624481261
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1687455625
Short name T84
Test name
Test status
Simulation time 126013979 ps
CPU time 2.5 seconds
Started Aug 03 05:24:32 PM PDT 24
Finished Aug 03 05:24:34 PM PDT 24
Peak memory 206784 kb
Host smart-c9e57436-b01a-41a9-b4a6-74a100dcc9c1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687455625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1687455625
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2964926297
Short name T711
Test name
Test status
Simulation time 130391360 ps
CPU time 2.03 seconds
Started Aug 03 05:24:27 PM PDT 24
Finished Aug 03 05:24:29 PM PDT 24
Peak memory 208540 kb
Host smart-698739bc-37a4-4075-b4da-78be347f0d12
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964926297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2964926297
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3709418038
Short name T857
Test name
Test status
Simulation time 109534535 ps
CPU time 4.18 seconds
Started Aug 03 05:24:26 PM PDT 24
Finished Aug 03 05:24:31 PM PDT 24
Peak memory 208384 kb
Host smart-421dae94-ce8d-4caa-8d81-85be3f1d1dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709418038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3709418038
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.499539718
Short name T586
Test name
Test status
Simulation time 95757676 ps
CPU time 2.56 seconds
Started Aug 03 05:24:28 PM PDT 24
Finished Aug 03 05:24:30 PM PDT 24
Peak memory 208408 kb
Host smart-c7e7a243-5cac-429e-a5fb-17fcd97625ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499539718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.499539718
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3658732730
Short name T891
Test name
Test status
Simulation time 13486495371 ps
CPU time 29.08 seconds
Started Aug 03 05:24:25 PM PDT 24
Finished Aug 03 05:24:54 PM PDT 24
Peak memory 222468 kb
Host smart-f935ae1d-9f59-44a2-8869-872367319832
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658732730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3658732730
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2302549229
Short name T313
Test name
Test status
Simulation time 24411224671 ps
CPU time 45.66 seconds
Started Aug 03 05:24:30 PM PDT 24
Finished Aug 03 05:25:16 PM PDT 24
Peak memory 214280 kb
Host smart-6100e2a1-dcc8-4e1c-b132-c0cf4d9ff475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302549229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2302549229
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1185056016
Short name T524
Test name
Test status
Simulation time 18075148 ps
CPU time 0.76 seconds
Started Aug 03 05:24:33 PM PDT 24
Finished Aug 03 05:24:34 PM PDT 24
Peak memory 205836 kb
Host smart-4a2f1495-f96c-4abf-a587-10a503d0d75e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185056016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1185056016
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2397710837
Short name T871
Test name
Test status
Simulation time 159121496 ps
CPU time 5.77 seconds
Started Aug 03 05:24:38 PM PDT 24
Finished Aug 03 05:24:44 PM PDT 24
Peak memory 221556 kb
Host smart-a202ef48-2bfb-47d8-b14d-0ab78bce72a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397710837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2397710837
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3289485206
Short name T359
Test name
Test status
Simulation time 207813428 ps
CPU time 3.18 seconds
Started Aug 03 05:24:33 PM PDT 24
Finished Aug 03 05:24:37 PM PDT 24
Peak memory 209868 kb
Host smart-4723b967-f2dc-4f04-ba74-636048040fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289485206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3289485206
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.822107829
Short name T24
Test name
Test status
Simulation time 203541687 ps
CPU time 7.08 seconds
Started Aug 03 05:24:34 PM PDT 24
Finished Aug 03 05:24:41 PM PDT 24
Peak memory 209320 kb
Host smart-99ad5f92-189f-4a7b-98ff-8bce4653f6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822107829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.822107829
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1720113208
Short name T386
Test name
Test status
Simulation time 119971612 ps
CPU time 2.98 seconds
Started Aug 03 05:24:36 PM PDT 24
Finished Aug 03 05:24:39 PM PDT 24
Peak memory 214252 kb
Host smart-3ca189d3-95fa-47ba-bb1c-f198032d25d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720113208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1720113208
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2730799413
Short name T872
Test name
Test status
Simulation time 199065780 ps
CPU time 6.2 seconds
Started Aug 03 05:24:35 PM PDT 24
Finished Aug 03 05:24:41 PM PDT 24
Peak memory 210980 kb
Host smart-d8356d77-f9f0-4ebb-ac32-b873338608df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730799413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2730799413
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1946936329
Short name T754
Test name
Test status
Simulation time 189241304 ps
CPU time 4.43 seconds
Started Aug 03 05:24:31 PM PDT 24
Finished Aug 03 05:24:36 PM PDT 24
Peak memory 209556 kb
Host smart-7830d51d-def8-43b5-9eb8-7da3fb977e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946936329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1946936329
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.310922892
Short name T83
Test name
Test status
Simulation time 109167796 ps
CPU time 3.03 seconds
Started Aug 03 05:24:33 PM PDT 24
Finished Aug 03 05:24:36 PM PDT 24
Peak memory 207056 kb
Host smart-88c520ad-f5e0-4f9b-bf70-dff8bcf6e11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310922892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.310922892
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.4156236088
Short name T710
Test name
Test status
Simulation time 75979848 ps
CPU time 3 seconds
Started Aug 03 05:24:34 PM PDT 24
Finished Aug 03 05:24:37 PM PDT 24
Peak memory 206844 kb
Host smart-8ffc704b-fb47-484b-9c53-3fd5fdaa4dac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156236088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.4156236088
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.688186238
Short name T295
Test name
Test status
Simulation time 162727680 ps
CPU time 5.7 seconds
Started Aug 03 05:24:33 PM PDT 24
Finished Aug 03 05:24:38 PM PDT 24
Peak memory 208960 kb
Host smart-05557b61-bc12-490b-9104-740752ef14ff
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688186238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.688186238
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.875868494
Short name T802
Test name
Test status
Simulation time 70761823 ps
CPU time 3.42 seconds
Started Aug 03 05:24:34 PM PDT 24
Finished Aug 03 05:24:38 PM PDT 24
Peak memory 208524 kb
Host smart-246f994a-53eb-4ae7-95db-fb60d278b367
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875868494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.875868494
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2804118851
Short name T635
Test name
Test status
Simulation time 44131491 ps
CPU time 2.11 seconds
Started Aug 03 05:24:33 PM PDT 24
Finished Aug 03 05:24:36 PM PDT 24
Peak memory 208476 kb
Host smart-7c1d6d15-2f69-4b82-9674-709c7ef3349c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804118851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2804118851
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1820899244
Short name T889
Test name
Test status
Simulation time 581929830 ps
CPU time 3.85 seconds
Started Aug 03 05:24:36 PM PDT 24
Finished Aug 03 05:24:40 PM PDT 24
Peak memory 207776 kb
Host smart-9550b18b-47b0-45ce-a761-f35b4b4c06e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820899244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1820899244
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.257513111
Short name T258
Test name
Test status
Simulation time 8134461741 ps
CPU time 172.37 seconds
Started Aug 03 05:24:36 PM PDT 24
Finished Aug 03 05:27:28 PM PDT 24
Peak memory 217356 kb
Host smart-dd3e2518-72b4-4c58-bbf5-3e286658a148
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257513111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.257513111
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.1789937889
Short name T867
Test name
Test status
Simulation time 465819794 ps
CPU time 10.38 seconds
Started Aug 03 05:24:33 PM PDT 24
Finished Aug 03 05:24:44 PM PDT 24
Peak memory 222432 kb
Host smart-423c7a83-b631-4778-9c0a-5db8ade87097
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789937889 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.1789937889
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1321788611
Short name T522
Test name
Test status
Simulation time 1038124293 ps
CPU time 27.34 seconds
Started Aug 03 05:24:35 PM PDT 24
Finished Aug 03 05:25:02 PM PDT 24
Peak memory 208200 kb
Host smart-50c5f427-014d-486b-9186-cb6acd1dada1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321788611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1321788611
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.4172523847
Short name T58
Test name
Test status
Simulation time 236767149 ps
CPU time 2.94 seconds
Started Aug 03 05:24:33 PM PDT 24
Finished Aug 03 05:24:36 PM PDT 24
Peak memory 209952 kb
Host smart-e5581bfa-9368-49e8-95ad-d6bfa42d2a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172523847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.4172523847
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1866547198
Short name T682
Test name
Test status
Simulation time 38262940 ps
CPU time 0.73 seconds
Started Aug 03 05:24:48 PM PDT 24
Finished Aug 03 05:24:49 PM PDT 24
Peak memory 205916 kb
Host smart-1bd59281-6388-4a69-8f12-64c49f9e93f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866547198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1866547198
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2074537739
Short name T614
Test name
Test status
Simulation time 126793574 ps
CPU time 5.38 seconds
Started Aug 03 05:24:33 PM PDT 24
Finished Aug 03 05:24:39 PM PDT 24
Peak memory 222616 kb
Host smart-d5416aea-7fa6-4bd9-9d0b-0b829c367cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074537739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2074537739
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.4194867910
Short name T612
Test name
Test status
Simulation time 295128982 ps
CPU time 4.58 seconds
Started Aug 03 05:24:33 PM PDT 24
Finished Aug 03 05:24:37 PM PDT 24
Peak memory 208564 kb
Host smart-53a5f21c-c556-4015-9d88-ce56a7c27fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194867910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.4194867910
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.403414585
Short name T855
Test name
Test status
Simulation time 257224285 ps
CPU time 2.53 seconds
Started Aug 03 05:24:34 PM PDT 24
Finished Aug 03 05:24:36 PM PDT 24
Peak memory 214540 kb
Host smart-3f8915a8-4bcc-4cb0-9ff2-08318be7e872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403414585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.403414585
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_random.165816476
Short name T722
Test name
Test status
Simulation time 217359078 ps
CPU time 4.21 seconds
Started Aug 03 05:24:34 PM PDT 24
Finished Aug 03 05:24:38 PM PDT 24
Peak memory 209008 kb
Host smart-693261ce-f686-43a2-bb85-d0bc76a33a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165816476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.165816476
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1631165440
Short name T854
Test name
Test status
Simulation time 120871277 ps
CPU time 3.33 seconds
Started Aug 03 05:24:32 PM PDT 24
Finished Aug 03 05:24:35 PM PDT 24
Peak memory 206668 kb
Host smart-470acdff-3fa1-49ee-9cb7-48bab5031327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631165440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1631165440
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3229667674
Short name T436
Test name
Test status
Simulation time 127106745 ps
CPU time 4.33 seconds
Started Aug 03 05:24:33 PM PDT 24
Finished Aug 03 05:24:38 PM PDT 24
Peak memory 208832 kb
Host smart-c320fdb8-d447-4fda-b444-42805bf5fdf9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229667674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3229667674
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.663058700
Short name T774
Test name
Test status
Simulation time 149408692 ps
CPU time 3.51 seconds
Started Aug 03 05:24:35 PM PDT 24
Finished Aug 03 05:24:39 PM PDT 24
Peak memory 208416 kb
Host smart-6f295b14-5e20-4538-802f-afbba091b182
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663058700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.663058700
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3723010029
Short name T840
Test name
Test status
Simulation time 616134423 ps
CPU time 4.95 seconds
Started Aug 03 05:24:31 PM PDT 24
Finished Aug 03 05:24:36 PM PDT 24
Peak memory 208804 kb
Host smart-8a575aef-36b7-4c2f-971e-6481dabf3445
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723010029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3723010029
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3424241119
Short name T358
Test name
Test status
Simulation time 71787988 ps
CPU time 2.11 seconds
Started Aug 03 05:24:33 PM PDT 24
Finished Aug 03 05:24:36 PM PDT 24
Peak memory 207564 kb
Host smart-13e0b0f8-9505-449f-86fa-c4d0cfa6dcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424241119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3424241119
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1267527992
Short name T427
Test name
Test status
Simulation time 208897956 ps
CPU time 2.49 seconds
Started Aug 03 05:24:32 PM PDT 24
Finished Aug 03 05:24:35 PM PDT 24
Peak memory 207376 kb
Host smart-0ed1636b-c488-4656-bf21-dd54c9eda01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267527992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1267527992
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1498316300
Short name T74
Test name
Test status
Simulation time 736948360 ps
CPU time 28.09 seconds
Started Aug 03 05:24:37 PM PDT 24
Finished Aug 03 05:25:06 PM PDT 24
Peak memory 222408 kb
Host smart-f469d2a9-ae29-4998-b91a-5aff85ff59f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498316300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1498316300
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.3939004665
Short name T75
Test name
Test status
Simulation time 653525987 ps
CPU time 11.37 seconds
Started Aug 03 05:24:33 PM PDT 24
Finished Aug 03 05:24:44 PM PDT 24
Peak memory 222632 kb
Host smart-cc844376-7e97-4370-ac70-669e271092e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939004665 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.3939004665
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1807306457
Short name T781
Test name
Test status
Simulation time 1328298564 ps
CPU time 9.68 seconds
Started Aug 03 05:24:35 PM PDT 24
Finished Aug 03 05:24:45 PM PDT 24
Peak memory 209908 kb
Host smart-90d53c83-e8d9-4687-8520-867e1c0dae4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807306457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1807306457
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3995935624
Short name T390
Test name
Test status
Simulation time 519794191 ps
CPU time 9.56 seconds
Started Aug 03 05:24:33 PM PDT 24
Finished Aug 03 05:24:43 PM PDT 24
Peak memory 210936 kb
Host smart-e904867e-5b35-4715-8882-5d89878f6e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995935624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3995935624
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2277028173
Short name T444
Test name
Test status
Simulation time 42878085 ps
CPU time 0.85 seconds
Started Aug 03 05:24:40 PM PDT 24
Finished Aug 03 05:24:41 PM PDT 24
Peak memory 205968 kb
Host smart-46d22db6-9963-4e69-934e-d4da01c6fb51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277028173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2277028173
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1356575042
Short name T636
Test name
Test status
Simulation time 167955211 ps
CPU time 2.05 seconds
Started Aug 03 05:24:39 PM PDT 24
Finished Aug 03 05:24:41 PM PDT 24
Peak memory 209956 kb
Host smart-24e0f655-48b0-49df-b757-dfb32262dd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356575042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1356575042
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.2387642277
Short name T49
Test name
Test status
Simulation time 130217704 ps
CPU time 3.84 seconds
Started Aug 03 05:24:40 PM PDT 24
Finished Aug 03 05:24:44 PM PDT 24
Peak memory 218276 kb
Host smart-09b0d610-bd8e-4872-9eb3-20909bdb1e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387642277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2387642277
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.4017252731
Short name T346
Test name
Test status
Simulation time 231223780 ps
CPU time 4.3 seconds
Started Aug 03 05:24:41 PM PDT 24
Finished Aug 03 05:24:45 PM PDT 24
Peak memory 222416 kb
Host smart-ea00b588-fb6c-41cf-93df-e14162c24a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017252731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.4017252731
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2498597949
Short name T246
Test name
Test status
Simulation time 121841381 ps
CPU time 3.5 seconds
Started Aug 03 05:24:47 PM PDT 24
Finished Aug 03 05:24:51 PM PDT 24
Peak memory 214308 kb
Host smart-c05f1839-6fbc-4e70-a848-4a605e946a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498597949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2498597949
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.983135057
Short name T197
Test name
Test status
Simulation time 669836131 ps
CPU time 5.55 seconds
Started Aug 03 05:24:46 PM PDT 24
Finished Aug 03 05:24:52 PM PDT 24
Peak memory 214268 kb
Host smart-2dd6b738-1b69-4239-a86f-fda6a4143eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983135057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.983135057
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.1650909899
Short name T598
Test name
Test status
Simulation time 69839603 ps
CPU time 2.55 seconds
Started Aug 03 05:24:44 PM PDT 24
Finished Aug 03 05:24:46 PM PDT 24
Peak memory 208704 kb
Host smart-10048077-138e-450e-b2b0-0610dfe50f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650909899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.1650909899
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.709596011
Short name T700
Test name
Test status
Simulation time 52950834 ps
CPU time 2.73 seconds
Started Aug 03 05:24:39 PM PDT 24
Finished Aug 03 05:24:42 PM PDT 24
Peak memory 207108 kb
Host smart-55971e24-660b-4d31-901c-56f8219955e2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709596011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.709596011
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3115198009
Short name T688
Test name
Test status
Simulation time 382234672 ps
CPU time 7.45 seconds
Started Aug 03 05:24:41 PM PDT 24
Finished Aug 03 05:24:48 PM PDT 24
Peak memory 207040 kb
Host smart-02ac1979-6ccf-4449-a3c6-bbd5f07f9d84
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115198009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3115198009
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.628562830
Short name T903
Test name
Test status
Simulation time 443675706 ps
CPU time 2.54 seconds
Started Aug 03 05:24:40 PM PDT 24
Finished Aug 03 05:24:43 PM PDT 24
Peak memory 206960 kb
Host smart-7bd148f8-b866-4123-941c-f73e1de0e098
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628562830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.628562830
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.421082320
Short name T80
Test name
Test status
Simulation time 37217657 ps
CPU time 2.59 seconds
Started Aug 03 05:24:42 PM PDT 24
Finished Aug 03 05:24:45 PM PDT 24
Peak memory 214312 kb
Host smart-7e910238-07fe-44cc-ab90-e54a2cb9765b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421082320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.421082320
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2359387885
Short name T480
Test name
Test status
Simulation time 97150863 ps
CPU time 2.54 seconds
Started Aug 03 05:24:42 PM PDT 24
Finished Aug 03 05:24:44 PM PDT 24
Peak memory 206784 kb
Host smart-2ab4519c-9c2a-4742-a4df-93cee6dcc67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359387885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2359387885
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.4052304905
Short name T227
Test name
Test status
Simulation time 3728261111 ps
CPU time 31.92 seconds
Started Aug 03 05:24:41 PM PDT 24
Finished Aug 03 05:25:13 PM PDT 24
Peak memory 215592 kb
Host smart-013b9d8d-5b67-4f7b-bbb2-5bf5467dda9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052304905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.4052304905
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2889640933
Short name T398
Test name
Test status
Simulation time 121348394 ps
CPU time 2.79 seconds
Started Aug 03 05:24:38 PM PDT 24
Finished Aug 03 05:24:41 PM PDT 24
Peak memory 207164 kb
Host smart-cef966ed-e642-485b-a565-12752f9f9f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889640933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2889640933
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.876275081
Short name T393
Test name
Test status
Simulation time 338679389 ps
CPU time 2.52 seconds
Started Aug 03 05:24:42 PM PDT 24
Finished Aug 03 05:24:45 PM PDT 24
Peak memory 210292 kb
Host smart-cdf80a2e-708e-48cb-b623-1cad8cec7599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876275081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.876275081
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2540045489
Short name T546
Test name
Test status
Simulation time 124809426 ps
CPU time 0.98 seconds
Started Aug 03 05:24:49 PM PDT 24
Finished Aug 03 05:24:51 PM PDT 24
Peak memory 206068 kb
Host smart-3eb017a5-4910-4cb2-9acc-42095220ed40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540045489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2540045489
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3483786345
Short name T408
Test name
Test status
Simulation time 259039401 ps
CPU time 5.12 seconds
Started Aug 03 05:24:40 PM PDT 24
Finished Aug 03 05:24:45 PM PDT 24
Peak memory 215796 kb
Host smart-fed78b57-a228-4561-831d-8cdd5676af9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3483786345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3483786345
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.599716395
Short name T600
Test name
Test status
Simulation time 572153105 ps
CPU time 5.59 seconds
Started Aug 03 05:24:49 PM PDT 24
Finished Aug 03 05:24:55 PM PDT 24
Peak memory 218172 kb
Host smart-36d89762-7a33-4094-b052-5360345a8457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599716395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.599716395
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.825760465
Short name T473
Test name
Test status
Simulation time 58646324 ps
CPU time 1.95 seconds
Started Aug 03 05:24:41 PM PDT 24
Finished Aug 03 05:24:43 PM PDT 24
Peak memory 208628 kb
Host smart-bccd696d-1694-4663-b32c-05f5105ca529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825760465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.825760465
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.572657633
Short name T874
Test name
Test status
Simulation time 743172929 ps
CPU time 16.44 seconds
Started Aug 03 05:24:47 PM PDT 24
Finished Aug 03 05:25:04 PM PDT 24
Peak memory 209272 kb
Host smart-1496d6f0-057e-44f4-8a76-cc01350bab58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572657633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.572657633
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3110941481
Short name T778
Test name
Test status
Simulation time 88734018 ps
CPU time 3.59 seconds
Started Aug 03 05:24:44 PM PDT 24
Finished Aug 03 05:24:48 PM PDT 24
Peak memory 214196 kb
Host smart-ff5a8e9c-6746-4dbf-a5ee-2f5f4f7edc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110941481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3110941481
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3601917981
Short name T496
Test name
Test status
Simulation time 478850848 ps
CPU time 5.13 seconds
Started Aug 03 05:24:48 PM PDT 24
Finished Aug 03 05:24:53 PM PDT 24
Peak memory 220684 kb
Host smart-da5369b9-6279-4fa8-a538-25fc71b66d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601917981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3601917981
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2089994553
Short name T85
Test name
Test status
Simulation time 81582742 ps
CPU time 3.59 seconds
Started Aug 03 05:24:42 PM PDT 24
Finished Aug 03 05:24:46 PM PDT 24
Peak memory 208132 kb
Host smart-1c812056-3826-4a51-9d8d-80edff6ebe71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089994553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2089994553
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2373952016
Short name T659
Test name
Test status
Simulation time 1488870858 ps
CPU time 8.69 seconds
Started Aug 03 05:24:39 PM PDT 24
Finished Aug 03 05:24:48 PM PDT 24
Peak memory 208736 kb
Host smart-2eb23ad3-a1b2-421f-bbff-d8c8e57349ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373952016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2373952016
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1438317134
Short name T709
Test name
Test status
Simulation time 300654152 ps
CPU time 3.88 seconds
Started Aug 03 05:24:46 PM PDT 24
Finished Aug 03 05:24:50 PM PDT 24
Peak memory 208860 kb
Host smart-f9bfe6ea-8a77-42e7-b7d5-e241ed3390ac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438317134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1438317134
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3176102895
Short name T691
Test name
Test status
Simulation time 169084449 ps
CPU time 5.25 seconds
Started Aug 03 05:24:46 PM PDT 24
Finished Aug 03 05:24:51 PM PDT 24
Peak memory 208716 kb
Host smart-08f9e574-9cf9-49cd-8366-b278aa26d30b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176102895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3176102895
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.20328754
Short name T466
Test name
Test status
Simulation time 35713304 ps
CPU time 2.05 seconds
Started Aug 03 05:24:48 PM PDT 24
Finished Aug 03 05:24:50 PM PDT 24
Peak memory 208044 kb
Host smart-2539a02c-fd06-4bfe-b13a-4d7ba40765f4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20328754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.20328754
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.114295209
Short name T330
Test name
Test status
Simulation time 34428392 ps
CPU time 1.91 seconds
Started Aug 03 05:24:41 PM PDT 24
Finished Aug 03 05:24:43 PM PDT 24
Peak memory 208012 kb
Host smart-33344cd0-eba3-46f9-b38f-85ca966ad71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114295209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.114295209
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.2015588399
Short name T437
Test name
Test status
Simulation time 81046696 ps
CPU time 3.5 seconds
Started Aug 03 05:24:39 PM PDT 24
Finished Aug 03 05:24:43 PM PDT 24
Peak memory 208644 kb
Host smart-64d34670-f0f6-48d6-bfee-195fdede5518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015588399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2015588399
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2292072853
Short name T338
Test name
Test status
Simulation time 996336043 ps
CPU time 12.23 seconds
Started Aug 03 05:24:44 PM PDT 24
Finished Aug 03 05:24:56 PM PDT 24
Peak memory 215260 kb
Host smart-bc3eb06b-69c9-4d70-a829-2c17575c19ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292072853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2292072853
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.4238371191
Short name T343
Test name
Test status
Simulation time 354148022 ps
CPU time 9.37 seconds
Started Aug 03 05:24:42 PM PDT 24
Finished Aug 03 05:24:51 PM PDT 24
Peak memory 222080 kb
Host smart-db97fa5f-d5aa-423a-84bc-66354044e634
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238371191 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.4238371191
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2290014644
Short name T361
Test name
Test status
Simulation time 237767210 ps
CPU time 2.47 seconds
Started Aug 03 05:24:43 PM PDT 24
Finished Aug 03 05:24:46 PM PDT 24
Peak memory 207148 kb
Host smart-234f6e47-8ffd-4f74-b10c-09ff8bb33f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290014644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2290014644
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2052090632
Short name T187
Test name
Test status
Simulation time 226923041 ps
CPU time 4.17 seconds
Started Aug 03 05:24:41 PM PDT 24
Finished Aug 03 05:24:45 PM PDT 24
Peak memory 209792 kb
Host smart-421e2778-b2e8-4635-8505-b6a683bfc739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052090632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2052090632
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2447505780
Short name T561
Test name
Test status
Simulation time 34416339 ps
CPU time 0.78 seconds
Started Aug 03 05:24:43 PM PDT 24
Finished Aug 03 05:24:44 PM PDT 24
Peak memory 205960 kb
Host smart-ebf32898-19fb-484d-b672-c7405aa22c2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447505780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2447505780
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2994403770
Short name T276
Test name
Test status
Simulation time 467127075 ps
CPU time 23.91 seconds
Started Aug 03 05:24:48 PM PDT 24
Finished Aug 03 05:25:13 PM PDT 24
Peak memory 214344 kb
Host smart-44aba107-c852-495b-a0f9-065112b079ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2994403770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2994403770
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1807613150
Short name T869
Test name
Test status
Simulation time 139628372 ps
CPU time 2.55 seconds
Started Aug 03 05:24:49 PM PDT 24
Finished Aug 03 05:24:51 PM PDT 24
Peak memory 214300 kb
Host smart-afacbc8a-12c9-4077-a0bb-5da0cddfe4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807613150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1807613150
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2985121468
Short name T638
Test name
Test status
Simulation time 267481060 ps
CPU time 2.22 seconds
Started Aug 03 05:24:41 PM PDT 24
Finished Aug 03 05:24:44 PM PDT 24
Peak memory 218148 kb
Host smart-1e36f36c-6ac3-4ea8-9a7e-e50960a463c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985121468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2985121468
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3727083055
Short name T94
Test name
Test status
Simulation time 38628027 ps
CPU time 2.61 seconds
Started Aug 03 05:24:44 PM PDT 24
Finished Aug 03 05:24:46 PM PDT 24
Peak memory 220608 kb
Host smart-18afe7e7-4ee6-413a-ac22-aea1ef495f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727083055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3727083055
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2902109422
Short name T837
Test name
Test status
Simulation time 424516558 ps
CPU time 2.64 seconds
Started Aug 03 05:24:38 PM PDT 24
Finished Aug 03 05:24:41 PM PDT 24
Peak memory 214224 kb
Host smart-3e708e0e-86ab-406e-b1f7-5e33dcad295e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902109422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2902109422
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.314507550
Short name T47
Test name
Test status
Simulation time 129224050 ps
CPU time 3.04 seconds
Started Aug 03 05:24:44 PM PDT 24
Finished Aug 03 05:24:47 PM PDT 24
Peak memory 214296 kb
Host smart-c1f914dc-c047-4644-b853-6f123dead4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314507550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.314507550
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.938312047
Short name T370
Test name
Test status
Simulation time 2591965249 ps
CPU time 17.21 seconds
Started Aug 03 05:24:43 PM PDT 24
Finished Aug 03 05:25:00 PM PDT 24
Peak memory 218528 kb
Host smart-337d1832-1697-4d92-b731-7b91e8c631ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938312047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.938312047
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.489989503
Short name T202
Test name
Test status
Simulation time 125455445 ps
CPU time 4.45 seconds
Started Aug 03 05:24:49 PM PDT 24
Finished Aug 03 05:24:54 PM PDT 24
Peak memory 208388 kb
Host smart-111d9f86-6f7e-4f1f-abfe-cc8b51154a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489989503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.489989503
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2420117033
Short name T377
Test name
Test status
Simulation time 140659796 ps
CPU time 3.45 seconds
Started Aug 03 05:24:41 PM PDT 24
Finished Aug 03 05:24:45 PM PDT 24
Peak memory 208560 kb
Host smart-67ebbac2-bcb4-43d8-b68d-046ec3f058ca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420117033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2420117033
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.228537380
Short name T723
Test name
Test status
Simulation time 191067496 ps
CPU time 5.05 seconds
Started Aug 03 05:24:43 PM PDT 24
Finished Aug 03 05:24:48 PM PDT 24
Peak memory 207952 kb
Host smart-8983c061-72c2-45ef-b062-c63dea9aa0f6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228537380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.228537380
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1550115501
Short name T555
Test name
Test status
Simulation time 7193734797 ps
CPU time 49.72 seconds
Started Aug 03 05:24:46 PM PDT 24
Finished Aug 03 05:25:36 PM PDT 24
Peak memory 208612 kb
Host smart-4bdd16fd-d9d7-44ee-a66e-1833c2ce8b02
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550115501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1550115501
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.4101945462
Short name T902
Test name
Test status
Simulation time 175830091 ps
CPU time 5.33 seconds
Started Aug 03 05:24:40 PM PDT 24
Finished Aug 03 05:24:46 PM PDT 24
Peak memory 209404 kb
Host smart-2a65cc7c-8433-4972-98b6-2e31ed25562d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101945462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.4101945462
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.1859305462
Short name T439
Test name
Test status
Simulation time 68300041 ps
CPU time 2.97 seconds
Started Aug 03 05:24:43 PM PDT 24
Finished Aug 03 05:24:46 PM PDT 24
Peak memory 208512 kb
Host smart-41564f4a-add3-42a0-bdd7-515ef511c0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859305462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1859305462
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1471092008
Short name T597
Test name
Test status
Simulation time 3108509226 ps
CPU time 9.43 seconds
Started Aug 03 05:24:48 PM PDT 24
Finished Aug 03 05:24:58 PM PDT 24
Peak memory 210428 kb
Host smart-4779a122-fab0-4e3c-ad96-550b74603b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471092008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1471092008
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1676130236
Short name T748
Test name
Test status
Simulation time 41708120 ps
CPU time 0.87 seconds
Started Aug 03 05:23:19 PM PDT 24
Finished Aug 03 05:23:21 PM PDT 24
Peak memory 205964 kb
Host smart-2df1925d-f53d-4f66-a604-d3b263b5883a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676130236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1676130236
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1040695750
Short name T315
Test name
Test status
Simulation time 479357695 ps
CPU time 4.68 seconds
Started Aug 03 05:23:20 PM PDT 24
Finished Aug 03 05:23:25 PM PDT 24
Peak memory 215388 kb
Host smart-8998b91f-e62c-4ece-b41e-652d8c8a1206
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1040695750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1040695750
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1869276696
Short name T468
Test name
Test status
Simulation time 298984193 ps
CPU time 2.54 seconds
Started Aug 03 05:23:19 PM PDT 24
Finished Aug 03 05:23:22 PM PDT 24
Peak memory 207536 kb
Host smart-acf4f312-c642-4d92-a91f-d7d4713ffe25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869276696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1869276696
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3078835471
Short name T95
Test name
Test status
Simulation time 311788985 ps
CPU time 5.58 seconds
Started Aug 03 05:23:20 PM PDT 24
Finished Aug 03 05:23:26 PM PDT 24
Peak memory 214376 kb
Host smart-3f410844-2f83-4d4f-b164-41dcd6198746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078835471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3078835471
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.4177746047
Short name T835
Test name
Test status
Simulation time 439493339 ps
CPU time 5.51 seconds
Started Aug 03 05:23:18 PM PDT 24
Finished Aug 03 05:23:24 PM PDT 24
Peak memory 222396 kb
Host smart-0d301884-4324-47e6-9f6e-775582d00953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177746047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.4177746047
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2631912608
Short name T628
Test name
Test status
Simulation time 1392607785 ps
CPU time 4.29 seconds
Started Aug 03 05:23:25 PM PDT 24
Finished Aug 03 05:23:30 PM PDT 24
Peak memory 219940 kb
Host smart-37ef1218-86fd-405e-b19a-ef7274ab872a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631912608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2631912608
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.1081073683
Short name T509
Test name
Test status
Simulation time 275683929 ps
CPU time 7.51 seconds
Started Aug 03 05:23:25 PM PDT 24
Finished Aug 03 05:23:32 PM PDT 24
Peak memory 214312 kb
Host smart-4d52b7dc-1428-46ad-a0f8-9ad867cd189a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081073683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1081073683
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1734412083
Short name T475
Test name
Test status
Simulation time 87693477 ps
CPU time 3.77 seconds
Started Aug 03 05:23:19 PM PDT 24
Finished Aug 03 05:23:23 PM PDT 24
Peak memory 206948 kb
Host smart-6ad8a220-6370-47b2-83a5-b36bde53bedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734412083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1734412083
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.4090472886
Short name T233
Test name
Test status
Simulation time 150202023 ps
CPU time 3.18 seconds
Started Aug 03 05:23:21 PM PDT 24
Finished Aug 03 05:23:24 PM PDT 24
Peak memory 208628 kb
Host smart-27d68f8c-9359-449a-8a81-1346b7c1ff87
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090472886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.4090472886
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.4192484936
Short name T827
Test name
Test status
Simulation time 29689233 ps
CPU time 2.12 seconds
Started Aug 03 05:23:18 PM PDT 24
Finished Aug 03 05:23:20 PM PDT 24
Peak memory 208816 kb
Host smart-d8b57b0b-0e3b-4a0a-a5c9-0e1367a7b489
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192484936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.4192484936
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.4174586645
Short name T111
Test name
Test status
Simulation time 777176339 ps
CPU time 8.84 seconds
Started Aug 03 05:23:19 PM PDT 24
Finished Aug 03 05:23:28 PM PDT 24
Peak memory 206944 kb
Host smart-a7310716-423a-47de-97aa-d3a59a767b54
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174586645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.4174586645
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.74280506
Short name T839
Test name
Test status
Simulation time 949772405 ps
CPU time 4.03 seconds
Started Aug 03 05:23:25 PM PDT 24
Finished Aug 03 05:23:29 PM PDT 24
Peak memory 214228 kb
Host smart-4224faeb-82ab-4586-963e-3064c55b4947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74280506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.74280506
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3574831345
Short name T765
Test name
Test status
Simulation time 464822434 ps
CPU time 3.77 seconds
Started Aug 03 05:23:19 PM PDT 24
Finished Aug 03 05:23:22 PM PDT 24
Peak memory 207028 kb
Host smart-c670b737-baba-4083-b9fc-37a040a6d93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574831345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3574831345
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2379474835
Short name T219
Test name
Test status
Simulation time 2721980312 ps
CPU time 20.52 seconds
Started Aug 03 05:23:21 PM PDT 24
Finished Aug 03 05:23:41 PM PDT 24
Peak memory 215868 kb
Host smart-21fdfc40-92fc-4879-ad22-d52961cd193a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379474835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2379474835
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.4193440949
Short name T198
Test name
Test status
Simulation time 448145006 ps
CPU time 4.13 seconds
Started Aug 03 05:23:20 PM PDT 24
Finished Aug 03 05:23:25 PM PDT 24
Peak memory 207536 kb
Host smart-81d8fa6c-a001-4016-8300-2e0be22af59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193440949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.4193440949
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2863019181
Short name T42
Test name
Test status
Simulation time 665875031 ps
CPU time 2.4 seconds
Started Aug 03 05:23:18 PM PDT 24
Finished Aug 03 05:23:20 PM PDT 24
Peak memory 210252 kb
Host smart-fd6ca006-c9b6-46b7-b7de-f42ad5184bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863019181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2863019181
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.425539907
Short name T617
Test name
Test status
Simulation time 8688046 ps
CPU time 0.71 seconds
Started Aug 03 05:24:44 PM PDT 24
Finished Aug 03 05:24:45 PM PDT 24
Peak memory 205916 kb
Host smart-616bf96f-2c5b-4e7a-9b2f-d6a870ac781e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425539907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.425539907
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.3946250430
Short name T848
Test name
Test status
Simulation time 116742072 ps
CPU time 2.71 seconds
Started Aug 03 05:24:45 PM PDT 24
Finished Aug 03 05:24:48 PM PDT 24
Peak memory 214320 kb
Host smart-9ae2c27d-c5e1-4ffe-b709-c21f540451f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3946250430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3946250430
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.4119222564
Short name T770
Test name
Test status
Simulation time 144753276 ps
CPU time 2.36 seconds
Started Aug 03 05:24:48 PM PDT 24
Finished Aug 03 05:24:51 PM PDT 24
Peak memory 208364 kb
Host smart-4071896a-723c-447a-a1fe-84838c54bb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119222564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.4119222564
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2518537559
Short name T830
Test name
Test status
Simulation time 791061083 ps
CPU time 2.69 seconds
Started Aug 03 05:24:44 PM PDT 24
Finished Aug 03 05:24:47 PM PDT 24
Peak memory 208496 kb
Host smart-70748d63-47f9-419e-b9e0-f796079b7991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518537559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2518537559
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.830871801
Short name T834
Test name
Test status
Simulation time 347386924 ps
CPU time 2.8 seconds
Started Aug 03 05:24:45 PM PDT 24
Finished Aug 03 05:24:48 PM PDT 24
Peak memory 214316 kb
Host smart-74c21c3f-633b-4098-a87a-f4577532d6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830871801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.830871801
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2531892776
Short name T666
Test name
Test status
Simulation time 50671017 ps
CPU time 1.98 seconds
Started Aug 03 05:24:46 PM PDT 24
Finished Aug 03 05:24:48 PM PDT 24
Peak memory 214240 kb
Host smart-b4bce4d7-ec9b-45ba-80bd-e1a9b1e0352c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531892776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2531892776
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2799229150
Short name T225
Test name
Test status
Simulation time 140049836 ps
CPU time 5.5 seconds
Started Aug 03 05:24:45 PM PDT 24
Finished Aug 03 05:24:51 PM PDT 24
Peak memory 209924 kb
Host smart-949c126a-2398-4657-9402-e8dca22b4787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799229150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2799229150
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1690191851
Short name T897
Test name
Test status
Simulation time 161827264 ps
CPU time 5.02 seconds
Started Aug 03 05:24:47 PM PDT 24
Finished Aug 03 05:24:52 PM PDT 24
Peak memory 207916 kb
Host smart-09216cf2-00f8-4fba-b750-6285d0f2e5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690191851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1690191851
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2565763500
Short name T687
Test name
Test status
Simulation time 1072674571 ps
CPU time 7.79 seconds
Started Aug 03 05:24:44 PM PDT 24
Finished Aug 03 05:24:52 PM PDT 24
Peak memory 208940 kb
Host smart-592f101b-f892-474d-8283-ebaddd99c003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565763500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2565763500
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.4067975162
Short name T741
Test name
Test status
Simulation time 119472681 ps
CPU time 3.13 seconds
Started Aug 03 05:24:45 PM PDT 24
Finished Aug 03 05:24:48 PM PDT 24
Peak memory 206868 kb
Host smart-2c0f7b2a-1afc-4235-be90-5af98ead325e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067975162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.4067975162
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1092555008
Short name T506
Test name
Test status
Simulation time 47633989 ps
CPU time 2.04 seconds
Started Aug 03 05:24:48 PM PDT 24
Finished Aug 03 05:24:51 PM PDT 24
Peak memory 208516 kb
Host smart-b7f94a9b-f2a2-4614-bc2c-7b4b7af6f0ae
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092555008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1092555008
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3010627227
Short name T641
Test name
Test status
Simulation time 48514225 ps
CPU time 2.75 seconds
Started Aug 03 05:24:45 PM PDT 24
Finished Aug 03 05:24:48 PM PDT 24
Peak memory 216068 kb
Host smart-cb044989-3e54-4214-b8f0-6bffa00b6611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010627227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3010627227
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2171612467
Short name T432
Test name
Test status
Simulation time 472839491 ps
CPU time 4.71 seconds
Started Aug 03 05:24:40 PM PDT 24
Finished Aug 03 05:24:45 PM PDT 24
Peak memory 208276 kb
Host smart-aa7aa5b8-c3a5-4fa2-8d03-cc5bc0f6a86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171612467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2171612467
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1316192619
Short name T850
Test name
Test status
Simulation time 196050196 ps
CPU time 6.68 seconds
Started Aug 03 05:24:45 PM PDT 24
Finished Aug 03 05:24:52 PM PDT 24
Peak memory 218384 kb
Host smart-ccc6515b-50a3-477d-90c3-96698fa89e6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316192619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1316192619
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.75688406
Short name T180
Test name
Test status
Simulation time 321615839 ps
CPU time 11.91 seconds
Started Aug 03 05:24:45 PM PDT 24
Finished Aug 03 05:24:57 PM PDT 24
Peak memory 219236 kb
Host smart-a96d5027-fc8e-4c44-9305-522d9af3cb0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75688406 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.75688406
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2080778821
Short name T784
Test name
Test status
Simulation time 971256733 ps
CPU time 7.79 seconds
Started Aug 03 05:24:50 PM PDT 24
Finished Aug 03 05:24:58 PM PDT 24
Peak memory 209028 kb
Host smart-4fa8b105-6c95-4e6f-9546-46a609a6c98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080778821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2080778821
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3622726754
Short name T745
Test name
Test status
Simulation time 134125360 ps
CPU time 3.78 seconds
Started Aug 03 05:24:44 PM PDT 24
Finished Aug 03 05:24:48 PM PDT 24
Peak memory 214296 kb
Host smart-d08a6cd9-2b8f-4aeb-bcfa-529ddddc95c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622726754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3622726754
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1515467292
Short name T453
Test name
Test status
Simulation time 31534931 ps
CPU time 0.78 seconds
Started Aug 03 05:24:48 PM PDT 24
Finished Aug 03 05:24:49 PM PDT 24
Peak memory 205944 kb
Host smart-faf7714f-c2ca-4057-882d-7e1685704377
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515467292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1515467292
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2981811995
Short name T31
Test name
Test status
Simulation time 74222221 ps
CPU time 3.17 seconds
Started Aug 03 05:24:45 PM PDT 24
Finished Aug 03 05:24:49 PM PDT 24
Peak memory 208948 kb
Host smart-1657694b-785d-4ae1-bb3b-42fc5bf38ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981811995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2981811995
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3705447070
Short name T76
Test name
Test status
Simulation time 62341811 ps
CPU time 2.07 seconds
Started Aug 03 05:24:47 PM PDT 24
Finished Aug 03 05:24:50 PM PDT 24
Peak memory 206824 kb
Host smart-0d4e03ea-4379-4caf-8017-2df4d68e931a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705447070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3705447070
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1995849480
Short name T526
Test name
Test status
Simulation time 55805875 ps
CPU time 1.95 seconds
Started Aug 03 05:24:49 PM PDT 24
Finished Aug 03 05:24:51 PM PDT 24
Peak memory 222332 kb
Host smart-c0e3f527-a754-4519-b2c7-ae4439ed872e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995849480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1995849480
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.639582641
Short name T485
Test name
Test status
Simulation time 70138532 ps
CPU time 3.73 seconds
Started Aug 03 05:24:48 PM PDT 24
Finished Aug 03 05:24:51 PM PDT 24
Peak memory 220600 kb
Host smart-34a35652-6bd0-40c4-b086-3d9edaaa9cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639582641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.639582641
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.511668423
Short name T266
Test name
Test status
Simulation time 161830084 ps
CPU time 5.09 seconds
Started Aug 03 05:24:46 PM PDT 24
Finished Aug 03 05:24:52 PM PDT 24
Peak memory 208684 kb
Host smart-ec7dbc89-5668-48d2-af15-fbbfb8f8d746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511668423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.511668423
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.4216609087
Short name T478
Test name
Test status
Simulation time 5304525716 ps
CPU time 17.53 seconds
Started Aug 03 05:24:49 PM PDT 24
Finished Aug 03 05:25:07 PM PDT 24
Peak memory 208572 kb
Host smart-a701e3e1-d501-42be-85cf-32ca483a9ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216609087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.4216609087
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1666357073
Short name T819
Test name
Test status
Simulation time 201523244 ps
CPU time 2.62 seconds
Started Aug 03 05:24:50 PM PDT 24
Finished Aug 03 05:24:52 PM PDT 24
Peak memory 206936 kb
Host smart-035f8135-c866-4b3d-9098-69f4d368aa2b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666357073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1666357073
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.4281613400
Short name T130
Test name
Test status
Simulation time 103988959 ps
CPU time 4.03 seconds
Started Aug 03 05:24:46 PM PDT 24
Finished Aug 03 05:24:50 PM PDT 24
Peak memory 208868 kb
Host smart-5eaa893a-e423-414b-b9e1-b6cd1b8f7bbd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281613400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.4281613400
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2779193452
Short name T521
Test name
Test status
Simulation time 4704081712 ps
CPU time 35.26 seconds
Started Aug 03 05:24:49 PM PDT 24
Finished Aug 03 05:25:24 PM PDT 24
Peak memory 208500 kb
Host smart-9db0e999-cf10-4387-bbbb-27ac9a92e621
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779193452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2779193452
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.146930339
Short name T852
Test name
Test status
Simulation time 352277783 ps
CPU time 2.75 seconds
Started Aug 03 05:24:44 PM PDT 24
Finished Aug 03 05:24:47 PM PDT 24
Peak memory 214300 kb
Host smart-7a69b7e9-e385-4ac1-9cd6-8abb40facb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146930339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.146930339
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1511689685
Short name T560
Test name
Test status
Simulation time 67536644 ps
CPU time 2.65 seconds
Started Aug 03 05:24:51 PM PDT 24
Finished Aug 03 05:24:54 PM PDT 24
Peak memory 206808 kb
Host smart-d864d157-10d0-4fcf-b08f-2fb6e721ea71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511689685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1511689685
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.2022252987
Short name T154
Test name
Test status
Simulation time 1152686646 ps
CPU time 14.07 seconds
Started Aug 03 05:24:44 PM PDT 24
Finished Aug 03 05:24:58 PM PDT 24
Peak memory 219824 kb
Host smart-d74aa0aa-826f-498c-a242-dad3a6b7b126
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022252987 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.2022252987
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2669083892
Short name T908
Test name
Test status
Simulation time 333900726 ps
CPU time 4.69 seconds
Started Aug 03 05:24:48 PM PDT 24
Finished Aug 03 05:24:52 PM PDT 24
Peak memory 208636 kb
Host smart-2c32e764-7319-44e7-9d36-9a5b2780738a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669083892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2669083892
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3878520322
Short name T539
Test name
Test status
Simulation time 50190407 ps
CPU time 1.67 seconds
Started Aug 03 05:24:51 PM PDT 24
Finished Aug 03 05:24:53 PM PDT 24
Peak memory 210020 kb
Host smart-077232b8-df9a-47d2-9eff-0ad4f77a4289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878520322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3878520322
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.4192402732
Short name T518
Test name
Test status
Simulation time 31081230 ps
CPU time 0.8 seconds
Started Aug 03 05:24:55 PM PDT 24
Finished Aug 03 05:24:55 PM PDT 24
Peak memory 205968 kb
Host smart-ed7f70c5-d524-43b4-b8eb-5821c9083c45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192402732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.4192402732
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3610053169
Short name T20
Test name
Test status
Simulation time 51882145 ps
CPU time 1.54 seconds
Started Aug 03 05:24:50 PM PDT 24
Finished Aug 03 05:24:52 PM PDT 24
Peak memory 215628 kb
Host smart-956db157-659b-485b-b476-41445441712b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610053169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3610053169
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.4054872911
Short name T544
Test name
Test status
Simulation time 205469431 ps
CPU time 3.61 seconds
Started Aug 03 05:24:47 PM PDT 24
Finished Aug 03 05:24:51 PM PDT 24
Peak memory 207948 kb
Host smart-637ebc34-c143-4209-94e8-045d5c03e23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054872911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.4054872911
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.407256059
Short name T589
Test name
Test status
Simulation time 335871975 ps
CPU time 8.13 seconds
Started Aug 03 05:24:51 PM PDT 24
Finished Aug 03 05:25:00 PM PDT 24
Peak memory 214344 kb
Host smart-8966e7a8-dfb4-420c-92ff-599069d88e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407256059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.407256059
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2725571863
Short name T324
Test name
Test status
Simulation time 44130938 ps
CPU time 2.88 seconds
Started Aug 03 05:24:51 PM PDT 24
Finished Aug 03 05:24:54 PM PDT 24
Peak memory 214156 kb
Host smart-45e68462-f7ac-4872-a335-9c4dbc2c876f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725571863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2725571863
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3270122035
Short name T68
Test name
Test status
Simulation time 1463028418 ps
CPU time 4.31 seconds
Started Aug 03 05:24:45 PM PDT 24
Finished Aug 03 05:24:49 PM PDT 24
Peak memory 214384 kb
Host smart-c22bc783-8674-422e-8dfc-6492d4d18ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270122035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3270122035
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3429481671
Short name T415
Test name
Test status
Simulation time 70304255 ps
CPU time 2.86 seconds
Started Aug 03 05:24:46 PM PDT 24
Finished Aug 03 05:24:49 PM PDT 24
Peak memory 214204 kb
Host smart-efdaa846-3ce9-4b23-9274-13d3d78c8f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429481671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3429481671
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1947021916
Short name T856
Test name
Test status
Simulation time 87247106 ps
CPU time 1.95 seconds
Started Aug 03 05:24:49 PM PDT 24
Finished Aug 03 05:24:51 PM PDT 24
Peak memory 208472 kb
Host smart-3336fd32-02ff-4c52-ae6b-072a35dd129d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947021916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1947021916
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3767776684
Short name T428
Test name
Test status
Simulation time 3017213463 ps
CPU time 28.04 seconds
Started Aug 03 05:24:49 PM PDT 24
Finished Aug 03 05:25:17 PM PDT 24
Peak memory 208516 kb
Host smart-7c7fc128-c3b4-40e5-b1c0-7092a6bca175
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767776684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3767776684
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1691122361
Short name T685
Test name
Test status
Simulation time 1300550685 ps
CPU time 12.19 seconds
Started Aug 03 05:24:49 PM PDT 24
Finished Aug 03 05:25:02 PM PDT 24
Peak memory 208936 kb
Host smart-578ce53c-f9bb-4cfc-9719-9f3dfc794999
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691122361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1691122361
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3826371984
Short name T667
Test name
Test status
Simulation time 53924547 ps
CPU time 3.03 seconds
Started Aug 03 05:24:45 PM PDT 24
Finished Aug 03 05:24:48 PM PDT 24
Peak memory 208908 kb
Host smart-5e2b1f31-b258-4fd9-bedd-415d34124e56
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826371984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3826371984
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.28093362
Short name T270
Test name
Test status
Simulation time 2218033491 ps
CPU time 3.8 seconds
Started Aug 03 05:24:54 PM PDT 24
Finished Aug 03 05:24:58 PM PDT 24
Peak memory 209804 kb
Host smart-e5d7828e-6ffa-4722-ac97-b0e7ab2aadd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28093362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.28093362
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3693937236
Short name T456
Test name
Test status
Simulation time 2702837439 ps
CPU time 21.16 seconds
Started Aug 03 05:24:49 PM PDT 24
Finished Aug 03 05:25:10 PM PDT 24
Peak memory 208436 kb
Host smart-8a4f0635-2b50-4a6d-acba-7cbfb0334344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693937236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3693937236
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.244894835
Short name T218
Test name
Test status
Simulation time 1214445433 ps
CPU time 16.72 seconds
Started Aug 03 05:24:51 PM PDT 24
Finished Aug 03 05:25:08 PM PDT 24
Peak memory 215032 kb
Host smart-24a02708-507c-4aa9-a3a1-3b21fde6696a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244894835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.244894835
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3760326521
Short name T689
Test name
Test status
Simulation time 988539590 ps
CPU time 5.7 seconds
Started Aug 03 05:24:44 PM PDT 24
Finished Aug 03 05:24:50 PM PDT 24
Peak memory 207560 kb
Host smart-018c6085-feea-48b0-844c-ba281b20136a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760326521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3760326521
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.913564659
Short name T465
Test name
Test status
Simulation time 375715702 ps
CPU time 3.51 seconds
Started Aug 03 05:24:52 PM PDT 24
Finished Aug 03 05:24:56 PM PDT 24
Peak memory 210016 kb
Host smart-cc4995b9-d7be-4804-a942-fd2ad93c922c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913564659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.913564659
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1187911807
Short name T892
Test name
Test status
Simulation time 18293291 ps
CPU time 1.01 seconds
Started Aug 03 05:24:51 PM PDT 24
Finished Aug 03 05:24:52 PM PDT 24
Peak memory 206180 kb
Host smart-5a19a3bf-2cf3-4d43-a4af-0368600caf2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187911807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1187911807
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2105568197
Short name T357
Test name
Test status
Simulation time 83198399 ps
CPU time 2.09 seconds
Started Aug 03 05:24:52 PM PDT 24
Finished Aug 03 05:24:54 PM PDT 24
Peak memory 209040 kb
Host smart-ed4a791e-d2dd-49ed-8de9-d14c61106adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105568197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2105568197
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1324949493
Short name T870
Test name
Test status
Simulation time 4920821126 ps
CPU time 50.94 seconds
Started Aug 03 05:24:51 PM PDT 24
Finished Aug 03 05:25:42 PM PDT 24
Peak memory 220716 kb
Host smart-9988c493-4e99-4b65-9114-c2ff02cee7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324949493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1324949493
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3024111356
Short name T267
Test name
Test status
Simulation time 52216168 ps
CPU time 2.98 seconds
Started Aug 03 05:24:55 PM PDT 24
Finished Aug 03 05:24:58 PM PDT 24
Peak memory 222364 kb
Host smart-e32aaed5-3d17-484a-8fbd-337d138d16f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024111356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3024111356
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2543499482
Short name T790
Test name
Test status
Simulation time 57389260 ps
CPU time 2.86 seconds
Started Aug 03 05:24:51 PM PDT 24
Finished Aug 03 05:24:54 PM PDT 24
Peak memory 208804 kb
Host smart-c4149281-ab4e-4e15-aa6d-3a05523d3630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543499482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2543499482
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2796930414
Short name T520
Test name
Test status
Simulation time 153894415 ps
CPU time 6.36 seconds
Started Aug 03 05:24:51 PM PDT 24
Finished Aug 03 05:24:57 PM PDT 24
Peak memory 208460 kb
Host smart-942cdae0-0528-4bca-8f67-323914d3aec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796930414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2796930414
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2703851306
Short name T547
Test name
Test status
Simulation time 186032222 ps
CPU time 2.91 seconds
Started Aug 03 05:24:49 PM PDT 24
Finished Aug 03 05:24:52 PM PDT 24
Peak memory 206744 kb
Host smart-aab30bf8-ace8-4fd8-bf1e-08c694ef418e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703851306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2703851306
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.911360926
Short name T438
Test name
Test status
Simulation time 1243939818 ps
CPU time 8.91 seconds
Started Aug 03 05:24:52 PM PDT 24
Finished Aug 03 05:25:01 PM PDT 24
Peak memory 207920 kb
Host smart-a47f501d-7695-4534-a619-6050e6238e97
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911360926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.911360926
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3551159383
Short name T476
Test name
Test status
Simulation time 5201340387 ps
CPU time 34.81 seconds
Started Aug 03 05:24:50 PM PDT 24
Finished Aug 03 05:25:25 PM PDT 24
Peak memory 208716 kb
Host smart-d58009bd-19cd-4ed2-badb-f7a55488c8bd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551159383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3551159383
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.4237314627
Short name T783
Test name
Test status
Simulation time 283970756 ps
CPU time 3.2 seconds
Started Aug 03 05:24:52 PM PDT 24
Finished Aug 03 05:24:56 PM PDT 24
Peak memory 208676 kb
Host smart-63ce9b1a-de53-4e6e-8ab0-b790a280e71e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237314627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.4237314627
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.847146742
Short name T703
Test name
Test status
Simulation time 303381243 ps
CPU time 4.52 seconds
Started Aug 03 05:24:50 PM PDT 24
Finished Aug 03 05:24:54 PM PDT 24
Peak memory 207888 kb
Host smart-e68b6afc-db48-4b3e-a832-3b5d6906c721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847146742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.847146742
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2934337398
Short name T900
Test name
Test status
Simulation time 150135813 ps
CPU time 5.09 seconds
Started Aug 03 05:24:55 PM PDT 24
Finished Aug 03 05:25:00 PM PDT 24
Peak memory 208340 kb
Host smart-12c33384-25e9-42f4-956a-161b180e9a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934337398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2934337398
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1069261612
Short name T759
Test name
Test status
Simulation time 620627097 ps
CPU time 8.16 seconds
Started Aug 03 05:24:53 PM PDT 24
Finished Aug 03 05:25:01 PM PDT 24
Peak memory 214972 kb
Host smart-faaaff65-a03a-447e-bb63-c3d5359cb072
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069261612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1069261612
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.2085302580
Short name T298
Test name
Test status
Simulation time 794008699 ps
CPU time 11.1 seconds
Started Aug 03 05:24:52 PM PDT 24
Finished Aug 03 05:25:03 PM PDT 24
Peak memory 222556 kb
Host smart-fcb45c7b-39eb-4b26-b8c9-b52a97fada2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085302580 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.2085302580
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3224588102
Short name T296
Test name
Test status
Simulation time 483776879 ps
CPU time 5.77 seconds
Started Aug 03 05:24:49 PM PDT 24
Finished Aug 03 05:24:55 PM PDT 24
Peak memory 210276 kb
Host smart-5c2b74a1-0221-45f4-9159-4cbe2cb035a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224588102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3224588102
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.156989761
Short name T467
Test name
Test status
Simulation time 155276915 ps
CPU time 1.72 seconds
Started Aug 03 05:24:53 PM PDT 24
Finished Aug 03 05:24:55 PM PDT 24
Peak memory 210408 kb
Host smart-789375d1-bf82-4bad-843c-9488a605bb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156989761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.156989761
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.27371230
Short name T498
Test name
Test status
Simulation time 58979314 ps
CPU time 1.01 seconds
Started Aug 03 05:24:57 PM PDT 24
Finished Aug 03 05:24:58 PM PDT 24
Peak memory 206096 kb
Host smart-8a1e70ae-2f61-4110-8582-e496e46834f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27371230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.27371230
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2344661887
Short name T417
Test name
Test status
Simulation time 155546689 ps
CPU time 3.16 seconds
Started Aug 03 05:24:49 PM PDT 24
Finished Aug 03 05:24:53 PM PDT 24
Peak memory 222464 kb
Host smart-8dce36cb-e67c-48c8-a55c-19bfe00ceace
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2344661887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2344661887
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3157945563
Short name T717
Test name
Test status
Simulation time 906696406 ps
CPU time 6.25 seconds
Started Aug 03 05:24:54 PM PDT 24
Finished Aug 03 05:25:00 PM PDT 24
Peak memory 214508 kb
Host smart-4e090b83-8bb6-49c7-9b2f-391881e3ff12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157945563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3157945563
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3843032224
Short name T72
Test name
Test status
Simulation time 2207141864 ps
CPU time 10.51 seconds
Started Aug 03 05:24:54 PM PDT 24
Finished Aug 03 05:25:04 PM PDT 24
Peak memory 209188 kb
Host smart-329710e6-4ef5-4711-a80a-2f6a821d5a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843032224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3843032224
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2179426389
Short name T290
Test name
Test status
Simulation time 650657416 ps
CPU time 3.87 seconds
Started Aug 03 05:24:55 PM PDT 24
Finished Aug 03 05:24:58 PM PDT 24
Peak memory 214860 kb
Host smart-415e7bb0-c6db-45b7-aefd-cf4c2c2f4c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179426389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2179426389
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3802259085
Short name T601
Test name
Test status
Simulation time 188026479 ps
CPU time 1.96 seconds
Started Aug 03 05:24:50 PM PDT 24
Finished Aug 03 05:24:53 PM PDT 24
Peak memory 220776 kb
Host smart-44413b1d-0da8-4bf9-9f83-316c2e3e7aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802259085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3802259085
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2616661938
Short name T46
Test name
Test status
Simulation time 511452581 ps
CPU time 3.8 seconds
Started Aug 03 05:24:51 PM PDT 24
Finished Aug 03 05:24:55 PM PDT 24
Peak memory 207772 kb
Host smart-b9fc7c53-bc08-4628-a911-72571318b03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616661938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2616661938
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.200963864
Short name T764
Test name
Test status
Simulation time 2679739667 ps
CPU time 14.37 seconds
Started Aug 03 05:24:50 PM PDT 24
Finished Aug 03 05:25:04 PM PDT 24
Peak memory 209744 kb
Host smart-b3dbe858-248a-4c2d-82c9-c7613987f92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200963864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.200963864
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3999259032
Short name T576
Test name
Test status
Simulation time 34640007 ps
CPU time 2.37 seconds
Started Aug 03 05:24:52 PM PDT 24
Finished Aug 03 05:24:55 PM PDT 24
Peak memory 206760 kb
Host smart-1dadc444-1f0d-4eda-9570-a91ae5d12756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999259032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3999259032
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2599300044
Short name T706
Test name
Test status
Simulation time 133837158 ps
CPU time 2.67 seconds
Started Aug 03 05:24:52 PM PDT 24
Finished Aug 03 05:24:55 PM PDT 24
Peak memory 206820 kb
Host smart-f7a94c24-af3e-477b-a6f4-b9a60f0e7f3d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599300044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2599300044
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3073122895
Short name T696
Test name
Test status
Simulation time 118021558 ps
CPU time 3.62 seconds
Started Aug 03 05:24:52 PM PDT 24
Finished Aug 03 05:24:55 PM PDT 24
Peak memory 208440 kb
Host smart-63c7a181-d911-4dc5-85fc-ea5b4d1cf457
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073122895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3073122895
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.340632360
Short name T847
Test name
Test status
Simulation time 51170503 ps
CPU time 2.55 seconds
Started Aug 03 05:24:55 PM PDT 24
Finished Aug 03 05:24:58 PM PDT 24
Peak memory 208160 kb
Host smart-f1142f34-b9dd-4653-8cd5-3d8b45bc27ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340632360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.340632360
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.316619127
Short name T886
Test name
Test status
Simulation time 1391344211 ps
CPU time 10.19 seconds
Started Aug 03 05:24:53 PM PDT 24
Finished Aug 03 05:25:03 PM PDT 24
Peak memory 218192 kb
Host smart-00a5701b-1a4d-4d28-a92d-cb4ed8b79004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316619127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.316619127
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.148172162
Short name T818
Test name
Test status
Simulation time 689803023 ps
CPU time 4.31 seconds
Started Aug 03 05:24:52 PM PDT 24
Finished Aug 03 05:24:57 PM PDT 24
Peak memory 208672 kb
Host smart-d4a506b1-5844-4af6-9e21-a3771a7c6c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148172162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.148172162
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2050964660
Short name T208
Test name
Test status
Simulation time 347403090 ps
CPU time 4.19 seconds
Started Aug 03 05:24:53 PM PDT 24
Finished Aug 03 05:24:58 PM PDT 24
Peak memory 209740 kb
Host smart-b928b4b2-2296-4870-98e9-633d078b76fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050964660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2050964660
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.183958924
Short name T5
Test name
Test status
Simulation time 460808085 ps
CPU time 4.22 seconds
Started Aug 03 05:24:53 PM PDT 24
Finished Aug 03 05:24:57 PM PDT 24
Peak memory 210316 kb
Host smart-0cd2ef55-b804-43ca-8e0d-ec43ece1c291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183958924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.183958924
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.649214429
Short name T807
Test name
Test status
Simulation time 16436802 ps
CPU time 0.77 seconds
Started Aug 03 05:24:57 PM PDT 24
Finished Aug 03 05:24:58 PM PDT 24
Peak memory 205940 kb
Host smart-fc4dae53-2ad5-4f3b-9183-addedea13ac7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649214429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.649214429
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.808706235
Short name T27
Test name
Test status
Simulation time 275608209 ps
CPU time 2.95 seconds
Started Aug 03 05:25:01 PM PDT 24
Finished Aug 03 05:25:04 PM PDT 24
Peak memory 210208 kb
Host smart-8de31d79-72de-4571-b22b-a862c3b1ae81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808706235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.808706235
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.668769722
Short name T888
Test name
Test status
Simulation time 159894287 ps
CPU time 4.81 seconds
Started Aug 03 05:24:58 PM PDT 24
Finished Aug 03 05:25:02 PM PDT 24
Peak memory 209324 kb
Host smart-08a9b5a5-9943-4294-821d-6662bbd140bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668769722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.668769722
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1122820250
Short name T619
Test name
Test status
Simulation time 417453539 ps
CPU time 3.13 seconds
Started Aug 03 05:24:58 PM PDT 24
Finished Aug 03 05:25:01 PM PDT 24
Peak memory 214312 kb
Host smart-f8b7af0d-705b-45c4-9429-4d6f6116e82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122820250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1122820250
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1356777577
Short name T364
Test name
Test status
Simulation time 110913481 ps
CPU time 2.74 seconds
Started Aug 03 05:24:57 PM PDT 24
Finished Aug 03 05:24:59 PM PDT 24
Peak memory 214184 kb
Host smart-b9391b89-78d9-4da1-8c3e-006092528a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356777577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1356777577
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2854230225
Short name T559
Test name
Test status
Simulation time 345567685 ps
CPU time 3.32 seconds
Started Aug 03 05:25:01 PM PDT 24
Finished Aug 03 05:25:05 PM PDT 24
Peak memory 222520 kb
Host smart-f217a2df-0df7-4435-b24d-7d9be638b655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854230225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2854230225
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.679531373
Short name T794
Test name
Test status
Simulation time 111161649 ps
CPU time 4.1 seconds
Started Aug 03 05:24:58 PM PDT 24
Finished Aug 03 05:25:02 PM PDT 24
Peak memory 208976 kb
Host smart-6360b1af-198e-4dc9-997f-683f5fbce05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679531373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.679531373
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1303868689
Short name T523
Test name
Test status
Simulation time 121235972 ps
CPU time 3.23 seconds
Started Aug 03 05:24:59 PM PDT 24
Finished Aug 03 05:25:02 PM PDT 24
Peak memory 208900 kb
Host smart-5d06ef74-1c1c-42a5-af5f-0b9af6c72239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303868689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1303868689
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3037602385
Short name T695
Test name
Test status
Simulation time 1418825331 ps
CPU time 20.15 seconds
Started Aug 03 05:24:59 PM PDT 24
Finished Aug 03 05:25:19 PM PDT 24
Peak memory 206992 kb
Host smart-9a8f2049-6628-43dd-8b02-0cb102783817
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037602385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3037602385
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2139330140
Short name T639
Test name
Test status
Simulation time 322470059 ps
CPU time 3.11 seconds
Started Aug 03 05:25:02 PM PDT 24
Finished Aug 03 05:25:05 PM PDT 24
Peak memory 208484 kb
Host smart-b7852003-a505-4914-87e6-eedd367db21e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139330140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2139330140
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.355173132
Short name T567
Test name
Test status
Simulation time 951505994 ps
CPU time 8.44 seconds
Started Aug 03 05:25:00 PM PDT 24
Finished Aug 03 05:25:09 PM PDT 24
Peak memory 208720 kb
Host smart-1ad0dedb-6030-472c-a2cc-eed9c45a0764
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355173132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.355173132
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3594210159
Short name T657
Test name
Test status
Simulation time 206515591 ps
CPU time 2.82 seconds
Started Aug 03 05:24:59 PM PDT 24
Finished Aug 03 05:25:02 PM PDT 24
Peak memory 209284 kb
Host smart-e127db21-c3e5-4304-b2a7-86f14c2b623f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594210159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3594210159
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.3558399572
Short name T881
Test name
Test status
Simulation time 48323782 ps
CPU time 2.39 seconds
Started Aug 03 05:25:00 PM PDT 24
Finished Aug 03 05:25:03 PM PDT 24
Peak memory 208148 kb
Host smart-8523747b-5c53-4f65-849a-b0c171d5b552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558399572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3558399572
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2621494362
Short name T311
Test name
Test status
Simulation time 6988783794 ps
CPU time 85.45 seconds
Started Aug 03 05:24:57 PM PDT 24
Finished Aug 03 05:26:22 PM PDT 24
Peak memory 220228 kb
Host smart-c9a0622c-fb99-4952-99f4-ada6743b0cd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621494362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2621494362
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.370072593
Short name T155
Test name
Test status
Simulation time 2789750533 ps
CPU time 17 seconds
Started Aug 03 05:25:01 PM PDT 24
Finished Aug 03 05:25:18 PM PDT 24
Peak memory 222608 kb
Host smart-38ab19b4-e5f1-4ebc-a46d-04441a0efa80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370072593 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.370072593
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2296731122
Short name T302
Test name
Test status
Simulation time 299647200 ps
CPU time 8.04 seconds
Started Aug 03 05:24:56 PM PDT 24
Finished Aug 03 05:25:04 PM PDT 24
Peak memory 207536 kb
Host smart-55ea6b3a-b897-4011-a35c-0a6d04e94ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296731122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2296731122
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2245431758
Short name T613
Test name
Test status
Simulation time 216171689 ps
CPU time 1.63 seconds
Started Aug 03 05:25:02 PM PDT 24
Finished Aug 03 05:25:04 PM PDT 24
Peak memory 209748 kb
Host smart-633092e9-597f-4e10-a7de-1a1f9001ae2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245431758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2245431758
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.1774027070
Short name T541
Test name
Test status
Simulation time 32873802 ps
CPU time 0.94 seconds
Started Aug 03 05:25:04 PM PDT 24
Finished Aug 03 05:25:05 PM PDT 24
Peak memory 206120 kb
Host smart-45e79d08-d4dd-445d-af3c-0336a7c4a225
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774027070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1774027070
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3191428493
Short name T418
Test name
Test status
Simulation time 532190075 ps
CPU time 14.85 seconds
Started Aug 03 05:25:02 PM PDT 24
Finished Aug 03 05:25:17 PM PDT 24
Peak memory 214320 kb
Host smart-a87ad3b7-dee0-4dbf-9a76-1ba8083e8e14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3191428493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3191428493
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.362623605
Short name T525
Test name
Test status
Simulation time 41849528 ps
CPU time 2.83 seconds
Started Aug 03 05:25:04 PM PDT 24
Finished Aug 03 05:25:07 PM PDT 24
Peak memory 214404 kb
Host smart-0449d19b-10dd-4cf4-81d7-3785b59df376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362623605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.362623605
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.750655507
Short name T99
Test name
Test status
Simulation time 210480910 ps
CPU time 5.13 seconds
Started Aug 03 05:25:04 PM PDT 24
Finished Aug 03 05:25:09 PM PDT 24
Peak memory 209632 kb
Host smart-38a974a6-cd79-49e7-8092-ba193eb901b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750655507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.750655507
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1891736518
Short name T514
Test name
Test status
Simulation time 206976686 ps
CPU time 4.67 seconds
Started Aug 03 05:25:02 PM PDT 24
Finished Aug 03 05:25:06 PM PDT 24
Peak memory 209440 kb
Host smart-a7eea5ed-6a50-46cd-bcb7-7e8720e998e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891736518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1891736518
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.2716964546
Short name T683
Test name
Test status
Simulation time 1371872617 ps
CPU time 5.15 seconds
Started Aug 03 05:24:58 PM PDT 24
Finished Aug 03 05:25:03 PM PDT 24
Peak memory 209356 kb
Host smart-b11256af-8ee9-4a77-8016-2c6e8f158ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716964546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2716964546
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.2049448218
Short name T196
Test name
Test status
Simulation time 202855422 ps
CPU time 2.91 seconds
Started Aug 03 05:24:56 PM PDT 24
Finished Aug 03 05:24:59 PM PDT 24
Peak memory 208680 kb
Host smart-c3ac4892-c5fc-4066-9559-1a9955da19e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049448218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.2049448218
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.228200627
Short name T590
Test name
Test status
Simulation time 1072086177 ps
CPU time 4.25 seconds
Started Aug 03 05:25:02 PM PDT 24
Finished Aug 03 05:25:06 PM PDT 24
Peak memory 208488 kb
Host smart-e9134b95-86b9-4fd7-8626-d8bf1608ca59
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228200627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.228200627
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2087997706
Short name T610
Test name
Test status
Simulation time 79161116 ps
CPU time 2.97 seconds
Started Aug 03 05:24:55 PM PDT 24
Finished Aug 03 05:24:58 PM PDT 24
Peak memory 208816 kb
Host smart-5745125d-cd33-46a8-a65c-c64b52949931
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087997706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2087997706
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2713497556
Short name T632
Test name
Test status
Simulation time 199782863 ps
CPU time 2.85 seconds
Started Aug 03 05:24:55 PM PDT 24
Finished Aug 03 05:24:58 PM PDT 24
Peak memory 206848 kb
Host smart-72927606-5f01-428a-a9f0-bc6d53a58bd6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713497556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2713497556
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2402226189
Short name T334
Test name
Test status
Simulation time 51137353 ps
CPU time 2.33 seconds
Started Aug 03 05:25:05 PM PDT 24
Finished Aug 03 05:25:07 PM PDT 24
Peak memory 208516 kb
Host smart-a8553cdd-d8d1-459c-adbf-6114f8af8598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402226189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2402226189
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2938875165
Short name T611
Test name
Test status
Simulation time 351377370 ps
CPU time 4.21 seconds
Started Aug 03 05:24:57 PM PDT 24
Finished Aug 03 05:25:02 PM PDT 24
Peak memory 207908 kb
Host smart-ae19b18a-ce4f-4a79-8548-7cc1a88e1328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938875165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2938875165
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1867804206
Short name T222
Test name
Test status
Simulation time 339701679 ps
CPU time 17.78 seconds
Started Aug 03 05:25:06 PM PDT 24
Finished Aug 03 05:25:24 PM PDT 24
Peak memory 222456 kb
Host smart-e3d87b4c-30eb-472a-b6de-905a2a8a475e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867804206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1867804206
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.4029862670
Short name T128
Test name
Test status
Simulation time 744127592 ps
CPU time 12.96 seconds
Started Aug 03 05:25:03 PM PDT 24
Finished Aug 03 05:25:16 PM PDT 24
Peak memory 222528 kb
Host smart-6320838d-aa37-4bb7-afcd-5516304e1457
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029862670 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.4029862670
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.124335120
Short name T873
Test name
Test status
Simulation time 2143216742 ps
CPU time 6.12 seconds
Started Aug 03 05:25:01 PM PDT 24
Finished Aug 03 05:25:07 PM PDT 24
Peak memory 222408 kb
Host smart-15504123-ca90-47c5-a502-5e064185ac61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124335120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.124335120
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1810127170
Short name T148
Test name
Test status
Simulation time 29787586 ps
CPU time 2.09 seconds
Started Aug 03 05:25:04 PM PDT 24
Finished Aug 03 05:25:06 PM PDT 24
Peak memory 209944 kb
Host smart-ecce204e-b445-41d4-9c0a-0f701efdf4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810127170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1810127170
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1788219324
Short name T537
Test name
Test status
Simulation time 47674355 ps
CPU time 0.78 seconds
Started Aug 03 05:25:06 PM PDT 24
Finished Aug 03 05:25:07 PM PDT 24
Peak memory 205932 kb
Host smart-f7f4a16c-9627-475f-a840-f0c50981a1e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788219324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1788219324
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.236384842
Short name T678
Test name
Test status
Simulation time 332636667 ps
CPU time 4.27 seconds
Started Aug 03 05:25:03 PM PDT 24
Finished Aug 03 05:25:08 PM PDT 24
Peak memory 209240 kb
Host smart-3477dfc1-6a23-4d20-9224-8d72089d5686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236384842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.236384842
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1105815843
Short name T697
Test name
Test status
Simulation time 57161869 ps
CPU time 2.71 seconds
Started Aug 03 05:25:04 PM PDT 24
Finished Aug 03 05:25:07 PM PDT 24
Peak memory 218508 kb
Host smart-440454ac-7150-47c5-a565-3c68aab2207f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105815843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1105815843
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2037540184
Short name T366
Test name
Test status
Simulation time 72810023 ps
CPU time 3.78 seconds
Started Aug 03 05:25:02 PM PDT 24
Finished Aug 03 05:25:06 PM PDT 24
Peak memory 214256 kb
Host smart-449364c1-93d5-4ac8-b6a2-7f24a7f265f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037540184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2037540184
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.659827453
Short name T773
Test name
Test status
Simulation time 168716055 ps
CPU time 6.06 seconds
Started Aug 03 05:25:06 PM PDT 24
Finished Aug 03 05:25:12 PM PDT 24
Peak memory 220684 kb
Host smart-89230a8c-417b-4bca-863a-0d4d8f74468e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659827453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.659827453
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2751909493
Short name T48
Test name
Test status
Simulation time 162586158 ps
CPU time 2.52 seconds
Started Aug 03 05:25:04 PM PDT 24
Finished Aug 03 05:25:06 PM PDT 24
Peak memory 209684 kb
Host smart-55fd3997-49d8-41f3-84c1-51374d6389c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751909493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2751909493
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.462126232
Short name T283
Test name
Test status
Simulation time 74319029 ps
CPU time 3.66 seconds
Started Aug 03 05:25:04 PM PDT 24
Finished Aug 03 05:25:08 PM PDT 24
Peak memory 208820 kb
Host smart-d7524be2-7e86-4ee9-aeeb-ac0fb767fc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462126232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.462126232
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1317099974
Short name T585
Test name
Test status
Simulation time 139142861 ps
CPU time 4.42 seconds
Started Aug 03 05:25:04 PM PDT 24
Finished Aug 03 05:25:08 PM PDT 24
Peak memory 208460 kb
Host smart-c3e75999-c7f7-4512-81ae-9f49e982c3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317099974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1317099974
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.2829568461
Short name T360
Test name
Test status
Simulation time 2064215504 ps
CPU time 30.12 seconds
Started Aug 03 05:25:04 PM PDT 24
Finished Aug 03 05:25:34 PM PDT 24
Peak memory 208688 kb
Host smart-c8c8a118-a9c8-449d-a673-692a03de7ec7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829568461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2829568461
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1141290031
Short name T452
Test name
Test status
Simulation time 826249850 ps
CPU time 4.86 seconds
Started Aug 03 05:25:04 PM PDT 24
Finished Aug 03 05:25:09 PM PDT 24
Peak memory 208072 kb
Host smart-25f58d02-ccf2-4804-b48f-4483e4100a67
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141290031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1141290031
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.83270478
Short name T698
Test name
Test status
Simulation time 113047191 ps
CPU time 3.3 seconds
Started Aug 03 05:25:03 PM PDT 24
Finished Aug 03 05:25:07 PM PDT 24
Peak memory 208308 kb
Host smart-98badf23-c95c-4e1e-923b-872a5bda35e6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83270478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.83270478
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1879680167
Short name T108
Test name
Test status
Simulation time 1504556698 ps
CPU time 18.85 seconds
Started Aug 03 05:25:07 PM PDT 24
Finished Aug 03 05:25:25 PM PDT 24
Peak memory 214328 kb
Host smart-009b6a4b-b465-49d5-8bad-8a15ffee61f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879680167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1879680167
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1601249711
Short name T568
Test name
Test status
Simulation time 1378045105 ps
CPU time 20.31 seconds
Started Aug 03 05:25:04 PM PDT 24
Finished Aug 03 05:25:25 PM PDT 24
Peak memory 208248 kb
Host smart-749552e1-77e5-4f2e-9fe4-85261506059f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601249711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1601249711
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1954060384
Short name T736
Test name
Test status
Simulation time 288883896 ps
CPU time 9.67 seconds
Started Aug 03 05:25:05 PM PDT 24
Finished Aug 03 05:25:14 PM PDT 24
Peak memory 208940 kb
Host smart-69fbf788-4104-4560-8258-0bc7b6a66659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954060384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1954060384
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.4018932131
Short name T901
Test name
Test status
Simulation time 95333273 ps
CPU time 3.63 seconds
Started Aug 03 05:25:07 PM PDT 24
Finished Aug 03 05:25:11 PM PDT 24
Peak memory 210252 kb
Host smart-202eab0b-1737-4336-aa69-b7ec241e2382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018932131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.4018932131
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.227651124
Short name T106
Test name
Test status
Simulation time 12224170 ps
CPU time 0.75 seconds
Started Aug 03 05:25:06 PM PDT 24
Finished Aug 03 05:25:07 PM PDT 24
Peak memory 205972 kb
Host smart-385978e1-f62c-4cca-abba-7fbdee5bbb7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227651124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.227651124
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.1640912779
Short name T409
Test name
Test status
Simulation time 110858625 ps
CPU time 3.4 seconds
Started Aug 03 05:25:14 PM PDT 24
Finished Aug 03 05:25:18 PM PDT 24
Peak memory 214448 kb
Host smart-af1c7ac8-f27e-409b-8556-1483cee5811f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1640912779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1640912779
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1713274208
Short name T67
Test name
Test status
Simulation time 327649516 ps
CPU time 3.87 seconds
Started Aug 03 05:25:10 PM PDT 24
Finished Aug 03 05:25:14 PM PDT 24
Peak memory 209380 kb
Host smart-1bdfeb54-e461-4207-a03b-90f116a77fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713274208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1713274208
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1474866860
Short name T416
Test name
Test status
Simulation time 149857275 ps
CPU time 2.01 seconds
Started Aug 03 05:25:09 PM PDT 24
Finished Aug 03 05:25:11 PM PDT 24
Peak memory 209348 kb
Host smart-71949d0c-a1ac-4d85-9e38-bb4361b0ded3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474866860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1474866860
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.572122072
Short name T268
Test name
Test status
Simulation time 189453889 ps
CPU time 6.94 seconds
Started Aug 03 05:25:09 PM PDT 24
Finished Aug 03 05:25:16 PM PDT 24
Peak memory 214560 kb
Host smart-a6cafa30-1d9b-440b-90e4-e0420d9a2f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572122072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.572122072
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.387732024
Short name T605
Test name
Test status
Simulation time 416845571 ps
CPU time 4.16 seconds
Started Aug 03 05:25:10 PM PDT 24
Finished Aug 03 05:25:15 PM PDT 24
Peak memory 214292 kb
Host smart-40b0bb40-e459-414c-88bf-cd049c25217f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387732024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.387732024
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.335284474
Short name T609
Test name
Test status
Simulation time 147956274 ps
CPU time 4.04 seconds
Started Aug 03 05:25:11 PM PDT 24
Finished Aug 03 05:25:15 PM PDT 24
Peak memory 207296 kb
Host smart-dc2d82dd-a3b4-4ccb-bd00-a18f120649e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335284474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.335284474
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1979338698
Short name T824
Test name
Test status
Simulation time 23630423 ps
CPU time 1.84 seconds
Started Aug 03 05:25:10 PM PDT 24
Finished Aug 03 05:25:12 PM PDT 24
Peak memory 206980 kb
Host smart-f52eb913-a34b-405a-943c-44e766160377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979338698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1979338698
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.822668076
Short name T776
Test name
Test status
Simulation time 97090670 ps
CPU time 2.9 seconds
Started Aug 03 05:25:08 PM PDT 24
Finished Aug 03 05:25:11 PM PDT 24
Peak memory 206972 kb
Host smart-8f89f344-e108-4c97-a234-371a15846b14
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822668076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.822668076
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2152706522
Short name T488
Test name
Test status
Simulation time 259764836 ps
CPU time 5.09 seconds
Started Aug 03 05:25:10 PM PDT 24
Finished Aug 03 05:25:15 PM PDT 24
Peak memory 206992 kb
Host smart-bd570df7-0d3a-4614-9476-a10ad6c29470
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152706522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2152706522
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1853398111
Short name T671
Test name
Test status
Simulation time 40251697 ps
CPU time 2.69 seconds
Started Aug 03 05:25:06 PM PDT 24
Finished Aug 03 05:25:09 PM PDT 24
Peak memory 208828 kb
Host smart-c2db51ec-4bd4-472d-9208-8b43eecbce77
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853398111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1853398111
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2963182281
Short name T826
Test name
Test status
Simulation time 223557894 ps
CPU time 2.44 seconds
Started Aug 03 05:25:08 PM PDT 24
Finished Aug 03 05:25:10 PM PDT 24
Peak memory 208268 kb
Host smart-939fae58-036d-4caf-9a81-7109d7c5bf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963182281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2963182281
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.869332162
Short name T858
Test name
Test status
Simulation time 174255362 ps
CPU time 2.8 seconds
Started Aug 03 05:25:17 PM PDT 24
Finished Aug 03 05:25:20 PM PDT 24
Peak memory 206800 kb
Host smart-9d5fa523-9b9f-438d-adbe-9135b2e5ea56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869332162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.869332162
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3584242303
Short name T210
Test name
Test status
Simulation time 7737341274 ps
CPU time 88.18 seconds
Started Aug 03 05:25:09 PM PDT 24
Finished Aug 03 05:26:37 PM PDT 24
Peak memory 221176 kb
Host smart-a55ee33a-b8ec-4a2e-84c0-8eab1f7c5b06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584242303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3584242303
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.3258015472
Short name T618
Test name
Test status
Simulation time 553080031 ps
CPU time 17.04 seconds
Started Aug 03 05:25:09 PM PDT 24
Finished Aug 03 05:25:27 PM PDT 24
Peak memory 220544 kb
Host smart-5f86ca70-2b5a-4a58-ba5b-68e71349e467
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258015472 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.3258015472
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2159347445
Short name T630
Test name
Test status
Simulation time 98362144 ps
CPU time 4.15 seconds
Started Aug 03 05:25:09 PM PDT 24
Finished Aug 03 05:25:13 PM PDT 24
Peak memory 207348 kb
Host smart-dd078ed7-b7f7-4609-81cb-d479bd8f6b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159347445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2159347445
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2378257030
Short name T170
Test name
Test status
Simulation time 152306753 ps
CPU time 3.1 seconds
Started Aug 03 05:25:10 PM PDT 24
Finished Aug 03 05:25:14 PM PDT 24
Peak memory 211036 kb
Host smart-deef1319-ad7e-486d-9c66-fb81aa9c5c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378257030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2378257030
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.953241513
Short name T469
Test name
Test status
Simulation time 36894224 ps
CPU time 0.83 seconds
Started Aug 03 05:25:10 PM PDT 24
Finished Aug 03 05:25:11 PM PDT 24
Peak memory 205952 kb
Host smart-69c00c4d-18bf-44e0-b1b7-c588ebbd20e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953241513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.953241513
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.125503832
Short name T56
Test name
Test status
Simulation time 133146666 ps
CPU time 2.82 seconds
Started Aug 03 05:25:07 PM PDT 24
Finished Aug 03 05:25:10 PM PDT 24
Peak memory 209796 kb
Host smart-2d429648-885b-4ae6-9742-c0cb1cddc5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125503832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.125503832
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.2247326645
Short name T780
Test name
Test status
Simulation time 305833306 ps
CPU time 3.84 seconds
Started Aug 03 05:25:08 PM PDT 24
Finished Aug 03 05:25:12 PM PDT 24
Peak memory 209372 kb
Host smart-897f3263-2444-4f27-b267-96342a438998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247326645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2247326645
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.574295549
Short name T103
Test name
Test status
Simulation time 989966956 ps
CPU time 19.46 seconds
Started Aug 03 05:25:09 PM PDT 24
Finished Aug 03 05:25:29 PM PDT 24
Peak memory 218336 kb
Host smart-c3837585-322e-4edb-9a0f-79a445f04c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574295549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.574295549
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.4040222179
Short name T822
Test name
Test status
Simulation time 144053887 ps
CPU time 2.24 seconds
Started Aug 03 05:25:10 PM PDT 24
Finished Aug 03 05:25:13 PM PDT 24
Peak memory 214320 kb
Host smart-89e11c2f-237c-4647-a3e3-3700162b5048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040222179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.4040222179
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.4169832410
Short name T209
Test name
Test status
Simulation time 376375518 ps
CPU time 1.7 seconds
Started Aug 03 05:25:09 PM PDT 24
Finished Aug 03 05:25:10 PM PDT 24
Peak memory 214312 kb
Host smart-6f7fb3d5-c90c-4c89-a983-477fc42264bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169832410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.4169832410
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2600728609
Short name T803
Test name
Test status
Simulation time 121801487 ps
CPU time 3.26 seconds
Started Aug 03 05:25:09 PM PDT 24
Finished Aug 03 05:25:13 PM PDT 24
Peak memory 207928 kb
Host smart-e2f86cbe-b361-4a02-a5a8-c39bedbddb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600728609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2600728609
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.951569862
Short name T885
Test name
Test status
Simulation time 4539556943 ps
CPU time 49.55 seconds
Started Aug 03 05:25:06 PM PDT 24
Finished Aug 03 05:25:56 PM PDT 24
Peak memory 208360 kb
Host smart-88914c5e-dd0e-4771-b341-9d4029cb7061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951569862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.951569862
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.4192076693
Short name T658
Test name
Test status
Simulation time 69650833 ps
CPU time 1.8 seconds
Started Aug 03 05:25:10 PM PDT 24
Finished Aug 03 05:25:12 PM PDT 24
Peak memory 206692 kb
Host smart-171b6137-e81c-4cd7-90a9-85ab24a1d84a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192076693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.4192076693
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1952384133
Short name T458
Test name
Test status
Simulation time 95836946 ps
CPU time 2.83 seconds
Started Aug 03 05:25:10 PM PDT 24
Finished Aug 03 05:25:13 PM PDT 24
Peak memory 207048 kb
Host smart-65ff55ce-8497-4893-84c7-244b36289cf9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952384133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1952384133
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3510645734
Short name T550
Test name
Test status
Simulation time 122675583 ps
CPU time 3.45 seconds
Started Aug 03 05:25:09 PM PDT 24
Finished Aug 03 05:25:13 PM PDT 24
Peak memory 208524 kb
Host smart-c27de859-fe56-448c-bf45-980b393c3bae
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510645734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3510645734
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2092691100
Short name T200
Test name
Test status
Simulation time 43187840 ps
CPU time 2.32 seconds
Started Aug 03 05:25:09 PM PDT 24
Finished Aug 03 05:25:12 PM PDT 24
Peak memory 215712 kb
Host smart-e0cc4d76-6b6a-421f-a3ce-ffcce6ca3944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092691100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2092691100
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1976178903
Short name T583
Test name
Test status
Simulation time 226272673 ps
CPU time 2.94 seconds
Started Aug 03 05:25:17 PM PDT 24
Finished Aug 03 05:25:20 PM PDT 24
Peak memory 206840 kb
Host smart-a1fcba75-48b4-4b2e-85b7-8491751ab882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976178903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1976178903
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2237871544
Short name T131
Test name
Test status
Simulation time 6301868014 ps
CPU time 30.98 seconds
Started Aug 03 05:25:06 PM PDT 24
Finished Aug 03 05:25:38 PM PDT 24
Peak memory 209056 kb
Host smart-0ffb9bfd-ed90-4e90-ace0-03f1c4c84ac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237871544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2237871544
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2436258210
Short name T606
Test name
Test status
Simulation time 53339251 ps
CPU time 3.47 seconds
Started Aug 03 05:25:09 PM PDT 24
Finished Aug 03 05:25:13 PM PDT 24
Peak memory 207732 kb
Host smart-8ebc15f6-bbf5-46d5-9816-020dded5409e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436258210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2436258210
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2937671916
Short name T451
Test name
Test status
Simulation time 97690061 ps
CPU time 0.92 seconds
Started Aug 03 05:23:28 PM PDT 24
Finished Aug 03 05:23:29 PM PDT 24
Peak memory 206092 kb
Host smart-19ef9817-6597-4886-8c8a-074f3394dc33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937671916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2937671916
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.4280504918
Short name T10
Test name
Test status
Simulation time 298823006 ps
CPU time 4.85 seconds
Started Aug 03 05:23:25 PM PDT 24
Finished Aug 03 05:23:30 PM PDT 24
Peak memory 208628 kb
Host smart-180e3d00-f504-493f-9249-3128c9889187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280504918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.4280504918
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.868346595
Short name T342
Test name
Test status
Simulation time 674868247 ps
CPU time 12.34 seconds
Started Aug 03 05:23:20 PM PDT 24
Finished Aug 03 05:23:32 PM PDT 24
Peak memory 208200 kb
Host smart-caf81794-166c-47b7-9ace-8de5f233c8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868346595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.868346595
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.924686551
Short name T536
Test name
Test status
Simulation time 222541571 ps
CPU time 4.41 seconds
Started Aug 03 05:23:26 PM PDT 24
Finished Aug 03 05:23:30 PM PDT 24
Peak memory 222448 kb
Host smart-808dcab5-7c50-4db7-9006-7f36f50e64ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924686551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.924686551
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.721766121
Short name T344
Test name
Test status
Simulation time 227057458 ps
CPU time 2.65 seconds
Started Aug 03 05:23:21 PM PDT 24
Finished Aug 03 05:23:24 PM PDT 24
Peak memory 214244 kb
Host smart-e1b64086-49b5-4af8-82f0-56d6ca33fb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721766121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.721766121
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1950469517
Short name T226
Test name
Test status
Simulation time 937486886 ps
CPU time 3.52 seconds
Started Aug 03 05:23:26 PM PDT 24
Finished Aug 03 05:23:29 PM PDT 24
Peak memory 207628 kb
Host smart-cd8ce634-2ee6-40ad-8fe8-4da13347d171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950469517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1950469517
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.65039681
Short name T660
Test name
Test status
Simulation time 731420286 ps
CPU time 5.96 seconds
Started Aug 03 05:23:20 PM PDT 24
Finished Aug 03 05:23:26 PM PDT 24
Peak memory 208048 kb
Host smart-45a74701-efb9-4766-9d40-49df3509702e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65039681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.65039681
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1978415863
Short name T11
Test name
Test status
Simulation time 626517620 ps
CPU time 5.27 seconds
Started Aug 03 05:23:26 PM PDT 24
Finished Aug 03 05:23:31 PM PDT 24
Peak memory 228800 kb
Host smart-88b0ae52-b258-4542-acca-99c6ae812335
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978415863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1978415863
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.4237325467
Short name T906
Test name
Test status
Simulation time 580579145 ps
CPU time 4.94 seconds
Started Aug 03 05:23:20 PM PDT 24
Finished Aug 03 05:23:25 PM PDT 24
Peak memory 206880 kb
Host smart-47824b33-7e61-4ae0-bbc4-b5a918599228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237325467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.4237325467
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.894226400
Short name T472
Test name
Test status
Simulation time 48008227 ps
CPU time 2.81 seconds
Started Aug 03 05:23:20 PM PDT 24
Finished Aug 03 05:23:23 PM PDT 24
Peak memory 206880 kb
Host smart-6e1f09ab-343d-4184-a200-988ca2657ce2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894226400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.894226400
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3288836572
Short name T534
Test name
Test status
Simulation time 12035194283 ps
CPU time 40.27 seconds
Started Aug 03 05:23:20 PM PDT 24
Finished Aug 03 05:24:00 PM PDT 24
Peak memory 208748 kb
Host smart-4262e939-7fb0-42f2-943e-f98942909eae
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288836572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3288836572
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1548615345
Short name T2
Test name
Test status
Simulation time 32296443 ps
CPU time 2.17 seconds
Started Aug 03 05:23:26 PM PDT 24
Finished Aug 03 05:23:28 PM PDT 24
Peak memory 207452 kb
Host smart-54ac9449-aec0-4f59-93c3-a482b715eaab
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548615345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1548615345
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.4057264245
Short name T490
Test name
Test status
Simulation time 140500800 ps
CPU time 2.1 seconds
Started Aug 03 05:23:28 PM PDT 24
Finished Aug 03 05:23:31 PM PDT 24
Peak memory 207432 kb
Host smart-f87c8e5c-c5d7-4dae-9797-4ac097f813a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057264245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.4057264245
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.354620016
Short name T558
Test name
Test status
Simulation time 72342719 ps
CPU time 1.58 seconds
Started Aug 03 05:23:18 PM PDT 24
Finished Aug 03 05:23:20 PM PDT 24
Peak memory 206876 kb
Host smart-01e3d72a-1793-4308-b4d5-d12223d9ad52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354620016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.354620016
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1689684982
Short name T805
Test name
Test status
Simulation time 724454223 ps
CPU time 29.43 seconds
Started Aug 03 05:23:26 PM PDT 24
Finished Aug 03 05:23:55 PM PDT 24
Peak memory 222488 kb
Host smart-7b91b778-fb07-4feb-922a-d5b6d060720c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689684982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1689684982
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.2180356307
Short name T181
Test name
Test status
Simulation time 203262756 ps
CPU time 6.14 seconds
Started Aug 03 05:23:25 PM PDT 24
Finished Aug 03 05:23:31 PM PDT 24
Peak memory 218716 kb
Host smart-b401b3b6-c953-4f7e-a63a-4b2c11facbc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180356307 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.2180356307
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2801986541
Short name T833
Test name
Test status
Simulation time 449267924 ps
CPU time 5.48 seconds
Started Aug 03 05:23:21 PM PDT 24
Finished Aug 03 05:23:26 PM PDT 24
Peak memory 214304 kb
Host smart-c426df3c-35fd-4632-a3e5-3e56e507e2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801986541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2801986541
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.970378576
Short name T699
Test name
Test status
Simulation time 48195517 ps
CPU time 0.92 seconds
Started Aug 03 05:25:13 PM PDT 24
Finished Aug 03 05:25:14 PM PDT 24
Peak memory 205956 kb
Host smart-acbb1ab9-1aca-4e69-a5e5-3015fa96f0c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970378576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.970378576
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.758087252
Short name T273
Test name
Test status
Simulation time 105808088 ps
CPU time 6.48 seconds
Started Aug 03 05:25:13 PM PDT 24
Finished Aug 03 05:25:20 PM PDT 24
Peak memory 215132 kb
Host smart-702731eb-0415-4b19-a572-ae8daad7457d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=758087252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.758087252
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1214300071
Short name T491
Test name
Test status
Simulation time 876308457 ps
CPU time 5.84 seconds
Started Aug 03 05:25:14 PM PDT 24
Finished Aug 03 05:25:20 PM PDT 24
Peak memory 207868 kb
Host smart-99f53a97-7e8c-4ac4-9168-b257dce0f6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214300071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1214300071
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.23512203
Short name T25
Test name
Test status
Simulation time 445196050 ps
CPU time 5.9 seconds
Started Aug 03 05:25:16 PM PDT 24
Finished Aug 03 05:25:22 PM PDT 24
Peak memory 214300 kb
Host smart-d6297e6e-e36c-44fa-b82c-bd3e7349e1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23512203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.23512203
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3976962786
Short name T642
Test name
Test status
Simulation time 287858269 ps
CPU time 3.7 seconds
Started Aug 03 05:25:11 PM PDT 24
Finished Aug 03 05:25:15 PM PDT 24
Peak memory 222424 kb
Host smart-a8c653f0-f144-4847-a8fe-d5b95d125cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976962786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3976962786
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.69360056
Short name T911
Test name
Test status
Simulation time 440725234 ps
CPU time 3.09 seconds
Started Aug 03 05:25:13 PM PDT 24
Finished Aug 03 05:25:17 PM PDT 24
Peak memory 214284 kb
Host smart-347f61f1-4d3d-4b68-971a-8c590f3df7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69360056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.69360056
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.3615183441
Short name T190
Test name
Test status
Simulation time 1066076176 ps
CPU time 34.47 seconds
Started Aug 03 05:25:16 PM PDT 24
Finished Aug 03 05:25:51 PM PDT 24
Peak memory 210104 kb
Host smart-a7cf976e-9ffe-48f6-a40e-2791bb8f6685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615183441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3615183441
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2343250591
Short name T587
Test name
Test status
Simulation time 62671974 ps
CPU time 2.23 seconds
Started Aug 03 05:25:12 PM PDT 24
Finished Aug 03 05:25:14 PM PDT 24
Peak memory 206896 kb
Host smart-5fd0fce0-3077-4a92-83c9-60de19a266b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343250591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2343250591
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1472970796
Short name T462
Test name
Test status
Simulation time 87777937 ps
CPU time 2.73 seconds
Started Aug 03 05:25:18 PM PDT 24
Finished Aug 03 05:25:21 PM PDT 24
Peak memory 208588 kb
Host smart-c202740d-b2a2-4aa1-8bce-74cc9ffa4ea8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472970796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1472970796
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3558185105
Short name T482
Test name
Test status
Simulation time 76255429 ps
CPU time 1.8 seconds
Started Aug 03 05:25:17 PM PDT 24
Finished Aug 03 05:25:19 PM PDT 24
Peak memory 206900 kb
Host smart-dac3a653-6274-46fa-aeca-9075a00b0361
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558185105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3558185105
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2841506708
Short name T895
Test name
Test status
Simulation time 219170845 ps
CPU time 6.33 seconds
Started Aug 03 05:25:13 PM PDT 24
Finished Aug 03 05:25:19 PM PDT 24
Peak memory 208392 kb
Host smart-2e75ad3f-210b-4c38-ad0d-ad95285751c3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841506708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2841506708
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3181126010
Short name T557
Test name
Test status
Simulation time 112427550 ps
CPU time 1.82 seconds
Started Aug 03 05:25:15 PM PDT 24
Finished Aug 03 05:25:17 PM PDT 24
Peak memory 208932 kb
Host smart-200f0cdf-a196-43fc-98ec-bebfd59d965b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181126010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3181126010
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3238684164
Short name T489
Test name
Test status
Simulation time 371244575 ps
CPU time 2.5 seconds
Started Aug 03 05:25:15 PM PDT 24
Finished Aug 03 05:25:17 PM PDT 24
Peak memory 206736 kb
Host smart-35d641c7-1806-45aa-a8cc-3248c5fdc9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238684164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3238684164
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.2421379059
Short name T335
Test name
Test status
Simulation time 219855373 ps
CPU time 14.39 seconds
Started Aug 03 05:25:16 PM PDT 24
Finished Aug 03 05:25:30 PM PDT 24
Peak memory 222324 kb
Host smart-540a7bed-b06f-4477-b60e-52197724c6d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421379059 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.2421379059
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3244306846
Short name T112
Test name
Test status
Simulation time 24875671 ps
CPU time 2.08 seconds
Started Aug 03 05:25:16 PM PDT 24
Finished Aug 03 05:25:18 PM PDT 24
Peak memory 206984 kb
Host smart-9a726188-e53c-40ee-9c84-7aafc088408f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244306846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3244306846
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2870772866
Short name T394
Test name
Test status
Simulation time 102119453 ps
CPU time 1.66 seconds
Started Aug 03 05:25:12 PM PDT 24
Finished Aug 03 05:25:14 PM PDT 24
Peak memory 209572 kb
Host smart-a724231f-d163-4b2e-af5f-4185455f2de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870772866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2870772866
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.507864657
Short name T431
Test name
Test status
Simulation time 13345719 ps
CPU time 0.78 seconds
Started Aug 03 05:25:19 PM PDT 24
Finished Aug 03 05:25:20 PM PDT 24
Peak memory 205900 kb
Host smart-a030754d-aaa0-4009-8b28-2906659661c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507864657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.507864657
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2117397564
Short name T312
Test name
Test status
Simulation time 4972342773 ps
CPU time 64.54 seconds
Started Aug 03 05:25:16 PM PDT 24
Finished Aug 03 05:26:21 PM PDT 24
Peak memory 214360 kb
Host smart-874ea0d3-af6e-4f6e-8fc6-e77434b08a38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2117397564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2117397564
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.3710791890
Short name T907
Test name
Test status
Simulation time 149985627 ps
CPU time 1.99 seconds
Started Aug 03 05:25:13 PM PDT 24
Finished Aug 03 05:25:15 PM PDT 24
Peak memory 207572 kb
Host smart-fb3deab0-abda-429a-924f-adc87c8901fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710791890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3710791890
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1937768984
Short name T726
Test name
Test status
Simulation time 43703760 ps
CPU time 2.52 seconds
Started Aug 03 05:25:13 PM PDT 24
Finished Aug 03 05:25:15 PM PDT 24
Peak memory 207496 kb
Host smart-6a55c185-7f24-40f2-ae86-a7af253a6709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937768984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1937768984
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.362950796
Short name T92
Test name
Test status
Simulation time 112015003 ps
CPU time 2.43 seconds
Started Aug 03 05:25:17 PM PDT 24
Finished Aug 03 05:25:20 PM PDT 24
Peak memory 214292 kb
Host smart-cbf01185-72d2-4ecb-afcd-c4f5fbbaf4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362950796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.362950796
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.4282474510
Short name T242
Test name
Test status
Simulation time 43254083 ps
CPU time 2.15 seconds
Started Aug 03 05:25:16 PM PDT 24
Finished Aug 03 05:25:18 PM PDT 24
Peak memory 213524 kb
Host smart-5d0d635f-45ad-4f3b-8d28-e38a51ec0a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282474510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.4282474510
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3936209806
Short name T798
Test name
Test status
Simulation time 32908016 ps
CPU time 2.51 seconds
Started Aug 03 05:25:15 PM PDT 24
Finished Aug 03 05:25:18 PM PDT 24
Peak memory 220220 kb
Host smart-9c04f33b-88fa-4a55-b6f9-295ecbac12d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936209806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3936209806
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3100475132
Short name T572
Test name
Test status
Simulation time 126425370 ps
CPU time 3.29 seconds
Started Aug 03 05:25:18 PM PDT 24
Finished Aug 03 05:25:22 PM PDT 24
Peak memory 214272 kb
Host smart-bcc0dd07-7822-4eec-b27b-bbfb101b5298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100475132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3100475132
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1747949324
Short name T883
Test name
Test status
Simulation time 466312257 ps
CPU time 6.58 seconds
Started Aug 03 05:25:12 PM PDT 24
Finished Aug 03 05:25:18 PM PDT 24
Peak memory 208672 kb
Host smart-c94eb1b6-a7ab-4751-9371-2b2b19f8dae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747949324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1747949324
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2890010815
Short name T249
Test name
Test status
Simulation time 68203306 ps
CPU time 3.62 seconds
Started Aug 03 05:25:12 PM PDT 24
Finished Aug 03 05:25:16 PM PDT 24
Peak memory 208880 kb
Host smart-bf15db8c-4d9d-4c0e-97b1-8dd9cbc766a0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890010815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2890010815
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3230735321
Short name T782
Test name
Test status
Simulation time 47441896 ps
CPU time 2.4 seconds
Started Aug 03 05:25:17 PM PDT 24
Finished Aug 03 05:25:20 PM PDT 24
Peak memory 206820 kb
Host smart-3f925275-5c90-485c-9b29-a586395e8fa1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230735321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3230735321
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2316021422
Short name T492
Test name
Test status
Simulation time 81556274 ps
CPU time 1.86 seconds
Started Aug 03 05:25:17 PM PDT 24
Finished Aug 03 05:25:19 PM PDT 24
Peak memory 207012 kb
Host smart-de42f611-560c-4ec4-a38b-e4de8093b8e4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316021422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2316021422
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1233071250
Short name T277
Test name
Test status
Simulation time 103340682 ps
CPU time 2.66 seconds
Started Aug 03 05:25:14 PM PDT 24
Finished Aug 03 05:25:16 PM PDT 24
Peak memory 218276 kb
Host smart-0cc4fd89-7e47-4a54-b034-eb9cac765331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233071250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1233071250
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2748802005
Short name T495
Test name
Test status
Simulation time 447974286 ps
CPU time 3.54 seconds
Started Aug 03 05:25:18 PM PDT 24
Finished Aug 03 05:25:21 PM PDT 24
Peak memory 208396 kb
Host smart-81018d3a-f149-48f8-99b1-cd67687cd614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748802005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2748802005
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.4153249886
Short name T51
Test name
Test status
Simulation time 4209276843 ps
CPU time 39.84 seconds
Started Aug 03 05:25:25 PM PDT 24
Finished Aug 03 05:26:05 PM PDT 24
Peak memory 222496 kb
Host smart-3ceeb68f-78e2-4766-a659-78de964fe167
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153249886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.4153249886
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.3743041904
Short name T788
Test name
Test status
Simulation time 246331529 ps
CPU time 9 seconds
Started Aug 03 05:25:21 PM PDT 24
Finished Aug 03 05:25:31 PM PDT 24
Peak memory 219072 kb
Host smart-52f2a811-c5db-4c1c-ba40-4e852703aeaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743041904 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.3743041904
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.943579100
Short name T234
Test name
Test status
Simulation time 53816999 ps
CPU time 3.11 seconds
Started Aug 03 05:25:16 PM PDT 24
Finished Aug 03 05:25:20 PM PDT 24
Peak memory 209932 kb
Host smart-3079cb79-3020-4402-841d-612e2bd86e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943579100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.943579100
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2635805117
Short name T599
Test name
Test status
Simulation time 19940503 ps
CPU time 0.8 seconds
Started Aug 03 05:25:20 PM PDT 24
Finished Aug 03 05:25:21 PM PDT 24
Peak memory 205956 kb
Host smart-d51b2345-baae-4f3e-8ba5-56ea5c07dc7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635805117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2635805117
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.584884214
Short name T397
Test name
Test status
Simulation time 112473377 ps
CPU time 3.75 seconds
Started Aug 03 05:25:20 PM PDT 24
Finished Aug 03 05:25:24 PM PDT 24
Peak memory 214260 kb
Host smart-77360148-2197-418e-bb83-b8cff1ec8e97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=584884214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.584884214
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3503618460
Short name T350
Test name
Test status
Simulation time 137998723 ps
CPU time 3.21 seconds
Started Aug 03 05:25:19 PM PDT 24
Finished Aug 03 05:25:23 PM PDT 24
Peak memory 222664 kb
Host smart-98c3bb18-ad65-4efc-8f9a-40708eed34bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503618460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3503618460
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.4167878611
Short name T317
Test name
Test status
Simulation time 451375589 ps
CPU time 5.49 seconds
Started Aug 03 05:25:18 PM PDT 24
Finished Aug 03 05:25:24 PM PDT 24
Peak memory 218496 kb
Host smart-a51e8e4d-7294-4d7a-89d4-35dadf7f2cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167878611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.4167878611
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.403386885
Short name T670
Test name
Test status
Simulation time 349731948 ps
CPU time 4.59 seconds
Started Aug 03 05:25:28 PM PDT 24
Finished Aug 03 05:25:33 PM PDT 24
Peak memory 222436 kb
Host smart-77e14539-ef8d-4d5b-98b9-d5b539f3dd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403386885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.403386885
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.4072454637
Short name T65
Test name
Test status
Simulation time 90383593 ps
CPU time 4.18 seconds
Started Aug 03 05:25:20 PM PDT 24
Finished Aug 03 05:25:24 PM PDT 24
Peak memory 220264 kb
Host smart-1df1dca9-e3c9-40e0-8a4a-d3f154818389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072454637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.4072454637
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2107224925
Short name T189
Test name
Test status
Simulation time 4948383966 ps
CPU time 12.12 seconds
Started Aug 03 05:25:23 PM PDT 24
Finished Aug 03 05:25:35 PM PDT 24
Peak memory 214360 kb
Host smart-37576002-1917-40b3-9e87-b91f6321c0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107224925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2107224925
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2456751225
Short name T751
Test name
Test status
Simulation time 133296605 ps
CPU time 2.47 seconds
Started Aug 03 05:25:22 PM PDT 24
Finished Aug 03 05:25:25 PM PDT 24
Peak memory 206972 kb
Host smart-4dbca113-23c9-4585-b344-fab97463e486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456751225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2456751225
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.551497504
Short name T756
Test name
Test status
Simulation time 863122842 ps
CPU time 7.12 seconds
Started Aug 03 05:25:18 PM PDT 24
Finished Aug 03 05:25:25 PM PDT 24
Peak memory 207104 kb
Host smart-ac420946-13af-4b4b-9d59-e50ec8745328
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551497504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.551497504
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2122196998
Short name T455
Test name
Test status
Simulation time 181269939 ps
CPU time 3.36 seconds
Started Aug 03 05:25:19 PM PDT 24
Finished Aug 03 05:25:23 PM PDT 24
Peak memory 208816 kb
Host smart-0c627ecf-46a0-4f49-b63d-44965b372bd7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122196998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2122196998
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3524221579
Short name T552
Test name
Test status
Simulation time 80788518 ps
CPU time 2.95 seconds
Started Aug 03 05:25:28 PM PDT 24
Finished Aug 03 05:25:31 PM PDT 24
Peak memory 206752 kb
Host smart-026d8452-cdfc-4df7-92c0-441778cf4c6d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524221579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3524221579
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2355440201
Short name T894
Test name
Test status
Simulation time 109273355 ps
CPU time 4.27 seconds
Started Aug 03 05:25:22 PM PDT 24
Finished Aug 03 05:25:26 PM PDT 24
Peak memory 218240 kb
Host smart-a84ce1d1-8fed-4451-ac66-a75f8ba3e782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355440201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2355440201
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.1209868880
Short name T517
Test name
Test status
Simulation time 714088226 ps
CPU time 15.61 seconds
Started Aug 03 05:25:21 PM PDT 24
Finished Aug 03 05:25:37 PM PDT 24
Peak memory 207872 kb
Host smart-9ec9ad85-ad30-47ee-a57b-2e44c6eec03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209868880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1209868880
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3224774323
Short name T403
Test name
Test status
Simulation time 856006473 ps
CPU time 6.72 seconds
Started Aug 03 05:25:19 PM PDT 24
Finished Aug 03 05:25:26 PM PDT 24
Peak memory 222528 kb
Host smart-2fd177c3-45cf-4145-ae6b-16d544ef4f43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224774323 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3224774323
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.587351931
Short name T663
Test name
Test status
Simulation time 195229620 ps
CPU time 4.6 seconds
Started Aug 03 05:25:28 PM PDT 24
Finished Aug 03 05:25:33 PM PDT 24
Peak memory 209388 kb
Host smart-36cbc440-c660-407a-ae5e-323036d8da3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587351931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.587351931
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3649222179
Short name T896
Test name
Test status
Simulation time 225235216 ps
CPU time 2.22 seconds
Started Aug 03 05:25:25 PM PDT 24
Finished Aug 03 05:25:27 PM PDT 24
Peak memory 209720 kb
Host smart-cb6a09de-a803-424e-b531-0c648a2c3bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649222179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3649222179
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.2837275982
Short name T448
Test name
Test status
Simulation time 84992777 ps
CPU time 0.97 seconds
Started Aug 03 05:25:27 PM PDT 24
Finished Aug 03 05:25:28 PM PDT 24
Peak memory 206180 kb
Host smart-68a62018-e4e3-4435-b19a-936fd9054338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837275982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2837275982
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3562553995
Short name T223
Test name
Test status
Simulation time 256628122 ps
CPU time 6.6 seconds
Started Aug 03 05:25:25 PM PDT 24
Finished Aug 03 05:25:32 PM PDT 24
Peak memory 220568 kb
Host smart-675d32a7-205b-44e3-aee7-77e1a7961ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562553995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3562553995
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2473074374
Short name T746
Test name
Test status
Simulation time 96179079 ps
CPU time 2.55 seconds
Started Aug 03 05:25:24 PM PDT 24
Finished Aug 03 05:25:26 PM PDT 24
Peak memory 208724 kb
Host smart-7659c601-2bcb-45de-9054-b6c7d65ac2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473074374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2473074374
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2317662227
Short name T880
Test name
Test status
Simulation time 490010728 ps
CPU time 4.21 seconds
Started Aug 03 05:25:26 PM PDT 24
Finished Aug 03 05:25:30 PM PDT 24
Peak memory 209296 kb
Host smart-46360234-9329-4e69-abd0-c7596a6e0a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317662227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2317662227
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2487299553
Short name T792
Test name
Test status
Simulation time 185271833 ps
CPU time 3.43 seconds
Started Aug 03 05:25:25 PM PDT 24
Finished Aug 03 05:25:29 PM PDT 24
Peak memory 207448 kb
Host smart-4c5d15e9-2bc5-4d47-ae73-e97d73f5160b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487299553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2487299553
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1275788042
Short name T747
Test name
Test status
Simulation time 137734063 ps
CPU time 4.01 seconds
Started Aug 03 05:25:27 PM PDT 24
Finished Aug 03 05:25:32 PM PDT 24
Peak memory 217860 kb
Host smart-598de706-9231-4518-ad63-882899797b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275788042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1275788042
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2648713381
Short name T551
Test name
Test status
Simulation time 97332278 ps
CPU time 3.81 seconds
Started Aug 03 05:25:27 PM PDT 24
Finished Aug 03 05:25:31 PM PDT 24
Peak memory 209052 kb
Host smart-f43612de-5d7e-4616-9e1e-49fac3e31308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648713381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2648713381
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1115517115
Short name T626
Test name
Test status
Simulation time 732234195 ps
CPU time 4.95 seconds
Started Aug 03 05:25:19 PM PDT 24
Finished Aug 03 05:25:24 PM PDT 24
Peak memory 206796 kb
Host smart-ff1fdc2f-953e-462e-bf8e-76ffa5420a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115517115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1115517115
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.4066085683
Short name T262
Test name
Test status
Simulation time 1667284811 ps
CPU time 53.92 seconds
Started Aug 03 05:25:28 PM PDT 24
Finished Aug 03 05:26:22 PM PDT 24
Peak memory 209152 kb
Host smart-85c034d4-0d20-4479-8119-1abbb2b06bee
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066085683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.4066085683
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2806231433
Short name T845
Test name
Test status
Simulation time 204065979 ps
CPU time 2.96 seconds
Started Aug 03 05:25:19 PM PDT 24
Finished Aug 03 05:25:22 PM PDT 24
Peak memory 206916 kb
Host smart-5e7720cf-01cb-4c0f-8f6c-db3b32bd77f8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806231433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2806231433
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1830303621
Short name T616
Test name
Test status
Simulation time 158300185 ps
CPU time 4.71 seconds
Started Aug 03 05:25:23 PM PDT 24
Finished Aug 03 05:25:28 PM PDT 24
Peak memory 208660 kb
Host smart-fb26a192-cb16-487e-8f6a-876aadf7739b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830303621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1830303621
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3247461180
Short name T497
Test name
Test status
Simulation time 1085568951 ps
CPU time 12.87 seconds
Started Aug 03 05:25:31 PM PDT 24
Finished Aug 03 05:25:44 PM PDT 24
Peak memory 208628 kb
Host smart-46382e2f-721b-4b12-aa91-9d475b3a1830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247461180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3247461180
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2505908936
Short name T724
Test name
Test status
Simulation time 66439830 ps
CPU time 2.94 seconds
Started Aug 03 05:25:20 PM PDT 24
Finished Aug 03 05:25:23 PM PDT 24
Peak memory 208808 kb
Host smart-d4626906-f2fd-47b9-883a-1b5e243b5485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505908936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2505908936
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2638417100
Short name T182
Test name
Test status
Simulation time 2519682134 ps
CPU time 39.21 seconds
Started Aug 03 05:25:26 PM PDT 24
Finished Aug 03 05:26:05 PM PDT 24
Peak memory 222620 kb
Host smart-1d948053-1f2e-46ff-9510-5ebea662a19d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638417100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2638417100
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.4123562407
Short name T177
Test name
Test status
Simulation time 315798227 ps
CPU time 11.87 seconds
Started Aug 03 05:25:23 PM PDT 24
Finished Aug 03 05:25:35 PM PDT 24
Peak memory 220400 kb
Host smart-61ff570e-c397-4b70-a9bb-4f4bacf78a46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123562407 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.4123562407
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3583590052
Short name T195
Test name
Test status
Simulation time 236558820 ps
CPU time 5.79 seconds
Started Aug 03 05:25:22 PM PDT 24
Finished Aug 03 05:25:28 PM PDT 24
Peak memory 206964 kb
Host smart-0f055bb0-1230-4f75-9846-192312897f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583590052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3583590052
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3681689919
Short name T37
Test name
Test status
Simulation time 157824115 ps
CPU time 3.45 seconds
Started Aug 03 05:25:22 PM PDT 24
Finished Aug 03 05:25:26 PM PDT 24
Peak memory 210624 kb
Host smart-7f50d009-3ffb-4a25-9140-e67a8b85af90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681689919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3681689919
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2119123337
Short name T752
Test name
Test status
Simulation time 61197940 ps
CPU time 0.75 seconds
Started Aug 03 05:25:26 PM PDT 24
Finished Aug 03 05:25:27 PM PDT 24
Peak memory 205892 kb
Host smart-e56c3b87-37b4-4a80-ad97-1318d82d1efb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119123337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2119123337
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2512497206
Short name T411
Test name
Test status
Simulation time 224170446 ps
CPU time 4.34 seconds
Started Aug 03 05:25:28 PM PDT 24
Finished Aug 03 05:25:33 PM PDT 24
Peak memory 215356 kb
Host smart-61d152f3-4105-41ca-b213-643cd2e17fd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2512497206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2512497206
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3797303941
Short name T708
Test name
Test status
Simulation time 386381751 ps
CPU time 3.06 seconds
Started Aug 03 05:25:29 PM PDT 24
Finished Aug 03 05:25:32 PM PDT 24
Peak memory 207596 kb
Host smart-3fb2af9d-4692-44b2-8468-bd3416b55361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797303941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3797303941
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2823117833
Short name T98
Test name
Test status
Simulation time 268255350 ps
CPU time 9.61 seconds
Started Aug 03 05:25:31 PM PDT 24
Finished Aug 03 05:25:41 PM PDT 24
Peak memory 214296 kb
Host smart-dca4284e-eaa2-4171-8e6f-bcda2239d6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823117833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2823117833
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.499249692
Short name T347
Test name
Test status
Simulation time 136947922 ps
CPU time 5.71 seconds
Started Aug 03 05:25:26 PM PDT 24
Finished Aug 03 05:25:32 PM PDT 24
Peak memory 222416 kb
Host smart-53dc47f7-9884-49d2-9fb1-8e389f5f53f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499249692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.499249692
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1360851268
Short name T750
Test name
Test status
Simulation time 152902352 ps
CPU time 3.36 seconds
Started Aug 03 05:25:21 PM PDT 24
Finished Aug 03 05:25:25 PM PDT 24
Peak memory 220544 kb
Host smart-3846c78c-496d-4d1b-888c-f2e39b4ae52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360851268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1360851268
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1960898921
Short name T570
Test name
Test status
Simulation time 891002941 ps
CPU time 8.81 seconds
Started Aug 03 05:25:33 PM PDT 24
Finished Aug 03 05:25:42 PM PDT 24
Peak memory 219956 kb
Host smart-93e344a5-234b-40ef-bf2d-bab3d7763e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960898921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1960898921
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.165200998
Short name T373
Test name
Test status
Simulation time 66441432 ps
CPU time 3.34 seconds
Started Aug 03 05:25:30 PM PDT 24
Finished Aug 03 05:25:33 PM PDT 24
Peak memory 207340 kb
Host smart-b44addf8-f9b6-4b37-a328-937518617ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165200998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.165200998
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1108664679
Short name T796
Test name
Test status
Simulation time 258200043 ps
CPU time 2.91 seconds
Started Aug 03 05:25:26 PM PDT 24
Finished Aug 03 05:25:29 PM PDT 24
Peak memory 206956 kb
Host smart-fe016b7c-1ebe-46cd-81c0-db135c034496
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108664679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1108664679
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3657403609
Short name T732
Test name
Test status
Simulation time 419305738 ps
CPU time 6.75 seconds
Started Aug 03 05:25:22 PM PDT 24
Finished Aug 03 05:25:29 PM PDT 24
Peak memory 208648 kb
Host smart-de817c3e-dfae-47f2-bd61-46e756a7231a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657403609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3657403609
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1526819469
Short name T890
Test name
Test status
Simulation time 140767646 ps
CPU time 4.57 seconds
Started Aug 03 05:25:28 PM PDT 24
Finished Aug 03 05:25:33 PM PDT 24
Peak memory 208000 kb
Host smart-7dbb618b-4f21-4495-a40e-4ab1cc1b4ecc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526819469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1526819469
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.181419208
Short name T656
Test name
Test status
Simulation time 42878001 ps
CPU time 2.06 seconds
Started Aug 03 05:25:24 PM PDT 24
Finished Aug 03 05:25:26 PM PDT 24
Peak memory 208612 kb
Host smart-d5fbbba1-0c0c-4e0f-8746-c95a0cb1ae44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181419208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.181419208
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2769730971
Short name T646
Test name
Test status
Simulation time 319913772 ps
CPU time 3.89 seconds
Started Aug 03 05:25:23 PM PDT 24
Finished Aug 03 05:25:27 PM PDT 24
Peak memory 206868 kb
Host smart-a6d41240-f769-4264-b7c0-e617e6c852fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769730971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2769730971
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.2906215829
Short name T127
Test name
Test status
Simulation time 446818886 ps
CPU time 9.55 seconds
Started Aug 03 05:25:26 PM PDT 24
Finished Aug 03 05:25:36 PM PDT 24
Peak memory 222472 kb
Host smart-ef1f272b-56cf-4efc-80f7-df4f2fd07a60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906215829 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.2906215829
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.258816579
Short name T263
Test name
Test status
Simulation time 968447931 ps
CPU time 7.28 seconds
Started Aug 03 05:25:27 PM PDT 24
Finished Aug 03 05:25:34 PM PDT 24
Peak memory 208244 kb
Host smart-a7085fa2-c64a-4e55-bede-593dabefabc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258816579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.258816579
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.463024064
Short name T391
Test name
Test status
Simulation time 42266046 ps
CPU time 2.11 seconds
Started Aug 03 05:25:28 PM PDT 24
Finished Aug 03 05:25:31 PM PDT 24
Peak memory 209880 kb
Host smart-3b7eda8e-917f-4eef-a275-d614471eeb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463024064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.463024064
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2513776527
Short name T104
Test name
Test status
Simulation time 15734483 ps
CPU time 0.78 seconds
Started Aug 03 05:25:28 PM PDT 24
Finished Aug 03 05:25:29 PM PDT 24
Peak memory 205896 kb
Host smart-329645fb-bd7d-4a6c-8d28-f7d99c286196
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513776527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2513776527
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.996504898
Short name T232
Test name
Test status
Simulation time 679932019 ps
CPU time 7.13 seconds
Started Aug 03 05:25:31 PM PDT 24
Finished Aug 03 05:25:38 PM PDT 24
Peak memory 214308 kb
Host smart-c3fb6be0-c29c-4dc0-846f-99b05af77b19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=996504898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.996504898
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1298821363
Short name T33
Test name
Test status
Simulation time 102578175 ps
CPU time 3.83 seconds
Started Aug 03 05:25:26 PM PDT 24
Finished Aug 03 05:25:30 PM PDT 24
Peak memory 214240 kb
Host smart-8afaaef9-b020-4cd0-a179-33279ffd9111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298821363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1298821363
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3404475742
Short name T593
Test name
Test status
Simulation time 134918551 ps
CPU time 3.9 seconds
Started Aug 03 05:25:27 PM PDT 24
Finished Aug 03 05:25:31 PM PDT 24
Peak memory 213580 kb
Host smart-44154cfa-26b4-49b4-8bb3-0fda4df841d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404475742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3404475742
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3894676048
Short name T50
Test name
Test status
Simulation time 73795135 ps
CPU time 1.59 seconds
Started Aug 03 05:25:28 PM PDT 24
Finished Aug 03 05:25:29 PM PDT 24
Peak memory 214236 kb
Host smart-85d33fa8-b45a-4b0a-b778-379b6ffbd0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894676048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3894676048
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3293497593
Short name T214
Test name
Test status
Simulation time 226067937 ps
CPU time 3 seconds
Started Aug 03 05:25:26 PM PDT 24
Finished Aug 03 05:25:29 PM PDT 24
Peak memory 214540 kb
Host smart-c4eeb738-25df-4924-936f-518493ddbf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293497593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3293497593
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1514957200
Short name T301
Test name
Test status
Simulation time 95030228 ps
CPU time 3.02 seconds
Started Aug 03 05:25:27 PM PDT 24
Finished Aug 03 05:25:30 PM PDT 24
Peak memory 206944 kb
Host smart-64d473c0-cfca-4805-8925-6a9ee3d49566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514957200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1514957200
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.587527945
Short name T110
Test name
Test status
Simulation time 35263079 ps
CPU time 1.7 seconds
Started Aug 03 05:25:26 PM PDT 24
Finished Aug 03 05:25:28 PM PDT 24
Peak memory 206836 kb
Host smart-a85977f8-a870-4759-a0e2-b2008089d2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587527945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.587527945
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2610011625
Short name T701
Test name
Test status
Simulation time 1239139721 ps
CPU time 3.54 seconds
Started Aug 03 05:25:27 PM PDT 24
Finished Aug 03 05:25:31 PM PDT 24
Peak memory 208664 kb
Host smart-3f0e49d6-802e-476d-899d-92272e37b665
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610011625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2610011625
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.716523161
Short name T381
Test name
Test status
Simulation time 214990562 ps
CPU time 6.79 seconds
Started Aug 03 05:25:25 PM PDT 24
Finished Aug 03 05:25:31 PM PDT 24
Peak memory 208148 kb
Host smart-280d6e46-4a69-47cc-93cb-bf2e35d60e18
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716523161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.716523161
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1974245897
Short name T562
Test name
Test status
Simulation time 151552071 ps
CPU time 2.4 seconds
Started Aug 03 05:25:27 PM PDT 24
Finished Aug 03 05:25:30 PM PDT 24
Peak memory 206108 kb
Host smart-abb8567a-0fdb-4427-ac9b-61cf3b367ed2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974245897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1974245897
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.4292609304
Short name T543
Test name
Test status
Simulation time 59671125 ps
CPU time 2.05 seconds
Started Aug 03 05:25:27 PM PDT 24
Finished Aug 03 05:25:29 PM PDT 24
Peak memory 207468 kb
Host smart-a674f89d-4729-48e2-ae7e-529d8f7c42a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292609304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.4292609304
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.870973277
Short name T426
Test name
Test status
Simulation time 832418641 ps
CPU time 3.39 seconds
Started Aug 03 05:25:26 PM PDT 24
Finished Aug 03 05:25:30 PM PDT 24
Peak memory 208328 kb
Host smart-444052ce-e011-4e75-9a49-4a197323cbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870973277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.870973277
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3909363234
Short name T327
Test name
Test status
Simulation time 195981987 ps
CPU time 9.01 seconds
Started Aug 03 05:25:30 PM PDT 24
Finished Aug 03 05:25:40 PM PDT 24
Peak memory 222388 kb
Host smart-e8c1350c-2988-4b22-b75d-b7b0c71798f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909363234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3909363234
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.4134279437
Short name T81
Test name
Test status
Simulation time 232906199 ps
CPU time 7.58 seconds
Started Aug 03 05:25:31 PM PDT 24
Finished Aug 03 05:25:38 PM PDT 24
Peak memory 221592 kb
Host smart-87c4a565-025f-4412-b8c6-00a14f5460d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134279437 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.4134279437
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.649253029
Short name T247
Test name
Test status
Simulation time 1239372931 ps
CPU time 5.43 seconds
Started Aug 03 05:25:25 PM PDT 24
Finished Aug 03 05:25:30 PM PDT 24
Peak memory 218204 kb
Host smart-58cbe0bc-2bf2-4d7b-89ac-9a426b72d8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649253029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.649253029
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.4054657879
Short name T704
Test name
Test status
Simulation time 418380947 ps
CPU time 3.05 seconds
Started Aug 03 05:25:29 PM PDT 24
Finished Aug 03 05:25:32 PM PDT 24
Peak memory 210100 kb
Host smart-deb2df06-a15e-4f2d-8c09-088f483d5d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054657879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.4054657879
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2649853619
Short name T789
Test name
Test status
Simulation time 13739155 ps
CPU time 0.81 seconds
Started Aug 03 05:25:32 PM PDT 24
Finished Aug 03 05:25:33 PM PDT 24
Peak memory 205932 kb
Host smart-b9dbdd3c-7a75-4a66-a2c9-840912f9548d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649853619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2649853619
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1218854975
Short name T235
Test name
Test status
Simulation time 37826766 ps
CPU time 2.78 seconds
Started Aug 03 05:25:34 PM PDT 24
Finished Aug 03 05:25:37 PM PDT 24
Peak memory 214292 kb
Host smart-8592c36f-928e-4e8b-aa1b-ea939234225d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1218854975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1218854975
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2261781904
Short name T34
Test name
Test status
Simulation time 53345078 ps
CPU time 1.36 seconds
Started Aug 03 05:25:30 PM PDT 24
Finished Aug 03 05:25:32 PM PDT 24
Peak memory 209576 kb
Host smart-e1536f67-d5a7-4681-8fc8-7e2c28fc07f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261781904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2261781904
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.540985281
Short name T604
Test name
Test status
Simulation time 42996477 ps
CPU time 1.64 seconds
Started Aug 03 05:25:31 PM PDT 24
Finished Aug 03 05:25:33 PM PDT 24
Peak memory 207128 kb
Host smart-19c0a23f-c03d-41e8-a9e8-3398d75fc114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540985281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.540985281
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2608966
Short name T306
Test name
Test status
Simulation time 420871132 ps
CPU time 3.27 seconds
Started Aug 03 05:25:39 PM PDT 24
Finished Aug 03 05:25:42 PM PDT 24
Peak memory 214276 kb
Host smart-0a702cc0-03bf-49cf-8d92-87f95f60db59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2608966
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.977853572
Short name T615
Test name
Test status
Simulation time 335347704 ps
CPU time 2.9 seconds
Started Aug 03 05:25:28 PM PDT 24
Finished Aug 03 05:25:31 PM PDT 24
Peak memory 218964 kb
Host smart-84727313-ff00-4282-830e-c79ceff972d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977853572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.977853572
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.944404276
Short name T836
Test name
Test status
Simulation time 141291945 ps
CPU time 6.04 seconds
Started Aug 03 05:25:39 PM PDT 24
Finished Aug 03 05:25:45 PM PDT 24
Peak memory 210216 kb
Host smart-c24a9e6f-3402-45e1-b9b7-7af924251681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944404276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.944404276
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2216327727
Short name T595
Test name
Test status
Simulation time 108917610 ps
CPU time 2.28 seconds
Started Aug 03 05:25:40 PM PDT 24
Finished Aug 03 05:25:43 PM PDT 24
Peak memory 206896 kb
Host smart-b418681f-a7e5-4ea3-b5cf-1f9e671d9623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216327727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2216327727
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.4189286976
Short name T314
Test name
Test status
Simulation time 96249323 ps
CPU time 3.21 seconds
Started Aug 03 05:25:30 PM PDT 24
Finished Aug 03 05:25:34 PM PDT 24
Peak memory 207680 kb
Host smart-6e05128a-5b02-4e0d-bab4-22958f3bb6a9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189286976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.4189286976
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2080262753
Short name T457
Test name
Test status
Simulation time 66843405 ps
CPU time 2.74 seconds
Started Aug 03 05:25:31 PM PDT 24
Finished Aug 03 05:25:34 PM PDT 24
Peak memory 206908 kb
Host smart-76ec8b41-d8b2-43dc-9457-32a2a8a7f5e5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080262753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2080262753
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3639216090
Short name T447
Test name
Test status
Simulation time 80934723 ps
CPU time 1.78 seconds
Started Aug 03 05:25:31 PM PDT 24
Finished Aug 03 05:25:33 PM PDT 24
Peak memory 206916 kb
Host smart-defce4eb-58fd-451c-800c-8062dbefddc3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639216090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3639216090
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2703224295
Short name T735
Test name
Test status
Simulation time 348476401 ps
CPU time 2.68 seconds
Started Aug 03 05:25:28 PM PDT 24
Finished Aug 03 05:25:31 PM PDT 24
Peak memory 207472 kb
Host smart-6b7b2e98-7246-4407-972f-a316826ec0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703224295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2703224295
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.530087205
Short name T820
Test name
Test status
Simulation time 183784541 ps
CPU time 3.81 seconds
Started Aug 03 05:25:30 PM PDT 24
Finished Aug 03 05:25:34 PM PDT 24
Peak memory 207840 kb
Host smart-df4ff803-ea92-470f-a842-fc4df069882c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530087205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.530087205
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2730768214
Short name T622
Test name
Test status
Simulation time 429023984 ps
CPU time 6.5 seconds
Started Aug 03 05:25:40 PM PDT 24
Finished Aug 03 05:25:46 PM PDT 24
Peak memory 218324 kb
Host smart-64d8a129-bad5-48fb-bc63-deea9dac7805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730768214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2730768214
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.887422005
Short name T753
Test name
Test status
Simulation time 928241783 ps
CPU time 2.81 seconds
Started Aug 03 05:25:28 PM PDT 24
Finished Aug 03 05:25:31 PM PDT 24
Peak memory 210276 kb
Host smart-e800895f-a3c8-40c7-8a79-85c0175ef276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887422005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.887422005
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.783246542
Short name T105
Test name
Test status
Simulation time 49058965 ps
CPU time 0.86 seconds
Started Aug 03 05:25:36 PM PDT 24
Finished Aug 03 05:25:37 PM PDT 24
Peak memory 205956 kb
Host smart-5340290d-cd0b-498b-99c2-ed1d5043f609
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783246542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.783246542
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2510854080
Short name T379
Test name
Test status
Simulation time 587580664 ps
CPU time 8.94 seconds
Started Aug 03 05:25:32 PM PDT 24
Finished Aug 03 05:25:41 PM PDT 24
Peak memory 222380 kb
Host smart-6b87e93a-8f1f-4aa9-8440-a2b5bdf0f033
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2510854080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2510854080
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1385113462
Short name T309
Test name
Test status
Simulation time 202888498 ps
CPU time 4.4 seconds
Started Aug 03 05:25:28 PM PDT 24
Finished Aug 03 05:25:33 PM PDT 24
Peak memory 218376 kb
Host smart-5fcb5444-617c-4da1-978c-665965c8ed5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385113462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1385113462
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2231740534
Short name T62
Test name
Test status
Simulation time 171106220 ps
CPU time 4.43 seconds
Started Aug 03 05:25:33 PM PDT 24
Finished Aug 03 05:25:38 PM PDT 24
Peak memory 207796 kb
Host smart-48f4603c-4e40-4196-bed3-d46b7db60691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231740534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2231740534
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.347262393
Short name T800
Test name
Test status
Simulation time 779213668 ps
CPU time 3.94 seconds
Started Aug 03 05:25:28 PM PDT 24
Finished Aug 03 05:25:32 PM PDT 24
Peak memory 209204 kb
Host smart-5c9c7fc2-123a-4dc3-b732-3396b972f435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347262393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.347262393
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3465348114
Short name T673
Test name
Test status
Simulation time 413590719 ps
CPU time 2.57 seconds
Started Aug 03 05:25:34 PM PDT 24
Finished Aug 03 05:25:36 PM PDT 24
Peak memory 208760 kb
Host smart-300b2ebd-5e82-4532-99f9-3e2321f7ed08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465348114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3465348114
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.77252671
Short name T86
Test name
Test status
Simulation time 111486015 ps
CPU time 2.96 seconds
Started Aug 03 05:25:33 PM PDT 24
Finished Aug 03 05:25:36 PM PDT 24
Peak memory 207448 kb
Host smart-c5f79d53-a767-4f1e-9cf9-20eb5d71150b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77252671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.77252671
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.2819372361
Short name T355
Test name
Test status
Simulation time 52026466 ps
CPU time 2.75 seconds
Started Aug 03 05:25:30 PM PDT 24
Finished Aug 03 05:25:33 PM PDT 24
Peak memory 206920 kb
Host smart-d6c53a2e-d87e-44c0-b628-566d037e9476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819372361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2819372361
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.475415938
Short name T893
Test name
Test status
Simulation time 36970889 ps
CPU time 2.29 seconds
Started Aug 03 05:25:27 PM PDT 24
Finished Aug 03 05:25:29 PM PDT 24
Peak memory 206848 kb
Host smart-bb98efe5-344a-4598-8c98-ac60a4c9cec1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475415938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.475415938
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2503540220
Short name T768
Test name
Test status
Simulation time 148142002 ps
CPU time 3.02 seconds
Started Aug 03 05:25:32 PM PDT 24
Finished Aug 03 05:25:35 PM PDT 24
Peak memory 207320 kb
Host smart-83836394-d9eb-4001-9f24-70a42c40aaee
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503540220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2503540220
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1147609264
Short name T533
Test name
Test status
Simulation time 222769405 ps
CPU time 2.89 seconds
Started Aug 03 05:25:30 PM PDT 24
Finished Aug 03 05:25:33 PM PDT 24
Peak memory 208608 kb
Host smart-bd3799f8-9d5d-463b-bb41-fe684476f6cb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147609264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1147609264
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1262654426
Short name T354
Test name
Test status
Simulation time 20290268 ps
CPU time 1.79 seconds
Started Aug 03 05:25:30 PM PDT 24
Finished Aug 03 05:25:32 PM PDT 24
Peak memory 208056 kb
Host smart-e66d46ac-80be-42a6-8a59-e153e17f0c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262654426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1262654426
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3765432921
Short name T740
Test name
Test status
Simulation time 126426100 ps
CPU time 3.49 seconds
Started Aug 03 05:25:31 PM PDT 24
Finished Aug 03 05:25:34 PM PDT 24
Peak memory 207116 kb
Host smart-04a5dc8b-2794-43da-aeaf-e3575f1b5f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765432921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3765432921
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.1886825158
Short name T811
Test name
Test status
Simulation time 203976600 ps
CPU time 5.15 seconds
Started Aug 03 05:25:28 PM PDT 24
Finished Aug 03 05:25:33 PM PDT 24
Peak memory 218276 kb
Host smart-6eb8ce0b-24b0-4a8e-8245-50b41977d67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886825158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1886825158
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2937593101
Short name T821
Test name
Test status
Simulation time 231302179 ps
CPU time 2.6 seconds
Started Aug 03 05:25:30 PM PDT 24
Finished Aug 03 05:25:33 PM PDT 24
Peak memory 210084 kb
Host smart-6fe3ac6f-ac0b-4e9f-b3d9-26228c704cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937593101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2937593101
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1341823777
Short name T107
Test name
Test status
Simulation time 11242995 ps
CPU time 0.8 seconds
Started Aug 03 05:25:32 PM PDT 24
Finished Aug 03 05:25:34 PM PDT 24
Peak memory 205968 kb
Host smart-3d04dced-1728-4f51-a8a0-8dd1cf6fd3fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341823777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1341823777
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.621163914
Short name T271
Test name
Test status
Simulation time 145825541 ps
CPU time 7.24 seconds
Started Aug 03 05:25:35 PM PDT 24
Finished Aug 03 05:25:42 PM PDT 24
Peak memory 214324 kb
Host smart-36593275-576c-4fec-9edc-c75b26f81c90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=621163914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.621163914
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2273942104
Short name T57
Test name
Test status
Simulation time 72833575 ps
CPU time 2.41 seconds
Started Aug 03 05:25:37 PM PDT 24
Finished Aug 03 05:25:40 PM PDT 24
Peak memory 220252 kb
Host smart-00d36148-7c96-4e39-9a4d-d2bf36c2de25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273942104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2273942104
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.4083840164
Short name T799
Test name
Test status
Simulation time 889648650 ps
CPU time 5.92 seconds
Started Aug 03 05:25:35 PM PDT 24
Finished Aug 03 05:25:41 PM PDT 24
Peak memory 218036 kb
Host smart-e46e9a3b-14a6-46ee-ae46-7168477afcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083840164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.4083840164
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1376380911
Short name T849
Test name
Test status
Simulation time 150765750 ps
CPU time 2.34 seconds
Started Aug 03 05:25:31 PM PDT 24
Finished Aug 03 05:25:33 PM PDT 24
Peak memory 214324 kb
Host smart-7fe5f7ed-b4d3-4c9f-af73-784793656305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376380911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1376380911
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2313791083
Short name T387
Test name
Test status
Simulation time 103311235 ps
CPU time 1.88 seconds
Started Aug 03 05:25:39 PM PDT 24
Finished Aug 03 05:25:41 PM PDT 24
Peak memory 214252 kb
Host smart-553e0a11-dc11-445f-99a0-c4ae3033a039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313791083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2313791083
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3930831753
Short name T212
Test name
Test status
Simulation time 394836205 ps
CPU time 4.2 seconds
Started Aug 03 05:25:28 PM PDT 24
Finished Aug 03 05:25:33 PM PDT 24
Peak memory 222464 kb
Host smart-832a7c31-6b7e-4db2-bf60-b90e00b6b405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930831753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3930831753
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.439115743
Short name T643
Test name
Test status
Simulation time 267134334 ps
CPU time 3.56 seconds
Started Aug 03 05:25:35 PM PDT 24
Finished Aug 03 05:25:38 PM PDT 24
Peak memory 208848 kb
Host smart-5623259c-597f-48a8-8008-cfe9d1413315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439115743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.439115743
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1860478354
Short name T265
Test name
Test status
Simulation time 36145872 ps
CPU time 2.16 seconds
Started Aug 03 05:25:31 PM PDT 24
Finished Aug 03 05:25:33 PM PDT 24
Peak memory 206124 kb
Host smart-c72c2bb6-04a5-44a5-9cad-3e5c3e844e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860478354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1860478354
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3034358812
Short name T731
Test name
Test status
Simulation time 428772961 ps
CPU time 3.23 seconds
Started Aug 03 05:25:28 PM PDT 24
Finished Aug 03 05:25:31 PM PDT 24
Peak memory 206912 kb
Host smart-b3b50aca-2e0b-4e68-80c5-f59665bfec31
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034358812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3034358812
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1237094879
Short name T838
Test name
Test status
Simulation time 166935023 ps
CPU time 3.96 seconds
Started Aug 03 05:25:35 PM PDT 24
Finished Aug 03 05:25:39 PM PDT 24
Peak memory 206820 kb
Host smart-5bd964db-96b4-4e69-b1f2-5b61cca5e3f0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237094879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1237094879
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3448751778
Short name T715
Test name
Test status
Simulation time 558522656 ps
CPU time 2.88 seconds
Started Aug 03 05:25:39 PM PDT 24
Finished Aug 03 05:25:42 PM PDT 24
Peak memory 206944 kb
Host smart-46f5a2b7-2f48-4c25-b58e-ddb17fc07873
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448751778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3448751778
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3820435594
Short name T578
Test name
Test status
Simulation time 374174639 ps
CPU time 3.65 seconds
Started Aug 03 05:25:32 PM PDT 24
Finished Aug 03 05:25:36 PM PDT 24
Peak memory 208752 kb
Host smart-4f5c6efb-b4ba-4491-af99-e49c28581d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820435594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3820435594
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.1415960869
Short name T862
Test name
Test status
Simulation time 1064743009 ps
CPU time 4.06 seconds
Started Aug 03 05:25:34 PM PDT 24
Finished Aug 03 05:25:38 PM PDT 24
Peak memory 207824 kb
Host smart-b5cc280f-a4f5-4ad8-8e77-0bf835253313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415960869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1415960869
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1206366912
Short name T279
Test name
Test status
Simulation time 210154871 ps
CPU time 6.4 seconds
Started Aug 03 05:25:31 PM PDT 24
Finished Aug 03 05:25:37 PM PDT 24
Peak memory 207632 kb
Host smart-355d9faf-8b61-479d-9cb3-0f19dba11db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206366912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1206366912
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1753473150
Short name T823
Test name
Test status
Simulation time 84873541 ps
CPU time 2.05 seconds
Started Aug 03 05:25:36 PM PDT 24
Finished Aug 03 05:25:38 PM PDT 24
Peak memory 210000 kb
Host smart-9b3d8461-21d2-4851-afa4-76ca4a9a2001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753473150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1753473150
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2915766223
Short name T766
Test name
Test status
Simulation time 46912714 ps
CPU time 0.86 seconds
Started Aug 03 05:25:36 PM PDT 24
Finished Aug 03 05:25:37 PM PDT 24
Peak memory 205952 kb
Host smart-10fa53e8-6914-4c88-b0f0-1e7151621ae9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915766223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2915766223
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.659741267
Short name T407
Test name
Test status
Simulation time 226919869 ps
CPU time 6.32 seconds
Started Aug 03 05:25:34 PM PDT 24
Finished Aug 03 05:25:40 PM PDT 24
Peak memory 215040 kb
Host smart-48ee7915-82de-42ef-afc1-462a532e135f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=659741267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.659741267
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3349015801
Short name T19
Test name
Test status
Simulation time 142490917 ps
CPU time 6.79 seconds
Started Aug 03 05:25:35 PM PDT 24
Finished Aug 03 05:25:42 PM PDT 24
Peak memory 210532 kb
Host smart-12531c23-6101-4da1-94dd-1c5fc3525e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349015801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3349015801
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3138092817
Short name T738
Test name
Test status
Simulation time 106735727 ps
CPU time 1.87 seconds
Started Aug 03 05:25:43 PM PDT 24
Finished Aug 03 05:25:45 PM PDT 24
Peak memory 209680 kb
Host smart-aacaf816-aa63-4c4d-8af8-831163a0507a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138092817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3138092817
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3989096179
Short name T91
Test name
Test status
Simulation time 147330542 ps
CPU time 5.62 seconds
Started Aug 03 05:25:35 PM PDT 24
Finished Aug 03 05:25:41 PM PDT 24
Peak memory 220784 kb
Host smart-79d97d84-a3f8-4197-a4b9-4ef49412b1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989096179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3989096179
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1409375277
Short name T323
Test name
Test status
Simulation time 1424557169 ps
CPU time 7.13 seconds
Started Aug 03 05:25:37 PM PDT 24
Finished Aug 03 05:25:45 PM PDT 24
Peak memory 214236 kb
Host smart-fa988124-c5f4-4d34-ac86-107abf4790e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409375277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1409375277
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_sideload.4251735959
Short name T402
Test name
Test status
Simulation time 233433127 ps
CPU time 3.17 seconds
Started Aug 03 05:25:34 PM PDT 24
Finished Aug 03 05:25:37 PM PDT 24
Peak memory 208428 kb
Host smart-bee0b49f-e527-4824-980a-89ebce0698ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251735959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.4251735959
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1809816301
Short name T477
Test name
Test status
Simulation time 30268432 ps
CPU time 2.11 seconds
Started Aug 03 05:25:52 PM PDT 24
Finished Aug 03 05:25:54 PM PDT 24
Peak memory 208948 kb
Host smart-81a2b111-70b2-4adc-aa7a-11b1124955fb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809816301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1809816301
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1143266991
Short name T470
Test name
Test status
Simulation time 825084995 ps
CPU time 7.25 seconds
Started Aug 03 05:25:34 PM PDT 24
Finished Aug 03 05:25:41 PM PDT 24
Peak memory 208576 kb
Host smart-7028fdf2-f96d-4d21-80ab-bcfed12c432f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143266991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1143266991
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3272602224
Short name T866
Test name
Test status
Simulation time 87077206 ps
CPU time 1.88 seconds
Started Aug 03 05:25:42 PM PDT 24
Finished Aug 03 05:25:44 PM PDT 24
Peak memory 208516 kb
Host smart-85543d98-2d2f-4329-9f64-bd2d24d952f4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272602224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3272602224
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.823323097
Short name T401
Test name
Test status
Simulation time 1140953038 ps
CPU time 5.84 seconds
Started Aug 03 05:25:35 PM PDT 24
Finished Aug 03 05:25:41 PM PDT 24
Peak memory 209140 kb
Host smart-9a8d0f1a-432e-417f-b1ce-81f8b5a80577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823323097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.823323097
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1998405195
Short name T652
Test name
Test status
Simulation time 2785048096 ps
CPU time 6.94 seconds
Started Aug 03 05:25:33 PM PDT 24
Finished Aug 03 05:25:41 PM PDT 24
Peak memory 208852 kb
Host smart-b833f0b0-67cc-47cf-a6f9-de4128f86d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998405195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1998405195
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3009240892
Short name T26
Test name
Test status
Simulation time 513924348 ps
CPU time 7.67 seconds
Started Aug 03 05:25:34 PM PDT 24
Finished Aug 03 05:25:42 PM PDT 24
Peak memory 215072 kb
Host smart-ebde90e0-fcf8-4cd3-a9a3-3978d990a8ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009240892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3009240892
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.601639543
Short name T203
Test name
Test status
Simulation time 464835392 ps
CPU time 11.92 seconds
Started Aug 03 05:25:32 PM PDT 24
Finished Aug 03 05:25:44 PM PDT 24
Peak memory 209792 kb
Host smart-4e303495-ae3d-4bba-97d0-a33227919ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601639543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.601639543
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.52071247
Short name T716
Test name
Test status
Simulation time 131866412 ps
CPU time 2.99 seconds
Started Aug 03 05:25:43 PM PDT 24
Finished Aug 03 05:25:46 PM PDT 24
Peak memory 210220 kb
Host smart-059480aa-5c63-4e56-bc25-504f58275b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52071247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.52071247
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2365724409
Short name T864
Test name
Test status
Simulation time 36331744 ps
CPU time 0.78 seconds
Started Aug 03 05:23:26 PM PDT 24
Finished Aug 03 05:23:27 PM PDT 24
Peak memory 205940 kb
Host smart-9938ee00-cffb-4751-b4f9-d5c0e6a115f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365724409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2365724409
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2594906788
Short name T875
Test name
Test status
Simulation time 959484459 ps
CPU time 45.31 seconds
Started Aug 03 05:23:26 PM PDT 24
Finished Aug 03 05:24:12 PM PDT 24
Peak memory 214552 kb
Host smart-3ff1dd7c-df5d-4047-8356-c2b22052f338
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2594906788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2594906788
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1292898235
Short name T686
Test name
Test status
Simulation time 312584612 ps
CPU time 4.52 seconds
Started Aug 03 05:23:24 PM PDT 24
Finished Aug 03 05:23:29 PM PDT 24
Peak memory 221240 kb
Host smart-d596b18e-5aea-4c69-9d17-09c840fcacd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292898235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1292898235
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.825953356
Short name T644
Test name
Test status
Simulation time 1746966090 ps
CPU time 4 seconds
Started Aug 03 05:23:29 PM PDT 24
Finished Aug 03 05:23:34 PM PDT 24
Peak memory 208196 kb
Host smart-38f69c27-dd83-4d0c-8ae6-ce77bc3d14df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825953356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.825953356
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.240489493
Short name T244
Test name
Test status
Simulation time 28829552 ps
CPU time 1.99 seconds
Started Aug 03 05:23:25 PM PDT 24
Finished Aug 03 05:23:27 PM PDT 24
Peak memory 214232 kb
Host smart-346bca4a-3b07-4e04-abee-62086d476004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240489493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.240489493
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1668802072
Short name T651
Test name
Test status
Simulation time 98101908 ps
CPU time 4.6 seconds
Started Aug 03 05:23:25 PM PDT 24
Finished Aug 03 05:23:30 PM PDT 24
Peak memory 220372 kb
Host smart-649f0156-5b7e-4258-91d4-871aead580ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668802072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1668802072
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.4010423346
Short name T655
Test name
Test status
Simulation time 612277694 ps
CPU time 3.58 seconds
Started Aug 03 05:23:26 PM PDT 24
Finished Aug 03 05:23:30 PM PDT 24
Peak memory 214308 kb
Host smart-69143898-f5b5-4c1e-abbc-cd083383efc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010423346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.4010423346
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3509176469
Short name T412
Test name
Test status
Simulation time 199185586 ps
CPU time 4.9 seconds
Started Aug 03 05:23:23 PM PDT 24
Finished Aug 03 05:23:28 PM PDT 24
Peak memory 209744 kb
Host smart-05d698a5-93d0-41d3-ae53-712b0f3485f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509176469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3509176469
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3497408529
Short name T340
Test name
Test status
Simulation time 315401458 ps
CPU time 2.89 seconds
Started Aug 03 05:23:26 PM PDT 24
Finished Aug 03 05:23:29 PM PDT 24
Peak memory 206900 kb
Host smart-eb968f6b-ae2e-43ba-98f6-ce477ac3608e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497408529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3497408529
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3202662744
Short name T779
Test name
Test status
Simulation time 67891377 ps
CPU time 3.55 seconds
Started Aug 03 05:23:25 PM PDT 24
Finished Aug 03 05:23:29 PM PDT 24
Peak memory 208628 kb
Host smart-f9b406b0-681e-4d12-bc86-85588259250f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202662744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3202662744
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3365825352
Short name T404
Test name
Test status
Simulation time 67744970 ps
CPU time 3 seconds
Started Aug 03 05:23:30 PM PDT 24
Finished Aug 03 05:23:33 PM PDT 24
Peak memory 207892 kb
Host smart-6b0bfcc7-7a67-48c8-b563-e87485a0f167
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365825352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3365825352
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.686962354
Short name T505
Test name
Test status
Simulation time 37699622 ps
CPU time 2.31 seconds
Started Aug 03 05:23:30 PM PDT 24
Finished Aug 03 05:23:32 PM PDT 24
Peak memory 207328 kb
Host smart-09de70cd-7f53-4a06-8c73-093e79cf27de
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686962354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.686962354
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2608964199
Short name T414
Test name
Test status
Simulation time 152000970 ps
CPU time 2.49 seconds
Started Aug 03 05:23:24 PM PDT 24
Finished Aug 03 05:23:27 PM PDT 24
Peak memory 209564 kb
Host smart-35369c55-f6ce-44b9-acc0-76d18d838b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608964199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2608964199
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.410677665
Short name T882
Test name
Test status
Simulation time 782486971 ps
CPU time 7.37 seconds
Started Aug 03 05:23:28 PM PDT 24
Finished Aug 03 05:23:36 PM PDT 24
Peak memory 206908 kb
Host smart-80281986-0fc4-4e55-a22e-f837ff8245f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410677665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.410677665
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.3874970527
Short name T281
Test name
Test status
Simulation time 936312879 ps
CPU time 17.91 seconds
Started Aug 03 05:23:25 PM PDT 24
Finished Aug 03 05:23:43 PM PDT 24
Peak memory 216596 kb
Host smart-376fb03f-6c31-4b00-930a-f40912af4d71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874970527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3874970527
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.127653866
Short name T178
Test name
Test status
Simulation time 587509763 ps
CPU time 21.14 seconds
Started Aug 03 05:23:25 PM PDT 24
Finished Aug 03 05:23:46 PM PDT 24
Peak memory 222464 kb
Host smart-a46d4806-a88a-41f8-91b2-3003336021ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127653866 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.127653866
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3528570880
Short name T718
Test name
Test status
Simulation time 126186174 ps
CPU time 2.61 seconds
Started Aug 03 05:23:26 PM PDT 24
Finished Aug 03 05:23:29 PM PDT 24
Peak memory 207560 kb
Host smart-613a8979-07ae-4357-b596-b02afcc3368f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528570880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3528570880
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3784444508
Short name T392
Test name
Test status
Simulation time 77562080 ps
CPU time 2.05 seconds
Started Aug 03 05:23:24 PM PDT 24
Finished Aug 03 05:23:26 PM PDT 24
Peak memory 209956 kb
Host smart-0f17ef90-2506-40d3-b95d-e01a83dd81ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784444508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3784444508
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1368554705
Short name T512
Test name
Test status
Simulation time 13215894 ps
CPU time 0.81 seconds
Started Aug 03 05:23:29 PM PDT 24
Finished Aug 03 05:23:30 PM PDT 24
Peak memory 205948 kb
Host smart-1aa4486b-4d55-421c-b895-313c9a07714e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368554705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1368554705
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.4071452965
Short name T831
Test name
Test status
Simulation time 371762142 ps
CPU time 3.51 seconds
Started Aug 03 05:23:33 PM PDT 24
Finished Aug 03 05:23:37 PM PDT 24
Peak memory 214320 kb
Host smart-dffc7452-940b-4adc-8a6f-f38a18a31f0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4071452965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.4071452965
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.4228930428
Short name T239
Test name
Test status
Simulation time 27712851 ps
CPU time 1.28 seconds
Started Aug 03 05:23:34 PM PDT 24
Finished Aug 03 05:23:35 PM PDT 24
Peak memory 207424 kb
Host smart-7732d8b6-51cc-46ee-8d62-393fdaf30c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228930428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.4228930428
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2048006514
Short name T241
Test name
Test status
Simulation time 115871951 ps
CPU time 2.69 seconds
Started Aug 03 05:23:33 PM PDT 24
Finished Aug 03 05:23:35 PM PDT 24
Peak memory 214344 kb
Host smart-84fdf9eb-de65-45ff-9d71-096692017d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048006514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2048006514
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3029114798
Short name T594
Test name
Test status
Simulation time 254937588 ps
CPU time 3.51 seconds
Started Aug 03 05:23:34 PM PDT 24
Finished Aug 03 05:23:37 PM PDT 24
Peak memory 214244 kb
Host smart-05e7c7bc-8e1f-4046-b724-3480ba3abe34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029114798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3029114798
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.4259114290
Short name T378
Test name
Test status
Simulation time 86200122 ps
CPU time 4.06 seconds
Started Aug 03 05:23:32 PM PDT 24
Finished Aug 03 05:23:36 PM PDT 24
Peak memory 214268 kb
Host smart-7b5cc948-78a1-40f5-b093-e22d1e1d57b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259114290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.4259114290
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1064261717
Short name T192
Test name
Test status
Simulation time 743223146 ps
CPU time 6.03 seconds
Started Aug 03 05:23:23 PM PDT 24
Finished Aug 03 05:23:29 PM PDT 24
Peak memory 208996 kb
Host smart-cb169662-b071-40db-88fb-635bf4b774bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064261717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1064261717
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1887095242
Short name T464
Test name
Test status
Simulation time 217147569 ps
CPU time 6.36 seconds
Started Aug 03 05:23:26 PM PDT 24
Finished Aug 03 05:23:32 PM PDT 24
Peak memory 208036 kb
Host smart-d3a3e919-ac2f-4b82-9e2e-6858ac032bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887095242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1887095242
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.2457863918
Short name T761
Test name
Test status
Simulation time 133274473 ps
CPU time 3.17 seconds
Started Aug 03 05:23:24 PM PDT 24
Finished Aug 03 05:23:27 PM PDT 24
Peak memory 208696 kb
Host smart-605b4cf5-c00a-41b0-8b13-343501a2aff8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457863918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2457863918
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.336024957
Short name T479
Test name
Test status
Simulation time 326150192 ps
CPU time 3.9 seconds
Started Aug 03 05:23:23 PM PDT 24
Finished Aug 03 05:23:27 PM PDT 24
Peak memory 208552 kb
Host smart-048908c3-5903-429c-af3a-70a6e2d705e3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336024957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.336024957
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3855900737
Short name T832
Test name
Test status
Simulation time 69923281 ps
CPU time 2.55 seconds
Started Aug 03 05:23:23 PM PDT 24
Finished Aug 03 05:23:26 PM PDT 24
Peak memory 208744 kb
Host smart-caadead6-1c7c-4c5d-8a15-e2afef21ce86
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855900737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3855900737
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2580542562
Short name T563
Test name
Test status
Simulation time 240620947 ps
CPU time 2.76 seconds
Started Aug 03 05:23:33 PM PDT 24
Finished Aug 03 05:23:35 PM PDT 24
Peak memory 215700 kb
Host smart-3ef69baf-7329-4603-9782-83f133419fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580542562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2580542562
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2906694459
Short name T633
Test name
Test status
Simulation time 355220116 ps
CPU time 4.08 seconds
Started Aug 03 05:23:25 PM PDT 24
Finished Aug 03 05:23:29 PM PDT 24
Peak memory 208496 kb
Host smart-ae287451-64cf-4230-879a-aed2c652aa00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906694459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2906694459
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2465267171
Short name T275
Test name
Test status
Simulation time 753625448 ps
CPU time 5.9 seconds
Started Aug 03 05:23:33 PM PDT 24
Finished Aug 03 05:23:39 PM PDT 24
Peak memory 218284 kb
Host smart-f1b3aaaa-7998-4129-9ea0-9f86ed0f00c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465267171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2465267171
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.4136085077
Short name T767
Test name
Test status
Simulation time 45093235 ps
CPU time 1.19 seconds
Started Aug 03 05:23:30 PM PDT 24
Finished Aug 03 05:23:32 PM PDT 24
Peak memory 208468 kb
Host smart-49d80ae0-c5dd-4ab3-a115-e8064769e1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136085077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.4136085077
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1798934141
Short name T571
Test name
Test status
Simulation time 13778411 ps
CPU time 0.75 seconds
Started Aug 03 05:23:37 PM PDT 24
Finished Aug 03 05:23:38 PM PDT 24
Peak memory 205932 kb
Host smart-7229809d-f3e1-4652-9648-d0fa7c4dc4ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798934141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1798934141
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.4184486875
Short name T349
Test name
Test status
Simulation time 2551160240 ps
CPU time 7.67 seconds
Started Aug 03 05:23:39 PM PDT 24
Finished Aug 03 05:23:47 PM PDT 24
Peak memory 221788 kb
Host smart-4c1277e8-b092-4a24-9044-5746a2b75cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184486875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.4184486875
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3019343149
Short name T18
Test name
Test status
Simulation time 113765695 ps
CPU time 2.23 seconds
Started Aug 03 05:23:31 PM PDT 24
Finished Aug 03 05:23:33 PM PDT 24
Peak memory 210376 kb
Host smart-2d27b788-7a31-4fdb-8858-cb3b0e85ccf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019343149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3019343149
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3425194955
Short name T307
Test name
Test status
Simulation time 270155366 ps
CPU time 2.9 seconds
Started Aug 03 05:23:39 PM PDT 24
Finished Aug 03 05:23:42 PM PDT 24
Peak memory 214384 kb
Host smart-9ffaa7f0-11fa-4bb5-b5d3-a206f13acb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425194955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3425194955
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1663793484
Short name T675
Test name
Test status
Simulation time 214116955 ps
CPU time 3.18 seconds
Started Aug 03 05:23:31 PM PDT 24
Finished Aug 03 05:23:34 PM PDT 24
Peak memory 214340 kb
Host smart-a6b3ed54-cca7-4961-95e6-6f722b95f4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663793484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1663793484
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.468271550
Short name T843
Test name
Test status
Simulation time 50342992 ps
CPU time 3.29 seconds
Started Aug 03 05:23:32 PM PDT 24
Finished Aug 03 05:23:35 PM PDT 24
Peak memory 209860 kb
Host smart-0c742001-0e8f-42a1-9267-66c8052481d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468271550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.468271550
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.4232875382
Short name T634
Test name
Test status
Simulation time 63922762 ps
CPU time 2.37 seconds
Started Aug 03 05:23:32 PM PDT 24
Finished Aug 03 05:23:34 PM PDT 24
Peak memory 207648 kb
Host smart-a3c27805-7128-4917-9caf-d933672df854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232875382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.4232875382
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3781724392
Short name T15
Test name
Test status
Simulation time 95013857 ps
CPU time 3.93 seconds
Started Aug 03 05:23:31 PM PDT 24
Finished Aug 03 05:23:35 PM PDT 24
Peak memory 208052 kb
Host smart-df4fa9af-9066-45a4-aef4-bbc4227ce9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781724392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3781724392
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1571042455
Short name T556
Test name
Test status
Simulation time 311325862 ps
CPU time 9.85 seconds
Started Aug 03 05:23:32 PM PDT 24
Finished Aug 03 05:23:42 PM PDT 24
Peak memory 208168 kb
Host smart-3fe1a7f2-d346-4dd0-be1e-e416ba5327aa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571042455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1571042455
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3521073316
Short name T406
Test name
Test status
Simulation time 1221409156 ps
CPU time 26.29 seconds
Started Aug 03 05:23:39 PM PDT 24
Finished Aug 03 05:24:06 PM PDT 24
Peak memory 208280 kb
Host smart-ad9b8b4d-be7c-4092-9d51-7c55991336c5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521073316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3521073316
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2761016956
Short name T504
Test name
Test status
Simulation time 227159050 ps
CPU time 3.97 seconds
Started Aug 03 05:23:30 PM PDT 24
Finished Aug 03 05:23:34 PM PDT 24
Peak memory 208564 kb
Host smart-7cc8ba5f-d7b1-4bb7-ae7b-7d5661809957
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761016956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2761016956
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3392644167
Short name T16
Test name
Test status
Simulation time 325966793 ps
CPU time 6.53 seconds
Started Aug 03 05:23:31 PM PDT 24
Finished Aug 03 05:23:38 PM PDT 24
Peak memory 209312 kb
Host smart-5ce3223c-8df3-4d80-8a29-a54b3a35e804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392644167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3392644167
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2177008670
Short name T814
Test name
Test status
Simulation time 194091745 ps
CPU time 2.77 seconds
Started Aug 03 05:23:30 PM PDT 24
Finished Aug 03 05:23:33 PM PDT 24
Peak memory 206808 kb
Host smart-3b1466ca-e7e8-4ced-a12a-58f06a999116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177008670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2177008670
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1528305405
Short name T206
Test name
Test status
Simulation time 154226707 ps
CPU time 6.73 seconds
Started Aug 03 05:23:32 PM PDT 24
Finished Aug 03 05:23:39 PM PDT 24
Peak memory 221612 kb
Host smart-4eac3b89-702d-45cf-af52-5016fe2b742c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528305405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1528305405
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.173532966
Short name T179
Test name
Test status
Simulation time 664742742 ps
CPU time 23.28 seconds
Started Aug 03 05:23:32 PM PDT 24
Finished Aug 03 05:23:55 PM PDT 24
Peak memory 222444 kb
Host smart-5503c8e2-2368-4792-9f14-e7b28a20fcf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173532966 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.173532966
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2472562878
Short name T860
Test name
Test status
Simulation time 42975639 ps
CPU time 1.89 seconds
Started Aug 03 05:23:33 PM PDT 24
Finished Aug 03 05:23:35 PM PDT 24
Peak memory 208288 kb
Host smart-0039a457-77ab-4e6f-ac95-11da082dab2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472562878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2472562878
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3506193753
Short name T162
Test name
Test status
Simulation time 180456115 ps
CPU time 2.7 seconds
Started Aug 03 05:23:33 PM PDT 24
Finished Aug 03 05:23:36 PM PDT 24
Peak memory 210452 kb
Host smart-dd3c446a-0a8b-45b0-86dc-573e18e27f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506193753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3506193753
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.474039703
Short name T607
Test name
Test status
Simulation time 96127433 ps
CPU time 0.76 seconds
Started Aug 03 05:23:40 PM PDT 24
Finished Aug 03 05:23:41 PM PDT 24
Peak memory 205876 kb
Host smart-df118e8f-c890-4294-b816-97fd44bcf592
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474039703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.474039703
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2451968352
Short name T321
Test name
Test status
Simulation time 106352126 ps
CPU time 5.01 seconds
Started Aug 03 05:23:36 PM PDT 24
Finished Aug 03 05:23:41 PM PDT 24
Peak memory 214268 kb
Host smart-0fd78cf2-1cd1-4f92-898e-d0a37f2e85ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2451968352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2451968352
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.931971038
Short name T32
Test name
Test status
Simulation time 222742810 ps
CPU time 3.98 seconds
Started Aug 03 05:23:36 PM PDT 24
Finished Aug 03 05:23:40 PM PDT 24
Peak memory 214228 kb
Host smart-a885f6b1-87bd-47d4-93a7-8d7103abaace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931971038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.931971038
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.4250273446
Short name T499
Test name
Test status
Simulation time 33210674 ps
CPU time 1.37 seconds
Started Aug 03 05:23:37 PM PDT 24
Finished Aug 03 05:23:39 PM PDT 24
Peak memory 207424 kb
Host smart-5502fea5-1457-4875-bd98-1db9ee3fc710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250273446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.4250273446
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.3455870043
Short name T199
Test name
Test status
Simulation time 74806103 ps
CPU time 3.44 seconds
Started Aug 03 05:23:35 PM PDT 24
Finished Aug 03 05:23:39 PM PDT 24
Peak memory 209188 kb
Host smart-c6ffb370-7532-4e6f-9cfd-ec9c5ace89c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455870043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3455870043
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3871932910
Short name T737
Test name
Test status
Simulation time 106904712 ps
CPU time 2.33 seconds
Started Aug 03 05:23:38 PM PDT 24
Finished Aug 03 05:23:40 PM PDT 24
Peak memory 207716 kb
Host smart-4fabebd3-b6f2-444f-a90d-d441b9805b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871932910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3871932910
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.632025696
Short name T680
Test name
Test status
Simulation time 883557470 ps
CPU time 4.53 seconds
Started Aug 03 05:23:36 PM PDT 24
Finished Aug 03 05:23:41 PM PDT 24
Peak memory 214400 kb
Host smart-f597f1b8-6a70-4d99-a243-8c94009ef717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632025696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.632025696
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.4010965102
Short name T372
Test name
Test status
Simulation time 153112200 ps
CPU time 5.19 seconds
Started Aug 03 05:23:35 PM PDT 24
Finished Aug 03 05:23:41 PM PDT 24
Peak memory 208832 kb
Host smart-3613aa0e-603a-4acf-8e77-fd140ae3970e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010965102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.4010965102
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.946997455
Short name T730
Test name
Test status
Simulation time 93132283 ps
CPU time 2.63 seconds
Started Aug 03 05:23:37 PM PDT 24
Finished Aug 03 05:23:40 PM PDT 24
Peak memory 206924 kb
Host smart-0e8b85ee-b2e6-4996-8dfa-8740d6f69f07
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946997455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.946997455
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1580745936
Short name T692
Test name
Test status
Simulation time 213425926 ps
CPU time 3 seconds
Started Aug 03 05:23:36 PM PDT 24
Finished Aug 03 05:23:40 PM PDT 24
Peak memory 207052 kb
Host smart-e1522999-dc90-4599-8de3-6c96f61fb9e5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580745936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1580745936
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1867042310
Short name T450
Test name
Test status
Simulation time 59656876 ps
CPU time 3.03 seconds
Started Aug 03 05:23:37 PM PDT 24
Finished Aug 03 05:23:40 PM PDT 24
Peak memory 208632 kb
Host smart-2d539995-9517-4379-9fe2-60f4d224e9e0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867042310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1867042310
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.3867992619
Short name T501
Test name
Test status
Simulation time 188011495 ps
CPU time 2.59 seconds
Started Aug 03 05:23:37 PM PDT 24
Finished Aug 03 05:23:40 PM PDT 24
Peak memory 207484 kb
Host smart-d2739bc2-2766-4102-8507-bbb85e9b089c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867992619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3867992619
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.660860936
Short name T744
Test name
Test status
Simulation time 1067681841 ps
CPU time 4.47 seconds
Started Aug 03 05:23:40 PM PDT 24
Finished Aug 03 05:23:45 PM PDT 24
Peak memory 208144 kb
Host smart-51e22f7c-28f4-4785-98ea-202bb5dc17aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660860936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.660860936
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2867103012
Short name T623
Test name
Test status
Simulation time 1875649418 ps
CPU time 22.38 seconds
Started Aug 03 05:23:40 PM PDT 24
Finished Aug 03 05:24:02 PM PDT 24
Peak memory 221304 kb
Host smart-f367f7b4-8147-4ae6-b83f-11af5ef3340f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867103012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2867103012
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.4109290495
Short name T341
Test name
Test status
Simulation time 214414718 ps
CPU time 8.24 seconds
Started Aug 03 05:23:34 PM PDT 24
Finished Aug 03 05:23:43 PM PDT 24
Peak memory 222568 kb
Host smart-ab5ddd58-d7eb-462d-9301-2545ec76dc22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109290495 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.4109290495
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2051452718
Short name T382
Test name
Test status
Simulation time 173918913 ps
CPU time 3.14 seconds
Started Aug 03 05:23:36 PM PDT 24
Finished Aug 03 05:23:39 PM PDT 24
Peak memory 207940 kb
Host smart-039910c6-08b2-4c44-82eb-ab6ac5613adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051452718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2051452718
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1394414859
Short name T785
Test name
Test status
Simulation time 34707762 ps
CPU time 0.74 seconds
Started Aug 03 05:23:44 PM PDT 24
Finished Aug 03 05:23:45 PM PDT 24
Peak memory 205932 kb
Host smart-7a839a65-34ee-4fa8-9b84-e7a09aeab923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394414859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1394414859
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.409121400
Short name T134
Test name
Test status
Simulation time 66251383 ps
CPU time 4.87 seconds
Started Aug 03 05:23:45 PM PDT 24
Finished Aug 03 05:23:49 PM PDT 24
Peak memory 214516 kb
Host smart-1f259366-0964-4a6e-b62f-d9a1ba32073f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=409121400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.409121400
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2062563722
Short name T284
Test name
Test status
Simulation time 214717719 ps
CPU time 5 seconds
Started Aug 03 05:23:44 PM PDT 24
Finished Aug 03 05:23:49 PM PDT 24
Peak memory 209800 kb
Host smart-082c359d-36b7-44c2-a74f-f466080e5d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062563722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2062563722
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.165051779
Short name T775
Test name
Test status
Simulation time 58170818 ps
CPU time 3.51 seconds
Started Aug 03 05:23:42 PM PDT 24
Finished Aug 03 05:23:46 PM PDT 24
Peak memory 220976 kb
Host smart-1318b97d-3cb0-414e-b76d-7eb835e707a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165051779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.165051779
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.3704642996
Short name T287
Test name
Test status
Simulation time 72817284 ps
CPU time 2.9 seconds
Started Aug 03 05:23:42 PM PDT 24
Finished Aug 03 05:23:45 PM PDT 24
Peak memory 220524 kb
Host smart-6b7d5e7b-e4da-4804-bac5-585f1a2c6278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704642996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.3704642996
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2720797619
Short name T400
Test name
Test status
Simulation time 609242466 ps
CPU time 4.69 seconds
Started Aug 03 05:23:43 PM PDT 24
Finished Aug 03 05:23:48 PM PDT 24
Peak memory 208680 kb
Host smart-17625b55-9ca4-44ae-a7c9-240e3d152992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720797619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2720797619
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3935960117
Short name T264
Test name
Test status
Simulation time 641205596 ps
CPU time 7.7 seconds
Started Aug 03 05:23:48 PM PDT 24
Finished Aug 03 05:23:56 PM PDT 24
Peak memory 208472 kb
Host smart-6513cd26-5bfb-43ff-8eae-c42bb055d9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935960117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3935960117
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.620665991
Short name T333
Test name
Test status
Simulation time 1319356296 ps
CPU time 44.64 seconds
Started Aug 03 05:23:37 PM PDT 24
Finished Aug 03 05:24:22 PM PDT 24
Peak memory 208336 kb
Host smart-7c91f997-5156-4842-ac6a-33455c2b383d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620665991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.620665991
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2068466419
Short name T853
Test name
Test status
Simulation time 1420068342 ps
CPU time 14.98 seconds
Started Aug 03 05:23:45 PM PDT 24
Finished Aug 03 05:24:00 PM PDT 24
Peak memory 208476 kb
Host smart-ec79fb9b-a605-43c9-aaf2-ce59a4f39e22
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068466419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2068466419
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.4144970559
Short name T712
Test name
Test status
Simulation time 1717557252 ps
CPU time 39.71 seconds
Started Aug 03 05:23:36 PM PDT 24
Finished Aug 03 05:24:16 PM PDT 24
Peak memory 208924 kb
Host smart-98178ee3-cf3a-4c4f-88f7-cc800a589568
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144970559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.4144970559
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.4170868150
Short name T513
Test name
Test status
Simulation time 113197634 ps
CPU time 3.66 seconds
Started Aug 03 05:23:48 PM PDT 24
Finished Aug 03 05:23:52 PM PDT 24
Peak memory 207088 kb
Host smart-b8e0cdf0-397f-4d48-9d17-cc129dc05b3c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170868150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.4170868150
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.283297518
Short name T665
Test name
Test status
Simulation time 161827677 ps
CPU time 2.17 seconds
Started Aug 03 05:23:43 PM PDT 24
Finished Aug 03 05:23:45 PM PDT 24
Peak memory 209260 kb
Host smart-338c4685-1640-4fa8-bedd-a1c6c976b9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283297518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.283297518
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2571592439
Short name T529
Test name
Test status
Simulation time 121013959 ps
CPU time 1.81 seconds
Started Aug 03 05:23:39 PM PDT 24
Finished Aug 03 05:23:41 PM PDT 24
Peak memory 206120 kb
Host smart-8c998ffe-bc7b-4964-b332-5b1a617bd0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571592439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2571592439
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.1684810665
Short name T71
Test name
Test status
Simulation time 325145422 ps
CPU time 18.99 seconds
Started Aug 03 05:23:43 PM PDT 24
Finished Aug 03 05:24:02 PM PDT 24
Peak memory 222600 kb
Host smart-e22484ec-ce38-4e78-9c35-d384dd21e159
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684810665 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.1684810665
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3982918031
Short name T339
Test name
Test status
Simulation time 66134045 ps
CPU time 3.44 seconds
Started Aug 03 05:23:45 PM PDT 24
Finished Aug 03 05:23:48 PM PDT 24
Peak memory 207956 kb
Host smart-218634bd-b5ee-4867-9fca-1a7eac8b8bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982918031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3982918031
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2779001683
Short name T461
Test name
Test status
Simulation time 42227145 ps
CPU time 1.81 seconds
Started Aug 03 05:23:42 PM PDT 24
Finished Aug 03 05:23:44 PM PDT 24
Peak memory 209684 kb
Host smart-21fe1a19-9cd4-4c72-b758-842fdf504a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779001683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2779001683
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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